1 /*
2 * linux/arch/arm/mach-omap2/timer-gp.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38
39 #include <asm/mach/time.h>
40 #include <plat/dmtimer.h>
41 #include <asm/localtimer.h>
42 #include <asm/sched_clock.h>
43 #include <plat/common.h>
44 #include <plat/omap_hwmod.h>
45
46 #include "timer-gp.h"
47
48
49 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
50 #define MAX_GPTIMER_ID 12
51
52 static struct omap_dm_timer *gptimer;
53 static struct clock_event_device clockevent_gpt;
54 static u8 __initdata gptimer_id = 1;
55 static u8 __initdata inited;
56 struct omap_dm_timer *gptimer_wakeup;
57
omap2_gp_timer_interrupt(int irq,void * dev_id)58 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
59 {
60 struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
61 struct clock_event_device *evt = &clockevent_gpt;
62
63 omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
64
65 evt->event_handler(evt);
66 return IRQ_HANDLED;
67 }
68
69 static struct irqaction omap2_gp_timer_irq = {
70 .name = "gp timer",
71 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
72 .handler = omap2_gp_timer_interrupt,
73 };
74
omap2_gp_timer_set_next_event(unsigned long cycles,struct clock_event_device * evt)75 static int omap2_gp_timer_set_next_event(unsigned long cycles,
76 struct clock_event_device *evt)
77 {
78 omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
79
80 return 0;
81 }
82
omap2_gp_timer_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)83 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
84 struct clock_event_device *evt)
85 {
86 u32 period;
87
88 omap_dm_timer_stop(gptimer);
89
90 switch (mode) {
91 case CLOCK_EVT_MODE_PERIODIC:
92 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
93 period -= 1;
94 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
95 break;
96 case CLOCK_EVT_MODE_ONESHOT:
97 break;
98 case CLOCK_EVT_MODE_UNUSED:
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 case CLOCK_EVT_MODE_RESUME:
101 break;
102 }
103 }
104
105 static struct clock_event_device clockevent_gpt = {
106 .name = "gp timer",
107 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
108 .shift = 32,
109 .set_next_event = omap2_gp_timer_set_next_event,
110 .set_mode = omap2_gp_timer_set_mode,
111 };
112
113 /**
114 * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
115 * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
116 *
117 * Define the GPTIMER that the system should use for the tick timer.
118 * Meant to be called from board-*.c files in the event that GPTIMER1, the
119 * default, is unsuitable. Returns -EINVAL on error or 0 on success.
120 */
omap2_gp_clockevent_set_gptimer(u8 id)121 int __init omap2_gp_clockevent_set_gptimer(u8 id)
122 {
123 if (id < 1 || id > MAX_GPTIMER_ID)
124 return -EINVAL;
125
126 BUG_ON(inited);
127
128 gptimer_id = id;
129
130 return 0;
131 }
132
omap2_gp_clockevent_init(void)133 static void __init omap2_gp_clockevent_init(void)
134 {
135 u32 tick_rate;
136 int src;
137 char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
138
139 inited = 1;
140
141 sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
142 omap_hwmod_setup_one(clockevent_hwmod_name);
143
144 gptimer = omap_dm_timer_request_specific(gptimer_id);
145 BUG_ON(gptimer == NULL);
146 gptimer_wakeup = gptimer;
147
148 #if defined(CONFIG_OMAP_32K_TIMER)
149 src = OMAP_TIMER_SRC_32_KHZ;
150 #else
151 src = OMAP_TIMER_SRC_SYS_CLK;
152 WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
153 "secure 32KiHz clock source\n");
154 #endif
155
156 if (gptimer_id != 12)
157 WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
158 "timer-gp: omap_dm_timer_set_source() failed\n");
159
160 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
161
162 pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
163 gptimer_id, tick_rate);
164
165 omap2_gp_timer_irq.dev_id = (void *)gptimer;
166 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
167 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
168
169 clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
170 clockevent_gpt.shift);
171 clockevent_gpt.max_delta_ns =
172 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
173 clockevent_gpt.min_delta_ns =
174 clockevent_delta2ns(3, &clockevent_gpt);
175 /* Timer internal resynch latency. */
176
177 clockevent_gpt.cpumask = cpumask_of(0);
178 clockevents_register_device(&clockevent_gpt);
179 }
180
181 /* Clocksource code */
182
183 #ifdef CONFIG_OMAP_32K_TIMER
184 /*
185 * When 32k-timer is enabled, don't use GPTimer for clocksource
186 * instead, just leave default clocksource which uses the 32k
187 * sync counter. See clocksource setup in plat-omap/counter_32k.c
188 */
189
omap2_gp_clocksource_init(void)190 static void __init omap2_gp_clocksource_init(void)
191 {
192 omap_init_clocksource_32k();
193 }
194
195 #else
196 /*
197 * clocksource
198 */
199 static DEFINE_CLOCK_DATA(cd);
200 static struct omap_dm_timer *gpt_clocksource;
clocksource_read_cycles(struct clocksource * cs)201 static cycle_t clocksource_read_cycles(struct clocksource *cs)
202 {
203 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
204 }
205
206 static struct clocksource clocksource_gpt = {
207 .name = "gp timer",
208 .rating = 300,
209 .read = clocksource_read_cycles,
210 .mask = CLOCKSOURCE_MASK(32),
211 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
212 };
213
dmtimer_update_sched_clock(void)214 static void notrace dmtimer_update_sched_clock(void)
215 {
216 u32 cyc;
217
218 cyc = omap_dm_timer_read_counter(gpt_clocksource);
219
220 update_sched_clock(&cd, cyc, (u32)~0);
221 }
222
223 /* Setup free-running counter for clocksource */
omap2_gp_clocksource_init(void)224 static void __init omap2_gp_clocksource_init(void)
225 {
226 static struct omap_dm_timer *gpt;
227 u32 tick_rate;
228 static char err1[] __initdata = KERN_ERR
229 "%s: failed to request dm-timer\n";
230 static char err2[] __initdata = KERN_ERR
231 "%s: can't register clocksource!\n";
232
233 gpt = omap_dm_timer_request();
234 if (!gpt)
235 printk(err1, clocksource_gpt.name);
236 gpt_clocksource = gpt;
237
238 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
239 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
240
241 omap_dm_timer_set_load_start(gpt, 1, 0);
242
243 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
244
245 if (clocksource_register_hz(&clocksource_gpt, tick_rate))
246 printk(err2, clocksource_gpt.name);
247 }
248 #endif
249
omap2_gp_timer_init(void)250 static void __init omap2_gp_timer_init(void)
251 {
252 #ifdef CONFIG_LOCAL_TIMERS
253 if (cpu_is_omap44xx()) {
254 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
255 BUG_ON(!twd_base);
256 }
257 #endif
258 omap_dm_timer_init();
259
260 omap2_gp_clockevent_init();
261 omap2_gp_clocksource_init();
262 }
263
264 struct sys_timer omap_timer = {
265 .init = omap2_gp_timer_init,
266 };
267