1 /*
2 * Copyright 2016 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24 #include "channv50.h"
25
26 #include <subdev/timer.h>
27
28 static int
gp102_disp_core_init(struct nv50_disp_chan * chan)29 gp102_disp_core_init(struct nv50_disp_chan *chan)
30 {
31 struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
32 struct nvkm_device *device = subdev->device;
33
34 /* initialise channel for dma command submission */
35 nvkm_wr32(device, 0x611494, chan->push);
36 nvkm_wr32(device, 0x611498, 0x00010000);
37 nvkm_wr32(device, 0x61149c, 0x00000001);
38 nvkm_mask(device, 0x610490, 0x00000010, 0x00000010);
39 nvkm_wr32(device, 0x640000, chan->suspend_put);
40 nvkm_wr32(device, 0x610490, 0x01000013);
41
42 /* wait for it to go inactive */
43 if (nvkm_msec(device, 2000,
44 if (!(nvkm_rd32(device, 0x610490) & 0x80000000))
45 break;
46 ) < 0) {
47 nvkm_error(subdev, "core init: %08x\n",
48 nvkm_rd32(device, 0x610490));
49 return -EBUSY;
50 }
51
52 return 0;
53 }
54
55 static const struct nv50_disp_chan_func
56 gp102_disp_core_func = {
57 .init = gp102_disp_core_init,
58 .fini = gf119_disp_core_fini,
59 .intr = gf119_disp_chan_intr,
60 .user = nv50_disp_chan_user,
61 .bind = gf119_disp_dmac_bind,
62 };
63
64 int
gp102_disp_core_new(const struct nvkm_oclass * oclass,void * argv,u32 argc,struct nv50_disp * disp,struct nvkm_object ** pobject)65 gp102_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
66 struct nv50_disp *disp, struct nvkm_object **pobject)
67 {
68 return nv50_disp_core_new_(&gp102_disp_core_func, &gk104_disp_core_mthd,
69 disp, 0, oclass, argv, argc, pobject);
70 }
71