1 /*
2  * Copyright 2019 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "priv.h"
23 
24 #include <core/firmware.h>
25 #include <core/memory.h>
26 #include <subdev/mmu.h>
27 #include <engine/sec2.h>
28 
29 #include <nvfw/acr.h>
30 #include <nvfw/flcn.h>
31 
32 void
gp102_acr_wpr_patch(struct nvkm_acr * acr,s64 adjust)33 gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
34 {
35 	struct wpr_header_v1 hdr;
36 	struct lsb_header_v1 lsb;
37 	struct nvkm_acr_lsfw *lsfw;
38 	u32 offset = 0;
39 
40 	do {
41 		nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
42 		wpr_header_v1_dump(&acr->subdev, &hdr);
43 
44 		list_for_each_entry(lsfw, &acr->lsfw, head) {
45 			if (lsfw->id != hdr.falcon_id)
46 				continue;
47 
48 			nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
49 			lsb_header_v1_dump(&acr->subdev, &lsb);
50 
51 			lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
52 			break;
53 		}
54 
55 		offset += sizeof(hdr);
56 	} while (hdr.falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID);
57 }
58 
59 int
gp102_acr_wpr_build_lsb(struct nvkm_acr * acr,struct nvkm_acr_lsfw * lsfw)60 gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
61 {
62 	struct lsb_header_v1 hdr;
63 
64 	if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
65 		return -EINVAL;
66 
67 	memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
68 	gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
69 
70 	nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
71 	return 0;
72 }
73 
74 int
gp102_acr_wpr_build(struct nvkm_acr * acr,struct nvkm_acr_lsf * rtos)75 gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
76 {
77 	struct nvkm_acr_lsfw *lsfw;
78 	u32 offset = 0;
79 	int ret;
80 
81 	/* Fill per-LSF structures. */
82 	list_for_each_entry(lsfw, &acr->lsfw, head) {
83 		struct lsf_signature_v1 *sig = (void *)lsfw->sig->data;
84 		struct wpr_header_v1 hdr = {
85 			.falcon_id = lsfw->id,
86 			.lsb_offset = lsfw->offset.lsb,
87 			.bootstrap_owner = NVKM_ACR_LSF_SEC2,
88 			.lazy_bootstrap = rtos && lsfw->id != rtos->id,
89 			.bin_version = sig->version,
90 			.status = WPR_HEADER_V1_STATUS_COPY,
91 		};
92 
93 		/* Write WPR header. */
94 		nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
95 		offset += sizeof(hdr);
96 
97 		/* Write LSB header. */
98 		ret = gp102_acr_wpr_build_lsb(acr, lsfw);
99 		if (ret)
100 			return ret;
101 
102 		/* Write ucode image. */
103 		nvkm_wobj(acr->wpr, lsfw->offset.img,
104 				    lsfw->img.data,
105 				    lsfw->img.size);
106 
107 		/* Write bootloader data. */
108 		lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
109 	}
110 
111 	/* Finalise WPR. */
112 	nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID);
113 	return 0;
114 }
115 
116 int
gp102_acr_wpr_alloc(struct nvkm_acr * acr,u32 wpr_size)117 gp102_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
118 {
119 	int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
120 				  ALIGN(wpr_size, 0x40000) << 1, 0x40000, true,
121 				  &acr->wpr);
122 	if (ret)
123 		return ret;
124 
125 	acr->shadow_start = nvkm_memory_addr(acr->wpr);
126 	acr->wpr_start = acr->shadow_start + (nvkm_memory_size(acr->wpr) >> 1);
127 	acr->wpr_end = acr->wpr_start + (nvkm_memory_size(acr->wpr) >> 1);
128 	return 0;
129 }
130 
131 u32
gp102_acr_wpr_layout(struct nvkm_acr * acr)132 gp102_acr_wpr_layout(struct nvkm_acr *acr)
133 {
134 	struct nvkm_acr_lsfw *lsfw;
135 	u32 wpr = 0;
136 
137 	wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header_v1);
138 	wpr  = ALIGN(wpr, 256);
139 
140 	wpr += 0x100; /* Shared sub-WPR headers. */
141 
142 	list_for_each_entry(lsfw, &acr->lsfw, head) {
143 		wpr  = ALIGN(wpr, 256);
144 		lsfw->offset.lsb = wpr;
145 		wpr += sizeof(struct lsb_header_v1);
146 
147 		wpr  = ALIGN(wpr, 4096);
148 		lsfw->offset.img = wpr;
149 		wpr += lsfw->img.size;
150 
151 		wpr  = ALIGN(wpr, 256);
152 		lsfw->offset.bld = wpr;
153 		lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
154 		wpr += lsfw->bl_data_size;
155 	}
156 
157 	return wpr;
158 }
159 
160 int
gp102_acr_wpr_parse(struct nvkm_acr * acr)161 gp102_acr_wpr_parse(struct nvkm_acr *acr)
162 {
163 	const struct wpr_header_v1 *hdr = (void *)acr->wpr_fw->data;
164 	struct nvkm_acr_lsfw *lsfw;
165 
166 	while (hdr->falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID) {
167 		wpr_header_v1_dump(&acr->subdev, hdr);
168 		lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id);
169 		if (IS_ERR(lsfw))
170 			return PTR_ERR(lsfw);
171 	}
172 
173 	return 0;
174 }
175 
176 MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin");
177 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin");
178 
179 MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin");
180 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin");
181 
182 MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin");
183 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin");
184 
185 MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin");
186 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin");
187 
188 static const struct nvkm_acr_hsf_fwif
189 gp102_acr_unload_fwif[] = {
190 	{ 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 },
191 	{}
192 };
193 
194 int
gp102_acr_load_load(struct nvkm_acr * acr,struct nvkm_acr_hsfw * hsfw)195 gp102_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
196 {
197 	struct flcn_acr_desc_v1 *desc = (void *)&hsfw->image[hsfw->data_addr];
198 
199 	desc->wpr_region_id = 1;
200 	desc->regions.no_regions = 2;
201 	desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
202 	desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
203 	desc->regions.region_props[0].region_id = 1;
204 	desc->regions.region_props[0].read_mask = 0xf;
205 	desc->regions.region_props[0].write_mask = 0xc;
206 	desc->regions.region_props[0].client_mask = 0x2;
207 	desc->regions.region_props[0].shadow_mem_start_addr =
208 		acr->shadow_start >> 8;
209 	flcn_acr_desc_v1_dump(&acr->subdev, desc);
210 
211 	return gm200_acr_hsfw_load(acr, hsfw,
212 				  &acr->subdev.device->sec2->falcon);
213 }
214 
215 static const struct nvkm_acr_hsf_func
216 gp102_acr_load_0 = {
217 	.load = gp102_acr_load_load,
218 	.boot = gm200_acr_load_boot,
219 	.bld = gm200_acr_hsfw_bld,
220 };
221 
222 MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin");
223 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin");
224 
225 MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin");
226 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin");
227 
228 MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin");
229 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin");
230 
231 MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin");
232 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin");
233 
234 static const struct nvkm_acr_hsf_fwif
235 gp102_acr_load_fwif[] = {
236 	{ 0, nvkm_acr_hsfw_load, &gp102_acr_load_0 },
237 	{}
238 };
239 
240 static const struct nvkm_acr_func
241 gp102_acr = {
242 	.load = gp102_acr_load_fwif,
243 	.unload = gp102_acr_unload_fwif,
244 	.wpr_parse = gp102_acr_wpr_parse,
245 	.wpr_layout = gp102_acr_wpr_layout,
246 	.wpr_alloc = gp102_acr_wpr_alloc,
247 	.wpr_build = gp102_acr_wpr_build,
248 	.wpr_patch = gp102_acr_wpr_patch,
249 	.wpr_check = gm200_acr_wpr_check,
250 	.init = gm200_acr_init,
251 };
252 
253 int
gp102_acr_load(struct nvkm_acr * acr,int ver,const struct nvkm_acr_fwif * fwif)254 gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
255 {
256 	struct nvkm_subdev *subdev = &acr->subdev;
257 	const struct nvkm_acr_hsf_fwif *hsfwif;
258 
259 	hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
260 				    acr, "acr/bl", "acr/ucode_load", "load");
261 	if (IS_ERR(hsfwif))
262 		return PTR_ERR(hsfwif);
263 
264 	hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
265 				    acr, "acr/unload_bl", "acr/ucode_unload",
266 				    "unload");
267 	if (IS_ERR(hsfwif))
268 		return PTR_ERR(hsfwif);
269 
270 	return 0;
271 }
272 
273 static const struct nvkm_acr_fwif
274 gp102_acr_fwif[] = {
275 	{  0, gp102_acr_load, &gp102_acr },
276 	{ -1, gm200_acr_nofw, &gm200_acr },
277 	{}
278 };
279 
280 int
gp102_acr_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_acr ** pacr)281 gp102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
282 	      struct nvkm_acr **pacr)
283 {
284 	return nvkm_acr_new_(gp102_acr_fwif, device, type, inst, pacr);
285 }
286