1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "hdmi.h"
27 #include "head.h"
28 #include "ior.h"
29
30 #include <nvif/class.h>
31
32 void
gk104_sor_hdmi_ctrl(struct nvkm_ior * ior,int head,bool enable,u8 max_ac_packet,u8 rekey,u8 * avi,u8 avi_size,u8 * vendor,u8 vendor_size)33 gk104_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet,
34 u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size)
35 {
36 struct nvkm_device *device = ior->disp->engine.subdev.device;
37 const u32 ctrl = 0x40000000 * enable |
38 max_ac_packet << 16 |
39 rekey;
40 const u32 hoff = head * 0x800;
41 const u32 hdmi = head * 0x400;
42 struct packed_hdmi_infoframe avi_infoframe;
43 struct packed_hdmi_infoframe vendor_infoframe;
44
45 pack_hdmi_infoframe(&avi_infoframe, avi, avi_size);
46 pack_hdmi_infoframe(&vendor_infoframe, vendor, vendor_size);
47
48 if (!(ctrl & 0x40000000)) {
49 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000);
50 nvkm_mask(device, 0x690100 + hdmi, 0x00000001, 0x00000000);
51 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
52 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000);
53 return;
54 }
55
56 /* AVI InfoFrame */
57 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000);
58 if (avi_size) {
59 nvkm_wr32(device, 0x690008 + hdmi, avi_infoframe.header);
60 nvkm_wr32(device, 0x69000c + hdmi, avi_infoframe.subpack0_low);
61 nvkm_wr32(device, 0x690010 + hdmi, avi_infoframe.subpack0_high);
62 nvkm_wr32(device, 0x690014 + hdmi, avi_infoframe.subpack1_low);
63 nvkm_wr32(device, 0x690018 + hdmi, avi_infoframe.subpack1_high);
64 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000001);
65 }
66
67 /* GENERIC(?) / Vendor InfoFrame? */
68 nvkm_mask(device, 0x690100 + hdmi, 0x00010001, 0x00000000);
69 if (vendor_size) {
70 nvkm_wr32(device, 0x690108 + hdmi, vendor_infoframe.header);
71 nvkm_wr32(device, 0x69010c + hdmi, vendor_infoframe.subpack0_low);
72 nvkm_wr32(device, 0x690110 + hdmi, vendor_infoframe.subpack0_high);
73 /* Is there a second (or further?) set of subpack registers here? */
74 nvkm_mask(device, 0x690100 + hdmi, 0x00000001, 0x00000001);
75 }
76
77
78 /* ??? InfoFrame? */
79 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
80 nvkm_wr32(device, 0x6900cc + hdmi, 0x00000010);
81 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
82
83 /* ??? */
84 nvkm_wr32(device, 0x690080 + hdmi, 0x82000000);
85
86 /* HDMI_CTRL */
87 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl);
88 }
89
90 static const struct nvkm_ior_func
91 gk104_sor = {
92 .state = gf119_sor_state,
93 .power = nv50_sor_power,
94 .clock = gf119_sor_clock,
95 .hdmi = {
96 .ctrl = gk104_sor_hdmi_ctrl,
97 },
98 .dp = &gf119_sor_dp,
99 .hda = &gf119_sor_hda,
100 };
101
102 int
gk104_sor_new(struct nvkm_disp * disp,int id)103 gk104_sor_new(struct nvkm_disp *disp, int id)
104 {
105 return nvkm_ior_new_(&gk104_sor, disp, SOR, id, true);
106 }
107
108 static const struct nvkm_disp_mthd_list
109 gk104_disp_ovly_mthd_base = {
110 .mthd = 0x0000,
111 .data = {
112 { 0x0080, 0x665080 },
113 { 0x0084, 0x665084 },
114 { 0x0088, 0x665088 },
115 { 0x008c, 0x66508c },
116 { 0x0090, 0x665090 },
117 { 0x0094, 0x665094 },
118 { 0x00a0, 0x6650a0 },
119 { 0x00a4, 0x6650a4 },
120 { 0x00b0, 0x6650b0 },
121 { 0x00b4, 0x6650b4 },
122 { 0x00b8, 0x6650b8 },
123 { 0x00c0, 0x6650c0 },
124 { 0x00c4, 0x6650c4 },
125 { 0x00e0, 0x6650e0 },
126 { 0x00e4, 0x6650e4 },
127 { 0x00e8, 0x6650e8 },
128 { 0x0100, 0x665100 },
129 { 0x0104, 0x665104 },
130 { 0x0108, 0x665108 },
131 { 0x010c, 0x66510c },
132 { 0x0110, 0x665110 },
133 { 0x0118, 0x665118 },
134 { 0x011c, 0x66511c },
135 { 0x0120, 0x665120 },
136 { 0x0124, 0x665124 },
137 { 0x0130, 0x665130 },
138 { 0x0134, 0x665134 },
139 { 0x0138, 0x665138 },
140 { 0x013c, 0x66513c },
141 { 0x0140, 0x665140 },
142 { 0x0144, 0x665144 },
143 { 0x0148, 0x665148 },
144 { 0x014c, 0x66514c },
145 { 0x0150, 0x665150 },
146 { 0x0154, 0x665154 },
147 { 0x0158, 0x665158 },
148 { 0x015c, 0x66515c },
149 { 0x0160, 0x665160 },
150 { 0x0164, 0x665164 },
151 { 0x0168, 0x665168 },
152 { 0x016c, 0x66516c },
153 { 0x0400, 0x665400 },
154 { 0x0404, 0x665404 },
155 { 0x0408, 0x665408 },
156 { 0x040c, 0x66540c },
157 { 0x0410, 0x665410 },
158 {}
159 }
160 };
161
162 const struct nvkm_disp_chan_mthd
163 gk104_disp_ovly_mthd = {
164 .name = "Overlay",
165 .addr = 0x001000,
166 .prev = -0x020000,
167 .data = {
168 { "Global", 1, &gk104_disp_ovly_mthd_base },
169 {}
170 }
171 };
172
173 const struct nvkm_disp_chan_user
174 gk104_disp_ovly = {
175 .func = &gf119_disp_dmac_func,
176 .ctrl = 5,
177 .user = 5,
178 .mthd = &gk104_disp_ovly_mthd,
179 };
180
181 static const struct nvkm_disp_mthd_list
182 gk104_disp_core_mthd_head = {
183 .mthd = 0x0300,
184 .addr = 0x000300,
185 .data = {
186 { 0x0400, 0x660400 },
187 { 0x0404, 0x660404 },
188 { 0x0408, 0x660408 },
189 { 0x040c, 0x66040c },
190 { 0x0410, 0x660410 },
191 { 0x0414, 0x660414 },
192 { 0x0418, 0x660418 },
193 { 0x041c, 0x66041c },
194 { 0x0420, 0x660420 },
195 { 0x0424, 0x660424 },
196 { 0x0428, 0x660428 },
197 { 0x042c, 0x66042c },
198 { 0x0430, 0x660430 },
199 { 0x0434, 0x660434 },
200 { 0x0438, 0x660438 },
201 { 0x0440, 0x660440 },
202 { 0x0444, 0x660444 },
203 { 0x0448, 0x660448 },
204 { 0x044c, 0x66044c },
205 { 0x0450, 0x660450 },
206 { 0x0454, 0x660454 },
207 { 0x0458, 0x660458 },
208 { 0x045c, 0x66045c },
209 { 0x0460, 0x660460 },
210 { 0x0468, 0x660468 },
211 { 0x046c, 0x66046c },
212 { 0x0470, 0x660470 },
213 { 0x0474, 0x660474 },
214 { 0x047c, 0x66047c },
215 { 0x0480, 0x660480 },
216 { 0x0484, 0x660484 },
217 { 0x0488, 0x660488 },
218 { 0x048c, 0x66048c },
219 { 0x0490, 0x660490 },
220 { 0x0494, 0x660494 },
221 { 0x0498, 0x660498 },
222 { 0x04a0, 0x6604a0 },
223 { 0x04b0, 0x6604b0 },
224 { 0x04b8, 0x6604b8 },
225 { 0x04bc, 0x6604bc },
226 { 0x04c0, 0x6604c0 },
227 { 0x04c4, 0x6604c4 },
228 { 0x04c8, 0x6604c8 },
229 { 0x04d0, 0x6604d0 },
230 { 0x04d4, 0x6604d4 },
231 { 0x04e0, 0x6604e0 },
232 { 0x04e4, 0x6604e4 },
233 { 0x04e8, 0x6604e8 },
234 { 0x04ec, 0x6604ec },
235 { 0x04f0, 0x6604f0 },
236 { 0x04f4, 0x6604f4 },
237 { 0x04f8, 0x6604f8 },
238 { 0x04fc, 0x6604fc },
239 { 0x0500, 0x660500 },
240 { 0x0504, 0x660504 },
241 { 0x0508, 0x660508 },
242 { 0x050c, 0x66050c },
243 { 0x0510, 0x660510 },
244 { 0x0514, 0x660514 },
245 { 0x0518, 0x660518 },
246 { 0x051c, 0x66051c },
247 { 0x0520, 0x660520 },
248 { 0x0524, 0x660524 },
249 { 0x052c, 0x66052c },
250 { 0x0530, 0x660530 },
251 { 0x054c, 0x66054c },
252 { 0x0550, 0x660550 },
253 { 0x0554, 0x660554 },
254 { 0x0558, 0x660558 },
255 { 0x055c, 0x66055c },
256 {}
257 }
258 };
259
260 const struct nvkm_disp_chan_mthd
261 gk104_disp_core_mthd = {
262 .name = "Core",
263 .addr = 0x000000,
264 .prev = -0x020000,
265 .data = {
266 { "Global", 1, &gf119_disp_core_mthd_base },
267 { "DAC", 3, &gf119_disp_core_mthd_dac },
268 { "SOR", 8, &gf119_disp_core_mthd_sor },
269 { "PIOR", 4, &gf119_disp_core_mthd_pior },
270 { "HEAD", 4, &gk104_disp_core_mthd_head },
271 {}
272 }
273 };
274
275 const struct nvkm_disp_chan_user
276 gk104_disp_core = {
277 .func = &gf119_disp_core_func,
278 .ctrl = 0,
279 .user = 0,
280 .mthd = &gk104_disp_core_mthd,
281 };
282
283 static const struct nvkm_disp_func
284 gk104_disp = {
285 .oneinit = nv50_disp_oneinit,
286 .init = gf119_disp_init,
287 .fini = gf119_disp_fini,
288 .intr = gf119_disp_intr,
289 .intr_error = gf119_disp_intr_error,
290 .super = gf119_disp_super,
291 .uevent = &gf119_disp_chan_uevent,
292 .head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
293 .dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
294 .sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
295 .root = { 0,0,GK104_DISP },
296 .user = {
297 {{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },
298 {{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },
299 {{0,0,GK104_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },
300 {{0,0,GK104_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gk104_disp_core },
301 {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },
302 {}
303 },
304 };
305
306 int
gk104_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)307 gk104_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
308 struct nvkm_disp **pdisp)
309 {
310 return nvkm_disp_new_(&gk104_disp, device, type, inst, pdisp);
311 }
312