1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
3
4 struct intel_hw_status_page {
5 u32 __iomem *page_addr;
6 unsigned int gfx_addr;
7 struct drm_i915_gem_object *obj;
8 };
9
10 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
11 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
12
13 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
14 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
15
16 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
17 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
18
19 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
20 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
21
22 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
23 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
24
25 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
26 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
27 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
28
29 struct intel_ring_buffer {
30 const char *name;
31 enum intel_ring_id {
32 RCS = 0x0,
33 VCS,
34 BCS,
35 } id;
36 #define I915_NUM_RINGS 3
37 u32 mmio_base;
38 void __iomem *virtual_start;
39 struct drm_device *dev;
40 struct drm_i915_gem_object *obj;
41
42 u32 head;
43 u32 tail;
44 int space;
45 int size;
46 int effective_size;
47 struct intel_hw_status_page status_page;
48
49 /** We track the position of the requests in the ring buffer, and
50 * when each is retired we increment last_retired_head as the GPU
51 * must have finished processing the request and so we know we
52 * can advance the ringbuffer up to that position.
53 *
54 * last_retired_head is set to -1 after the value is consumed so
55 * we can detect new retirements.
56 */
57 u32 last_retired_head;
58
59 spinlock_t irq_lock;
60 u32 irq_refcount;
61 u32 irq_mask;
62 u32 irq_seqno; /* last seq seem at irq time */
63 u32 trace_irq_seqno;
64 u32 waiting_seqno;
65 u32 sync_seqno[I915_NUM_RINGS-1];
66 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
67 void (*irq_put)(struct intel_ring_buffer *ring);
68
69 int (*init)(struct intel_ring_buffer *ring);
70
71 void (*write_tail)(struct intel_ring_buffer *ring,
72 u32 value);
73 int __must_check (*flush)(struct intel_ring_buffer *ring,
74 u32 invalidate_domains,
75 u32 flush_domains);
76 int (*add_request)(struct intel_ring_buffer *ring,
77 u32 *seqno);
78 u32 (*get_seqno)(struct intel_ring_buffer *ring);
79 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
80 u32 offset, u32 length);
81 void (*cleanup)(struct intel_ring_buffer *ring);
82 int (*sync_to)(struct intel_ring_buffer *ring,
83 struct intel_ring_buffer *to,
84 u32 seqno);
85
86 u32 semaphore_register[3]; /*our mbox written by others */
87 u32 signal_mbox[2]; /* mboxes this ring signals to */
88 /**
89 * List of objects currently involved in rendering from the
90 * ringbuffer.
91 *
92 * Includes buffers having the contents of their GPU caches
93 * flushed, not necessarily primitives. last_rendering_seqno
94 * represents when the rendering involved will be completed.
95 *
96 * A reference is held on the buffer while on this list.
97 */
98 struct list_head active_list;
99
100 /**
101 * List of breadcrumbs associated with GPU requests currently
102 * outstanding.
103 */
104 struct list_head request_list;
105
106 /**
107 * List of objects currently pending a GPU write flush.
108 *
109 * All elements on this list will belong to either the
110 * active_list or flushing_list, last_rendering_seqno can
111 * be used to differentiate between the two elements.
112 */
113 struct list_head gpu_write_list;
114
115 /**
116 * Do we have some not yet emitted requests outstanding?
117 */
118 u32 outstanding_lazy_request;
119
120 wait_queue_head_t irq_queue;
121 drm_local_map_t map;
122
123 void *private;
124 };
125
126 static inline unsigned
intel_ring_flag(struct intel_ring_buffer * ring)127 intel_ring_flag(struct intel_ring_buffer *ring)
128 {
129 return 1 << ring->id;
130 }
131
132 static inline u32
intel_ring_sync_index(struct intel_ring_buffer * ring,struct intel_ring_buffer * other)133 intel_ring_sync_index(struct intel_ring_buffer *ring,
134 struct intel_ring_buffer *other)
135 {
136 int idx;
137
138 /*
139 * cs -> 0 = vcs, 1 = bcs
140 * vcs -> 0 = bcs, 1 = cs,
141 * bcs -> 0 = cs, 1 = vcs.
142 */
143
144 idx = (other - ring) - 1;
145 if (idx < 0)
146 idx += I915_NUM_RINGS;
147
148 return idx;
149 }
150
151 static inline u32
intel_read_status_page(struct intel_ring_buffer * ring,int reg)152 intel_read_status_page(struct intel_ring_buffer *ring,
153 int reg)
154 {
155 return ioread32(ring->status_page.page_addr + reg);
156 }
157
158 /**
159 * Reads a dword out of the status page, which is written to from the command
160 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
161 * MI_STORE_DATA_IMM.
162 *
163 * The following dwords have a reserved meaning:
164 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
165 * 0x04: ring 0 head pointer
166 * 0x05: ring 1 head pointer (915-class)
167 * 0x06: ring 2 head pointer (915-class)
168 * 0x10-0x1b: Context status DWords (GM45)
169 * 0x1f: Last written status offset. (GM45)
170 *
171 * The area from dword 0x20 to 0x3ff is available for driver usage.
172 */
173 #define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
174 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
175 #define I915_GEM_HWS_INDEX 0x20
176 #define I915_BREADCRUMB_INDEX 0x21
177
178 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
179
180 int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
intel_wait_ring_idle(struct intel_ring_buffer * ring)181 static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
182 {
183 return intel_wait_ring_buffer(ring, ring->size - 8);
184 }
185
186 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
187
intel_ring_emit(struct intel_ring_buffer * ring,u32 data)188 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
189 u32 data)
190 {
191 iowrite32(data, ring->virtual_start + ring->tail);
192 ring->tail += 4;
193 }
194
195 void intel_ring_advance(struct intel_ring_buffer *ring);
196
197 u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
198
199 int intel_init_render_ring_buffer(struct drm_device *dev);
200 int intel_init_bsd_ring_buffer(struct drm_device *dev);
201 int intel_init_blt_ring_buffer(struct drm_device *dev);
202
203 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
204 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
205
intel_ring_get_tail(struct intel_ring_buffer * ring)206 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
207 {
208 return ring->tail;
209 }
210
i915_trace_irq_get(struct intel_ring_buffer * ring,u32 seqno)211 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
212 {
213 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
214 ring->trace_irq_seqno = seqno;
215 }
216
217 /* DRI warts */
218 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
219
220 #endif /* _INTEL_RINGBUFFER_H_ */
221