1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "ior.h"
25
26 #include <subdev/timer.h>
27
28 void
gf119_sor_dp_watermark(struct nvkm_ior * sor,int head,u8 watermark)29 gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark)
30 {
31 struct nvkm_device *device = sor->disp->engine.subdev.device;
32 const u32 hoff = head * 0x800;
33 nvkm_mask(device, 0x616610 + hoff, 0x0800003f, 0x08000000 | watermark);
34 }
35
36 void
gf119_sor_dp_audio_sym(struct nvkm_ior * sor,int head,u16 h,u32 v)37 gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
38 {
39 struct nvkm_device *device = sor->disp->engine.subdev.device;
40 const u32 hoff = head * 0x800;
41 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, h);
42 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v);
43 }
44
45 void
gf119_sor_dp_audio(struct nvkm_ior * sor,int head,bool enable)46 gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
47 {
48 struct nvkm_device *device = sor->disp->engine.subdev.device;
49 const u32 hoff = 0x800 * head;
50 const u32 data = 0x80000000 | (0x00000001 * enable);
51 const u32 mask = 0x8000000d;
52 nvkm_mask(device, 0x616618 + hoff, mask, data);
53 nvkm_msec(device, 2000,
54 if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000))
55 break;
56 );
57 }
58
59 void
gf119_sor_dp_vcpi(struct nvkm_ior * sor,int head,u8 slot,u8 slot_nr,u16 pbn,u16 aligned)60 gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head,
61 u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
62 {
63 struct nvkm_device *device = sor->disp->engine.subdev.device;
64 const u32 hoff = head * 0x800;
65
66 nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
67 nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn);
68 }
69
70 void
gf119_sor_dp_drive(struct nvkm_ior * sor,int ln,int pc,int dc,int pe,int pu)71 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
72 {
73 struct nvkm_device *device = sor->disp->engine.subdev.device;
74 const u32 loff = nv50_sor_link(sor);
75 const u32 shift = sor->func->dp.lanes[ln] * 8;
76 u32 data[4];
77
78 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
79 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
80 data[2] = nvkm_rd32(device, 0x61c130 + loff);
81 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)
82 data[2] = (data[2] & ~0x0000ff00) | (pu << 8);
83 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
84 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
85 nvkm_wr32(device, 0x61c130 + loff, data[2]);
86 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
87 nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift));
88 }
89
90 void
gf119_sor_dp_pattern(struct nvkm_ior * sor,int pattern)91 gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
92 {
93 struct nvkm_device *device = sor->disp->engine.subdev.device;
94 const u32 soff = nv50_ior_base(sor);
95 u32 data;
96
97 switch (pattern) {
98 case 0: data = 0x10101010; break;
99 case 1: data = 0x01010101; break;
100 case 2: data = 0x02020202; break;
101 case 3: data = 0x03030303; break;
102 default:
103 WARN_ON(1);
104 return;
105 }
106
107 nvkm_mask(device, 0x61c110 + soff, 0x1f1f1f1f, data);
108 }
109
110 int
gf119_sor_dp_links(struct nvkm_ior * sor,struct nvkm_i2c_aux * aux)111 gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
112 {
113 struct nvkm_device *device = sor->disp->engine.subdev.device;
114 const u32 soff = nv50_ior_base(sor);
115 const u32 loff = nv50_sor_link(sor);
116 u32 dpctrl = 0x00000000;
117 u32 clksor = 0x00000000;
118
119 clksor |= sor->dp.bw << 18;
120 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
121 if (sor->dp.mst)
122 dpctrl |= 0x40000000;
123 if (sor->dp.ef)
124 dpctrl |= 0x00004000;
125
126 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
127 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
128 return 0;
129 }
130
131 void
gf119_sor_clock(struct nvkm_ior * sor)132 gf119_sor_clock(struct nvkm_ior *sor)
133 {
134 struct nvkm_device *device = sor->disp->engine.subdev.device;
135 const u32 soff = nv50_ior_base(sor);
136 u32 div1 = sor->asy.link == 3;
137 u32 div2 = sor->asy.link == 3;
138 if (sor->asy.proto == TMDS) {
139 const u32 speed = sor->tmds.high_speed ? 0x14 : 0x0a;
140 nvkm_mask(device, 0x612300 + soff, 0x007c0000, speed << 18);
141 if (sor->tmds.high_speed)
142 div2 = 1;
143 }
144 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1);
145 }
146
147 void
gf119_sor_state(struct nvkm_ior * sor,struct nvkm_ior_state * state)148 gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
149 {
150 struct nvkm_device *device = sor->disp->engine.subdev.device;
151 const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20;
152 u32 ctrl = nvkm_rd32(device, 0x640200 + coff);
153
154 state->proto_evo = (ctrl & 0x00000f00) >> 8;
155 switch (state->proto_evo) {
156 case 0: state->proto = LVDS; state->link = 1; break;
157 case 1: state->proto = TMDS; state->link = 1; break;
158 case 2: state->proto = TMDS; state->link = 2; break;
159 case 5: state->proto = TMDS; state->link = 3; break;
160 case 8: state->proto = DP; state->link = 1; break;
161 case 9: state->proto = DP; state->link = 2; break;
162 default:
163 state->proto = UNKNOWN;
164 break;
165 }
166
167 state->head = ctrl & 0x0000000f;
168 }
169
170 static const struct nvkm_ior_func
171 gf119_sor = {
172 .state = gf119_sor_state,
173 .power = nv50_sor_power,
174 .clock = gf119_sor_clock,
175 .hdmi = {
176 .ctrl = gf119_hdmi_ctrl,
177 },
178 .dp = {
179 .lanes = { 2, 1, 0, 3 },
180 .links = gf119_sor_dp_links,
181 .power = g94_sor_dp_power,
182 .pattern = gf119_sor_dp_pattern,
183 .drive = gf119_sor_dp_drive,
184 .vcpi = gf119_sor_dp_vcpi,
185 .audio = gf119_sor_dp_audio,
186 .audio_sym = gf119_sor_dp_audio_sym,
187 .watermark = gf119_sor_dp_watermark,
188 },
189 .hda = {
190 .hpd = gf119_hda_hpd,
191 .eld = gf119_hda_eld,
192 .device_entry = gf119_hda_device_entry,
193 },
194 };
195
196 int
gf119_sor_new(struct nvkm_disp * disp,int id)197 gf119_sor_new(struct nvkm_disp *disp, int id)
198 {
199 return nvkm_ior_new_(&gf119_sor, disp, SOR, id);
200 }
201
202 int
gf119_sor_cnt(struct nvkm_disp * disp,unsigned long * pmask)203 gf119_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask)
204 {
205 struct nvkm_device *device = disp->engine.subdev.device;
206 *pmask = (nvkm_rd32(device, 0x612004) & 0x0000ff00) >> 8;
207 return 8;
208 }
209