1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/fpu/xstate.h>
18 #include <asm/intel_ds.h>
19 #include <asm/cpu.h>
20
21 /* To enable MSR tracing please use the generic trace points. */
22
23 /*
24 * | NHM/WSM | SNB |
25 * register -------------------------------
26 * | HT | no HT | HT | no HT |
27 *-----------------------------------------
28 * offcore | core | core | cpu | core |
29 * lbr_sel | core | core | cpu | core |
30 * ld_lat | cpu | core | cpu | core |
31 *-----------------------------------------
32 *
33 * Given that there is a small number of shared regs,
34 * we can pre-allocate their slot in the per-cpu
35 * per-core reg tables.
36 */
37 enum extra_reg_type {
38 EXTRA_REG_NONE = -1, /* not used */
39
40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
42 EXTRA_REG_LBR = 2, /* lbr_select */
43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
44 EXTRA_REG_FE = 4, /* fe_* */
45
46 EXTRA_REG_MAX /* number of entries needed */
47 };
48
49 struct event_constraint {
50 union {
51 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
52 u64 idxmsk64;
53 };
54 u64 code;
55 u64 cmask;
56 int weight;
57 int overlap;
58 int flags;
59 unsigned int size;
60 };
61
constraint_match(struct event_constraint * c,u64 ecode)62 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
63 {
64 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
65 }
66
67 /*
68 * struct hw_perf_event.flags flags
69 */
70 #define PERF_X86_EVENT_PEBS_LDLAT 0x00001 /* ld+ldlat data address sampling */
71 #define PERF_X86_EVENT_PEBS_ST 0x00002 /* st data address sampling */
72 #define PERF_X86_EVENT_PEBS_ST_HSW 0x00004 /* haswell style datala, store */
73 #define PERF_X86_EVENT_PEBS_LD_HSW 0x00008 /* haswell style datala, load */
74 #define PERF_X86_EVENT_PEBS_NA_HSW 0x00010 /* haswell style datala, unknown */
75 #define PERF_X86_EVENT_EXCL 0x00020 /* HT exclusivity on counter */
76 #define PERF_X86_EVENT_DYNAMIC 0x00040 /* dynamic alloc'd constraint */
77
78 #define PERF_X86_EVENT_EXCL_ACCT 0x00100 /* accounted EXCL event */
79 #define PERF_X86_EVENT_AUTO_RELOAD 0x00200 /* use PEBS auto-reload */
80 #define PERF_X86_EVENT_LARGE_PEBS 0x00400 /* use large PEBS */
81 #define PERF_X86_EVENT_PEBS_VIA_PT 0x00800 /* use PT buffer for PEBS */
82 #define PERF_X86_EVENT_PAIR 0x01000 /* Large Increment per Cycle */
83 #define PERF_X86_EVENT_LBR_SELECT 0x02000 /* Save/Restore MSR_LBR_SELECT */
84 #define PERF_X86_EVENT_TOPDOWN 0x04000 /* Count Topdown slots/metrics events */
85 #define PERF_X86_EVENT_PEBS_STLAT 0x08000 /* st+stlat data address sampling */
86 #define PERF_X86_EVENT_AMD_BRS 0x10000 /* AMD Branch Sampling */
87 #define PERF_X86_EVENT_PEBS_LAT_HYBRID 0x20000 /* ld and st lat for hybrid */
88
is_topdown_count(struct perf_event * event)89 static inline bool is_topdown_count(struct perf_event *event)
90 {
91 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
92 }
93
is_metric_event(struct perf_event * event)94 static inline bool is_metric_event(struct perf_event *event)
95 {
96 u64 config = event->attr.config;
97
98 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
99 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
100 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
101 }
102
is_slots_event(struct perf_event * event)103 static inline bool is_slots_event(struct perf_event *event)
104 {
105 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
106 }
107
is_topdown_event(struct perf_event * event)108 static inline bool is_topdown_event(struct perf_event *event)
109 {
110 return is_metric_event(event) || is_slots_event(event);
111 }
112
113 struct amd_nb {
114 int nb_id; /* NorthBridge id */
115 int refcnt; /* reference count */
116 struct perf_event *owners[X86_PMC_IDX_MAX];
117 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
118 };
119
120 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
121 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
122 #define PEBS_OUTPUT_OFFSET 61
123 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
124 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
125 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
126
127 /*
128 * Flags PEBS can handle without an PMI.
129 *
130 * TID can only be handled by flushing at context switch.
131 * REGS_USER can be handled for events limited to ring 3.
132 *
133 */
134 #define LARGE_PEBS_FLAGS \
135 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
136 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
137 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
138 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
139 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
140 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
141
142 #define PEBS_GP_REGS \
143 ((1ULL << PERF_REG_X86_AX) | \
144 (1ULL << PERF_REG_X86_BX) | \
145 (1ULL << PERF_REG_X86_CX) | \
146 (1ULL << PERF_REG_X86_DX) | \
147 (1ULL << PERF_REG_X86_DI) | \
148 (1ULL << PERF_REG_X86_SI) | \
149 (1ULL << PERF_REG_X86_SP) | \
150 (1ULL << PERF_REG_X86_BP) | \
151 (1ULL << PERF_REG_X86_IP) | \
152 (1ULL << PERF_REG_X86_FLAGS) | \
153 (1ULL << PERF_REG_X86_R8) | \
154 (1ULL << PERF_REG_X86_R9) | \
155 (1ULL << PERF_REG_X86_R10) | \
156 (1ULL << PERF_REG_X86_R11) | \
157 (1ULL << PERF_REG_X86_R12) | \
158 (1ULL << PERF_REG_X86_R13) | \
159 (1ULL << PERF_REG_X86_R14) | \
160 (1ULL << PERF_REG_X86_R15))
161
162 /*
163 * Per register state.
164 */
165 struct er_account {
166 raw_spinlock_t lock; /* per-core: protect structure */
167 u64 config; /* extra MSR config */
168 u64 reg; /* extra MSR number */
169 atomic_t ref; /* reference count */
170 };
171
172 /*
173 * Per core/cpu state
174 *
175 * Used to coordinate shared registers between HT threads or
176 * among events on a single PMU.
177 */
178 struct intel_shared_regs {
179 struct er_account regs[EXTRA_REG_MAX];
180 int refcnt; /* per-core: #HT threads */
181 unsigned core_id; /* per-core: core id */
182 };
183
184 enum intel_excl_state_type {
185 INTEL_EXCL_UNUSED = 0, /* counter is unused */
186 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
187 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
188 };
189
190 struct intel_excl_states {
191 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
192 bool sched_started; /* true if scheduling has started */
193 };
194
195 struct intel_excl_cntrs {
196 raw_spinlock_t lock;
197
198 struct intel_excl_states states[2];
199
200 union {
201 u16 has_exclusive[2];
202 u32 exclusive_present;
203 };
204
205 int refcnt; /* per-core: #HT threads */
206 unsigned core_id; /* per-core: core id */
207 };
208
209 struct x86_perf_task_context;
210 #define MAX_LBR_ENTRIES 32
211
212 enum {
213 LBR_FORMAT_32 = 0x00,
214 LBR_FORMAT_LIP = 0x01,
215 LBR_FORMAT_EIP = 0x02,
216 LBR_FORMAT_EIP_FLAGS = 0x03,
217 LBR_FORMAT_EIP_FLAGS2 = 0x04,
218 LBR_FORMAT_INFO = 0x05,
219 LBR_FORMAT_TIME = 0x06,
220 LBR_FORMAT_INFO2 = 0x07,
221 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2,
222 };
223
224 enum {
225 X86_PERF_KFREE_SHARED = 0,
226 X86_PERF_KFREE_EXCL = 1,
227 X86_PERF_KFREE_MAX
228 };
229
230 struct cpu_hw_events {
231 /*
232 * Generic x86 PMC bits
233 */
234 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
235 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
236 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
237 int enabled;
238
239 int n_events; /* the # of events in the below arrays */
240 int n_added; /* the # last events in the below arrays;
241 they've never been enabled yet */
242 int n_txn; /* the # last events in the below arrays;
243 added in the current transaction */
244 int n_txn_pair;
245 int n_txn_metric;
246 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
247 u64 tags[X86_PMC_IDX_MAX];
248
249 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
250 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
251
252 int n_excl; /* the number of exclusive events */
253
254 unsigned int txn_flags;
255 int is_fake;
256
257 /*
258 * Intel DebugStore bits
259 */
260 struct debug_store *ds;
261 void *ds_pebs_vaddr;
262 void *ds_bts_vaddr;
263 u64 pebs_enabled;
264 int n_pebs;
265 int n_large_pebs;
266 int n_pebs_via_pt;
267 int pebs_output;
268
269 /* Current super set of events hardware configuration */
270 u64 pebs_data_cfg;
271 u64 active_pebs_data_cfg;
272 int pebs_record_size;
273
274 /*
275 * Intel LBR bits
276 */
277 int lbr_users;
278 int lbr_pebs_users;
279 struct perf_branch_stack lbr_stack;
280 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
281 union {
282 struct er_account *lbr_sel;
283 struct er_account *lbr_ctl;
284 };
285 u64 br_sel;
286 void *last_task_ctx;
287 int last_log_id;
288 int lbr_select;
289 void *lbr_xsave;
290
291 /*
292 * Intel host/guest exclude bits
293 */
294 u64 intel_ctrl_guest_mask;
295 u64 intel_ctrl_host_mask;
296 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
297
298 /*
299 * Intel checkpoint mask
300 */
301 u64 intel_cp_status;
302
303 /*
304 * manage shared (per-core, per-cpu) registers
305 * used on Intel NHM/WSM/SNB
306 */
307 struct intel_shared_regs *shared_regs;
308 /*
309 * manage exclusive counter access between hyperthread
310 */
311 struct event_constraint *constraint_list; /* in enable order */
312 struct intel_excl_cntrs *excl_cntrs;
313 int excl_thread_id; /* 0 or 1 */
314
315 /*
316 * SKL TSX_FORCE_ABORT shadow
317 */
318 u64 tfa_shadow;
319
320 /*
321 * Perf Metrics
322 */
323 /* number of accepted metrics events */
324 int n_metric;
325
326 /*
327 * AMD specific bits
328 */
329 struct amd_nb *amd_nb;
330 int brs_active; /* BRS is enabled */
331
332 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
333 u64 perf_ctr_virt_mask;
334 int n_pair; /* Large increment events */
335
336 void *kfree_on_online[X86_PERF_KFREE_MAX];
337
338 struct pmu *pmu;
339 };
340
341 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
342 { .idxmsk64 = (n) }, \
343 .code = (c), \
344 .size = (e) - (c), \
345 .cmask = (m), \
346 .weight = (w), \
347 .overlap = (o), \
348 .flags = f, \
349 }
350
351 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
352 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
353
354 #define EVENT_CONSTRAINT(c, n, m) \
355 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
356
357 /*
358 * The constraint_match() function only works for 'simple' event codes
359 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
360 */
361 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
362 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
363
364 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
365 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
366 0, PERF_X86_EVENT_EXCL)
367
368 /*
369 * The overlap flag marks event constraints with overlapping counter
370 * masks. This is the case if the counter mask of such an event is not
371 * a subset of any other counter mask of a constraint with an equal or
372 * higher weight, e.g.:
373 *
374 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
375 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
376 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
377 *
378 * The event scheduler may not select the correct counter in the first
379 * cycle because it needs to know which subsequent events will be
380 * scheduled. It may fail to schedule the events then. So we set the
381 * overlap flag for such constraints to give the scheduler a hint which
382 * events to select for counter rescheduling.
383 *
384 * Care must be taken as the rescheduling algorithm is O(n!) which
385 * will increase scheduling cycles for an over-committed system
386 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
387 * and its counter masks must be kept at a minimum.
388 */
389 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
390 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
391
392 /*
393 * Constraint on the Event code.
394 */
395 #define INTEL_EVENT_CONSTRAINT(c, n) \
396 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
397
398 /*
399 * Constraint on a range of Event codes
400 */
401 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
402 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
403
404 /*
405 * Constraint on the Event code + UMask + fixed-mask
406 *
407 * filter mask to validate fixed counter events.
408 * the following filters disqualify for fixed counters:
409 * - inv
410 * - edge
411 * - cnt-mask
412 * - in_tx
413 * - in_tx_checkpointed
414 * The other filters are supported by fixed counters.
415 * The any-thread option is supported starting with v3.
416 */
417 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
418 #define FIXED_EVENT_CONSTRAINT(c, n) \
419 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
420
421 /*
422 * The special metric counters do not actually exist. They are calculated from
423 * the combination of the FxCtr3 + MSR_PERF_METRICS.
424 *
425 * The special metric counters are mapped to a dummy offset for the scheduler.
426 * The sharing between multiple users of the same metric without multiplexing
427 * is not allowed, even though the hardware supports that in principle.
428 */
429
430 #define METRIC_EVENT_CONSTRAINT(c, n) \
431 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
432 INTEL_ARCH_EVENT_MASK)
433
434 /*
435 * Constraint on the Event code + UMask
436 */
437 #define INTEL_UEVENT_CONSTRAINT(c, n) \
438 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
439
440 /* Constraint on specific umask bit only + event */
441 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
442 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
443
444 /* Like UEVENT_CONSTRAINT, but match flags too */
445 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
446 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
447
448 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
449 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
450 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
451
452 #define INTEL_PLD_CONSTRAINT(c, n) \
453 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
454 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
455
456 #define INTEL_PSD_CONSTRAINT(c, n) \
457 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
458 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
459
460 #define INTEL_PST_CONSTRAINT(c, n) \
461 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
462 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
463
464 #define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \
465 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
466 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID)
467
468 /* Event constraint, but match on all event flags too. */
469 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
470 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
471
472 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
473 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
474
475 /* Check only flags, but allow all event/umask */
476 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
477 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
478
479 /* Check flags and event code, and set the HSW store flag */
480 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
481 __EVENT_CONSTRAINT(code, n, \
482 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
483 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
484
485 /* Check flags and event code, and set the HSW load flag */
486 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
487 __EVENT_CONSTRAINT(code, n, \
488 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
489 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
490
491 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
492 __EVENT_CONSTRAINT_RANGE(code, end, n, \
493 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
494 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
495
496 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
497 __EVENT_CONSTRAINT(code, n, \
498 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
499 HWEIGHT(n), 0, \
500 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
501
502 /* Check flags and event code/umask, and set the HSW store flag */
503 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
504 __EVENT_CONSTRAINT(code, n, \
505 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
506 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
507
508 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
509 __EVENT_CONSTRAINT(code, n, \
510 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
511 HWEIGHT(n), 0, \
512 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
513
514 /* Check flags and event code/umask, and set the HSW load flag */
515 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
516 __EVENT_CONSTRAINT(code, n, \
517 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
518 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
519
520 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
521 __EVENT_CONSTRAINT(code, n, \
522 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
523 HWEIGHT(n), 0, \
524 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
525
526 /* Check flags and event code/umask, and set the HSW N/A flag */
527 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
528 __EVENT_CONSTRAINT(code, n, \
529 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
530 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
531
532
533 /*
534 * We define the end marker as having a weight of -1
535 * to enable blacklisting of events using a counter bitmask
536 * of zero and thus a weight of zero.
537 * The end marker has a weight that cannot possibly be
538 * obtained from counting the bits in the bitmask.
539 */
540 #define EVENT_CONSTRAINT_END { .weight = -1 }
541
542 /*
543 * Check for end marker with weight == -1
544 */
545 #define for_each_event_constraint(e, c) \
546 for ((e) = (c); (e)->weight != -1; (e)++)
547
548 /*
549 * Extra registers for specific events.
550 *
551 * Some events need large masks and require external MSRs.
552 * Those extra MSRs end up being shared for all events on
553 * a PMU and sometimes between PMU of sibling HT threads.
554 * In either case, the kernel needs to handle conflicting
555 * accesses to those extra, shared, regs. The data structure
556 * to manage those registers is stored in cpu_hw_event.
557 */
558 struct extra_reg {
559 unsigned int event;
560 unsigned int msr;
561 u64 config_mask;
562 u64 valid_mask;
563 int idx; /* per_xxx->regs[] reg index */
564 bool extra_msr_access;
565 };
566
567 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
568 .event = (e), \
569 .msr = (ms), \
570 .config_mask = (m), \
571 .valid_mask = (vm), \
572 .idx = EXTRA_REG_##i, \
573 .extra_msr_access = true, \
574 }
575
576 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
577 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
578
579 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
580 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
581 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
582
583 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
584 INTEL_UEVENT_EXTRA_REG(c, \
585 MSR_PEBS_LD_LAT_THRESHOLD, \
586 0xffff, \
587 LDLAT)
588
589 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
590
591 union perf_capabilities {
592 struct {
593 u64 lbr_format:6;
594 u64 pebs_trap:1;
595 u64 pebs_arch_reg:1;
596 u64 pebs_format:4;
597 u64 smm_freeze:1;
598 /*
599 * PMU supports separate counter range for writing
600 * values > 32bit.
601 */
602 u64 full_width_write:1;
603 u64 pebs_baseline:1;
604 u64 perf_metrics:1;
605 u64 pebs_output_pt_available:1;
606 u64 anythread_deprecated:1;
607 };
608 u64 capabilities;
609 };
610
611 struct x86_pmu_quirk {
612 struct x86_pmu_quirk *next;
613 void (*func)(void);
614 };
615
616 union x86_pmu_config {
617 struct {
618 u64 event:8,
619 umask:8,
620 usr:1,
621 os:1,
622 edge:1,
623 pc:1,
624 interrupt:1,
625 __reserved1:1,
626 en:1,
627 inv:1,
628 cmask:8,
629 event2:4,
630 __reserved2:4,
631 go:1,
632 ho:1;
633 } bits;
634 u64 value;
635 };
636
637 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
638
639 enum {
640 x86_lbr_exclusive_lbr,
641 x86_lbr_exclusive_bts,
642 x86_lbr_exclusive_pt,
643 x86_lbr_exclusive_max,
644 };
645
646 #define PERF_PEBS_DATA_SOURCE_MAX 0x10
647
648 struct x86_hybrid_pmu {
649 struct pmu pmu;
650 const char *name;
651 u8 cpu_type;
652 cpumask_t supported_cpus;
653 union perf_capabilities intel_cap;
654 u64 intel_ctrl;
655 int max_pebs_events;
656 int num_counters;
657 int num_counters_fixed;
658 struct event_constraint unconstrained;
659
660 u64 hw_cache_event_ids
661 [PERF_COUNT_HW_CACHE_MAX]
662 [PERF_COUNT_HW_CACHE_OP_MAX]
663 [PERF_COUNT_HW_CACHE_RESULT_MAX];
664 u64 hw_cache_extra_regs
665 [PERF_COUNT_HW_CACHE_MAX]
666 [PERF_COUNT_HW_CACHE_OP_MAX]
667 [PERF_COUNT_HW_CACHE_RESULT_MAX];
668 struct event_constraint *event_constraints;
669 struct event_constraint *pebs_constraints;
670 struct extra_reg *extra_regs;
671
672 unsigned int late_ack :1,
673 mid_ack :1,
674 enabled_ack :1;
675
676 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];
677 };
678
hybrid_pmu(struct pmu * pmu)679 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)
680 {
681 return container_of(pmu, struct x86_hybrid_pmu, pmu);
682 }
683
684 extern struct static_key_false perf_is_hybrid;
685 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid)
686
687 #define hybrid(_pmu, _field) \
688 (*({ \
689 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
690 \
691 if (is_hybrid() && (_pmu)) \
692 __Fp = &hybrid_pmu(_pmu)->_field; \
693 \
694 __Fp; \
695 }))
696
697 #define hybrid_var(_pmu, _var) \
698 (*({ \
699 typeof(&_var) __Fp = &_var; \
700 \
701 if (is_hybrid() && (_pmu)) \
702 __Fp = &hybrid_pmu(_pmu)->_var; \
703 \
704 __Fp; \
705 }))
706
707 #define hybrid_bit(_pmu, _field) \
708 ({ \
709 bool __Fp = x86_pmu._field; \
710 \
711 if (is_hybrid() && (_pmu)) \
712 __Fp = hybrid_pmu(_pmu)->_field; \
713 \
714 __Fp; \
715 })
716
717 enum hybrid_pmu_type {
718 hybrid_big = 0x40,
719 hybrid_small = 0x20,
720
721 hybrid_big_small = hybrid_big | hybrid_small,
722 };
723
724 #define X86_HYBRID_PMU_ATOM_IDX 0
725 #define X86_HYBRID_PMU_CORE_IDX 1
726
727 #define X86_HYBRID_NUM_PMUS 2
728
729 /*
730 * struct x86_pmu - generic x86 pmu
731 */
732 struct x86_pmu {
733 /*
734 * Generic x86 PMC bits
735 */
736 const char *name;
737 int version;
738 int (*handle_irq)(struct pt_regs *);
739 void (*disable_all)(void);
740 void (*enable_all)(int added);
741 void (*enable)(struct perf_event *);
742 void (*disable)(struct perf_event *);
743 void (*assign)(struct perf_event *event, int idx);
744 void (*add)(struct perf_event *);
745 void (*del)(struct perf_event *);
746 void (*read)(struct perf_event *event);
747 int (*hw_config)(struct perf_event *event);
748 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
749 unsigned eventsel;
750 unsigned perfctr;
751 int (*addr_offset)(int index, bool eventsel);
752 int (*rdpmc_index)(int index);
753 u64 (*event_map)(int);
754 int max_events;
755 int num_counters;
756 int num_counters_fixed;
757 int cntval_bits;
758 u64 cntval_mask;
759 union {
760 unsigned long events_maskl;
761 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
762 };
763 int events_mask_len;
764 int apic;
765 u64 max_period;
766 struct event_constraint *
767 (*get_event_constraints)(struct cpu_hw_events *cpuc,
768 int idx,
769 struct perf_event *event);
770
771 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
772 struct perf_event *event);
773
774 void (*start_scheduling)(struct cpu_hw_events *cpuc);
775
776 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
777
778 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
779
780 struct event_constraint *event_constraints;
781 struct x86_pmu_quirk *quirks;
782 int perfctr_second_write;
783 u64 (*limit_period)(struct perf_event *event, u64 l);
784
785 /* PMI handler bits */
786 unsigned int late_ack :1,
787 mid_ack :1,
788 enabled_ack :1;
789 /*
790 * sysfs attrs
791 */
792 int attr_rdpmc_broken;
793 int attr_rdpmc;
794 struct attribute **format_attrs;
795
796 ssize_t (*events_sysfs_show)(char *page, u64 config);
797 const struct attribute_group **attr_update;
798
799 unsigned long attr_freeze_on_smi;
800
801 /*
802 * CPU Hotplug hooks
803 */
804 int (*cpu_prepare)(int cpu);
805 void (*cpu_starting)(int cpu);
806 void (*cpu_dying)(int cpu);
807 void (*cpu_dead)(int cpu);
808
809 void (*check_microcode)(void);
810 void (*sched_task)(struct perf_event_context *ctx,
811 bool sched_in);
812
813 /*
814 * Intel Arch Perfmon v2+
815 */
816 u64 intel_ctrl;
817 union perf_capabilities intel_cap;
818
819 /*
820 * Intel DebugStore bits
821 */
822 unsigned int bts :1,
823 bts_active :1,
824 pebs :1,
825 pebs_active :1,
826 pebs_broken :1,
827 pebs_prec_dist :1,
828 pebs_no_tlb :1,
829 pebs_no_isolation :1,
830 pebs_block :1;
831 int pebs_record_size;
832 int pebs_buffer_size;
833 int max_pebs_events;
834 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
835 struct event_constraint *pebs_constraints;
836 void (*pebs_aliases)(struct perf_event *event);
837 u64 (*pebs_latency_data)(struct perf_event *event, u64 status);
838 unsigned long large_pebs_flags;
839 u64 rtm_abort_event;
840
841 /*
842 * Intel LBR
843 */
844 unsigned int lbr_tos, lbr_from, lbr_to,
845 lbr_info, lbr_nr; /* LBR base regs and size */
846 union {
847 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
848 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
849 };
850 union {
851 const int *lbr_sel_map; /* lbr_select mappings */
852 int *lbr_ctl_map; /* LBR_CTL mappings */
853 };
854 bool lbr_double_abort; /* duplicated lbr aborts */
855 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
856
857 unsigned int lbr_has_info:1;
858 unsigned int lbr_has_tsx:1;
859 unsigned int lbr_from_flags:1;
860 unsigned int lbr_to_cycles:1;
861
862 /*
863 * Intel Architectural LBR CPUID Enumeration
864 */
865 unsigned int lbr_depth_mask:8;
866 unsigned int lbr_deep_c_reset:1;
867 unsigned int lbr_lip:1;
868 unsigned int lbr_cpl:1;
869 unsigned int lbr_filter:1;
870 unsigned int lbr_call_stack:1;
871 unsigned int lbr_mispred:1;
872 unsigned int lbr_timed_lbr:1;
873 unsigned int lbr_br_type:1;
874
875 void (*lbr_reset)(void);
876 void (*lbr_read)(struct cpu_hw_events *cpuc);
877 void (*lbr_save)(void *ctx);
878 void (*lbr_restore)(void *ctx);
879
880 /*
881 * Intel PT/LBR/BTS are exclusive
882 */
883 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
884
885 /*
886 * Intel perf metrics
887 */
888 int num_topdown_events;
889 u64 (*update_topdown_event)(struct perf_event *event);
890 int (*set_topdown_event_period)(struct perf_event *event);
891
892 /*
893 * perf task context (i.e. struct perf_event_context::task_ctx_data)
894 * switch helper to bridge calls from perf/core to perf/x86.
895 * See struct pmu::swap_task_ctx() usage for examples;
896 */
897 void (*swap_task_ctx)(struct perf_event_context *prev,
898 struct perf_event_context *next);
899
900 /*
901 * AMD bits
902 */
903 unsigned int amd_nb_constraints : 1;
904 u64 perf_ctr_pair_en;
905
906 /*
907 * Extra registers for events
908 */
909 struct extra_reg *extra_regs;
910 unsigned int flags;
911
912 /*
913 * Intel host/guest support (KVM)
914 */
915 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
916
917 /*
918 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
919 */
920 int (*check_period) (struct perf_event *event, u64 period);
921
922 int (*aux_output_match) (struct perf_event *event);
923
924 int (*filter_match)(struct perf_event *event);
925 /*
926 * Hybrid support
927 *
928 * Most PMU capabilities are the same among different hybrid PMUs.
929 * The global x86_pmu saves the architecture capabilities, which
930 * are available for all PMUs. The hybrid_pmu only includes the
931 * unique capabilities.
932 */
933 int num_hybrid_pmus;
934 struct x86_hybrid_pmu *hybrid_pmu;
935 u8 (*get_hybrid_cpu_type) (void);
936 };
937
938 struct x86_perf_task_context_opt {
939 int lbr_callstack_users;
940 int lbr_stack_state;
941 int log_id;
942 };
943
944 struct x86_perf_task_context {
945 u64 lbr_sel;
946 int tos;
947 int valid_lbrs;
948 struct x86_perf_task_context_opt opt;
949 struct lbr_entry lbr[MAX_LBR_ENTRIES];
950 };
951
952 struct x86_perf_task_context_arch_lbr {
953 struct x86_perf_task_context_opt opt;
954 struct lbr_entry entries[];
955 };
956
957 /*
958 * Add padding to guarantee the 64-byte alignment of the state buffer.
959 *
960 * The structure is dynamically allocated. The size of the LBR state may vary
961 * based on the number of LBR registers.
962 *
963 * Do not put anything after the LBR state.
964 */
965 struct x86_perf_task_context_arch_lbr_xsave {
966 struct x86_perf_task_context_opt opt;
967
968 union {
969 struct xregs_state xsave;
970 struct {
971 struct fxregs_state i387;
972 struct xstate_header header;
973 struct arch_lbr_state lbr;
974 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
975 };
976 };
977
978 #define x86_add_quirk(func_) \
979 do { \
980 static struct x86_pmu_quirk __quirk __initdata = { \
981 .func = func_, \
982 }; \
983 __quirk.next = x86_pmu.quirks; \
984 x86_pmu.quirks = &__quirk; \
985 } while (0)
986
987 /*
988 * x86_pmu flags
989 */
990 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
991 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
992 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
993 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
994 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
995 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
996 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
997 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
998 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
999
1000 #define EVENT_VAR(_id) event_attr_##_id
1001 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
1002
1003 #define EVENT_ATTR(_name, _id) \
1004 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
1005 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1006 .id = PERF_COUNT_HW_##_id, \
1007 .event_str = NULL, \
1008 };
1009
1010 #define EVENT_ATTR_STR(_name, v, str) \
1011 static struct perf_pmu_events_attr event_attr_##v = { \
1012 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1013 .id = 0, \
1014 .event_str = str, \
1015 };
1016
1017 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
1018 static struct perf_pmu_events_ht_attr event_attr_##v = { \
1019 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
1020 .id = 0, \
1021 .event_str_noht = noht, \
1022 .event_str_ht = ht, \
1023 }
1024
1025 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \
1026 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \
1027 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\
1028 .id = 0, \
1029 .event_str = str, \
1030 .pmu_type = _pmu, \
1031 }
1032
1033 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr)
1034
1035 #define FORMAT_ATTR_HYBRID(_name, _pmu) \
1036 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
1037 .attr = __ATTR_RO(_name), \
1038 .pmu_type = _pmu, \
1039 }
1040
1041 struct pmu *x86_get_pmu(unsigned int cpu);
1042 extern struct x86_pmu x86_pmu __read_mostly;
1043
task_context_opt(void * ctx)1044 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
1045 {
1046 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
1047 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
1048
1049 return &((struct x86_perf_task_context *)ctx)->opt;
1050 }
1051
x86_pmu_has_lbr_callstack(void)1052 static inline bool x86_pmu_has_lbr_callstack(void)
1053 {
1054 return x86_pmu.lbr_sel_map &&
1055 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
1056 }
1057
1058 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
1059
1060 int x86_perf_event_set_period(struct perf_event *event);
1061
1062 /*
1063 * Generalized hw caching related hw_event table, filled
1064 * in on a per model basis. A value of 0 means
1065 * 'not supported', -1 means 'hw_event makes no sense on
1066 * this CPU', any other value means the raw hw_event
1067 * ID.
1068 */
1069
1070 #define C(x) PERF_COUNT_HW_CACHE_##x
1071
1072 extern u64 __read_mostly hw_cache_event_ids
1073 [PERF_COUNT_HW_CACHE_MAX]
1074 [PERF_COUNT_HW_CACHE_OP_MAX]
1075 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1076 extern u64 __read_mostly hw_cache_extra_regs
1077 [PERF_COUNT_HW_CACHE_MAX]
1078 [PERF_COUNT_HW_CACHE_OP_MAX]
1079 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1080
1081 u64 x86_perf_event_update(struct perf_event *event);
1082
x86_pmu_config_addr(int index)1083 static inline unsigned int x86_pmu_config_addr(int index)
1084 {
1085 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
1086 x86_pmu.addr_offset(index, true) : index);
1087 }
1088
x86_pmu_event_addr(int index)1089 static inline unsigned int x86_pmu_event_addr(int index)
1090 {
1091 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
1092 x86_pmu.addr_offset(index, false) : index);
1093 }
1094
x86_pmu_rdpmc_index(int index)1095 static inline int x86_pmu_rdpmc_index(int index)
1096 {
1097 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
1098 }
1099
1100 bool check_hw_exists(struct pmu *pmu, int num_counters,
1101 int num_counters_fixed);
1102
1103 int x86_add_exclusive(unsigned int what);
1104
1105 void x86_del_exclusive(unsigned int what);
1106
1107 int x86_reserve_hardware(void);
1108
1109 void x86_release_hardware(void);
1110
1111 int x86_pmu_max_precise(void);
1112
1113 void hw_perf_lbr_event_destroy(struct perf_event *event);
1114
1115 int x86_setup_perfctr(struct perf_event *event);
1116
1117 int x86_pmu_hw_config(struct perf_event *event);
1118
1119 void x86_pmu_disable_all(void);
1120
has_amd_brs(struct hw_perf_event * hwc)1121 static inline bool has_amd_brs(struct hw_perf_event *hwc)
1122 {
1123 return hwc->flags & PERF_X86_EVENT_AMD_BRS;
1124 }
1125
is_counter_pair(struct hw_perf_event * hwc)1126 static inline bool is_counter_pair(struct hw_perf_event *hwc)
1127 {
1128 return hwc->flags & PERF_X86_EVENT_PAIR;
1129 }
1130
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)1131 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
1132 u64 enable_mask)
1133 {
1134 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1135
1136 if (hwc->extra_reg.reg)
1137 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
1138
1139 /*
1140 * Add enabled Merge event on next counter
1141 * if large increment event being enabled on this counter
1142 */
1143 if (is_counter_pair(hwc))
1144 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1145
1146 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1147 }
1148
1149 void x86_pmu_enable_all(int added);
1150
1151 int perf_assign_events(struct event_constraint **constraints, int n,
1152 int wmin, int wmax, int gpmax, int *assign);
1153 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1154
1155 void x86_pmu_stop(struct perf_event *event, int flags);
1156
x86_pmu_disable_event(struct perf_event * event)1157 static inline void x86_pmu_disable_event(struct perf_event *event)
1158 {
1159 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1160 struct hw_perf_event *hwc = &event->hw;
1161
1162 wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
1163
1164 if (is_counter_pair(hwc))
1165 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
1166 }
1167
1168 void x86_pmu_enable_event(struct perf_event *event);
1169
1170 int x86_pmu_handle_irq(struct pt_regs *regs);
1171
1172 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
1173 u64 intel_ctrl);
1174
1175 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu);
1176
1177 extern struct event_constraint emptyconstraint;
1178
1179 extern struct event_constraint unconstrained;
1180
kernel_ip(unsigned long ip)1181 static inline bool kernel_ip(unsigned long ip)
1182 {
1183 #ifdef CONFIG_X86_32
1184 return ip > PAGE_OFFSET;
1185 #else
1186 return (long)ip < 0;
1187 #endif
1188 }
1189
1190 /*
1191 * Not all PMUs provide the right context information to place the reported IP
1192 * into full context. Specifically segment registers are typically not
1193 * supplied.
1194 *
1195 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1196 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1197 * to reflect this.
1198 *
1199 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1200 * much we can do about that but pray and treat it like a linear address.
1201 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)1202 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1203 {
1204 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1205 if (regs->flags & X86_VM_MASK)
1206 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1207 regs->ip = ip;
1208 }
1209
1210 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1211 ssize_t intel_event_sysfs_show(char *page, u64 config);
1212
1213 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1214 char *page);
1215 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1216 char *page);
1217 ssize_t events_hybrid_sysfs_show(struct device *dev,
1218 struct device_attribute *attr,
1219 char *page);
1220
fixed_counter_disabled(int i,struct pmu * pmu)1221 static inline bool fixed_counter_disabled(int i, struct pmu *pmu)
1222 {
1223 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
1224
1225 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));
1226 }
1227
1228 #ifdef CONFIG_CPU_SUP_AMD
1229
1230 int amd_pmu_init(void);
1231
1232 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1233 int amd_brs_init(void);
1234 void amd_brs_disable(void);
1235 void amd_brs_enable(void);
1236 void amd_brs_enable_all(void);
1237 void amd_brs_disable_all(void);
1238 void amd_brs_drain(void);
1239 void amd_brs_lopwr_init(void);
1240 void amd_brs_disable_all(void);
1241 int amd_brs_setup_filter(struct perf_event *event);
1242 void amd_brs_reset(void);
1243
amd_pmu_brs_add(struct perf_event * event)1244 static inline void amd_pmu_brs_add(struct perf_event *event)
1245 {
1246 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1247
1248 perf_sched_cb_inc(event->ctx->pmu);
1249 cpuc->lbr_users++;
1250 /*
1251 * No need to reset BRS because it is reset
1252 * on brs_enable() and it is saturating
1253 */
1254 }
1255
amd_pmu_brs_del(struct perf_event * event)1256 static inline void amd_pmu_brs_del(struct perf_event *event)
1257 {
1258 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1259
1260 cpuc->lbr_users--;
1261 WARN_ON_ONCE(cpuc->lbr_users < 0);
1262
1263 perf_sched_cb_dec(event->ctx->pmu);
1264 }
1265
1266 void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in);
1267 #else
amd_brs_init(void)1268 static inline int amd_brs_init(void)
1269 {
1270 return 0;
1271 }
amd_brs_disable(void)1272 static inline void amd_brs_disable(void) {}
amd_brs_enable(void)1273 static inline void amd_brs_enable(void) {}
amd_brs_drain(void)1274 static inline void amd_brs_drain(void) {}
amd_brs_lopwr_init(void)1275 static inline void amd_brs_lopwr_init(void) {}
amd_brs_disable_all(void)1276 static inline void amd_brs_disable_all(void) {}
amd_brs_setup_filter(struct perf_event * event)1277 static inline int amd_brs_setup_filter(struct perf_event *event)
1278 {
1279 return 0;
1280 }
amd_brs_reset(void)1281 static inline void amd_brs_reset(void) {}
1282
amd_pmu_brs_add(struct perf_event * event)1283 static inline void amd_pmu_brs_add(struct perf_event *event)
1284 {
1285 }
1286
amd_pmu_brs_del(struct perf_event * event)1287 static inline void amd_pmu_brs_del(struct perf_event *event)
1288 {
1289 }
1290
amd_pmu_brs_sched_task(struct perf_event_context * ctx,bool sched_in)1291 static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in)
1292 {
1293 }
1294
amd_brs_enable_all(void)1295 static inline void amd_brs_enable_all(void)
1296 {
1297 }
1298
1299 #endif
1300
1301 #else /* CONFIG_CPU_SUP_AMD */
1302
amd_pmu_init(void)1303 static inline int amd_pmu_init(void)
1304 {
1305 return 0;
1306 }
1307
amd_brs_init(void)1308 static inline int amd_brs_init(void)
1309 {
1310 return -EOPNOTSUPP;
1311 }
1312
amd_brs_drain(void)1313 static inline void amd_brs_drain(void)
1314 {
1315 }
1316
amd_brs_enable_all(void)1317 static inline void amd_brs_enable_all(void)
1318 {
1319 }
1320
amd_brs_disable_all(void)1321 static inline void amd_brs_disable_all(void)
1322 {
1323 }
1324 #endif /* CONFIG_CPU_SUP_AMD */
1325
is_pebs_pt(struct perf_event * event)1326 static inline int is_pebs_pt(struct perf_event *event)
1327 {
1328 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1329 }
1330
1331 #ifdef CONFIG_CPU_SUP_INTEL
1332
intel_pmu_has_bts_period(struct perf_event * event,u64 period)1333 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1334 {
1335 struct hw_perf_event *hwc = &event->hw;
1336 unsigned int hw_event, bts_event;
1337
1338 if (event->attr.freq)
1339 return false;
1340
1341 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1342 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1343
1344 return hw_event == bts_event && period == 1;
1345 }
1346
intel_pmu_has_bts(struct perf_event * event)1347 static inline bool intel_pmu_has_bts(struct perf_event *event)
1348 {
1349 struct hw_perf_event *hwc = &event->hw;
1350
1351 return intel_pmu_has_bts_period(event, hwc->sample_period);
1352 }
1353
__intel_pmu_pebs_disable_all(void)1354 static __always_inline void __intel_pmu_pebs_disable_all(void)
1355 {
1356 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1357 }
1358
__intel_pmu_arch_lbr_disable(void)1359 static __always_inline void __intel_pmu_arch_lbr_disable(void)
1360 {
1361 wrmsrl(MSR_ARCH_LBR_CTL, 0);
1362 }
1363
__intel_pmu_lbr_disable(void)1364 static __always_inline void __intel_pmu_lbr_disable(void)
1365 {
1366 u64 debugctl;
1367
1368 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1369 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1370 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1371 }
1372
1373 int intel_pmu_save_and_restart(struct perf_event *event);
1374
1375 struct event_constraint *
1376 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1377 struct perf_event *event);
1378
1379 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1380 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1381
1382 int intel_pmu_init(void);
1383
1384 void init_debug_store_on_cpu(int cpu);
1385
1386 void fini_debug_store_on_cpu(int cpu);
1387
1388 void release_ds_buffers(void);
1389
1390 void reserve_ds_buffers(void);
1391
1392 void release_lbr_buffers(void);
1393
1394 void reserve_lbr_buffers(void);
1395
1396 extern struct event_constraint bts_constraint;
1397 extern struct event_constraint vlbr_constraint;
1398
1399 void intel_pmu_enable_bts(u64 config);
1400
1401 void intel_pmu_disable_bts(void);
1402
1403 int intel_pmu_drain_bts_buffer(void);
1404
1405 u64 adl_latency_data_small(struct perf_event *event, u64 status);
1406
1407 extern struct event_constraint intel_core2_pebs_event_constraints[];
1408
1409 extern struct event_constraint intel_atom_pebs_event_constraints[];
1410
1411 extern struct event_constraint intel_slm_pebs_event_constraints[];
1412
1413 extern struct event_constraint intel_glm_pebs_event_constraints[];
1414
1415 extern struct event_constraint intel_glp_pebs_event_constraints[];
1416
1417 extern struct event_constraint intel_grt_pebs_event_constraints[];
1418
1419 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1420
1421 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1422
1423 extern struct event_constraint intel_snb_pebs_event_constraints[];
1424
1425 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1426
1427 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1428
1429 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1430
1431 extern struct event_constraint intel_skl_pebs_event_constraints[];
1432
1433 extern struct event_constraint intel_icl_pebs_event_constraints[];
1434
1435 extern struct event_constraint intel_spr_pebs_event_constraints[];
1436
1437 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1438
1439 void intel_pmu_pebs_add(struct perf_event *event);
1440
1441 void intel_pmu_pebs_del(struct perf_event *event);
1442
1443 void intel_pmu_pebs_enable(struct perf_event *event);
1444
1445 void intel_pmu_pebs_disable(struct perf_event *event);
1446
1447 void intel_pmu_pebs_enable_all(void);
1448
1449 void intel_pmu_pebs_disable_all(void);
1450
1451 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1452
1453 void intel_pmu_auto_reload_read(struct perf_event *event);
1454
1455 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1456
1457 void intel_ds_init(void);
1458
1459 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
1460 struct perf_event_context *next);
1461
1462 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1463
1464 u64 lbr_from_signext_quirk_wr(u64 val);
1465
1466 void intel_pmu_lbr_reset(void);
1467
1468 void intel_pmu_lbr_reset_32(void);
1469
1470 void intel_pmu_lbr_reset_64(void);
1471
1472 void intel_pmu_lbr_add(struct perf_event *event);
1473
1474 void intel_pmu_lbr_del(struct perf_event *event);
1475
1476 void intel_pmu_lbr_enable_all(bool pmi);
1477
1478 void intel_pmu_lbr_disable_all(void);
1479
1480 void intel_pmu_lbr_read(void);
1481
1482 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1483
1484 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1485
1486 void intel_pmu_lbr_save(void *ctx);
1487
1488 void intel_pmu_lbr_restore(void *ctx);
1489
1490 void intel_pmu_lbr_init_core(void);
1491
1492 void intel_pmu_lbr_init_nhm(void);
1493
1494 void intel_pmu_lbr_init_atom(void);
1495
1496 void intel_pmu_lbr_init_slm(void);
1497
1498 void intel_pmu_lbr_init_snb(void);
1499
1500 void intel_pmu_lbr_init_hsw(void);
1501
1502 void intel_pmu_lbr_init_skl(void);
1503
1504 void intel_pmu_lbr_init_knl(void);
1505
1506 void intel_pmu_lbr_init(void);
1507
1508 void intel_pmu_arch_lbr_init(void);
1509
1510 void intel_pmu_pebs_data_source_nhm(void);
1511
1512 void intel_pmu_pebs_data_source_skl(bool pmem);
1513
1514 void intel_pmu_pebs_data_source_adl(void);
1515
1516 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1517
1518 void intel_pt_interrupt(void);
1519
1520 int intel_bts_interrupt(void);
1521
1522 void intel_bts_enable_local(void);
1523
1524 void intel_bts_disable_local(void);
1525
1526 int p4_pmu_init(void);
1527
1528 int p6_pmu_init(void);
1529
1530 int knc_pmu_init(void);
1531
is_ht_workaround_enabled(void)1532 static inline int is_ht_workaround_enabled(void)
1533 {
1534 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1535 }
1536
1537 #else /* CONFIG_CPU_SUP_INTEL */
1538
reserve_ds_buffers(void)1539 static inline void reserve_ds_buffers(void)
1540 {
1541 }
1542
release_ds_buffers(void)1543 static inline void release_ds_buffers(void)
1544 {
1545 }
1546
release_lbr_buffers(void)1547 static inline void release_lbr_buffers(void)
1548 {
1549 }
1550
reserve_lbr_buffers(void)1551 static inline void reserve_lbr_buffers(void)
1552 {
1553 }
1554
intel_pmu_init(void)1555 static inline int intel_pmu_init(void)
1556 {
1557 return 0;
1558 }
1559
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)1560 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1561 {
1562 return 0;
1563 }
1564
intel_cpuc_finish(struct cpu_hw_events * cpuc)1565 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1566 {
1567 }
1568
is_ht_workaround_enabled(void)1569 static inline int is_ht_workaround_enabled(void)
1570 {
1571 return 0;
1572 }
1573 #endif /* CONFIG_CPU_SUP_INTEL */
1574
1575 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1576 int zhaoxin_pmu_init(void);
1577 #else
zhaoxin_pmu_init(void)1578 static inline int zhaoxin_pmu_init(void)
1579 {
1580 return 0;
1581 }
1582 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/
1583