1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #ifndef _DPU_HW_CTL_H
7 #define _DPU_HW_CTL_H
8
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_util.h"
11 #include "dpu_hw_catalog.h"
12 #include "dpu_hw_sspp.h"
13 #include "dpu_hw_blk.h"
14
15 /**
16 * dpu_ctl_mode_sel: Interface mode selection
17 * DPU_CTL_MODE_SEL_VID: Video mode interface
18 * DPU_CTL_MODE_SEL_CMD: Command mode interface
19 */
20 enum dpu_ctl_mode_sel {
21 DPU_CTL_MODE_SEL_VID = 0,
22 DPU_CTL_MODE_SEL_CMD
23 };
24
25 struct dpu_hw_ctl;
26 /**
27 * struct dpu_hw_stage_cfg - blending stage cfg
28 * @stage : SSPP_ID at each stage
29 * @multirect_index: index of the rectangle of SSPP.
30 */
31 struct dpu_hw_stage_cfg {
32 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
33 enum dpu_sspp_multirect_index multirect_index
34 [DPU_STAGE_MAX][PIPES_PER_STAGE];
35 };
36
37 /**
38 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
39 * @intf : Interface id
40 * @mode_3d: 3d mux configuration
41 * @merge_3d: 3d merge block used
42 * @intf_mode_sel: Interface mode, cmd / vid
43 * @stream_sel: Stream selection for multi-stream interfaces
44 * @dsc: DSC BIT masks used
45 */
46 struct dpu_hw_intf_cfg {
47 enum dpu_intf intf;
48 enum dpu_wb wb;
49 enum dpu_3d_blend_mode mode_3d;
50 enum dpu_merge_3d merge_3d;
51 enum dpu_ctl_mode_sel intf_mode_sel;
52 int stream_sel;
53 unsigned int dsc;
54 };
55
56 /**
57 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
58 * Assumption is these functions will be called after clocks are enabled
59 */
60 struct dpu_hw_ctl_ops {
61 /**
62 * kickoff hw operation for Sw controlled interfaces
63 * DSI cmd mode and WB interface are SW controlled
64 * @ctx : ctl path ctx pointer
65 */
66 void (*trigger_start)(struct dpu_hw_ctl *ctx);
67
68 /**
69 * check if the ctl is started
70 * @ctx : ctl path ctx pointer
71 * @Return: true if started, false if stopped
72 */
73 bool (*is_started)(struct dpu_hw_ctl *ctx);
74
75 /**
76 * kickoff prepare is in progress hw operation for sw
77 * controlled interfaces: DSI cmd mode and WB interface
78 * are SW controlled
79 * @ctx : ctl path ctx pointer
80 */
81 void (*trigger_pending)(struct dpu_hw_ctl *ctx);
82
83 /**
84 * Clear the value of the cached pending_flush_mask
85 * No effect on hardware
86 * @ctx : ctl path ctx pointer
87 */
88 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
89
90 /**
91 * Query the value of the cached pending_flush_mask
92 * No effect on hardware
93 * @ctx : ctl path ctx pointer
94 */
95 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
96
97 /**
98 * OR in the given flushbits to the cached pending_flush_mask
99 * No effect on hardware
100 * @ctx : ctl path ctx pointer
101 * @flushbits : module flushmask
102 */
103 void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
104 u32 flushbits);
105
106 /**
107 * OR in the given flushbits to the cached pending_(wb_)flush_mask
108 * No effect on hardware
109 * @ctx : ctl path ctx pointer
110 * @blk : writeback block index
111 */
112 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx,
113 enum dpu_wb blk);
114
115 /**
116 * OR in the given flushbits to the cached pending_(intf_)flush_mask
117 * No effect on hardware
118 * @ctx : ctl path ctx pointer
119 * @blk : interface block index
120 */
121 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
122 enum dpu_intf blk);
123
124 /**
125 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
126 * No effect on hardware
127 * @ctx : ctl path ctx pointer
128 * @blk : interface block index
129 */
130 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
131 enum dpu_merge_3d blk);
132
133 /**
134 * Write the value of the pending_flush_mask to hardware
135 * @ctx : ctl path ctx pointer
136 */
137 void (*trigger_flush)(struct dpu_hw_ctl *ctx);
138
139 /**
140 * Read the value of the flush register
141 * @ctx : ctl path ctx pointer
142 * @Return: value of the ctl flush register.
143 */
144 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
145
146 /**
147 * Setup ctl_path interface config
148 * @ctx
149 * @cfg : interface config structure pointer
150 */
151 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
152 struct dpu_hw_intf_cfg *cfg);
153
154 /**
155 * reset ctl_path interface config
156 * @ctx : ctl path ctx pointer
157 * @cfg : interface config structure pointer
158 */
159 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
160 struct dpu_hw_intf_cfg *cfg);
161
162 int (*reset)(struct dpu_hw_ctl *c);
163
164 /*
165 * wait_reset_status - checks ctl reset status
166 * @ctx : ctl path ctx pointer
167 *
168 * This function checks the ctl reset status bit.
169 * If the reset bit is set, it keeps polling the status till the hw
170 * reset is complete.
171 * Returns: 0 on success or -error if reset incomplete within interval
172 */
173 int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
174
175 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx,
176 enum dpu_sspp blk);
177
178 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
179 enum dpu_lm blk);
180
181 uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx,
182 enum dpu_dspp blk);
183
184 /**
185 * Set all blend stages to disabled
186 * @ctx : ctl path ctx pointer
187 */
188 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
189
190 /**
191 * Configure layer mixer to pipe configuration
192 * @ctx : ctl path ctx pointer
193 * @lm : layer mixer enumeration
194 * @cfg : blend stage configuration
195 */
196 void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
197 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
198
199 void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
200 unsigned long *fetch_active);
201 };
202
203 /**
204 * struct dpu_hw_ctl : CTL PATH driver object
205 * @base: hardware block base structure
206 * @hw: block register map object
207 * @idx: control path index
208 * @caps: control path capabilities
209 * @mixer_count: number of mixers
210 * @mixer_hw_caps: mixer hardware capabilities
211 * @pending_flush_mask: storage for pending ctl_flush managed via ops
212 * @pending_intf_flush_mask: pending INTF flush
213 * @pending_wb_flush_mask: pending WB flush
214 * @ops: operation list
215 */
216 struct dpu_hw_ctl {
217 struct dpu_hw_blk base;
218 struct dpu_hw_blk_reg_map hw;
219
220 /* ctl path */
221 int idx;
222 const struct dpu_ctl_cfg *caps;
223 int mixer_count;
224 const struct dpu_lm_cfg *mixer_hw_caps;
225 u32 pending_flush_mask;
226 u32 pending_intf_flush_mask;
227 u32 pending_wb_flush_mask;
228 u32 pending_merge_3d_flush_mask;
229
230 /* ops */
231 struct dpu_hw_ctl_ops ops;
232 };
233
234 /**
235 * dpu_hw_ctl - convert base object dpu_hw_base to container
236 * @hw: Pointer to base hardware block
237 * return: Pointer to hardware block container
238 */
to_dpu_hw_ctl(struct dpu_hw_blk * hw)239 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
240 {
241 return container_of(hw, struct dpu_hw_ctl, base);
242 }
243
244 /**
245 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object.
246 * should be called before accessing every ctl path registers.
247 * @idx: ctl_path index for which driver object is required
248 * @addr: mapped register io address of MDP
249 * @m : pointer to mdss catalog data
250 */
251 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
252 void __iomem *addr,
253 const struct dpu_mdss_cfg *m);
254
255 /**
256 * dpu_hw_ctl_destroy(): Destroys ctl driver context
257 * should be called to free the context
258 */
259 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);
260
261 #endif /*_DPU_HW_CTL_H */
262