1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #include <linux/sched/clock.h>
7 
8 #include "i915_drv.h"
9 #include "i915_irq.h"
10 #include "intel_breadcrumbs.h"
11 #include "intel_gt.h"
12 #include "intel_gt_irq.h"
13 #include "intel_gt_regs.h"
14 #include "intel_uncore.h"
15 #include "intel_rps.h"
16 #include "pxp/intel_pxp_irq.h"
17 
guc_irq_handler(struct intel_guc * guc,u16 iir)18 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
19 {
20 	if (iir & GUC_INTR_GUC2HOST)
21 		intel_guc_to_host_event_handler(guc);
22 }
23 
24 static u32
gen11_gt_engine_identity(struct intel_gt * gt,const unsigned int bank,const unsigned int bit)25 gen11_gt_engine_identity(struct intel_gt *gt,
26 			 const unsigned int bank, const unsigned int bit)
27 {
28 	void __iomem * const regs = gt->uncore->regs;
29 	u32 timeout_ts;
30 	u32 ident;
31 
32 	lockdep_assert_held(gt->irq_lock);
33 
34 	raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
35 
36 	/*
37 	 * NB: Specs do not specify how long to spin wait,
38 	 * so we do ~100us as an educated guess.
39 	 */
40 	timeout_ts = (local_clock() >> 10) + 100;
41 	do {
42 		ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
43 	} while (!(ident & GEN11_INTR_DATA_VALID) &&
44 		 !time_after32(local_clock() >> 10, timeout_ts));
45 
46 	if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
47 		DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
48 			  bank, bit, ident);
49 		return 0;
50 	}
51 
52 	raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
53 		      GEN11_INTR_DATA_VALID);
54 
55 	return ident;
56 }
57 
58 static void
gen11_other_irq_handler(struct intel_gt * gt,const u8 instance,const u16 iir)59 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
60 			const u16 iir)
61 {
62 	struct intel_gt *media_gt = gt->i915->media_gt;
63 
64 	if (instance == OTHER_GUC_INSTANCE)
65 		return guc_irq_handler(&gt->uc.guc, iir);
66 	if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
67 		return guc_irq_handler(&media_gt->uc.guc, iir);
68 
69 	if (instance == OTHER_GTPM_INSTANCE)
70 		return gen11_rps_irq_handler(&gt->rps, iir);
71 	if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
72 		return gen11_rps_irq_handler(&media_gt->rps, iir);
73 
74 	if (instance == OTHER_KCR_INSTANCE)
75 		return intel_pxp_irq_handler(&gt->pxp, iir);
76 
77 	if (instance == OTHER_GSC_INSTANCE)
78 		return intel_gsc_irq_handler(gt, iir);
79 
80 	WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
81 		  instance, iir);
82 }
83 
84 static void
gen11_engine_irq_handler(struct intel_gt * gt,const u8 class,const u8 instance,const u16 iir)85 gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
86 			 const u8 instance, const u16 iir)
87 {
88 	struct intel_engine_cs *engine;
89 
90 	/*
91 	 * Platforms with standalone media have their media engines in another
92 	 * GT.
93 	 */
94 	if (MEDIA_VER(gt->i915) >= 13 &&
95 	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
96 		if (!gt->i915->media_gt)
97 			goto err;
98 
99 		gt = gt->i915->media_gt;
100 	}
101 
102 	if (instance <= MAX_ENGINE_INSTANCE)
103 		engine = gt->engine_class[class][instance];
104 	else
105 		engine = NULL;
106 
107 	if (likely(engine))
108 		return intel_engine_cs_irq(engine, iir);
109 
110 err:
111 	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
112 		  class, instance);
113 }
114 
115 static void
gen11_gt_identity_handler(struct intel_gt * gt,const u32 identity)116 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
117 {
118 	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
119 	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
120 	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
121 
122 	if (unlikely(!intr))
123 		return;
124 
125 	if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
126 		return gen11_engine_irq_handler(gt, class, instance, intr);
127 
128 	if (class == OTHER_CLASS)
129 		return gen11_other_irq_handler(gt, instance, intr);
130 
131 	WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
132 		  class, instance, intr);
133 }
134 
135 static void
gen11_gt_bank_handler(struct intel_gt * gt,const unsigned int bank)136 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
137 {
138 	void __iomem * const regs = gt->uncore->regs;
139 	unsigned long intr_dw;
140 	unsigned int bit;
141 
142 	lockdep_assert_held(gt->irq_lock);
143 
144 	intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
145 
146 	for_each_set_bit(bit, &intr_dw, 32) {
147 		const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
148 
149 		gen11_gt_identity_handler(gt, ident);
150 	}
151 
152 	/* Clear must be after shared has been served for engine */
153 	raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
154 }
155 
gen11_gt_irq_handler(struct intel_gt * gt,const u32 master_ctl)156 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
157 {
158 	unsigned int bank;
159 
160 	spin_lock(gt->irq_lock);
161 
162 	for (bank = 0; bank < 2; bank++) {
163 		if (master_ctl & GEN11_GT_DW_IRQ(bank))
164 			gen11_gt_bank_handler(gt, bank);
165 	}
166 
167 	spin_unlock(gt->irq_lock);
168 }
169 
gen11_gt_reset_one_iir(struct intel_gt * gt,const unsigned int bank,const unsigned int bit)170 bool gen11_gt_reset_one_iir(struct intel_gt *gt,
171 			    const unsigned int bank, const unsigned int bit)
172 {
173 	void __iomem * const regs = gt->uncore->regs;
174 	u32 dw;
175 
176 	lockdep_assert_held(gt->irq_lock);
177 
178 	dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
179 	if (dw & BIT(bit)) {
180 		/*
181 		 * According to the BSpec, DW_IIR bits cannot be cleared without
182 		 * first servicing the Selector & Shared IIR registers.
183 		 */
184 		gen11_gt_engine_identity(gt, bank, bit);
185 
186 		/*
187 		 * We locked GT INT DW by reading it. If we want to (try
188 		 * to) recover from this successfully, we need to clear
189 		 * our bit, otherwise we are locking the register for
190 		 * everybody.
191 		 */
192 		raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
193 
194 		return true;
195 	}
196 
197 	return false;
198 }
199 
gen11_gt_irq_reset(struct intel_gt * gt)200 void gen11_gt_irq_reset(struct intel_gt *gt)
201 {
202 	struct intel_uncore *uncore = gt->uncore;
203 
204 	/* Disable RCS, BCS, VCS and VECS class engines. */
205 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
206 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
207 	if (CCS_MASK(gt))
208 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
209 	if (HAS_HECI_GSC(gt->i915))
210 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
211 
212 	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
213 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,	~0);
214 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK,	~0);
215 	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
216 		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
217 	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
218 		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
219 	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
220 		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
221 	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
222 		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
223 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,	~0);
224 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,	~0);
225 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
226 		intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK,   ~0);
227 	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
228 		intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK,   ~0);
229 	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK,	~0);
230 	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
231 		intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
232 	if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
233 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
234 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
235 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
236 	if (HAS_HECI_GSC(gt->i915))
237 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
238 
239 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
240 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
241 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
242 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK,  ~0);
243 
244 	intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
245 	intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK,  ~0);
246 }
247 
gen11_gt_irq_postinstall(struct intel_gt * gt)248 void gen11_gt_irq_postinstall(struct intel_gt *gt)
249 {
250 	struct intel_uncore *uncore = gt->uncore;
251 	u32 irqs = GT_RENDER_USER_INTERRUPT;
252 	const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
253 	u32 dmask;
254 	u32 smask;
255 
256 	if (!intel_uc_wants_guc_submission(&gt->uc))
257 		irqs |= GT_CS_MASTER_ERROR_INTERRUPT |
258 			GT_CONTEXT_SWITCH_INTERRUPT |
259 			GT_WAIT_SEMAPHORE_INTERRUPT;
260 
261 	dmask = irqs << 16 | irqs;
262 	smask = irqs << 16;
263 
264 	BUILD_BUG_ON(irqs & 0xffff0000);
265 
266 	/* Enable RCS, BCS, VCS and VECS class interrupts. */
267 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
268 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
269 	if (CCS_MASK(gt))
270 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
271 	if (HAS_HECI_GSC(gt->i915))
272 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
273 				   gsc_mask);
274 
275 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
276 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
277 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
278 	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
279 		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
280 	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
281 		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
282 	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
283 		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
284 	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
285 		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
286 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
287 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
288 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
289 		intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
290 	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
291 		intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
292 	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
293 	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
294 		intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
295 	if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
296 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
297 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
298 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
299 	if (HAS_HECI_GSC(gt->i915))
300 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
301 
302 	/*
303 	 * RPS interrupts will get enabled/disabled on demand when RPS itself
304 	 * is enabled/disabled.
305 	 */
306 	gt->pm_ier = 0x0;
307 	gt->pm_imr = ~gt->pm_ier;
308 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
309 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
310 
311 	/* Same thing for GuC interrupts */
312 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
313 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK,  ~0);
314 }
315 
gen5_gt_irq_handler(struct intel_gt * gt,u32 gt_iir)316 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
317 {
318 	if (gt_iir & GT_RENDER_USER_INTERRUPT)
319 		intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
320 				    gt_iir);
321 
322 	if (gt_iir & ILK_BSD_USER_INTERRUPT)
323 		intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
324 				    gt_iir);
325 }
326 
gen7_parity_error_irq_handler(struct intel_gt * gt,u32 iir)327 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
328 {
329 	if (!HAS_L3_DPF(gt->i915))
330 		return;
331 
332 	spin_lock(gt->irq_lock);
333 	gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));
334 	spin_unlock(gt->irq_lock);
335 
336 	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
337 		gt->i915->l3_parity.which_slice |= 1 << 1;
338 
339 	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
340 		gt->i915->l3_parity.which_slice |= 1 << 0;
341 
342 	schedule_work(&gt->i915->l3_parity.error_work);
343 }
344 
gen6_gt_irq_handler(struct intel_gt * gt,u32 gt_iir)345 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
346 {
347 	if (gt_iir & GT_RENDER_USER_INTERRUPT)
348 		intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
349 				    gt_iir);
350 
351 	if (gt_iir & GT_BSD_USER_INTERRUPT)
352 		intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
353 				    gt_iir >> 12);
354 
355 	if (gt_iir & GT_BLT_USER_INTERRUPT)
356 		intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
357 				    gt_iir >> 22);
358 
359 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
360 		      GT_BSD_CS_ERROR_INTERRUPT |
361 		      GT_CS_MASTER_ERROR_INTERRUPT))
362 		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
363 
364 	if (gt_iir & GT_PARITY_ERROR(gt->i915))
365 		gen7_parity_error_irq_handler(gt, gt_iir);
366 }
367 
gen8_gt_irq_handler(struct intel_gt * gt,u32 master_ctl)368 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
369 {
370 	void __iomem * const regs = gt->uncore->regs;
371 	u32 iir;
372 
373 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
374 		iir = raw_reg_read(regs, GEN8_GT_IIR(0));
375 		if (likely(iir)) {
376 			intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
377 					    iir >> GEN8_RCS_IRQ_SHIFT);
378 			intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
379 					    iir >> GEN8_BCS_IRQ_SHIFT);
380 			raw_reg_write(regs, GEN8_GT_IIR(0), iir);
381 		}
382 	}
383 
384 	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
385 		iir = raw_reg_read(regs, GEN8_GT_IIR(1));
386 		if (likely(iir)) {
387 			intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
388 					    iir >> GEN8_VCS0_IRQ_SHIFT);
389 			intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1],
390 					    iir >> GEN8_VCS1_IRQ_SHIFT);
391 			raw_reg_write(regs, GEN8_GT_IIR(1), iir);
392 		}
393 	}
394 
395 	if (master_ctl & GEN8_GT_VECS_IRQ) {
396 		iir = raw_reg_read(regs, GEN8_GT_IIR(3));
397 		if (likely(iir)) {
398 			intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
399 					    iir >> GEN8_VECS_IRQ_SHIFT);
400 			raw_reg_write(regs, GEN8_GT_IIR(3), iir);
401 		}
402 	}
403 
404 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
405 		iir = raw_reg_read(regs, GEN8_GT_IIR(2));
406 		if (likely(iir)) {
407 			gen6_rps_irq_handler(&gt->rps, iir);
408 			guc_irq_handler(&gt->uc.guc, iir >> 16);
409 			raw_reg_write(regs, GEN8_GT_IIR(2), iir);
410 		}
411 	}
412 }
413 
gen8_gt_irq_reset(struct intel_gt * gt)414 void gen8_gt_irq_reset(struct intel_gt *gt)
415 {
416 	struct intel_uncore *uncore = gt->uncore;
417 
418 	GEN8_IRQ_RESET_NDX(uncore, GT, 0);
419 	GEN8_IRQ_RESET_NDX(uncore, GT, 1);
420 	GEN8_IRQ_RESET_NDX(uncore, GT, 2);
421 	GEN8_IRQ_RESET_NDX(uncore, GT, 3);
422 }
423 
gen8_gt_irq_postinstall(struct intel_gt * gt)424 void gen8_gt_irq_postinstall(struct intel_gt *gt)
425 {
426 	/* These are interrupts we'll toggle with the ring mask register */
427 	const u32 irqs =
428 		GT_CS_MASTER_ERROR_INTERRUPT |
429 		GT_RENDER_USER_INTERRUPT |
430 		GT_CONTEXT_SWITCH_INTERRUPT |
431 		GT_WAIT_SEMAPHORE_INTERRUPT;
432 	const u32 gt_interrupts[] = {
433 		irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
434 		irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
435 		0,
436 		irqs << GEN8_VECS_IRQ_SHIFT,
437 	};
438 	struct intel_uncore *uncore = gt->uncore;
439 
440 	gt->pm_ier = 0x0;
441 	gt->pm_imr = ~gt->pm_ier;
442 	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
443 	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
444 	/*
445 	 * RPS interrupts will get enabled/disabled on demand when RPS itself
446 	 * is enabled/disabled. Same wil be the case for GuC interrupts.
447 	 */
448 	GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);
449 	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
450 }
451 
gen5_gt_update_irq(struct intel_gt * gt,u32 interrupt_mask,u32 enabled_irq_mask)452 static void gen5_gt_update_irq(struct intel_gt *gt,
453 			       u32 interrupt_mask,
454 			       u32 enabled_irq_mask)
455 {
456 	lockdep_assert_held(gt->irq_lock);
457 
458 	GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask);
459 
460 	gt->gt_imr &= ~interrupt_mask;
461 	gt->gt_imr |= (~enabled_irq_mask & interrupt_mask);
462 	intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr);
463 }
464 
gen5_gt_enable_irq(struct intel_gt * gt,u32 mask)465 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask)
466 {
467 	gen5_gt_update_irq(gt, mask, mask);
468 	intel_uncore_posting_read_fw(gt->uncore, GTIMR);
469 }
470 
gen5_gt_disable_irq(struct intel_gt * gt,u32 mask)471 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask)
472 {
473 	gen5_gt_update_irq(gt, mask, 0);
474 }
475 
gen5_gt_irq_reset(struct intel_gt * gt)476 void gen5_gt_irq_reset(struct intel_gt *gt)
477 {
478 	struct intel_uncore *uncore = gt->uncore;
479 
480 	GEN3_IRQ_RESET(uncore, GT);
481 	if (GRAPHICS_VER(gt->i915) >= 6)
482 		GEN3_IRQ_RESET(uncore, GEN6_PM);
483 }
484 
gen5_gt_irq_postinstall(struct intel_gt * gt)485 void gen5_gt_irq_postinstall(struct intel_gt *gt)
486 {
487 	struct intel_uncore *uncore = gt->uncore;
488 	u32 pm_irqs = 0;
489 	u32 gt_irqs = 0;
490 
491 	gt->gt_imr = ~0;
492 	if (HAS_L3_DPF(gt->i915)) {
493 		/* L3 parity interrupt is always unmasked. */
494 		gt->gt_imr = ~GT_PARITY_ERROR(gt->i915);
495 		gt_irqs |= GT_PARITY_ERROR(gt->i915);
496 	}
497 
498 	gt_irqs |= GT_RENDER_USER_INTERRUPT;
499 	if (GRAPHICS_VER(gt->i915) == 5)
500 		gt_irqs |= ILK_BSD_USER_INTERRUPT;
501 	else
502 		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
503 
504 	GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
505 
506 	if (GRAPHICS_VER(gt->i915) >= 6) {
507 		/*
508 		 * RPS interrupts will get enabled/disabled on demand when RPS
509 		 * itself is enabled/disabled.
510 		 */
511 		if (HAS_ENGINE(gt, VECS0)) {
512 			pm_irqs |= PM_VEBOX_USER_INTERRUPT;
513 			gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;
514 		}
515 
516 		gt->pm_imr = 0xffffffff;
517 		GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs);
518 	}
519 }
520