1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/gpio/gpio.h> 3#include <dt-bindings/interrupt-controller/irq.h> 4 5#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "marvell,dove"; 11 model = "Marvell Armada 88AP510 SoC"; 12 interrupt-parent = <&intc>; 13 14 aliases { 15 gpio0 = &gpio0; 16 gpio1 = &gpio1; 17 gpio2 = &gpio2; 18 }; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "marvell,pj4a", "marvell,sheeva-v7"; 26 device_type = "cpu"; 27 next-level-cache = <&l2>; 28 reg = <0>; 29 }; 30 }; 31 32 l2: l2-cache { 33 compatible = "marvell,tauros2-cache"; 34 marvell,tauros2-cache-features = <0>; 35 }; 36 37 gpu-subsystem { 38 compatible = "marvell,dove-gpu-subsystem"; 39 cores = <&gpu>; 40 status = "disabled"; 41 }; 42 43 i2c-mux { 44 compatible = "i2c-mux-pinctrl"; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 i2c-parent = <&i2c>; 49 50 pinctrl-names = "i2c0", "i2c1", "i2c2"; 51 pinctrl-0 = <&pmx_i2cmux_0>; 52 pinctrl-1 = <&pmx_i2cmux_1>; 53 pinctrl-2 = <&pmx_i2cmux_2>; 54 55 i2c0: i2c@0 { 56 reg = <0>; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 status = "okay"; 60 }; 61 62 i2c1: i2c@1 { 63 reg = <1>; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 /* Requires pmx_i2c1 on i2c controller node */ 67 status = "disabled"; 68 }; 69 70 i2c2: i2c@2 { 71 reg = <2>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 /* Requires pmx_i2c2 on i2c controller node */ 75 status = "disabled"; 76 }; 77 }; 78 79 mbus { 80 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; 81 #address-cells = <2>; 82 #size-cells = <1>; 83 controller = <&mbusc>; 84 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ 85 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ 86 87 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ 88 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ 89 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ 90 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ 91 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ 92 93 pcie: pcie { 94 compatible = "marvell,dove-pcie"; 95 status = "disabled"; 96 device_type = "pci"; 97 #address-cells = <3>; 98 #size-cells = <2>; 99 100 msi-parent = <&intc>; 101 bus-range = <0x00 0xff>; 102 103 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 104 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 105 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ 106 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ 107 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 108 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ 109 110 pcie0: pcie@1 { 111 device_type = "pci"; 112 status = "disabled"; 113 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 114 reg = <0x0800 0 0 0 0>; 115 clocks = <&gate_clk 4>; 116 marvell,pcie-port = <0>; 117 118 #address-cells = <3>; 119 #size-cells = <2>; 120 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 121 0x81000000 0 0 0x81000000 0x1 0 1 0>; 122 bus-range = <0x00 0xff>; 123 124 #interrupt-cells = <1>; 125 interrupt-names = "intx", "error"; 126 interrupts = <16>, <15>; 127 interrupt-map-mask = <0 0 0 7>; 128 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 129 <0 0 0 2 &pcie0_intc 1>, 130 <0 0 0 3 &pcie0_intc 2>, 131 <0 0 0 4 &pcie0_intc 3>; 132 133 pcie0_intc: interrupt-controller { 134 interrupt-controller; 135 #interrupt-cells = <1>; 136 }; 137 }; 138 139 pcie1: pcie@2 { 140 device_type = "pci"; 141 status = "disabled"; 142 assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; 143 reg = <0x1000 0 0 0 0>; 144 clocks = <&gate_clk 5>; 145 marvell,pcie-port = <1>; 146 147 #address-cells = <3>; 148 #size-cells = <2>; 149 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 150 0x81000000 0 0 0x81000000 0x2 0 1 0>; 151 bus-range = <0x00 0xff>; 152 153 #interrupt-cells = <1>; 154 interrupt-names = "intx", "error"; 155 interrupts = <18>, <17>; 156 interrupt-map-mask = <0 0 0 7>; 157 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 158 <0 0 0 2 &pcie1_intc 1>, 159 <0 0 0 3 &pcie1_intc 2>, 160 <0 0 0 4 &pcie1_intc 3>; 161 162 pcie1_intc: interrupt-controller { 163 interrupt-controller; 164 #interrupt-cells = <1>; 165 }; 166 }; 167 }; 168 169 internal-regs { 170 compatible = "simple-bus"; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ 174 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ 175 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ 176 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ 177 178 spi0: spi@10600 { 179 compatible = "marvell,orion-spi"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 cell-index = <0>; 183 interrupts = <6>; 184 reg = <0x10600 0x28>; 185 clocks = <&core_clk 0>; 186 pinctrl-0 = <&pmx_spi0>; 187 pinctrl-names = "default"; 188 status = "disabled"; 189 }; 190 191 i2c: i2c@11000 { 192 compatible = "marvell,mv64xxx-i2c"; 193 reg = <0x11000 0x20>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 interrupts = <11>; 197 clock-frequency = <400000>; 198 clocks = <&core_clk 0>; 199 status = "okay"; 200 }; 201 202 uart0: serial@12000 { 203 compatible = "ns16550a"; 204 reg = <0x12000 0x100>; 205 reg-shift = <2>; 206 interrupts = <7>; 207 clocks = <&core_clk 0>; 208 status = "disabled"; 209 }; 210 211 uart1: serial@12100 { 212 compatible = "ns16550a"; 213 reg = <0x12100 0x100>; 214 reg-shift = <2>; 215 interrupts = <8>; 216 clocks = <&core_clk 0>; 217 pinctrl-0 = <&pmx_uart1>; 218 pinctrl-names = "default"; 219 status = "disabled"; 220 }; 221 222 uart2: serial@12200 { 223 compatible = "ns16550a"; 224 reg = <0x12200 0x100>; 225 reg-shift = <2>; 226 interrupts = <9>; 227 clocks = <&core_clk 0>; 228 status = "disabled"; 229 }; 230 231 uart3: serial@12300 { 232 compatible = "ns16550a"; 233 reg = <0x12300 0x100>; 234 reg-shift = <2>; 235 interrupts = <10>; 236 clocks = <&core_clk 0>; 237 status = "disabled"; 238 }; 239 240 spi1: spi@14600 { 241 compatible = "marvell,orion-spi"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 cell-index = <1>; 245 interrupts = <5>; 246 reg = <0x14600 0x28>; 247 clocks = <&core_clk 0>; 248 status = "disabled"; 249 }; 250 251 mbusc: mbus-ctrl@20000 { 252 compatible = "marvell,mbus-controller"; 253 reg = <0x20000 0x80>, <0x800100 0x8>; 254 }; 255 256 sysc: system-ctrl@20000 { 257 compatible = "marvell,orion-system-controller"; 258 reg = <0x20000 0x110>; 259 }; 260 261 bridge_intc: bridge-interrupt-ctrl@20110 { 262 compatible = "marvell,orion-bridge-intc"; 263 interrupt-controller; 264 #interrupt-cells = <1>; 265 reg = <0x20110 0x8>; 266 interrupts = <0>; 267 marvell,#interrupts = <5>; 268 }; 269 270 intc: interrupt-controller@20200 { 271 compatible = "marvell,orion-intc"; 272 interrupt-controller; 273 #interrupt-cells = <1>; 274 reg = <0x20200 0x10>, <0x20210 0x10>; 275 }; 276 277 timer: timer@20300 { 278 compatible = "marvell,orion-timer"; 279 reg = <0x20300 0x20>; 280 interrupt-parent = <&bridge_intc>; 281 interrupts = <1>, <2>; 282 clocks = <&core_clk 0>; 283 }; 284 285 watchdog@20300 { 286 compatible = "marvell,orion-wdt"; 287 reg = <0x20300 0x28>, <0x20108 0x4>; 288 interrupt-parent = <&bridge_intc>; 289 interrupts = <3>; 290 clocks = <&core_clk 0>; 291 }; 292 293 crypto: crypto-engine@30000 { 294 compatible = "marvell,dove-crypto"; 295 reg = <0x30000 0x10000>; 296 reg-names = "regs"; 297 interrupts = <31>; 298 clocks = <&gate_clk 15>; 299 marvell,crypto-srams = <&crypto_sram>; 300 marvell,crypto-sram-size = <0x800>; 301 status = "okay"; 302 }; 303 304 ehci0: usb-host@50000 { 305 compatible = "marvell,orion-ehci"; 306 reg = <0x50000 0x1000>; 307 interrupts = <24>; 308 clocks = <&gate_clk 0>; 309 status = "okay"; 310 }; 311 312 ehci1: usb-host@51000 { 313 compatible = "marvell,orion-ehci"; 314 reg = <0x51000 0x1000>; 315 interrupts = <25>; 316 clocks = <&gate_clk 1>; 317 status = "okay"; 318 }; 319 320 xor0: dma-engine@60800 { 321 compatible = "marvell,orion-xor"; 322 reg = <0x60800 0x100 323 0x60a00 0x100>; 324 clocks = <&gate_clk 23>; 325 status = "okay"; 326 327 channel0 { 328 interrupts = <39>; 329 dmacap,memcpy; 330 dmacap,xor; 331 }; 332 333 channel1 { 334 interrupts = <40>; 335 dmacap,memcpy; 336 dmacap,xor; 337 }; 338 }; 339 340 xor1: dma-engine@60900 { 341 compatible = "marvell,orion-xor"; 342 reg = <0x60900 0x100 343 0x60b00 0x100>; 344 clocks = <&gate_clk 24>; 345 status = "okay"; 346 347 channel0 { 348 interrupts = <42>; 349 dmacap,memcpy; 350 dmacap,xor; 351 }; 352 353 channel1 { 354 interrupts = <43>; 355 dmacap,memcpy; 356 dmacap,xor; 357 }; 358 }; 359 360 sdio1: sdio-host@90000 { 361 compatible = "marvell,dove-sdhci"; 362 reg = <0x90000 0x100>; 363 interrupts = <36>, <38>; 364 clocks = <&gate_clk 9>; 365 pinctrl-0 = <&pmx_sdio1>; 366 pinctrl-names = "default"; 367 status = "disabled"; 368 }; 369 370 eth: ethernet-ctrl@72000 { 371 compatible = "marvell,orion-eth"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 reg = <0x72000 0x4000>; 375 clocks = <&gate_clk 2>; 376 marvell,tx-checksum-limit = <1600>; 377 status = "disabled"; 378 379 ethernet-port@0 { 380 compatible = "marvell,orion-eth-port"; 381 reg = <0>; 382 interrupts = <29>; 383 /* overwrite MAC address in bootloader */ 384 local-mac-address = [00 00 00 00 00 00]; 385 phy-handle = <ðphy>; 386 }; 387 }; 388 389 mdio: mdio-bus@72004 { 390 compatible = "marvell,orion-mdio"; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 reg = <0x72004 0x84>; 394 interrupts = <30>; 395 clocks = <&gate_clk 2>; 396 status = "disabled"; 397 398 ethphy: ethernet-phy { 399 /* set phy address in board file */ 400 }; 401 }; 402 403 sdio0: sdio-host@92000 { 404 compatible = "marvell,dove-sdhci"; 405 reg = <0x92000 0x100>; 406 interrupts = <35>, <37>; 407 clocks = <&gate_clk 8>; 408 pinctrl-0 = <&pmx_sdio0>; 409 pinctrl-names = "default"; 410 status = "disabled"; 411 }; 412 413 sata0: sata-host@a0000 { 414 compatible = "marvell,orion-sata"; 415 reg = <0xa0000 0x2400>; 416 interrupts = <62>; 417 clocks = <&gate_clk 3>; 418 phys = <&sata_phy0>; 419 phy-names = "port0"; 420 nr-ports = <1>; 421 status = "disabled"; 422 }; 423 424 sata_phy0: sata-phy@a2000 { 425 compatible = "marvell,mvebu-sata-phy"; 426 reg = <0xa2000 0x0334>; 427 clocks = <&gate_clk 3>; 428 clock-names = "sata"; 429 #phy-cells = <0>; 430 status = "ok"; 431 }; 432 433 audio0: audio-controller@b0000 { 434 compatible = "marvell,dove-audio"; 435 reg = <0xb0000 0x2210>; 436 interrupts = <19>, <20>; 437 clocks = <&gate_clk 12>; 438 clock-names = "internal"; 439 status = "disabled"; 440 }; 441 442 audio1: audio-controller@b4000 { 443 compatible = "marvell,dove-audio"; 444 reg = <0xb4000 0x2210>; 445 interrupts = <21>, <22>; 446 clocks = <&gate_clk 13>; 447 clock-names = "internal"; 448 status = "disabled"; 449 }; 450 451 pmu: power-management@d0000 { 452 compatible = "marvell,dove-pmu", "simple-bus"; 453 reg = <0xd0000 0x8000>, <0xd8000 0x8000>; 454 ranges = <0x00000000 0x000d0000 0x8000 455 0x00008000 0x000d8000 0x8000>; 456 interrupts = <33>; 457 interrupt-controller; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 #interrupt-cells = <1>; 461 #reset-cells = <1>; 462 463 domains { 464 vpu_domain: vpu-domain { 465 #power-domain-cells = <0>; 466 marvell,pmu_pwr_mask = <0x00000008>; 467 marvell,pmu_iso_mask = <0x00000001>; 468 resets = <&pmu 16>; 469 }; 470 471 gpu_domain: gpu-domain { 472 #power-domain-cells = <0>; 473 marvell,pmu_pwr_mask = <0x00000004>; 474 marvell,pmu_iso_mask = <0x00000002>; 475 resets = <&pmu 18>; 476 }; 477 }; 478 479 thermal: thermal-diode@1c { 480 compatible = "marvell,dove-thermal"; 481 reg = <0x001c 0x0c>, <0x005c 0x08>; 482 }; 483 484 gate_clk: clock-gating-ctrl@38 { 485 compatible = "marvell,dove-gating-clock"; 486 reg = <0x0038 0x4>; 487 clocks = <&core_clk 0>; 488 #clock-cells = <1>; 489 }; 490 491 divider_clk: core-clock@64 { 492 compatible = "marvell,dove-divider-clock"; 493 reg = <0x0064 0x8>; 494 #clock-cells = <1>; 495 }; 496 497 pinctrl: pin-ctrl@200 { 498 compatible = "marvell,dove-pinctrl"; 499 reg = <0x0200 0x14>, 500 <0x0440 0x04>; 501 clocks = <&gate_clk 22>; 502 503 pmx_gpio_0: pmx-gpio-0 { 504 marvell,pins = "mpp0"; 505 marvell,function = "gpio"; 506 }; 507 508 pmx_gpio_1: pmx-gpio-1 { 509 marvell,pins = "mpp1"; 510 marvell,function = "gpio"; 511 }; 512 513 pmx_gpio_2: pmx-gpio-2 { 514 marvell,pins = "mpp2"; 515 marvell,function = "gpio"; 516 }; 517 518 pmx_gpio_3: pmx-gpio-3 { 519 marvell,pins = "mpp3"; 520 marvell,function = "gpio"; 521 }; 522 523 pmx_gpio_4: pmx-gpio-4 { 524 marvell,pins = "mpp4"; 525 marvell,function = "gpio"; 526 }; 527 528 pmx_gpio_5: pmx-gpio-5 { 529 marvell,pins = "mpp5"; 530 marvell,function = "gpio"; 531 }; 532 533 pmx_gpio_6: pmx-gpio-6 { 534 marvell,pins = "mpp6"; 535 marvell,function = "gpio"; 536 }; 537 538 pmx_gpio_7: pmx-gpio-7 { 539 marvell,pins = "mpp7"; 540 marvell,function = "gpio"; 541 }; 542 543 pmx_gpio_8: pmx-gpio-8 { 544 marvell,pins = "mpp8"; 545 marvell,function = "gpio"; 546 }; 547 548 pmx_gpio_9: pmx-gpio-9 { 549 marvell,pins = "mpp9"; 550 marvell,function = "gpio"; 551 }; 552 553 pmx_pcie1_clkreq: pmx-pcie1-clkreq { 554 marvell,pins = "mpp9"; 555 marvell,function = "pex1"; 556 }; 557 558 pmx_gpio_10: pmx-gpio-10 { 559 marvell,pins = "mpp10"; 560 marvell,function = "gpio"; 561 }; 562 563 pmx_gpio_11: pmx-gpio-11 { 564 marvell,pins = "mpp11"; 565 marvell,function = "gpio"; 566 }; 567 568 pmx_pcie0_clkreq: pmx-pcie0-clkreq { 569 marvell,pins = "mpp11"; 570 marvell,function = "pex0"; 571 }; 572 573 pmx_gpio_12: pmx-gpio-12 { 574 marvell,pins = "mpp12"; 575 marvell,function = "gpio"; 576 }; 577 578 pmx_gpio_13: pmx-gpio-13 { 579 marvell,pins = "mpp13"; 580 marvell,function = "gpio"; 581 }; 582 583 pmx_audio1_extclk: pmx-audio1-extclk { 584 marvell,pins = "mpp13"; 585 marvell,function = "audio1"; 586 }; 587 588 pmx_gpio_14: pmx-gpio-14 { 589 marvell,pins = "mpp14"; 590 marvell,function = "gpio"; 591 }; 592 593 pmx_gpio_15: pmx-gpio-15 { 594 marvell,pins = "mpp15"; 595 marvell,function = "gpio"; 596 }; 597 598 pmx_gpio_16: pmx-gpio-16 { 599 marvell,pins = "mpp16"; 600 marvell,function = "gpio"; 601 }; 602 603 pmx_gpio_17: pmx-gpio-17 { 604 marvell,pins = "mpp17"; 605 marvell,function = "gpio"; 606 }; 607 608 pmx_gpio_18: pmx-gpio-18 { 609 marvell,pins = "mpp18"; 610 marvell,function = "gpio"; 611 }; 612 613 pmx_gpio_19: pmx-gpio-19 { 614 marvell,pins = "mpp19"; 615 marvell,function = "gpio"; 616 }; 617 618 pmx_gpio_20: pmx-gpio-20 { 619 marvell,pins = "mpp20"; 620 marvell,function = "gpio"; 621 }; 622 623 pmx_gpio_21: pmx-gpio-21 { 624 marvell,pins = "mpp21"; 625 marvell,function = "gpio"; 626 }; 627 628 pmx_camera: pmx-camera { 629 marvell,pins = "mpp_camera"; 630 marvell,function = "camera"; 631 }; 632 633 pmx_camera_gpio: pmx-camera-gpio { 634 marvell,pins = "mpp_camera"; 635 marvell,function = "gpio"; 636 }; 637 638 pmx_sdio0: pmx-sdio0 { 639 marvell,pins = "mpp_sdio0"; 640 marvell,function = "sdio0"; 641 }; 642 643 pmx_sdio0_gpio: pmx-sdio0-gpio { 644 marvell,pins = "mpp_sdio0"; 645 marvell,function = "gpio"; 646 }; 647 648 pmx_sdio1: pmx-sdio1 { 649 marvell,pins = "mpp_sdio1"; 650 marvell,function = "sdio1"; 651 }; 652 653 pmx_sdio1_gpio: pmx-sdio1-gpio { 654 marvell,pins = "mpp_sdio1"; 655 marvell,function = "gpio"; 656 }; 657 658 pmx_audio1_gpio: pmx-audio1-gpio { 659 marvell,pins = "mpp_audio1"; 660 marvell,function = "gpio"; 661 }; 662 663 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { 664 marvell,pins = "mpp_audio1"; 665 marvell,function = "i2s1/spdifo"; 666 }; 667 668 pmx_spi0: pmx-spi0 { 669 marvell,pins = "mpp_spi0"; 670 marvell,function = "spi0"; 671 }; 672 673 pmx_spi0_gpio: pmx-spi0-gpio { 674 marvell,pins = "mpp_spi0"; 675 marvell,function = "gpio"; 676 }; 677 678 pmx_spi1_4_7: pmx-spi1-4-7 { 679 marvell,pins = "mpp4", "mpp5", 680 "mpp6", "mpp7"; 681 marvell,function = "spi1"; 682 }; 683 684 pmx_spi1_20_23: pmx-spi1-20-23 { 685 marvell,pins = "mpp20", "mpp21", 686 "mpp22", "mpp23"; 687 marvell,function = "spi1"; 688 }; 689 690 pmx_uart1: pmx-uart1 { 691 marvell,pins = "mpp_uart1"; 692 marvell,function = "uart1"; 693 }; 694 695 pmx_uart1_gpio: pmx-uart1-gpio { 696 marvell,pins = "mpp_uart1"; 697 marvell,function = "gpio"; 698 }; 699 700 pmx_nand: pmx-nand { 701 marvell,pins = "mpp_nand"; 702 marvell,function = "nand"; 703 }; 704 705 pmx_nand_gpo: pmx-nand-gpo { 706 marvell,pins = "mpp_nand"; 707 marvell,function = "gpo"; 708 }; 709 710 pmx_i2c1: pmx-i2c1 { 711 marvell,pins = "mpp17", "mpp19"; 712 marvell,function = "twsi"; 713 }; 714 715 pmx_i2c2: pmx-i2c2 { 716 marvell,pins = "mpp_audio1"; 717 marvell,function = "twsi"; 718 }; 719 720 pmx_ssp_i2c2: pmx-ssp-i2c2 { 721 marvell,pins = "mpp_audio1"; 722 marvell,function = "ssp/twsi"; 723 }; 724 725 pmx_i2cmux_0: pmx-i2cmux-0 { 726 marvell,pins = "twsi"; 727 marvell,function = "twsi-opt1"; 728 }; 729 730 pmx_i2cmux_1: pmx-i2cmux-1 { 731 marvell,pins = "twsi"; 732 marvell,function = "twsi-opt2"; 733 }; 734 735 pmx_i2cmux_2: pmx-i2cmux-2 { 736 marvell,pins = "twsi"; 737 marvell,function = "twsi-opt3"; 738 }; 739 }; 740 741 core_clk: core-clocks@214 { 742 compatible = "marvell,dove-core-clock"; 743 reg = <0x0214 0x4>; 744 #clock-cells = <1>; 745 }; 746 747 gpio0: gpio-ctrl@400 { 748 compatible = "marvell,orion-gpio"; 749 #gpio-cells = <2>; 750 gpio-controller; 751 reg = <0x0400 0x20>; 752 ngpios = <32>; 753 interrupt-controller; 754 #interrupt-cells = <2>; 755 interrupt-parent = <&intc>; 756 interrupts = <12>, <13>, <14>, <60>; 757 }; 758 759 gpio1: gpio-ctrl@420 { 760 compatible = "marvell,orion-gpio"; 761 #gpio-cells = <2>; 762 gpio-controller; 763 reg = <0x0420 0x20>; 764 ngpios = <32>; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 interrupt-parent = <&intc>; 768 interrupts = <61>; 769 }; 770 771 rtc: real-time-clock@8500 { 772 compatible = "marvell,orion-rtc"; 773 reg = <0x8500 0x20>; 774 interrupts = <5>; 775 }; 776 }; 777 778 gconf: global-config@e802c { 779 compatible = "marvell,dove-global-config", 780 "syscon"; 781 reg = <0xe802c 0x14>; 782 }; 783 784 gpio2: gpio-ctrl@e8400 { 785 compatible = "marvell,orion-gpio"; 786 #gpio-cells = <2>; 787 gpio-controller; 788 reg = <0xe8400 0x0c>; 789 ngpios = <8>; 790 }; 791 792 lcd1: lcd-controller@810000 { 793 compatible = "marvell,dove-lcd"; 794 reg = <0x810000 0x1000>; 795 interrupts = <46>; 796 status = "disabled"; 797 }; 798 799 lcd0: lcd-controller@820000 { 800 compatible = "marvell,dove-lcd"; 801 reg = <0x820000 0x1000>; 802 interrupts = <47>; 803 status = "disabled"; 804 }; 805 806 crypto_sram: sram@ffffe000 { 807 compatible = "mmio-sram"; 808 reg = <0xffffe000 0x800>; 809 clocks = <&gate_clk 15>; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 }; 813 814 gpu: gpu@840000 { 815 clocks = <÷r_clk 1>; 816 clock-names = "core"; 817 compatible = "vivante,gc"; 818 interrupts = <48>; 819 power-domains = <&gpu_domain>; 820 reg = <0x840000 0x4000>; 821 status = "disabled"; 822 }; 823 }; 824 }; 825}; 826