1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright 2020-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8 #include "gaudi2P.h"
9 #include "../include/gaudi2/asic_reg/gaudi2_regs.h"
10
11 #define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))
12
13 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK
14 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK
15 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK
16 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK
17 #define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK
18 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \
19 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK
20 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \
21 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK
22 #define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \
23 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK
24
25 /* LBW RR */
26 #define SFT_NUM_OF_LBW_RTR 1
27 #define SFT_LBW_RTR_OFFSET 0
28 #define RR_LBW_LONG_MASK 0x7FFFFFFull
29 #define RR_LBW_SHORT_MASK 0x7FFF000ull
30
31 /* HBW RR */
32 #define SFT_NUM_OF_HBW_RTR 2
33 #define RR_HBW_SHORT_LO_MASK 0xFFFFFFFF000ull
34 #define RR_HBW_SHORT_HI_MASK 0xF00000000000ull
35 #define RR_HBW_LONG_LO_MASK 0xFFFFFFFF000ull
36 #define RR_HBW_LONG_HI_MASK 0xFFFFF00000000000ull
37
38 struct rr_config {
39 u64 min;
40 u64 max;
41 u32 index;
42 u8 type;
43 };
44
45 struct gaudi2_atypical_bp_blocks {
46 u32 mm_block_base_addr;
47 u32 block_size;
48 u32 glbl_sec_offset;
49 u32 glbl_sec_length;
50 };
51
52 static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
53 mmDCORE0_SYNC_MNGR_OBJS_BASE,
54 128 * 1024,
55 SM_OBJS_PROT_BITS_OFFS,
56 640
57 };
58
59 static const u32 gaudi2_pb_sft0[] = {
60 mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
61 mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
62 mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
63 mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
64 mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
65 mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
66 mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
67 mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
68 mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
69 mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
70 mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
71 mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
72 mmSFT0_BASE,
73 };
74
75 static const u32 gaudi2_pb_dcr0_hif[] = {
76 mmDCORE0_HIF0_BASE,
77 };
78
79 static const u32 gaudi2_pb_dcr0_rtr0[] = {
80 mmDCORE0_RTR0_CTRL_BASE,
81 mmDCORE0_RTR0_H3_BASE,
82 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
83 mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
84 mmDCORE0_RTR0_BASE,
85 mmDCORE0_RTR0_DBG_ADDR_BASE,
86 };
87
88 static const u32 gaudi2_pb_dcr0_hmmu0[] = {
89 mmDCORE0_HMMU0_MMU_BASE,
90 mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
91 mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
92 mmDCORE0_HMMU0_STLB_BASE,
93 };
94
95 static const u32 gaudi2_pb_cpu_if[] = {
96 mmCPU_IF_BASE,
97 };
98
99 static const u32 gaudi2_pb_cpu[] = {
100 mmCPU_CA53_CFG_BASE,
101 mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
102 };
103
104 static const u32 gaudi2_pb_kdma[] = {
105 mmARC_FARM_KDMA_BASE,
106 mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
107 };
108
109 static const u32 gaudi2_pb_pdma0[] = {
110 mmPDMA0_CORE_BASE,
111 mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
112 mmPDMA0_QM_BASE,
113 };
114
115 static const u32 gaudi2_pb_pdma0_arc[] = {
116 mmPDMA0_QM_ARC_AUX_BASE,
117 };
118
119 static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
120 {mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
121 {mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
122 {mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
123 {mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
124 {mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
125 {mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
126 {mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
127 {mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
128 {mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
129 };
130
131 static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {
132 mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
133 mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,
134 mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,
135 mmPDMA0_CORE_CTX_WR_COMP_WDATA,
136 mmPDMA0_CORE_CTX_SRC_BASE_LO,
137 mmPDMA0_CORE_CTX_SRC_BASE_HI,
138 mmPDMA0_CORE_CTX_DST_BASE_LO,
139 mmPDMA0_CORE_CTX_DST_BASE_HI,
140 mmPDMA0_CORE_CTX_SRC_TSIZE_0,
141 mmPDMA0_CORE_CTX_SRC_TSIZE_1,
142 mmPDMA0_CORE_CTX_SRC_TSIZE_2,
143 mmPDMA0_CORE_CTX_SRC_TSIZE_3,
144 mmPDMA0_CORE_CTX_SRC_TSIZE_4,
145 mmPDMA0_CORE_CTX_SRC_STRIDE_1,
146 mmPDMA0_CORE_CTX_SRC_STRIDE_2,
147 mmPDMA0_CORE_CTX_SRC_STRIDE_3,
148 mmPDMA0_CORE_CTX_SRC_STRIDE_4,
149 mmPDMA0_CORE_CTX_SRC_OFFSET_LO,
150 mmPDMA0_CORE_CTX_SRC_OFFSET_HI,
151 mmPDMA0_CORE_CTX_DST_TSIZE_0,
152 mmPDMA0_CORE_CTX_DST_TSIZE_1,
153 mmPDMA0_CORE_CTX_DST_TSIZE_2,
154 mmPDMA0_CORE_CTX_DST_TSIZE_3,
155 mmPDMA0_CORE_CTX_DST_TSIZE_4,
156 mmPDMA0_CORE_CTX_DST_STRIDE_1,
157 mmPDMA0_CORE_CTX_DST_STRIDE_2,
158 mmPDMA0_CORE_CTX_DST_STRIDE_3,
159 mmPDMA0_CORE_CTX_DST_STRIDE_4,
160 mmPDMA0_CORE_CTX_DST_OFFSET_LO,
161 mmPDMA0_CORE_CTX_DST_OFFSET_HI,
162 mmPDMA0_CORE_CTX_COMMIT,
163 mmPDMA0_CORE_CTX_CTRL,
164 mmPDMA0_CORE_CTX_TE_NUMROWS,
165 mmPDMA0_CORE_CTX_IDX,
166 mmPDMA0_CORE_CTX_IDX_INC,
167 mmPDMA0_QM_CQ_CFG0_0,
168 mmPDMA0_QM_CQ_CFG0_1,
169 mmPDMA0_QM_CQ_CFG0_2,
170 mmPDMA0_QM_CQ_CFG0_3,
171 mmPDMA0_QM_CQ_CFG0_4,
172 mmPDMA0_QM_CP_FENCE0_RDATA_0,
173 mmPDMA0_QM_CP_FENCE0_RDATA_1,
174 mmPDMA0_QM_CP_FENCE0_RDATA_2,
175 mmPDMA0_QM_CP_FENCE0_RDATA_3,
176 mmPDMA0_QM_CP_FENCE0_RDATA_4,
177 mmPDMA0_QM_CP_FENCE1_RDATA_0,
178 mmPDMA0_QM_CP_FENCE1_RDATA_1,
179 mmPDMA0_QM_CP_FENCE1_RDATA_2,
180 mmPDMA0_QM_CP_FENCE1_RDATA_3,
181 mmPDMA0_QM_CP_FENCE1_RDATA_4,
182 mmPDMA0_QM_CP_FENCE2_RDATA_0,
183 mmPDMA0_QM_CP_FENCE2_RDATA_1,
184 mmPDMA0_QM_CP_FENCE2_RDATA_2,
185 mmPDMA0_QM_CP_FENCE2_RDATA_3,
186 mmPDMA0_QM_CP_FENCE2_RDATA_4,
187 mmPDMA0_QM_CP_FENCE3_RDATA_0,
188 mmPDMA0_QM_CP_FENCE3_RDATA_1,
189 mmPDMA0_QM_CP_FENCE3_RDATA_2,
190 mmPDMA0_QM_CP_FENCE3_RDATA_3,
191 mmPDMA0_QM_CP_FENCE3_RDATA_4,
192 mmPDMA0_QM_CP_FENCE0_CNT_0,
193 mmPDMA0_QM_CP_FENCE0_CNT_1,
194 mmPDMA0_QM_CP_FENCE0_CNT_2,
195 mmPDMA0_QM_CP_FENCE0_CNT_3,
196 mmPDMA0_QM_CP_FENCE0_CNT_4,
197 mmPDMA0_QM_CP_FENCE1_CNT_0,
198 mmPDMA0_QM_CP_FENCE1_CNT_1,
199 mmPDMA0_QM_CP_FENCE1_CNT_2,
200 mmPDMA0_QM_CP_FENCE1_CNT_3,
201 mmPDMA0_QM_CP_FENCE1_CNT_4,
202 mmPDMA0_QM_CP_FENCE2_CNT_0,
203 mmPDMA0_QM_CP_FENCE2_CNT_1,
204 mmPDMA0_QM_CP_FENCE2_CNT_2,
205 mmPDMA0_QM_CP_FENCE2_CNT_3,
206 mmPDMA0_QM_CP_FENCE2_CNT_4,
207 mmPDMA0_QM_CP_FENCE3_CNT_0,
208 mmPDMA0_QM_CP_FENCE3_CNT_1,
209 mmPDMA0_QM_CP_FENCE3_CNT_2,
210 mmPDMA0_QM_CP_FENCE3_CNT_3,
211 mmPDMA0_QM_CP_FENCE3_CNT_4,
212 mmPDMA0_QM_CQ_PTR_LO_0,
213 mmPDMA0_QM_CQ_PTR_HI_0,
214 mmPDMA0_QM_CQ_TSIZE_0,
215 mmPDMA0_QM_CQ_CTL_0,
216 mmPDMA0_QM_CQ_PTR_LO_1,
217 mmPDMA0_QM_CQ_PTR_HI_1,
218 mmPDMA0_QM_CQ_TSIZE_1,
219 mmPDMA0_QM_CQ_CTL_1,
220 mmPDMA0_QM_CQ_PTR_LO_2,
221 mmPDMA0_QM_CQ_PTR_HI_2,
222 mmPDMA0_QM_CQ_TSIZE_2,
223 mmPDMA0_QM_CQ_CTL_2,
224 mmPDMA0_QM_CQ_PTR_LO_3,
225 mmPDMA0_QM_CQ_PTR_HI_3,
226 mmPDMA0_QM_CQ_TSIZE_3,
227 mmPDMA0_QM_CQ_CTL_3,
228 mmPDMA0_QM_CQ_PTR_LO_4,
229 mmPDMA0_QM_CQ_PTR_HI_4,
230 mmPDMA0_QM_CQ_TSIZE_4,
231 mmPDMA0_QM_CQ_CTL_4,
232 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
233 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
234 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
235 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
236 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
237 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
238 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
239 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
240 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
241 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
242 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
243 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
244 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
245 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
246 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
247 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
248 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
249 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
250 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
251 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
252 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
253 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
254 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
255 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
256 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
257 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
258 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
259 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
260 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
261 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
262 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
263 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
264 mmPDMA0_QM_ARC_CQ_PTR_LO,
265 mmPDMA0_QM_ARC_CQ_PTR_LO_STS,
266 mmPDMA0_QM_ARC_CQ_PTR_HI,
267 mmPDMA0_QM_ARC_CQ_PTR_HI_STS,
268 mmPDMA0_QM_ARB_CFG_0,
269 mmPDMA0_QM_ARB_MST_QUIET_PER,
270 mmPDMA0_QM_ARB_CHOICE_Q_PUSH,
271 mmPDMA0_QM_ARB_WRR_WEIGHT_0,
272 mmPDMA0_QM_ARB_WRR_WEIGHT_1,
273 mmPDMA0_QM_ARB_WRR_WEIGHT_2,
274 mmPDMA0_QM_ARB_WRR_WEIGHT_3,
275 mmPDMA0_QM_ARB_BASE_LO,
276 mmPDMA0_QM_ARB_BASE_HI,
277 mmPDMA0_QM_ARB_MST_SLAVE_EN,
278 mmPDMA0_QM_ARB_MST_SLAVE_EN_1,
279 mmPDMA0_QM_ARB_MST_CRED_INC,
280 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
281 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
282 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
283 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
284 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
285 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
286 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
287 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
288 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
289 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
290 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
291 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
292 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
293 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
294 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
295 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
296 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
297 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
298 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
299 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
300 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
301 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
302 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
303 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
304 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
305 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
306 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
307 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
308 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
309 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
310 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
311 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
312 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
313 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
314 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
315 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
316 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
317 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
318 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
319 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
320 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
321 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
322 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
323 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
324 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
325 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
326 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
327 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
328 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
329 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
330 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
331 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
332 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
333 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
334 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
335 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
336 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
337 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
338 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
339 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
340 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
341 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
342 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
343 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
344 mmPDMA0_QM_ARB_SLV_ID,
345 mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
346 mmPDMA0_QM_ARC_CQ_CFG0,
347 mmPDMA0_QM_CQ_IFIFO_CI_0,
348 mmPDMA0_QM_CQ_IFIFO_CI_1,
349 mmPDMA0_QM_CQ_IFIFO_CI_2,
350 mmPDMA0_QM_CQ_IFIFO_CI_3,
351 mmPDMA0_QM_CQ_IFIFO_CI_4,
352 mmPDMA0_QM_ARC_CQ_IFIFO_CI,
353 mmPDMA0_QM_CQ_CTL_CI_0,
354 mmPDMA0_QM_CQ_CTL_CI_1,
355 mmPDMA0_QM_CQ_CTL_CI_2,
356 mmPDMA0_QM_CQ_CTL_CI_3,
357 mmPDMA0_QM_CQ_CTL_CI_4,
358 mmPDMA0_QM_ARC_CQ_CTL_CI,
359 mmPDMA0_QM_ARC_CQ_TSIZE,
360 mmPDMA0_QM_ARC_CQ_CTL,
361 mmPDMA0_QM_CP_SWITCH_WD_SET,
362 mmPDMA0_QM_CP_EXT_SWITCH,
363 mmPDMA0_QM_CP_PRED_0,
364 mmPDMA0_QM_CP_PRED_1,
365 mmPDMA0_QM_CP_PRED_2,
366 mmPDMA0_QM_CP_PRED_3,
367 mmPDMA0_QM_CP_PRED_4,
368 mmPDMA0_QM_CP_PRED_UPEN_0,
369 mmPDMA0_QM_CP_PRED_UPEN_1,
370 mmPDMA0_QM_CP_PRED_UPEN_2,
371 mmPDMA0_QM_CP_PRED_UPEN_3,
372 mmPDMA0_QM_CP_PRED_UPEN_4,
373 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
374 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
375 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
376 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
377 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
378 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
379 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
380 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
381 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
382 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
383 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
384 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
385 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
386 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
387 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
388 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
389 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
390 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
391 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
392 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
393 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
394 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
395 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
396 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
397 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
398 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
399 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
400 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
401 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
402 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
403 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
404 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
405 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
406 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
407 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
408 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
409 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
410 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
411 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
412 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
413 mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
414 mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
415 mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
416 mmPDMA0_QM_CQ_CTL_MSG_BASE_LO
417 };
418
419 static const u32 gaudi2_pb_dcr0_edma0[] = {
420 mmDCORE0_EDMA0_CORE_BASE,
421 mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
422 mmDCORE0_EDMA0_QM_BASE,
423 };
424
425 static const u32 gaudi2_pb_dcr0_edma0_arc[] = {
426 mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
427 };
428
429 static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {
430 {mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},
431 {mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
432 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},
433 {mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
434 {mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,
435 mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
436 {mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,
437 mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
438 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
439 mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
440 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
441 mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
442 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
443 mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
444 };
445
446 static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {
447 mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
448 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,
449 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,
450 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,
451 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,
452 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,
453 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,
454 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,
455 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,
456 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,
457 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,
458 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,
459 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,
460 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,
461 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,
462 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,
463 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,
464 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,
465 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,
466 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,
467 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,
468 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,
469 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,
470 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,
471 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,
472 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,
473 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,
474 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,
475 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,
476 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,
477 mmDCORE0_EDMA0_CORE_CTX_COMMIT,
478 mmDCORE0_EDMA0_CORE_CTX_CTRL,
479 mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,
480 mmDCORE0_EDMA0_CORE_CTX_IDX,
481 mmDCORE0_EDMA0_CORE_CTX_IDX_INC,
482 mmDCORE0_EDMA0_QM_CQ_CFG0_0,
483 mmDCORE0_EDMA0_QM_CQ_CFG0_1,
484 mmDCORE0_EDMA0_QM_CQ_CFG0_2,
485 mmDCORE0_EDMA0_QM_CQ_CFG0_3,
486 mmDCORE0_EDMA0_QM_CQ_CFG0_4,
487 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,
488 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,
489 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,
490 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,
491 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,
492 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,
493 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,
494 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,
495 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,
496 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,
497 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,
498 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,
499 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,
500 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,
501 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,
502 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,
503 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,
504 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,
505 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,
506 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,
507 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,
508 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,
509 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,
510 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,
511 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,
512 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,
513 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,
514 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,
515 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,
516 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,
517 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,
518 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,
519 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,
520 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,
521 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,
522 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,
523 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,
524 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,
525 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,
526 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,
527 mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,
528 mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,
529 mmDCORE0_EDMA0_QM_CQ_TSIZE_0,
530 mmDCORE0_EDMA0_QM_CQ_CTL_0,
531 mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,
532 mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,
533 mmDCORE0_EDMA0_QM_CQ_TSIZE_1,
534 mmDCORE0_EDMA0_QM_CQ_CTL_1,
535 mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,
536 mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,
537 mmDCORE0_EDMA0_QM_CQ_TSIZE_2,
538 mmDCORE0_EDMA0_QM_CQ_CTL_2,
539 mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,
540 mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,
541 mmDCORE0_EDMA0_QM_CQ_TSIZE_3,
542 mmDCORE0_EDMA0_QM_CQ_CTL_3,
543 mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,
544 mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,
545 mmDCORE0_EDMA0_QM_CQ_TSIZE_4,
546 mmDCORE0_EDMA0_QM_CQ_CTL_4,
547 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
548 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
549 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
550 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
551 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
552 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
553 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
554 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
555 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
556 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
557 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
558 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
559 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
560 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
561 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
562 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
563 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
564 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
565 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
566 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
567 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
568 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
569 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
570 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
571 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
572 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
573 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
574 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
575 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
576 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
577 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
578 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
579 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,
580 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,
581 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,
582 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,
583 mmDCORE0_EDMA0_QM_ARB_CFG_0,
584 mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,
585 mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,
586 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,
587 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,
588 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,
589 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,
590 mmDCORE0_EDMA0_QM_ARB_BASE_LO,
591 mmDCORE0_EDMA0_QM_ARB_BASE_HI,
592 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,
593 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,
594 mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,
595 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
596 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
597 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
598 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
599 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
600 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
601 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
602 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
603 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
604 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
605 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
606 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
607 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
608 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
609 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
610 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
611 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
612 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
613 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
614 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
615 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
616 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
617 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
618 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
619 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
620 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
621 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
622 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
623 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
624 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
625 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
626 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
627 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
628 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
629 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
630 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
631 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
632 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
633 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
634 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
635 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
636 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
637 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
638 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
639 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
640 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
641 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
642 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
643 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
644 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
645 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
646 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
647 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
648 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
649 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
650 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
651 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
652 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
653 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
654 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
655 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
656 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
657 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
658 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
659 mmDCORE0_EDMA0_QM_ARB_SLV_ID,
660 mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
661 mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,
662 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,
663 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,
664 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,
665 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,
666 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,
667 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,
668 mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,
669 mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,
670 mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,
671 mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,
672 mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,
673 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,
674 mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,
675 mmDCORE0_EDMA0_QM_ARC_CQ_CTL,
676 mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,
677 mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,
678 mmDCORE0_EDMA0_QM_CP_PRED_0,
679 mmDCORE0_EDMA0_QM_CP_PRED_1,
680 mmDCORE0_EDMA0_QM_CP_PRED_2,
681 mmDCORE0_EDMA0_QM_CP_PRED_3,
682 mmDCORE0_EDMA0_QM_CP_PRED_4,
683 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,
684 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,
685 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,
686 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,
687 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,
688 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
689 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
690 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
691 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
692 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
693 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
694 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
695 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
696 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
697 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
698 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
699 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
700 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
701 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
702 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
703 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
704 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
705 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
706 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
707 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
708 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
709 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
710 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
711 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
712 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
713 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
714 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
715 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
716 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
717 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
718 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
719 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
720 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
721 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
722 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
723 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
724 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
725 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
726 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
727 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
728 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
729 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
730 mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
731 mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO
732 };
733
734 static const u32 gaudi2_pb_dcr0_mme_sbte[] = {
735 mmDCORE0_MME_SBTE0_BASE,
736 mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,
737 };
738
739 static const u32 gaudi2_pb_dcr0_mme_qm[] = {
740 mmDCORE0_MME_QM_BASE,
741 };
742
743 static const u32 gaudi2_pb_dcr0_mme_eng[] = {
744 mmDCORE0_MME_ACC_BASE,
745 mmDCORE0_MME_CTRL_HI_BASE,
746 mmDCORE0_MME_CTRL_LO_BASE,
747 mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,
748 mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,
749 mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,
750 };
751
752 static const u32 gaudi2_pb_dcr0_mme_arc[] = {
753 mmDCORE0_MME_QM_ARC_AUX_BASE,
754 mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,
755 };
756
757 static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {
758 {mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},
759 {mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},
760 {mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},
761 {mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
762 {mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
763 {mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
764 {mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
765 mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
766 {mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
767 mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
768 {mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
769 mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
770 {mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,
771 mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},
772 {mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,
773 mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},
774 };
775
776 static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {
777 mmDCORE0_MME_QM_CQ_CFG0_0,
778 mmDCORE0_MME_QM_CQ_CFG0_1,
779 mmDCORE0_MME_QM_CQ_CFG0_2,
780 mmDCORE0_MME_QM_CQ_CFG0_3,
781 mmDCORE0_MME_QM_CQ_CFG0_4,
782 mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,
783 mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,
784 mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,
785 mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,
786 mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,
787 mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,
788 mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,
789 mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,
790 mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,
791 mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,
792 mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,
793 mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,
794 mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,
795 mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,
796 mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,
797 mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,
798 mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,
799 mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,
800 mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,
801 mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,
802 mmDCORE0_MME_QM_CP_FENCE0_CNT_0,
803 mmDCORE0_MME_QM_CP_FENCE0_CNT_1,
804 mmDCORE0_MME_QM_CP_FENCE0_CNT_2,
805 mmDCORE0_MME_QM_CP_FENCE0_CNT_3,
806 mmDCORE0_MME_QM_CP_FENCE0_CNT_4,
807 mmDCORE0_MME_QM_CP_FENCE1_CNT_0,
808 mmDCORE0_MME_QM_CP_FENCE1_CNT_1,
809 mmDCORE0_MME_QM_CP_FENCE1_CNT_2,
810 mmDCORE0_MME_QM_CP_FENCE1_CNT_3,
811 mmDCORE0_MME_QM_CP_FENCE1_CNT_4,
812 mmDCORE0_MME_QM_CP_FENCE2_CNT_0,
813 mmDCORE0_MME_QM_CP_FENCE2_CNT_1,
814 mmDCORE0_MME_QM_CP_FENCE2_CNT_2,
815 mmDCORE0_MME_QM_CP_FENCE2_CNT_3,
816 mmDCORE0_MME_QM_CP_FENCE2_CNT_4,
817 mmDCORE0_MME_QM_CP_FENCE3_CNT_0,
818 mmDCORE0_MME_QM_CP_FENCE3_CNT_1,
819 mmDCORE0_MME_QM_CP_FENCE3_CNT_2,
820 mmDCORE0_MME_QM_CP_FENCE3_CNT_3,
821 mmDCORE0_MME_QM_CP_FENCE3_CNT_4,
822 mmDCORE0_MME_QM_CQ_PTR_LO_0,
823 mmDCORE0_MME_QM_CQ_PTR_HI_0,
824 mmDCORE0_MME_QM_CQ_TSIZE_0,
825 mmDCORE0_MME_QM_CQ_CTL_0,
826 mmDCORE0_MME_QM_CQ_PTR_LO_1,
827 mmDCORE0_MME_QM_CQ_PTR_HI_1,
828 mmDCORE0_MME_QM_CQ_TSIZE_1,
829 mmDCORE0_MME_QM_CQ_CTL_1,
830 mmDCORE0_MME_QM_CQ_PTR_LO_2,
831 mmDCORE0_MME_QM_CQ_PTR_HI_2,
832 mmDCORE0_MME_QM_CQ_TSIZE_2,
833 mmDCORE0_MME_QM_CQ_CTL_2,
834 mmDCORE0_MME_QM_CQ_PTR_LO_3,
835 mmDCORE0_MME_QM_CQ_PTR_HI_3,
836 mmDCORE0_MME_QM_CQ_TSIZE_3,
837 mmDCORE0_MME_QM_CQ_CTL_3,
838 mmDCORE0_MME_QM_CQ_PTR_LO_4,
839 mmDCORE0_MME_QM_CQ_PTR_HI_4,
840 mmDCORE0_MME_QM_CQ_TSIZE_4,
841 mmDCORE0_MME_QM_CQ_CTL_4,
842 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,
843 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
844 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,
845 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
846 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,
847 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
848 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,
849 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
850 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,
851 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
852 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,
853 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
854 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,
855 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
856 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,
857 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
858 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,
859 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
860 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,
861 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
862 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,
863 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
864 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,
865 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
866 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,
867 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
868 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,
869 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
870 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,
871 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
872 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,
873 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
874 mmDCORE0_MME_QM_ARC_CQ_PTR_LO,
875 mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,
876 mmDCORE0_MME_QM_ARC_CQ_PTR_HI,
877 mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,
878 mmDCORE0_MME_QM_ARB_CFG_0,
879 mmDCORE0_MME_QM_ARB_MST_QUIET_PER,
880 mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,
881 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,
882 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,
883 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,
884 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,
885 mmDCORE0_MME_QM_ARB_BASE_LO,
886 mmDCORE0_MME_QM_ARB_BASE_HI,
887 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,
888 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,
889 mmDCORE0_MME_QM_ARB_MST_CRED_INC,
890 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,
891 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,
892 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,
893 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,
894 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,
895 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,
896 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,
897 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,
898 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,
899 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,
900 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,
901 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,
902 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,
903 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,
904 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,
905 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,
906 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,
907 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,
908 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,
909 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,
910 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,
911 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,
912 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,
913 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,
914 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,
915 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,
916 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,
917 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,
918 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,
919 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,
920 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,
921 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,
922 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,
923 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,
924 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,
925 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,
926 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,
927 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,
928 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,
929 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,
930 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,
931 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,
932 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,
933 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,
934 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,
935 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,
936 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,
937 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,
938 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,
939 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,
940 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,
941 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,
942 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,
943 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,
944 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,
945 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,
946 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,
947 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,
948 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,
949 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,
950 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,
951 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,
952 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,
953 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,
954 mmDCORE0_MME_QM_ARB_SLV_ID,
955 mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,
956 mmDCORE0_MME_QM_ARC_CQ_CFG0,
957 mmDCORE0_MME_QM_CQ_IFIFO_CI_0,
958 mmDCORE0_MME_QM_CQ_IFIFO_CI_1,
959 mmDCORE0_MME_QM_CQ_IFIFO_CI_2,
960 mmDCORE0_MME_QM_CQ_IFIFO_CI_3,
961 mmDCORE0_MME_QM_CQ_IFIFO_CI_4,
962 mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,
963 mmDCORE0_MME_QM_CQ_CTL_CI_0,
964 mmDCORE0_MME_QM_CQ_CTL_CI_1,
965 mmDCORE0_MME_QM_CQ_CTL_CI_2,
966 mmDCORE0_MME_QM_CQ_CTL_CI_3,
967 mmDCORE0_MME_QM_CQ_CTL_CI_4,
968 mmDCORE0_MME_QM_ARC_CQ_CTL_CI,
969 mmDCORE0_MME_QM_ARC_CQ_TSIZE,
970 mmDCORE0_MME_QM_ARC_CQ_CTL,
971 mmDCORE0_MME_QM_CP_SWITCH_WD_SET,
972 mmDCORE0_MME_QM_CP_EXT_SWITCH,
973 mmDCORE0_MME_QM_CP_PRED_0,
974 mmDCORE0_MME_QM_CP_PRED_1,
975 mmDCORE0_MME_QM_CP_PRED_2,
976 mmDCORE0_MME_QM_CP_PRED_3,
977 mmDCORE0_MME_QM_CP_PRED_4,
978 mmDCORE0_MME_QM_CP_PRED_UPEN_0,
979 mmDCORE0_MME_QM_CP_PRED_UPEN_1,
980 mmDCORE0_MME_QM_CP_PRED_UPEN_2,
981 mmDCORE0_MME_QM_CP_PRED_UPEN_3,
982 mmDCORE0_MME_QM_CP_PRED_UPEN_4,
983 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,
984 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,
985 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,
986 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,
987 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,
988 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,
989 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,
990 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,
991 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,
992 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,
993 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,
994 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,
995 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,
996 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,
997 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,
998 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,
999 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,
1000 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,
1001 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,
1002 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,
1003 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,
1004 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,
1005 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,
1006 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,
1007 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,
1008 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,
1009 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,
1010 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,
1011 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,
1012 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,
1013 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,
1014 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,
1015 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,
1016 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,
1017 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,
1018 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,
1019 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,
1020 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,
1021 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,
1022 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,
1023 mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1024 mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,
1025 mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,
1026 mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO
1027 };
1028
1029 static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {
1030 mmDCORE0_MME_CTRL_LO_CMD,
1031 mmDCORE0_MME_CTRL_LO_AGU,
1032 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,
1033 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,
1034 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,
1035 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,
1036 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,
1037 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,
1038 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,
1039 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,
1040 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,
1041 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,
1042 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,
1043 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,
1044 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,
1045 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,
1046 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,
1047 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,
1048 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,
1049 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,
1050 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,
1051 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,
1052 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,
1053 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,
1054 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,
1055 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,
1056 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,
1057 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,
1058 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,
1059 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,
1060 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,
1061 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,
1062 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,
1063 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,
1064 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,
1065 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,
1066 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,
1067 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,
1068 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,
1069 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,
1070 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,
1071 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,
1072 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,
1073 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,
1074 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,
1075 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,
1076 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,
1077 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,
1078 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,
1079 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,
1080 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,
1081 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,
1082 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,
1083 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,
1084 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,
1085 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,
1086 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,
1087 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,
1088 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,
1089 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,
1090 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,
1091 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,
1092 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,
1093 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,
1094 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,
1095 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,
1096 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,
1097 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,
1098 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,
1099 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,
1100 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,
1101 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,
1102 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,
1103 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,
1104 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,
1105 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,
1106 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,
1107 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,
1108 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,
1109 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,
1110 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,
1111 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,
1112 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,
1113 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,
1114 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,
1115 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,
1116 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,
1117 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,
1118 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,
1119 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,
1120 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,
1121 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,
1122 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,
1123 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,
1124 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,
1125 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,
1126 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,
1127 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,
1128 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,
1129 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,
1130 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,
1131 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,
1132 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,
1133 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,
1134 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,
1135 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,
1136 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,
1137 mmDCORE0_MME_CTRL_LO_ARCH_STATUS,
1138 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,
1139 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,
1140 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,
1141 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,
1142 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,
1143 mmDCORE0_MME_CTRL_LO_ARCH_A_SS,
1144 mmDCORE0_MME_CTRL_LO_ARCH_B_SS,
1145 mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,
1146 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,
1147 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,
1148 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,
1149 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,
1150 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,
1151 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,
1152 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,
1153 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,
1154 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,
1155 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,
1156 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,
1157 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,
1158 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,
1159 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,
1160 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,
1161 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,
1162 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,
1163 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,
1164 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,
1165 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,
1166 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,
1167 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,
1168 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,
1169 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,
1170 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,
1171 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,
1172 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,
1173 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,
1174 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,
1175 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,
1176 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,
1177 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,
1178 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,
1179 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,
1180 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,
1181 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,
1182 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,
1183 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,
1184 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,
1185 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,
1186 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,
1187 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,
1188 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,
1189 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,
1190 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,
1191 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,
1192 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,
1193 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,
1194 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,
1195 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,
1196 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,
1197 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,
1198 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,
1199 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,
1200 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,
1201 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,
1202 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,
1203 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,
1204 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,
1205 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,
1206 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,
1207 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,
1208 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,
1209 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,
1210 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,
1211 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,
1212 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,
1213 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,
1214 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,
1215 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,
1216 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,
1217 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,
1218 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,
1219 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,
1220 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,
1221 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,
1222 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,
1223 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,
1224 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,
1225 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,
1226 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,
1227 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,
1228 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,
1229 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,
1230 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,
1231 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,
1232 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,
1233 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,
1234 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,
1235 mmDCORE0_MME_ACC_AP_LFSR_POLY,
1236 mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,
1237 mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,
1238 mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,
1239 mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,
1240 mmDCORE0_MME_ACC_WBC_SRC_BP,
1241 };
1242
1243 static const u32 gaudi2_pb_dcr0_tpc0[] = {
1244 mmDCORE0_TPC0_QM_BASE,
1245 mmDCORE0_TPC0_CFG_BASE,
1246 mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,
1247 };
1248
1249 static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {
1250 mmDCORE0_TPC0_QM_ARC_AUX_BASE,
1251 };
1252
1253 static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {
1254 {mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},
1255 {mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},
1256 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},
1257 {mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
1258 {mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
1259 {mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
1260 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
1261 mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
1262 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
1263 mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
1264 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
1265 mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
1266 };
1267
1268 static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {
1269 mmDCORE0_TPC0_QM_CQ_CFG0_0,
1270 mmDCORE0_TPC0_QM_CQ_CFG0_1,
1271 mmDCORE0_TPC0_QM_CQ_CFG0_2,
1272 mmDCORE0_TPC0_QM_CQ_CFG0_3,
1273 mmDCORE0_TPC0_QM_CQ_CFG0_4,
1274 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,
1275 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,
1276 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,
1277 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,
1278 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,
1279 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,
1280 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,
1281 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,
1282 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,
1283 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,
1284 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,
1285 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,
1286 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,
1287 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,
1288 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,
1289 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,
1290 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,
1291 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,
1292 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,
1293 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,
1294 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,
1295 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,
1296 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,
1297 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,
1298 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,
1299 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,
1300 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,
1301 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,
1302 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,
1303 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,
1304 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,
1305 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,
1306 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,
1307 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,
1308 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,
1309 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,
1310 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,
1311 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,
1312 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,
1313 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,
1314 mmDCORE0_TPC0_QM_CQ_PTR_LO_0,
1315 mmDCORE0_TPC0_QM_CQ_PTR_HI_0,
1316 mmDCORE0_TPC0_QM_CQ_TSIZE_0,
1317 mmDCORE0_TPC0_QM_CQ_CTL_0,
1318 mmDCORE0_TPC0_QM_CQ_PTR_LO_1,
1319 mmDCORE0_TPC0_QM_CQ_PTR_HI_1,
1320 mmDCORE0_TPC0_QM_CQ_TSIZE_1,
1321 mmDCORE0_TPC0_QM_CQ_CTL_1,
1322 mmDCORE0_TPC0_QM_CQ_PTR_LO_2,
1323 mmDCORE0_TPC0_QM_CQ_PTR_HI_2,
1324 mmDCORE0_TPC0_QM_CQ_TSIZE_2,
1325 mmDCORE0_TPC0_QM_CQ_CTL_2,
1326 mmDCORE0_TPC0_QM_CQ_PTR_LO_3,
1327 mmDCORE0_TPC0_QM_CQ_PTR_HI_3,
1328 mmDCORE0_TPC0_QM_CQ_TSIZE_3,
1329 mmDCORE0_TPC0_QM_CQ_CTL_3,
1330 mmDCORE0_TPC0_QM_CQ_PTR_LO_4,
1331 mmDCORE0_TPC0_QM_CQ_PTR_HI_4,
1332 mmDCORE0_TPC0_QM_CQ_TSIZE_4,
1333 mmDCORE0_TPC0_QM_CQ_CTL_4,
1334 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,
1335 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
1336 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,
1337 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
1338 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,
1339 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
1340 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,
1341 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
1342 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,
1343 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
1344 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,
1345 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
1346 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,
1347 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
1348 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,
1349 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
1350 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,
1351 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
1352 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,
1353 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
1354 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,
1355 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
1356 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,
1357 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
1358 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,
1359 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
1360 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,
1361 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
1362 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,
1363 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
1364 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,
1365 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
1366 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,
1367 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,
1368 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,
1369 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,
1370 mmDCORE0_TPC0_QM_ARB_CFG_0,
1371 mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,
1372 mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,
1373 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,
1374 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,
1375 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,
1376 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,
1377 mmDCORE0_TPC0_QM_ARB_BASE_LO,
1378 mmDCORE0_TPC0_QM_ARB_BASE_HI,
1379 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,
1380 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,
1381 mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,
1382 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
1383 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
1384 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
1385 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
1386 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
1387 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
1388 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
1389 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
1390 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
1391 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
1392 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
1393 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
1394 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
1395 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
1396 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
1397 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
1398 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
1399 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
1400 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
1401 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
1402 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
1403 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
1404 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
1405 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
1406 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
1407 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
1408 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
1409 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
1410 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
1411 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
1412 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
1413 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
1414 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
1415 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
1416 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
1417 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
1418 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
1419 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
1420 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
1421 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
1422 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
1423 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
1424 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
1425 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
1426 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
1427 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
1428 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
1429 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
1430 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
1431 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
1432 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
1433 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
1434 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
1435 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
1436 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
1437 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
1438 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
1439 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
1440 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
1441 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
1442 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
1443 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
1444 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
1445 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
1446 mmDCORE0_TPC0_QM_ARB_SLV_ID,
1447 mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
1448 mmDCORE0_TPC0_QM_ARC_CQ_CFG0,
1449 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,
1450 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,
1451 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,
1452 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,
1453 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,
1454 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,
1455 mmDCORE0_TPC0_QM_CQ_CTL_CI_0,
1456 mmDCORE0_TPC0_QM_CQ_CTL_CI_1,
1457 mmDCORE0_TPC0_QM_CQ_CTL_CI_2,
1458 mmDCORE0_TPC0_QM_CQ_CTL_CI_3,
1459 mmDCORE0_TPC0_QM_CQ_CTL_CI_4,
1460 mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,
1461 mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,
1462 mmDCORE0_TPC0_QM_ARC_CQ_CTL,
1463 mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,
1464 mmDCORE0_TPC0_QM_CP_EXT_SWITCH,
1465 mmDCORE0_TPC0_QM_CP_PRED_0,
1466 mmDCORE0_TPC0_QM_CP_PRED_1,
1467 mmDCORE0_TPC0_QM_CP_PRED_2,
1468 mmDCORE0_TPC0_QM_CP_PRED_3,
1469 mmDCORE0_TPC0_QM_CP_PRED_4,
1470 mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,
1471 mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,
1472 mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,
1473 mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,
1474 mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,
1475 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,
1476 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,
1477 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,
1478 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,
1479 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,
1480 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,
1481 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,
1482 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,
1483 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,
1484 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,
1485 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,
1486 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,
1487 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,
1488 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,
1489 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,
1490 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,
1491 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,
1492 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,
1493 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,
1494 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,
1495 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,
1496 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,
1497 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,
1498 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,
1499 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,
1500 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,
1501 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,
1502 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,
1503 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,
1504 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,
1505 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,
1506 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,
1507 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,
1508 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,
1509 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,
1510 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,
1511 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,
1512 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,
1513 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,
1514 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,
1515 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1516 mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,
1517 mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,
1518 mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,
1519 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,
1520 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,
1521 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,
1522 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,
1523 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,
1524 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,
1525 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,
1526 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,
1527 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,
1528 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,
1529 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,
1530 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,
1531 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,
1532 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,
1533 mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,
1534 mmDCORE0_TPC0_CFG_QM_KERNEL_ID,
1535 mmDCORE0_TPC0_CFG_QM_POWER_LOOP,
1536 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,
1537 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,
1538 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,
1539 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,
1540 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,
1541 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,
1542 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,
1543 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,
1544 mmDCORE0_TPC0_CFG_ROUND_CSR,
1545 mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,
1546 mmDCORE0_TPC0_CFG_SEMAPHORE,
1547 mmDCORE0_TPC0_CFG_LFSR_POLYNOM,
1548 mmDCORE0_TPC0_CFG_STATUS,
1549 mmDCORE0_TPC0_CFG_TPC_CMD,
1550 mmDCORE0_TPC0_CFG_TPC_EXECUTE,
1551 mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,
1552 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,
1553 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,
1554 mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,
1555 mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,
1556 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,
1557 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,
1558 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,
1559 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,
1560 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,
1561 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,
1562 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,
1563 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,
1564 mmDCORE0_TPC0_CFG_KERNEL_SRF_0,
1565 mmDCORE0_TPC0_CFG_KERNEL_SRF_1,
1566 mmDCORE0_TPC0_CFG_KERNEL_SRF_2,
1567 mmDCORE0_TPC0_CFG_KERNEL_SRF_3,
1568 mmDCORE0_TPC0_CFG_KERNEL_SRF_4,
1569 mmDCORE0_TPC0_CFG_KERNEL_SRF_5,
1570 mmDCORE0_TPC0_CFG_KERNEL_SRF_6,
1571 mmDCORE0_TPC0_CFG_KERNEL_SRF_7,
1572 mmDCORE0_TPC0_CFG_KERNEL_SRF_8,
1573 mmDCORE0_TPC0_CFG_KERNEL_SRF_9,
1574 mmDCORE0_TPC0_CFG_KERNEL_SRF_10,
1575 mmDCORE0_TPC0_CFG_KERNEL_SRF_11,
1576 mmDCORE0_TPC0_CFG_KERNEL_SRF_12,
1577 mmDCORE0_TPC0_CFG_KERNEL_SRF_13,
1578 mmDCORE0_TPC0_CFG_KERNEL_SRF_14,
1579 mmDCORE0_TPC0_CFG_KERNEL_SRF_15,
1580 mmDCORE0_TPC0_CFG_KERNEL_SRF_16,
1581 mmDCORE0_TPC0_CFG_KERNEL_SRF_17,
1582 mmDCORE0_TPC0_CFG_KERNEL_SRF_18,
1583 mmDCORE0_TPC0_CFG_KERNEL_SRF_19,
1584 mmDCORE0_TPC0_CFG_KERNEL_SRF_20,
1585 mmDCORE0_TPC0_CFG_KERNEL_SRF_21,
1586 mmDCORE0_TPC0_CFG_KERNEL_SRF_22,
1587 mmDCORE0_TPC0_CFG_KERNEL_SRF_23,
1588 mmDCORE0_TPC0_CFG_KERNEL_SRF_24,
1589 mmDCORE0_TPC0_CFG_KERNEL_SRF_25,
1590 mmDCORE0_TPC0_CFG_KERNEL_SRF_26,
1591 mmDCORE0_TPC0_CFG_KERNEL_SRF_27,
1592 mmDCORE0_TPC0_CFG_KERNEL_SRF_28,
1593 mmDCORE0_TPC0_CFG_KERNEL_SRF_29,
1594 mmDCORE0_TPC0_CFG_KERNEL_SRF_30,
1595 mmDCORE0_TPC0_CFG_KERNEL_SRF_31,
1596 mmDCORE0_TPC0_CFG_TPC_SB_L0CD,
1597 mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,
1598 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,
1599 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,
1600 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,
1601 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,
1602 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,
1603 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,
1604 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,
1605 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,
1606 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3
1607 };
1608
1609 static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {
1610 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,
1611 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,
1612 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,
1613 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,
1614 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,
1615 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,
1616 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,
1617 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,
1618 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,
1619 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,
1620 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,
1621 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,
1622 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,
1623 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,
1624 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,
1625 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1626 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1627 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1628 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1629 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1630 };
1631
1632 static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {
1633 mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,
1634 mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,
1635 mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,
1636 mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,
1637 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,
1638 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,
1639 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,
1640 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,
1641 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,
1642 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,
1643 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,
1644 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,
1645 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,
1646 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,
1647 mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,
1648 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1649 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1650 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1651 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1652 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1653 };
1654
1655 static const u32 gaudi2_pb_dcr0_sram0[] = {
1656 mmDCORE0_SRAM0_BANK_BASE,
1657 mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,
1658 mmDCORE0_SRAM0_RTR_BASE,
1659 };
1660
1661 static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {
1662 mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,
1663 };
1664
1665 static const u32 gaudi2_pb_dcr0_sm_glbl[] = {
1666 mmDCORE0_SYNC_MNGR_GLBL_BASE,
1667 };
1668
1669 static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
1670 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1671 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1672 {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1673 {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
1674 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1675 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1676 {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
1677 {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1678 };
1679
1680 static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {
1681 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1682 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1683 {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1684 {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
1685 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1686 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1687 {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
1688 {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1689 };
1690
1691 static const u32 gaudi2_pb_arc_sched[] = {
1692 mmARC_FARM_ARC0_AUX_BASE,
1693 mmARC_FARM_ARC0_DUP_ENG_BASE,
1694 mmARC_FARM_ARC0_ACP_ENG_BASE,
1695 };
1696
1697 static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {
1698 {mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},
1699 {mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},
1700 {mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},
1701 {mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},
1702 {mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},
1703 {mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},
1704 {mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},
1705 {mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},
1706 {mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},
1707 {mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},
1708 {mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},
1709 {mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},
1710 };
1711
1712 static const u32 gaudi2_pb_xbar_mid[] = {
1713 mmXBAR_MID_0_BASE,
1714 };
1715
1716 static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {
1717 mmXBAR_MID_0_UPSCALE,
1718 mmXBAR_MID_0_DOWN_CONV,
1719 mmXBAR_MID_0_DOWN_CONV_LFSR_EN,
1720 mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,
1721 mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,
1722 mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,
1723 };
1724
1725 static const u32 gaudi2_pb_xbar_edge[] = {
1726 mmXBAR_EDGE_0_BASE,
1727 };
1728
1729 static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {
1730 mmXBAR_EDGE_0_UPSCALE,
1731 mmXBAR_EDGE_0_DOWN_CONV,
1732 mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,
1733 mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,
1734 mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,
1735 mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,
1736 };
1737
1738 static const u32 gaudi2_pb_nic0[] = {
1739 mmNIC0_TMR_BASE,
1740 mmNIC0_RXB_CORE_BASE,
1741 mmNIC0_RXE0_BASE,
1742 mmNIC0_RXE1_BASE,
1743 mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,
1744 mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,
1745 mmNIC0_TXS0_BASE,
1746 mmNIC0_TXS1_BASE,
1747 mmNIC0_TXE0_BASE,
1748 mmNIC0_TXE1_BASE,
1749 mmNIC0_TXB_BASE,
1750 mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,
1751 };
1752
1753 static const u32 gaudi2_pb_nic0_qm_qpc[] = {
1754 mmNIC0_QM0_BASE,
1755 mmNIC0_QPC0_BASE,
1756 };
1757
1758 static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {
1759 mmNIC0_QM_ARC_AUX0_BASE,
1760 };
1761
1762 static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {
1763 {mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},
1764 {mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},
1765 {mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},
1766 {mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},
1767 {mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},
1768 {mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},
1769 {mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},
1770 {mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},
1771 };
1772
1773 static const u32 gaudi2_pb_nic0_umr[] = {
1774 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,
1775 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1776 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1777 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1778 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1779 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1780 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1781 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1782 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1783 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1784 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1785 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1786 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1787 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1788 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1789 };
1790
1791 static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {
1792 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,
1793 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},
1794 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1795 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},
1796 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1797 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},
1798 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1799 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},
1800 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1801 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},
1802 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1803 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},
1804 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1805 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},
1806 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1807 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},
1808 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1809 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},
1810 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1811 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},
1812 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1813 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},
1814 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1815 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},
1816 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1817 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},
1818 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1819 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},
1820 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1821 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},
1822 };
1823
1824 /*
1825 * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit
1826 * registers and since the user writes in bulks of 64 bits we need to un-secure
1827 * also the following 32 bits (that's why we added also the next 4 bytes to the
1828 * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes
1829 * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be
1830 * unsecured as well.
1831 */
1832 #define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)
1833 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)
1834 #define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60
1835
1836 static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {
1837 mmNIC0_QPC0_LINEAR_WQE_STATIC_0,
1838 mmNIC0_QPC0_LINEAR_WQE_STATIC_1,
1839 mmNIC0_QPC0_LINEAR_WQE_STATIC_2,
1840 mmNIC0_QPC0_LINEAR_WQE_STATIC_3,
1841 mmNIC0_QPC0_LINEAR_WQE_STATIC_4,
1842 mmNIC0_QPC0_LINEAR_WQE_STATIC_5,
1843 mmNIC0_QPC0_LINEAR_WQE_STATIC_6,
1844 mmNIC0_QPC0_LINEAR_WQE_STATIC_7,
1845 mmNIC0_QPC0_LINEAR_WQE_STATIC_8,
1846 mmNIC0_QPC0_LINEAR_WQE_STATIC_9,
1847 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,
1848 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,
1849 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,
1850 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,
1851 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,
1852 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,
1853 mmNIC0_QPC0_LINEAR_WQE_QPN,
1854 mmNIC0_QPC0_LINEAR_WQE_RSV,
1855 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,
1856 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,
1857 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,
1858 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,
1859 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,
1860 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,
1861 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,
1862 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,
1863 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,
1864 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,
1865 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,
1866 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,
1867 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,
1868 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,
1869 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,
1870 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,
1871 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,
1872 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,
1873 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,
1874 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,
1875 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,
1876 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,
1877 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,
1878 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,
1879 mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,
1880 mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,
1881 mmNIC0_QPC0_QMAN_DOORBELL,
1882 mmNIC0_QPC0_QMAN_DOORBELL_QPN,
1883 mmNIC0_QPC0_SPECIAL_GLBL_SPARE,
1884 mmNIC0_QM0_CQ_CFG0_0,
1885 mmNIC0_QM0_CQ_CFG0_1,
1886 mmNIC0_QM0_CQ_CFG0_2,
1887 mmNIC0_QM0_CQ_CFG0_3,
1888 mmNIC0_QM0_CQ_CFG0_4,
1889 mmNIC0_QM0_CP_FENCE0_RDATA_0,
1890 mmNIC0_QM0_CP_FENCE0_RDATA_1,
1891 mmNIC0_QM0_CP_FENCE0_RDATA_2,
1892 mmNIC0_QM0_CP_FENCE0_RDATA_3,
1893 mmNIC0_QM0_CP_FENCE0_RDATA_4,
1894 mmNIC0_QM0_CP_FENCE1_RDATA_0,
1895 mmNIC0_QM0_CP_FENCE1_RDATA_1,
1896 mmNIC0_QM0_CP_FENCE1_RDATA_2,
1897 mmNIC0_QM0_CP_FENCE1_RDATA_3,
1898 mmNIC0_QM0_CP_FENCE1_RDATA_4,
1899 mmNIC0_QM0_CP_FENCE2_RDATA_0,
1900 mmNIC0_QM0_CP_FENCE2_RDATA_1,
1901 mmNIC0_QM0_CP_FENCE2_RDATA_2,
1902 mmNIC0_QM0_CP_FENCE2_RDATA_3,
1903 mmNIC0_QM0_CP_FENCE2_RDATA_4,
1904 mmNIC0_QM0_CP_FENCE3_RDATA_0,
1905 mmNIC0_QM0_CP_FENCE3_RDATA_1,
1906 mmNIC0_QM0_CP_FENCE3_RDATA_2,
1907 mmNIC0_QM0_CP_FENCE3_RDATA_3,
1908 mmNIC0_QM0_CP_FENCE3_RDATA_4,
1909 mmNIC0_QM0_CP_FENCE0_CNT_0,
1910 mmNIC0_QM0_CP_FENCE0_CNT_1,
1911 mmNIC0_QM0_CP_FENCE0_CNT_2,
1912 mmNIC0_QM0_CP_FENCE0_CNT_3,
1913 mmNIC0_QM0_CP_FENCE0_CNT_4,
1914 mmNIC0_QM0_CP_FENCE1_CNT_0,
1915 mmNIC0_QM0_CP_FENCE1_CNT_1,
1916 mmNIC0_QM0_CP_FENCE1_CNT_2,
1917 mmNIC0_QM0_CP_FENCE1_CNT_3,
1918 mmNIC0_QM0_CP_FENCE1_CNT_4,
1919 mmNIC0_QM0_CP_FENCE2_CNT_0,
1920 mmNIC0_QM0_CP_FENCE2_CNT_1,
1921 mmNIC0_QM0_CP_FENCE2_CNT_2,
1922 mmNIC0_QM0_CP_FENCE2_CNT_3,
1923 mmNIC0_QM0_CP_FENCE2_CNT_4,
1924 mmNIC0_QM0_CP_FENCE3_CNT_0,
1925 mmNIC0_QM0_CP_FENCE3_CNT_1,
1926 mmNIC0_QM0_CP_FENCE3_CNT_2,
1927 mmNIC0_QM0_CP_FENCE3_CNT_3,
1928 mmNIC0_QM0_CP_FENCE3_CNT_4,
1929 mmNIC0_QM0_CQ_PTR_LO_0,
1930 mmNIC0_QM0_CQ_PTR_HI_0,
1931 mmNIC0_QM0_CQ_TSIZE_0,
1932 mmNIC0_QM0_CQ_CTL_0,
1933 mmNIC0_QM0_CQ_PTR_LO_1,
1934 mmNIC0_QM0_CQ_PTR_HI_1,
1935 mmNIC0_QM0_CQ_TSIZE_1,
1936 mmNIC0_QM0_CQ_CTL_1,
1937 mmNIC0_QM0_CQ_PTR_LO_2,
1938 mmNIC0_QM0_CQ_PTR_HI_2,
1939 mmNIC0_QM0_CQ_TSIZE_2,
1940 mmNIC0_QM0_CQ_CTL_2,
1941 mmNIC0_QM0_CQ_PTR_LO_3,
1942 mmNIC0_QM0_CQ_PTR_HI_3,
1943 mmNIC0_QM0_CQ_TSIZE_3,
1944 mmNIC0_QM0_CQ_CTL_3,
1945 mmNIC0_QM0_CQ_PTR_LO_4,
1946 mmNIC0_QM0_CQ_PTR_HI_4,
1947 mmNIC0_QM0_CQ_TSIZE_4,
1948 mmNIC0_QM0_CQ_CTL_4,
1949 mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,
1950 mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,
1951 mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,
1952 mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,
1953 mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,
1954 mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,
1955 mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,
1956 mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,
1957 mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,
1958 mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,
1959 mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,
1960 mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,
1961 mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,
1962 mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,
1963 mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,
1964 mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,
1965 mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,
1966 mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,
1967 mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,
1968 mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,
1969 mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,
1970 mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,
1971 mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,
1972 mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,
1973 mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,
1974 mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,
1975 mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,
1976 mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,
1977 mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,
1978 mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,
1979 mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,
1980 mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,
1981 mmNIC0_QM0_ARC_CQ_PTR_LO,
1982 mmNIC0_QM0_ARC_CQ_PTR_LO_STS,
1983 mmNIC0_QM0_ARC_CQ_PTR_HI,
1984 mmNIC0_QM0_ARC_CQ_PTR_HI_STS,
1985 mmNIC0_QM0_ARB_CFG_0,
1986 mmNIC0_QM0_ARB_MST_QUIET_PER,
1987 mmNIC0_QM0_ARB_CHOICE_Q_PUSH,
1988 mmNIC0_QM0_ARB_WRR_WEIGHT_0,
1989 mmNIC0_QM0_ARB_WRR_WEIGHT_1,
1990 mmNIC0_QM0_ARB_WRR_WEIGHT_2,
1991 mmNIC0_QM0_ARB_WRR_WEIGHT_3,
1992 mmNIC0_QM0_ARB_BASE_LO,
1993 mmNIC0_QM0_ARB_BASE_HI,
1994 mmNIC0_QM0_ARB_MST_SLAVE_EN,
1995 mmNIC0_QM0_ARB_MST_SLAVE_EN_1,
1996 mmNIC0_QM0_ARB_MST_CRED_INC,
1997 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,
1998 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,
1999 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,
2000 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,
2001 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,
2002 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,
2003 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,
2004 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,
2005 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,
2006 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,
2007 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,
2008 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,
2009 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,
2010 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,
2011 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,
2012 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,
2013 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,
2014 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,
2015 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,
2016 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,
2017 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,
2018 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,
2019 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,
2020 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,
2021 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,
2022 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,
2023 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,
2024 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,
2025 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,
2026 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,
2027 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,
2028 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,
2029 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,
2030 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,
2031 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,
2032 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,
2033 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,
2034 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,
2035 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,
2036 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,
2037 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,
2038 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,
2039 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,
2040 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,
2041 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,
2042 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,
2043 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,
2044 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,
2045 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,
2046 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,
2047 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,
2048 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,
2049 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,
2050 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,
2051 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,
2052 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,
2053 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,
2054 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,
2055 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,
2056 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,
2057 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,
2058 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,
2059 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,
2060 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,
2061 mmNIC0_QM0_ARB_SLV_ID,
2062 mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,
2063 mmNIC0_QM0_ARC_CQ_CFG0,
2064 mmNIC0_QM0_CQ_IFIFO_CI_0,
2065 mmNIC0_QM0_CQ_IFIFO_CI_1,
2066 mmNIC0_QM0_CQ_IFIFO_CI_2,
2067 mmNIC0_QM0_CQ_IFIFO_CI_3,
2068 mmNIC0_QM0_CQ_IFIFO_CI_4,
2069 mmNIC0_QM0_ARC_CQ_IFIFO_CI,
2070 mmNIC0_QM0_CQ_CTL_CI_0,
2071 mmNIC0_QM0_CQ_CTL_CI_1,
2072 mmNIC0_QM0_CQ_CTL_CI_2,
2073 mmNIC0_QM0_CQ_CTL_CI_3,
2074 mmNIC0_QM0_CQ_CTL_CI_4,
2075 mmNIC0_QM0_ARC_CQ_CTL_CI,
2076 mmNIC0_QM0_ARC_CQ_TSIZE,
2077 mmNIC0_QM0_ARC_CQ_CTL,
2078 mmNIC0_QM0_CP_SWITCH_WD_SET,
2079 mmNIC0_QM0_CP_EXT_SWITCH,
2080 mmNIC0_QM0_CP_PRED_0,
2081 mmNIC0_QM0_CP_PRED_1,
2082 mmNIC0_QM0_CP_PRED_2,
2083 mmNIC0_QM0_CP_PRED_3,
2084 mmNIC0_QM0_CP_PRED_4,
2085 mmNIC0_QM0_CP_PRED_UPEN_0,
2086 mmNIC0_QM0_CP_PRED_UPEN_1,
2087 mmNIC0_QM0_CP_PRED_UPEN_2,
2088 mmNIC0_QM0_CP_PRED_UPEN_3,
2089 mmNIC0_QM0_CP_PRED_UPEN_4,
2090 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,
2091 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,
2092 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,
2093 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,
2094 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,
2095 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,
2096 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,
2097 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,
2098 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,
2099 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,
2100 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,
2101 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,
2102 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,
2103 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,
2104 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,
2105 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,
2106 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,
2107 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,
2108 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,
2109 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,
2110 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,
2111 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,
2112 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,
2113 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,
2114 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,
2115 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,
2116 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,
2117 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,
2118 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,
2119 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,
2120 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,
2121 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,
2122 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,
2123 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,
2124 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,
2125 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,
2126 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,
2127 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,
2128 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,
2129 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,
2130 mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,
2131 mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,
2132 mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,
2133 mmNIC0_QM0_CQ_CTL_MSG_BASE_LO
2134 };
2135
2136 static const u32 gaudi2_pb_rot0[] = {
2137 mmROT0_BASE,
2138 mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,
2139 mmROT0_QM_BASE,
2140 };
2141
2142 static const u32 gaudi2_pb_rot0_arc[] = {
2143 mmROT0_QM_ARC_AUX_BASE
2144 };
2145
2146 static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {
2147 {mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},
2148 {mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},
2149 {mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},
2150 {mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
2151 {mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
2152 {mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
2153 {mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
2154 {mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
2155 {mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
2156 };
2157
2158 static const u32 gaudi2_pb_rot0_unsecured_regs[] = {
2159 mmROT0_QM_CQ_CFG0_0,
2160 mmROT0_QM_CQ_CFG0_1,
2161 mmROT0_QM_CQ_CFG0_2,
2162 mmROT0_QM_CQ_CFG0_3,
2163 mmROT0_QM_CQ_CFG0_4,
2164 mmROT0_QM_CP_FENCE0_RDATA_0,
2165 mmROT0_QM_CP_FENCE0_RDATA_1,
2166 mmROT0_QM_CP_FENCE0_RDATA_2,
2167 mmROT0_QM_CP_FENCE0_RDATA_3,
2168 mmROT0_QM_CP_FENCE0_RDATA_4,
2169 mmROT0_QM_CP_FENCE1_RDATA_0,
2170 mmROT0_QM_CP_FENCE1_RDATA_1,
2171 mmROT0_QM_CP_FENCE1_RDATA_2,
2172 mmROT0_QM_CP_FENCE1_RDATA_3,
2173 mmROT0_QM_CP_FENCE1_RDATA_4,
2174 mmROT0_QM_CP_FENCE2_RDATA_0,
2175 mmROT0_QM_CP_FENCE2_RDATA_1,
2176 mmROT0_QM_CP_FENCE2_RDATA_2,
2177 mmROT0_QM_CP_FENCE2_RDATA_3,
2178 mmROT0_QM_CP_FENCE2_RDATA_4,
2179 mmROT0_QM_CP_FENCE3_RDATA_0,
2180 mmROT0_QM_CP_FENCE3_RDATA_1,
2181 mmROT0_QM_CP_FENCE3_RDATA_2,
2182 mmROT0_QM_CP_FENCE3_RDATA_3,
2183 mmROT0_QM_CP_FENCE3_RDATA_4,
2184 mmROT0_QM_CP_FENCE0_CNT_0,
2185 mmROT0_QM_CP_FENCE0_CNT_1,
2186 mmROT0_QM_CP_FENCE0_CNT_2,
2187 mmROT0_QM_CP_FENCE0_CNT_3,
2188 mmROT0_QM_CP_FENCE0_CNT_4,
2189 mmROT0_QM_CP_FENCE1_CNT_0,
2190 mmROT0_QM_CP_FENCE1_CNT_1,
2191 mmROT0_QM_CP_FENCE1_CNT_2,
2192 mmROT0_QM_CP_FENCE1_CNT_3,
2193 mmROT0_QM_CP_FENCE1_CNT_4,
2194 mmROT0_QM_CP_FENCE2_CNT_0,
2195 mmROT0_QM_CP_FENCE2_CNT_1,
2196 mmROT0_QM_CP_FENCE2_CNT_2,
2197 mmROT0_QM_CP_FENCE2_CNT_3,
2198 mmROT0_QM_CP_FENCE2_CNT_4,
2199 mmROT0_QM_CP_FENCE3_CNT_0,
2200 mmROT0_QM_CP_FENCE3_CNT_1,
2201 mmROT0_QM_CP_FENCE3_CNT_2,
2202 mmROT0_QM_CP_FENCE3_CNT_3,
2203 mmROT0_QM_CP_FENCE3_CNT_4,
2204 mmROT0_QM_CQ_PTR_LO_0,
2205 mmROT0_QM_CQ_PTR_HI_0,
2206 mmROT0_QM_CQ_TSIZE_0,
2207 mmROT0_QM_CQ_CTL_0,
2208 mmROT0_QM_CQ_PTR_LO_1,
2209 mmROT0_QM_CQ_PTR_HI_1,
2210 mmROT0_QM_CQ_TSIZE_1,
2211 mmROT0_QM_CQ_CTL_1,
2212 mmROT0_QM_CQ_PTR_LO_2,
2213 mmROT0_QM_CQ_PTR_HI_2,
2214 mmROT0_QM_CQ_TSIZE_2,
2215 mmROT0_QM_CQ_CTL_2,
2216 mmROT0_QM_CQ_PTR_LO_3,
2217 mmROT0_QM_CQ_PTR_HI_3,
2218 mmROT0_QM_CQ_TSIZE_3,
2219 mmROT0_QM_CQ_CTL_3,
2220 mmROT0_QM_CQ_PTR_LO_4,
2221 mmROT0_QM_CQ_PTR_HI_4,
2222 mmROT0_QM_CQ_TSIZE_4,
2223 mmROT0_QM_CQ_CTL_4,
2224 mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,
2225 mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
2226 mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,
2227 mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
2228 mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,
2229 mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
2230 mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,
2231 mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
2232 mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,
2233 mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
2234 mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,
2235 mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
2236 mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,
2237 mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
2238 mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,
2239 mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
2240 mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,
2241 mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
2242 mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,
2243 mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
2244 mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,
2245 mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
2246 mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,
2247 mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
2248 mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,
2249 mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
2250 mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,
2251 mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
2252 mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,
2253 mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
2254 mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,
2255 mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
2256 mmROT0_QM_ARC_CQ_PTR_LO,
2257 mmROT0_QM_ARC_CQ_PTR_LO_STS,
2258 mmROT0_QM_ARC_CQ_PTR_HI,
2259 mmROT0_QM_ARC_CQ_PTR_HI_STS,
2260 mmROT0_QM_ARB_CFG_0,
2261 mmROT0_QM_ARB_MST_QUIET_PER,
2262 mmROT0_QM_ARB_CHOICE_Q_PUSH,
2263 mmROT0_QM_ARB_WRR_WEIGHT_0,
2264 mmROT0_QM_ARB_WRR_WEIGHT_1,
2265 mmROT0_QM_ARB_WRR_WEIGHT_2,
2266 mmROT0_QM_ARB_WRR_WEIGHT_3,
2267 mmROT0_QM_ARB_BASE_LO,
2268 mmROT0_QM_ARB_BASE_HI,
2269 mmROT0_QM_ARB_MST_SLAVE_EN,
2270 mmROT0_QM_ARB_MST_SLAVE_EN_1,
2271 mmROT0_QM_ARB_MST_CRED_INC,
2272 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
2273 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
2274 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
2275 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
2276 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
2277 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
2278 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
2279 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
2280 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
2281 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
2282 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
2283 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
2284 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
2285 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
2286 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
2287 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
2288 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
2289 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
2290 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
2291 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
2292 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
2293 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
2294 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
2295 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
2296 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
2297 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
2298 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
2299 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
2300 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
2301 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
2302 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
2303 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
2304 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
2305 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
2306 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
2307 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
2308 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
2309 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
2310 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
2311 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
2312 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
2313 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
2314 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
2315 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
2316 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
2317 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
2318 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
2319 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
2320 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
2321 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
2322 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
2323 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
2324 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
2325 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
2326 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
2327 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
2328 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
2329 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
2330 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
2331 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
2332 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
2333 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
2334 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
2335 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
2336 mmROT0_QM_ARB_SLV_ID,
2337 mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
2338 mmROT0_QM_ARC_CQ_CFG0,
2339 mmROT0_QM_CQ_IFIFO_CI_0,
2340 mmROT0_QM_CQ_IFIFO_CI_1,
2341 mmROT0_QM_CQ_IFIFO_CI_2,
2342 mmROT0_QM_CQ_IFIFO_CI_3,
2343 mmROT0_QM_CQ_IFIFO_CI_4,
2344 mmROT0_QM_ARC_CQ_IFIFO_CI,
2345 mmROT0_QM_CQ_CTL_CI_0,
2346 mmROT0_QM_CQ_CTL_CI_1,
2347 mmROT0_QM_CQ_CTL_CI_2,
2348 mmROT0_QM_CQ_CTL_CI_3,
2349 mmROT0_QM_CQ_CTL_CI_4,
2350 mmROT0_QM_ARC_CQ_CTL_CI,
2351 mmROT0_QM_ARC_CQ_TSIZE,
2352 mmROT0_QM_ARC_CQ_CTL,
2353 mmROT0_QM_CP_SWITCH_WD_SET,
2354 mmROT0_QM_CP_EXT_SWITCH,
2355 mmROT0_QM_CP_PRED_0,
2356 mmROT0_QM_CP_PRED_1,
2357 mmROT0_QM_CP_PRED_2,
2358 mmROT0_QM_CP_PRED_3,
2359 mmROT0_QM_CP_PRED_4,
2360 mmROT0_QM_CP_PRED_UPEN_0,
2361 mmROT0_QM_CP_PRED_UPEN_1,
2362 mmROT0_QM_CP_PRED_UPEN_2,
2363 mmROT0_QM_CP_PRED_UPEN_3,
2364 mmROT0_QM_CP_PRED_UPEN_4,
2365 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,
2366 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,
2367 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,
2368 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,
2369 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,
2370 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,
2371 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,
2372 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,
2373 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,
2374 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,
2375 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,
2376 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,
2377 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,
2378 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,
2379 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,
2380 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,
2381 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,
2382 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,
2383 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,
2384 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,
2385 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,
2386 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,
2387 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,
2388 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,
2389 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,
2390 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,
2391 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,
2392 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,
2393 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,
2394 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,
2395 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,
2396 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,
2397 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,
2398 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,
2399 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,
2400 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,
2401 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,
2402 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,
2403 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,
2404 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,
2405 mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
2406 mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,
2407 mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,
2408 mmROT0_QM_CQ_CTL_MSG_BASE_LO,
2409 mmROT0_DESC_CONTEXT_ID,
2410 mmROT0_DESC_IN_IMG_START_ADDR_L,
2411 mmROT0_DESC_IN_IMG_START_ADDR_H,
2412 mmROT0_DESC_OUT_IMG_START_ADDR_L,
2413 mmROT0_DESC_OUT_IMG_START_ADDR_H,
2414 mmROT0_DESC_CFG,
2415 mmROT0_DESC_IM_READ_SLOPE,
2416 mmROT0_DESC_SIN_D,
2417 mmROT0_DESC_COS_D,
2418 mmROT0_DESC_IN_IMG,
2419 mmROT0_DESC_IN_STRIDE,
2420 mmROT0_DESC_IN_STRIPE,
2421 mmROT0_DESC_IN_CENTER,
2422 mmROT0_DESC_OUT_IMG,
2423 mmROT0_DESC_OUT_STRIDE,
2424 mmROT0_DESC_OUT_STRIPE,
2425 mmROT0_DESC_OUT_CENTER,
2426 mmROT0_DESC_BACKGROUND,
2427 mmROT0_DESC_CPL_MSG_EN,
2428 mmROT0_DESC_IDLE_STATE,
2429 mmROT0_DESC_CPL_MSG_ADDR,
2430 mmROT0_DESC_CPL_MSG_DATA,
2431 mmROT0_DESC_X_I_START_OFFSET,
2432 mmROT0_DESC_X_I_START_OFFSET_FLIP,
2433 mmROT0_DESC_X_I_FIRST,
2434 mmROT0_DESC_Y_I_FIRST,
2435 mmROT0_DESC_Y_I,
2436 mmROT0_DESC_OUT_STRIPE_SIZE,
2437 mmROT0_DESC_RSB_CFG_0,
2438 mmROT0_DESC_RSB_PAD_VAL,
2439 mmROT0_DESC_OWM_CFG,
2440 mmROT0_DESC_CTRL_CFG,
2441 mmROT0_DESC_PIXEL_PAD,
2442 mmROT0_DESC_PREC_SHIFT,
2443 mmROT0_DESC_MAX_VAL,
2444 mmROT0_DESC_A0_M11,
2445 mmROT0_DESC_A1_M12,
2446 mmROT0_DESC_A2,
2447 mmROT0_DESC_B0_M21,
2448 mmROT0_DESC_B1_M22,
2449 mmROT0_DESC_B2,
2450 mmROT0_DESC_C0,
2451 mmROT0_DESC_C1,
2452 mmROT0_DESC_C2,
2453 mmROT0_DESC_D0,
2454 mmROT0_DESC_D1,
2455 mmROT0_DESC_D2,
2456 mmROT0_DESC_INV_PROC_SIZE_M_1,
2457 mmROT0_DESC_MESH_IMG_START_ADDR_L,
2458 mmROT0_DESC_MESH_IMG_START_ADDR_H,
2459 mmROT0_DESC_MESH_IMG,
2460 mmROT0_DESC_MESH_STRIDE,
2461 mmROT0_DESC_MESH_STRIPE,
2462 mmROT0_DESC_MESH_CTRL,
2463 mmROT0_DESC_MESH_GH,
2464 mmROT0_DESC_MESH_GV,
2465 mmROT0_DESC_MRSB_CFG_0,
2466 mmROT0_DESC_MRSB_PAD_VAL,
2467 mmROT0_DESC_BUF_CFG,
2468 mmROT0_DESC_CID_OFFSET,
2469 mmROT0_DESC_PUSH_DESC
2470 };
2471
2472 static const u32 gaudi2_pb_psoc_global_conf[] = {
2473 mmPSOC_GLOBAL_CONF_BASE
2474 };
2475
2476 static const u32 gaudi2_pb_psoc[] = {
2477 mmPSOC_EFUSE_BASE,
2478 mmPSOC_BTL_BASE,
2479 mmPSOC_CS_TRACE_BASE,
2480 mmPSOC_DFT_EFUSE_BASE,
2481 mmPSOC_PID_BASE,
2482 mmPSOC_ARC0_CFG_BASE,
2483 mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,
2484 mmPSOC_ARC0_AUX_BASE,
2485 mmPSOC_ARC1_CFG_BASE,
2486 mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,
2487 mmPSOC_ARC1_AUX_BASE,
2488 mmJT_MSTR_IF_RR_SHRD_HBW_BASE,
2489 mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,
2490 mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,
2491 mmPSOC_SVID0_BASE,
2492 mmPSOC_SVID1_BASE,
2493 mmPSOC_SVID2_BASE,
2494 mmPSOC_AVS0_BASE,
2495 mmPSOC_AVS1_BASE,
2496 mmPSOC_AVS2_BASE,
2497 mmPSOC_PWM0_BASE,
2498 mmPSOC_PWM1_BASE,
2499 mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,
2500 };
2501
2502 static const u32 gaudi2_pb_pmmu[] = {
2503 mmPMMU_HBW_MMU_BASE,
2504 mmPMMU_HBW_STLB_BASE,
2505 mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,
2506 mmPMMU_PIF_BASE,
2507 };
2508
2509 static const u32 gaudi2_pb_psoc_pll[] = {
2510 mmPSOC_MME_PLL_CTRL_BASE,
2511 mmPSOC_CPU_PLL_CTRL_BASE,
2512 mmPSOC_VID_PLL_CTRL_BASE
2513 };
2514
2515 static const u32 gaudi2_pb_pmmu_pll[] = {
2516 mmPMMU_MME_PLL_CTRL_BASE,
2517 mmPMMU_VID_PLL_CTRL_BASE
2518 };
2519
2520 static const u32 gaudi2_pb_xbar_pll[] = {
2521 mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,
2522 mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,
2523 mmDCORE0_XBAR_IF_PLL_CTRL_BASE,
2524 mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,
2525 mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,
2526 mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,
2527 mmDCORE1_XBAR_IF_PLL_CTRL_BASE,
2528 mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,
2529 mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,
2530 mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,
2531 mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,
2532 mmDCORE2_XBAR_IF_PLL_CTRL_BASE,
2533 mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,
2534 mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,
2535 mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,
2536 mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,
2537 mmDCORE3_XBAR_IF_PLL_CTRL_BASE,
2538 mmDCORE3_XBAR_BANK_PLL_CTRL_BASE
2539 };
2540
2541 static const u32 gaudi2_pb_xft_pll[] = {
2542 mmDCORE0_HBM_PLL_CTRL_BASE,
2543 mmDCORE0_TPC_PLL_CTRL_BASE,
2544 mmDCORE0_PCI_PLL_CTRL_BASE,
2545 mmDCORE1_HBM_PLL_CTRL_BASE,
2546 mmDCORE1_TPC_PLL_CTRL_BASE,
2547 mmDCORE1_NIC_PLL_CTRL_BASE,
2548 mmDCORE2_HBM_PLL_CTRL_BASE,
2549 mmDCORE2_TPC_PLL_CTRL_BASE,
2550 mmDCORE3_HBM_PLL_CTRL_BASE,
2551 mmDCORE3_TPC_PLL_CTRL_BASE,
2552 mmDCORE3_NIC_PLL_CTRL_BASE,
2553 };
2554
2555 static const u32 gaudi2_pb_pcie[] = {
2556 mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2557 mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2558 mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2559 mmPCIE_WRAP_BASE,
2560 };
2561
2562 static const u32 gaudi2_pb_pcie_unsecured_regs[] = {
2563 mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0,
2564 };
2565
2566 static const u32 gaudi2_pb_thermal_sensor0[] = {
2567 mmDCORE0_XFT_BASE,
2568 mmDCORE0_TSTDVS_BASE,
2569 };
2570
2571 static const u32 gaudi2_pb_hbm[] = {
2572 mmHBM0_MC0_BASE,
2573 mmHBM0_MC1_BASE,
2574 };
2575
2576 static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {
2577 mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,
2578 };
2579
2580 static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {
2581 {mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},
2582 };
2583
2584 struct gaudi2_tpc_pb_data {
2585 struct hl_block_glbl_sec *glbl_sec;
2586 u32 block_array_size;
2587 };
2588
gaudi2_config_tpcs_glbl_sec(struct hl_device * hdev,int dcore,int inst,u32 offset,struct iterate_module_ctx * ctx)2589 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
2590 struct iterate_module_ctx *ctx)
2591 {
2592 struct gaudi2_tpc_pb_data *pb_data = ctx->data;
2593
2594 hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
2595 offset, pb_data->block_array_size);
2596 }
2597
gaudi2_init_pb_tpc(struct hl_device * hdev)2598 static int gaudi2_init_pb_tpc(struct hl_device *hdev)
2599 {
2600 u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;
2601 struct gaudi2_tpc_pb_data tpc_pb_data;
2602 struct hl_block_glbl_sec *glbl_sec;
2603 struct iterate_module_ctx tpc_iter;
2604 int i;
2605
2606 block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
2607
2608 glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);
2609 if (!glbl_sec)
2610 return -ENOMEM;
2611
2612 kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -
2613 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;
2614 qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;
2615
2616 hl_secure_block(hdev, glbl_sec, block_array_size);
2617 hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
2618 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),
2619 0, gaudi2_pb_dcr0_tpc0, glbl_sec,
2620 block_array_size);
2621
2622 /* Unsecure all TPC kernel tensors */
2623 for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)
2624 hl_unsecure_registers(hdev,
2625 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,
2626 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),
2627 i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,
2628 glbl_sec, block_array_size);
2629
2630 /* Unsecure all TPC QM tensors */
2631 for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)
2632 hl_unsecure_registers(hdev,
2633 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,
2634 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),
2635 i * qm_tensor_stride,
2636 gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);
2637
2638 /* unsecure all 32 TPC QM SRF regs */
2639 stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;
2640 for (i = 0 ; i < 32 ; i++)
2641 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
2642 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2643 block_array_size);
2644
2645 /* unsecure the 4 TPC LOCK VALUE regs */
2646 stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;
2647 for (i = 0 ; i < 4 ; i++)
2648 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
2649 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2650 block_array_size);
2651
2652 /* prepare data for TPC iterator */
2653 tpc_pb_data.glbl_sec = glbl_sec;
2654 tpc_pb_data.block_array_size = block_array_size;
2655 tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;
2656 tpc_iter.data = &tpc_pb_data;
2657 gaudi2_iterate_tpcs(hdev, &tpc_iter);
2658
2659 kfree(glbl_sec);
2660
2661 return 0;
2662 }
2663
2664 struct gaudi2_tpc_arc_pb_data {
2665 u32 unsecured_regs_arr_size;
2666 u32 arc_regs_arr_size;
2667 };
2668
gaudi2_config_tpcs_pb_ranges(struct hl_device * hdev,int dcore,int inst,u32 offset,struct iterate_module_ctx * ctx)2669 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
2670 struct iterate_module_ctx *ctx)
2671 {
2672 struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data;
2673
2674 ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
2675 offset, gaudi2_pb_dcr0_tpc0_arc,
2676 pb_data->arc_regs_arr_size,
2677 gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,
2678 pb_data->unsecured_regs_arr_size);
2679 }
2680
gaudi2_init_pb_tpc_arc(struct hl_device * hdev)2681 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
2682 {
2683 struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;
2684 struct iterate_module_ctx tpc_iter;
2685
2686 tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
2687 tpc_arc_pb_data.unsecured_regs_arr_size =
2688 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);
2689
2690 tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;
2691 tpc_iter.data = &tpc_arc_pb_data;
2692 gaudi2_iterate_tpcs(hdev, &tpc_iter);
2693
2694 return tpc_iter.rc;
2695 }
2696
gaudi2_init_pb_sm_objs(struct hl_device * hdev)2697 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
2698 {
2699 int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;
2700 u32 sec_entry, *sec_array, array_base, first_sob, first_mon;
2701
2702 array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +
2703 gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;
2704
2705 sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);
2706 if (!sec_array)
2707 return -ENOMEM;
2708
2709 first_sob = GAUDI2_RESERVED_SOB_NUMBER;
2710 first_mon = GAUDI2_RESERVED_MON_NUMBER;
2711
2712 /* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */
2713 for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)
2714 UNSET_GLBL_SEC_BIT(sec_array, j);
2715
2716 /* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */
2717 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2718 UNSET_GLBL_SEC_BIT(sec_array, j);
2719
2720 /* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */
2721 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2722 UNSET_GLBL_SEC_BIT(sec_array, j);
2723
2724 /* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */
2725 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2726 UNSET_GLBL_SEC_BIT(sec_array, j);
2727
2728 /* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */
2729 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2730 UNSET_GLBL_SEC_BIT(sec_array, j);
2731
2732 /* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */
2733 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2734 UNSET_GLBL_SEC_BIT(sec_array, j);
2735
2736 /* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */
2737 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2738 UNSET_GLBL_SEC_BIT(sec_array, j);
2739
2740 /* Unsecure selected Dcore0 registers */
2741 for (i = 0 ; i < glbl_sec_array_len ; i++) {
2742 sec_entry = array_base + i * sizeof(u32);
2743 WREG32(sec_entry, sec_array[i]);
2744 }
2745
2746 /* Unsecure Dcore1 - Dcore3 registers */
2747 memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));
2748
2749 for (i = 1 ; i < NUM_OF_DCORES ; i++) {
2750 for (j = 0 ; j < glbl_sec_array_len ; j++) {
2751 sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);
2752 WREG32(sec_entry, sec_array[j]);
2753 }
2754 }
2755
2756 kfree(sec_array);
2757
2758 return 0;
2759 }
2760
gaudi2_write_lbw_range_register(struct hl_device * hdev,u64 base,void * data)2761 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2762 {
2763 u32 reg_min_offset, reg_max_offset, write_min, write_max;
2764 struct rr_config *rr_cfg = (struct rr_config *) data;
2765
2766 switch (rr_cfg->type) {
2767 case RR_TYPE_SHORT:
2768 reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;
2769 reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;
2770 break;
2771
2772 case RR_TYPE_LONG:
2773 reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;
2774 reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;
2775 break;
2776
2777 case RR_TYPE_SHORT_PRIV:
2778 reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;
2779 reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;
2780 break;
2781
2782 case RR_TYPE_LONG_PRIV:
2783 reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;
2784 reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;
2785 break;
2786
2787 default:
2788 dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
2789 return;
2790 }
2791
2792 reg_min_offset += rr_cfg->index * sizeof(u32);
2793 reg_max_offset += rr_cfg->index * sizeof(u32);
2794
2795 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
2796 write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));
2797 write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));
2798
2799 } else {
2800 write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));
2801 write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));
2802 }
2803
2804 /* Configure LBW RR:
2805 * Both RR types start blocking from base address 0x1000007FF8000000
2806 * SHORT RRs address bits [26:12]
2807 * LONG RRs address bits [26:0]
2808 */
2809 WREG32(base + reg_min_offset, write_min);
2810 WREG32(base + reg_max_offset, write_max);
2811 }
2812
gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device * hdev,u8 rr_type,u32 rr_index,u64 min_val,u64 max_val)2813 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
2814 u64 max_val)
2815 {
2816 struct dup_block_ctx block_ctx;
2817 struct rr_config rr_cfg;
2818
2819 if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
2820 rr_index >= NUM_SHORT_LBW_RR) {
2821
2822 dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
2823 rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
2824 return;
2825 }
2826
2827 if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
2828 rr_index >= NUM_LONG_LBW_RR) {
2829
2830 dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
2831 rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
2832 return;
2833 }
2834
2835 rr_cfg.type = rr_type;
2836 rr_cfg.index = rr_index;
2837 rr_cfg.min = min_val;
2838 rr_cfg.max = max_val;
2839
2840 block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;
2841 block_ctx.data = &rr_cfg;
2842
2843 /* SFT */
2844 block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;
2845 block_ctx.blocks = NUM_OF_SFT;
2846 block_ctx.block_off = SFT_OFFSET;
2847 block_ctx.instances = SFT_NUM_OF_LBW_RTR;
2848 block_ctx.instance_off = SFT_LBW_RTR_OFFSET;
2849 gaudi2_init_blocks(hdev, &block_ctx);
2850
2851 /* SIF */
2852 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;
2853 block_ctx.blocks = NUM_OF_DCORES;
2854 block_ctx.block_off = DCORE_OFFSET;
2855 block_ctx.instances = NUM_OF_RTR_PER_DCORE;
2856 block_ctx.instance_off = DCORE_RTR_OFFSET;
2857 gaudi2_init_blocks(hdev, &block_ctx);
2858
2859 block_ctx.blocks = 1;
2860 block_ctx.block_off = 0;
2861 block_ctx.instances = 1;
2862 block_ctx.instance_off = 0;
2863
2864 /* PCIE ELBI */
2865 block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2866 gaudi2_init_blocks(hdev, &block_ctx);
2867
2868 /* PCIE MSTR */
2869 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2870 gaudi2_init_blocks(hdev, &block_ctx);
2871
2872 /* PCIE LBW */
2873 block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2874 gaudi2_init_blocks(hdev, &block_ctx);
2875 }
2876
gaudi2_init_lbw_range_registers_secure(struct hl_device * hdev)2877 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
2878 {
2879 int i;
2880
2881 /* Up to 14 14bit-address regs.
2882 *
2883 * - range 0: NIC0_CFG
2884 * - range 1: NIC1_CFG
2885 * - range 2: NIC2_CFG
2886 * - range 3: NIC3_CFG
2887 * - range 4: NIC4_CFG
2888 * - range 5: NIC5_CFG
2889 * - range 6: NIC6_CFG
2890 * - range 7: NIC7_CFG
2891 * - range 8: NIC8_CFG
2892 * - range 9: NIC9_CFG
2893 * - range 10: NIC10_CFG
2894 * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)
2895 *
2896 * If F/W security is not enabled:
2897 * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP)
2898 */
2899 u64 lbw_range_min_short[] = {
2900 mmNIC0_TX_AXUSER_BASE,
2901 mmNIC1_TX_AXUSER_BASE,
2902 mmNIC2_TX_AXUSER_BASE,
2903 mmNIC3_TX_AXUSER_BASE,
2904 mmNIC4_TX_AXUSER_BASE,
2905 mmNIC5_TX_AXUSER_BASE,
2906 mmNIC6_TX_AXUSER_BASE,
2907 mmNIC7_TX_AXUSER_BASE,
2908 mmNIC8_TX_AXUSER_BASE,
2909 mmNIC9_TX_AXUSER_BASE,
2910 mmNIC10_TX_AXUSER_BASE,
2911 mmNIC11_TX_AXUSER_BASE,
2912 mmPSOC_I2C_M0_BASE,
2913 mmPSOC_EFUSE_BASE
2914 };
2915 u64 lbw_range_max_short[] = {
2916 mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2917 mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2918 mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2919 mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2920 mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2921 mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2922 mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2923 mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2924 mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2925 mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2926 mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2927 mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,
2928 mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,
2929 mmSVID2_AC_BASE + HL_BLOCK_SIZE
2930 };
2931
2932 /* Up to 4 26bit-address regs.
2933 *
2934 * - range 0: TPC_DBG
2935 * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF
2936 * - range 2/3: used in soft reset to block access to several blocks and are cleared here
2937 */
2938 u64 lbw_range_min_long[] = {
2939 mmDCORE0_TPC0_ROM_TABLE_BASE,
2940 mmPCIE_DBI_MSIX_DOORBELL_OFF,
2941 0x0,
2942 0x0
2943 };
2944 u64 lbw_range_max_long[] = {
2945 mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,
2946 mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,
2947 0x0,
2948 0x0
2949 };
2950
2951 /* write short range registers to all lbw rtrs */
2952 for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {
2953 if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||
2954 lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&
2955 hdev->asic_prop.fw_security_enabled)
2956 continue;
2957
2958 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
2959 lbw_range_min_short[i], lbw_range_max_short[i]);
2960 }
2961
2962 /* write long range registers to all lbw rtrs */
2963 for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {
2964 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
2965 lbw_range_min_long[i], lbw_range_max_long[i]);
2966 }
2967 }
2968
gaudi2_init_lbw_range_registers(struct hl_device * hdev)2969 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
2970 {
2971 gaudi2_init_lbw_range_registers_secure(hdev);
2972 }
2973
gaudi2_write_hbw_range_register(struct hl_device * hdev,u64 base,void * data)2974 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
2975 {
2976 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
2977 struct rr_config *rr_cfg = (struct rr_config *) data;
2978 u64 val_min, val_max;
2979
2980 switch (rr_cfg->type) {
2981 case RR_TYPE_SHORT:
2982 min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;
2983 min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;
2984 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;
2985 max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;
2986 break;
2987
2988 case RR_TYPE_LONG:
2989 min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;
2990 min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;
2991 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;
2992 max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;
2993 break;
2994
2995 case RR_TYPE_SHORT_PRIV:
2996 min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;
2997 min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;
2998 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;
2999 max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;
3000 break;
3001
3002 case RR_TYPE_LONG_PRIV:
3003 min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;
3004 min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;
3005 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;
3006 max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;
3007 break;
3008
3009 default:
3010 dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
3011 return;
3012 }
3013
3014 min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3015 min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3016 max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3017 max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3018
3019 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
3020 val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |
3021 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);
3022 val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |
3023 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);
3024 } else {
3025 val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |
3026 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);
3027 val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |
3028 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);
3029 }
3030
3031 /* Configure HBW RR:
3032 * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]
3033 * LONG RRs (0x<52bits>000) - HI: address bits [63:44], LO: address bits [43:12]
3034 */
3035 WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));
3036 WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));
3037 WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));
3038 WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));
3039 }
3040
gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device * hdev,u8 rr_type,u32 rr_index,u64 min_val,u64 max_val)3041 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
3042 u64 min_val, u64 max_val)
3043 {
3044 struct dup_block_ctx block_ctx;
3045 struct rr_config rr_cfg;
3046
3047 if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
3048 rr_index >= NUM_SHORT_HBW_RR) {
3049
3050 dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
3051 rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
3052 return;
3053 }
3054
3055 if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
3056 rr_index >= NUM_LONG_HBW_RR) {
3057
3058 dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
3059 rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
3060 return;
3061 }
3062
3063 rr_cfg.type = rr_type;
3064 rr_cfg.index = rr_index;
3065 rr_cfg.min = min_val;
3066 rr_cfg.max = max_val;
3067
3068 block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;
3069 block_ctx.data = &rr_cfg;
3070
3071 /* SFT */
3072 block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;
3073 block_ctx.blocks = NUM_OF_SFT;
3074 block_ctx.block_off = SFT_OFFSET;
3075 block_ctx.instances = SFT_NUM_OF_HBW_RTR;
3076 block_ctx.instance_off = SFT_IF_RTR_OFFSET;
3077 gaudi2_init_blocks(hdev, &block_ctx);
3078
3079 /* SIF */
3080 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
3081 block_ctx.blocks = NUM_OF_DCORES;
3082 block_ctx.block_off = DCORE_OFFSET;
3083 block_ctx.instances = NUM_OF_RTR_PER_DCORE;
3084 block_ctx.instance_off = DCORE_RTR_OFFSET;
3085 gaudi2_init_blocks(hdev, &block_ctx);
3086
3087 /* PCIE MSTR */
3088 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;
3089 block_ctx.blocks = 1;
3090 block_ctx.block_off = 0;
3091 block_ctx.instances = 1;
3092 block_ctx.instance_off = 0;
3093 gaudi2_init_blocks(hdev, &block_ctx);
3094 }
3095
gaudi2_init_hbw_range_registers(struct hl_device * hdev)3096 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
3097 {
3098 int i;
3099
3100 /* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).
3101 *
3102 * - short range 0:
3103 * SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM
3104 */
3105 u64 hbw_range_min_short[] = {
3106 SPI_FLASH_BASE_ADDR
3107 };
3108 u64 hbw_range_max_short[] = {
3109 PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE
3110 };
3111
3112 for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {
3113 gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
3114 hbw_range_max_short[i]);
3115 }
3116 }
3117
gaudi2_write_mmu_range_register(struct hl_device * hdev,u64 base,struct rr_config * rr_cfg)3118 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3119 struct rr_config *rr_cfg)
3120 {
3121 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
3122
3123 switch (rr_cfg->type) {
3124 case RR_TYPE_LONG:
3125 min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;
3126 min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;
3127 max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;
3128 max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;
3129 break;
3130
3131 case RR_TYPE_LONG_PRIV:
3132 min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;
3133 min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;
3134 max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;
3135 max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;
3136 break;
3137
3138 default:
3139 dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
3140 return;
3141 }
3142
3143 min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3144 min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3145 max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3146 max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3147
3148 /* Configure MMU RR (address bits [63:0]) */
3149 WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));
3150 WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));
3151 WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));
3152 WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));
3153 }
3154
gaudi2_init_mmu_range_registers(struct hl_device * hdev)3155 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
3156 {
3157 u32 dcore_id, hmmu_id, hmmu_base;
3158 struct rr_config rr_cfg;
3159
3160 /* Up to 8 ranges [63:0].
3161 *
3162 * - range 0: Reserved HBM area for F/W and driver
3163 */
3164
3165 /* The RRs are located after the HMMU so need to use the scrambled addresses */
3166 rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
3167 rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
3168 rr_cfg.index = 0;
3169 rr_cfg.type = RR_TYPE_LONG;
3170
3171 for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
3172 for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
3173 if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
3174 continue;
3175
3176 hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +
3177 hmmu_id * DCORE_HMMU_OFFSET;
3178
3179 gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
3180 }
3181 }
3182 }
3183
3184 /**
3185 * gaudi2_init_range_registers -
3186 * Initialize range registers of all initiators
3187 *
3188 * @hdev: pointer to hl_device structure
3189 */
gaudi2_init_range_registers(struct hl_device * hdev)3190 static void gaudi2_init_range_registers(struct hl_device *hdev)
3191 {
3192 gaudi2_init_lbw_range_registers(hdev);
3193 gaudi2_init_hbw_range_registers(hdev);
3194 gaudi2_init_mmu_range_registers(hdev);
3195 }
3196
3197 /**
3198 * gaudi2_init_protection_bits -
3199 * Initialize protection bits of specific registers
3200 *
3201 * @hdev: pointer to hl_device structure
3202 *
3203 * All protection bits are 1 by default, means not protected. Need to set to 0
3204 * each bit that belongs to a protected register.
3205 *
3206 */
gaudi2_init_protection_bits(struct hl_device * hdev)3207 static int gaudi2_init_protection_bits(struct hl_device *hdev)
3208 {
3209 struct asic_fixed_properties *prop = &hdev->asic_prop;
3210 u32 instance_offset;
3211 int rc = 0;
3212 u8 i;
3213
3214 /* SFT */
3215 instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3216 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3217 gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),
3218 NULL, HL_PB_NA);
3219
3220 /* HIF */
3221 instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3222 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3223 NUM_OF_HIF_PER_DCORE, instance_offset,
3224 gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3225 NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3226
3227 /* RTR */
3228 instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3229 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3230 gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),
3231 NULL, HL_PB_NA);
3232
3233 /* HMMU */
3234 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3235 NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3236 gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3237 NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3238
3239 /* CPU.
3240 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3241 * by privileged RR.
3242 */
3243 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3244 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3245 gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),
3246 NULL, HL_PB_NA);
3247
3248 if (!hdev->asic_prop.fw_security_enabled)
3249 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3250 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3251 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),
3252 NULL, HL_PB_NA);
3253
3254 /* KDMA */
3255 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3256 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3257 gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),
3258 NULL, HL_PB_NA);
3259
3260 /* PDMA */
3261 instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3262 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3263 gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),
3264 gaudi2_pb_pdma0_unsecured_regs,
3265 ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));
3266
3267 /* ARC PDMA */
3268 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
3269 instance_offset, gaudi2_pb_pdma0_arc,
3270 ARRAY_SIZE(gaudi2_pb_pdma0_arc),
3271 gaudi2_pb_pdma0_arc_unsecured_regs,
3272 ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));
3273
3274 /* EDMA */
3275 instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3276 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3277 instance_offset, gaudi2_pb_dcr0_edma0,
3278 ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3279 gaudi2_pb_dcr0_edma0_unsecured_regs,
3280 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),
3281 prop->edma_enabled_mask);
3282
3283 /* ARC EDMA */
3284 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3285 instance_offset, gaudi2_pb_dcr0_edma0_arc,
3286 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3287 gaudi2_pb_dcr0_edma0_arc_unsecured_regs,
3288 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),
3289 prop->edma_enabled_mask);
3290
3291 /* MME */
3292 instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3293
3294 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3295 /* MME SBTE */
3296 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3297 instance_offset, gaudi2_pb_dcr0_mme_sbte,
3298 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,
3299 HL_PB_NA);
3300
3301 /* MME */
3302 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3303 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3304 gaudi2_pb_dcr0_mme_eng,
3305 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),
3306 gaudi2_pb_dcr0_mme_eng_unsecured_regs,
3307 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));
3308 }
3309
3310 /*
3311 * we have special iteration for case in which we would like to
3312 * configure stubbed MME's ARC/QMAN
3313 */
3314 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3315 /* MME QM */
3316 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3317 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3318 gaudi2_pb_dcr0_mme_qm,
3319 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),
3320 gaudi2_pb_dcr0_mme_qm_unsecured_regs,
3321 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));
3322
3323 /* ARC MME */
3324 rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
3325 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3326 gaudi2_pb_dcr0_mme_arc,
3327 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),
3328 gaudi2_pb_dcr0_mme_arc_unsecured_regs,
3329 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));
3330 }
3331
3332 /* MME QM ARC ACP ENG */
3333 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3334 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3335 gaudi2_pb_mme_qm_arc_acp_eng,
3336 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3337 gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,
3338 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),
3339 (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3340
3341 /* TPC */
3342 rc |= gaudi2_init_pb_tpc(hdev);
3343 rc |= gaudi2_init_pb_tpc_arc(hdev);
3344
3345 /* SRAM */
3346 instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3347 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3348 gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),
3349 NULL, HL_PB_NA);
3350
3351 /* Sync Manager MSTR IF */
3352 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3353 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3354 gaudi2_pb_dcr0_sm_mstr_if,
3355 ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),
3356 NULL, HL_PB_NA);
3357
3358 /* Sync Manager GLBL */
3359
3360 /* Unsecure all CQ registers */
3361 rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3362 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3363 gaudi2_pb_dcr0_sm_glbl,
3364 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
3365 gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
3366 ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
3367
3368 /* Secure Dcore0 CQ0 registers */
3369 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3370 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3371 gaudi2_pb_dcr0_sm_glbl,
3372 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
3373 gaudi2_pb_dcr0_sm_glbl_unsecured_regs,
3374 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));
3375
3376 /* PSOC.
3377 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3378 * protected by privileged RR.
3379 */
3380 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3381 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3382 gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),
3383 NULL, HL_PB_NA);
3384
3385 if (!hdev->asic_prop.fw_security_enabled)
3386 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3387 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3388 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),
3389 NULL, HL_PB_NA);
3390
3391 /* PMMU */
3392 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3393 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3394 gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),
3395 NULL, HL_PB_NA);
3396
3397 /* PLL.
3398 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3399 * privileged RR.
3400 */
3401 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3402 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3403 gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),
3404 NULL, HL_PB_NA);
3405 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3406 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3407 gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),
3408 NULL, HL_PB_NA);
3409
3410 if (!hdev->asic_prop.fw_security_enabled) {
3411 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3412 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3413 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),
3414 NULL, HL_PB_NA);
3415 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3416 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3417 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),
3418 NULL, HL_PB_NA);
3419 }
3420
3421 /* PCIE */
3422 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3423 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3424 gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),
3425 gaudi2_pb_pcie_unsecured_regs,
3426 ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs));
3427
3428 /* Thermal Sensor.
3429 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3430 */
3431 if (!hdev->asic_prop.fw_security_enabled) {
3432 instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3433 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3434 gaudi2_pb_thermal_sensor0,
3435 ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);
3436 }
3437
3438 /* HBM */
3439 /* Temporarily skip until SW-63348 is solved
3440 * instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
3441 * rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3442 * instance_offset, gaudi2_pb_hbm,
3443 * ARRAY_SIZE(gaudi2_pb_hbm), NULL, HL_PB_NA,
3444 * prop->dram_enabled_mask);
3445 */
3446
3447 /* Scheduler ARCs */
3448 instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3449 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3450 NUM_OF_ARC_FARMS_ARC,
3451 instance_offset, gaudi2_pb_arc_sched,
3452 ARRAY_SIZE(gaudi2_pb_arc_sched),
3453 gaudi2_pb_arc_sched_unsecured_regs,
3454 ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));
3455
3456 /* XBAR MIDs */
3457 instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3458 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3459 instance_offset, gaudi2_pb_xbar_mid,
3460 ARRAY_SIZE(gaudi2_pb_xbar_mid),
3461 gaudi2_pb_xbar_mid_unsecured_regs,
3462 ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));
3463
3464 /* XBAR EDGEs */
3465 instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3466 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3467 instance_offset, gaudi2_pb_xbar_edge,
3468 ARRAY_SIZE(gaudi2_pb_xbar_edge),
3469 gaudi2_pb_xbar_edge_unsecured_regs,
3470 ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),
3471 prop->xbar_edge_enabled_mask);
3472
3473 /* NIC */
3474 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3475 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3476 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),
3477 NULL, HL_PB_NA, hdev->nic_ports_mask);
3478
3479 /* NIC QM and QPC */
3480 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3481 NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3482 gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3483 gaudi2_pb_nic0_qm_qpc_unsecured_regs,
3484 ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),
3485 hdev->nic_ports_mask);
3486
3487 /* NIC QM ARC */
3488 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3489 NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3490 gaudi2_pb_nic0_qm_arc_aux0,
3491 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),
3492 gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,
3493 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),
3494 hdev->nic_ports_mask);
3495
3496 /* NIC UMR */
3497 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3498 NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3499 gaudi2_pb_nic0_umr,
3500 ARRAY_SIZE(gaudi2_pb_nic0_umr),
3501 gaudi2_pb_nic0_umr_unsecured_regs,
3502 ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),
3503 hdev->nic_ports_mask);
3504
3505 /* Rotators */
3506 instance_offset = mmROT1_BASE - mmROT0_BASE;
3507 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
3508 instance_offset, gaudi2_pb_rot0,
3509 ARRAY_SIZE(gaudi2_pb_rot0),
3510 gaudi2_pb_rot0_unsecured_regs,
3511 ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),
3512 (BIT(NUM_OF_ROT) - 1));
3513
3514 /* Rotators ARCS */
3515 rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
3516 HL_PB_NA, NUM_OF_ROT, instance_offset,
3517 gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),
3518 gaudi2_pb_rot0_arc_unsecured_regs,
3519 ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),
3520 (BIT(NUM_OF_ROT) - 1));
3521
3522 rc |= gaudi2_init_pb_sm_objs(hdev);
3523
3524 return rc;
3525 }
3526
3527 /**
3528 * gaudi2_init_security - Initialize security model
3529 *
3530 * @hdev: pointer to hl_device structure
3531 *
3532 * Initialize the security model of the device
3533 * That includes range registers and protection bit per register.
3534 */
gaudi2_init_security(struct hl_device * hdev)3535 int gaudi2_init_security(struct hl_device *hdev)
3536 {
3537 int rc;
3538
3539 rc = gaudi2_init_protection_bits(hdev);
3540 if (rc)
3541 return rc;
3542
3543 gaudi2_init_range_registers(hdev);
3544
3545 return 0;
3546 }
3547
3548 struct gaudi2_ack_pb_tpc_data {
3549 u32 tpc_regs_array_size;
3550 u32 arc_tpc_regs_array_size;
3551 };
3552
gaudi2_ack_pb_tpc_config(struct hl_device * hdev,int dcore,int inst,u32 offset,struct iterate_module_ctx * ctx)3553 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
3554 struct iterate_module_ctx *ctx)
3555 {
3556 struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data;
3557
3558 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3559 gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);
3560
3561 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3562 gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);
3563 }
3564
gaudi2_ack_pb_tpc(struct hl_device * hdev)3565 static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
3566 {
3567 struct iterate_module_ctx tpc_iter = {
3568 .fn = &gaudi2_ack_pb_tpc_config,
3569 };
3570 struct gaudi2_ack_pb_tpc_data data;
3571
3572 data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
3573 data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
3574 tpc_iter.data = &data;
3575
3576 gaudi2_iterate_tpcs(hdev, &tpc_iter);
3577 }
3578
3579 /**
3580 * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits
3581 * and for every protection error found, display the appropriate error message
3582 * and clear the error.
3583 *
3584 * @hdev: pointer to hl_device structure
3585 *
3586 * All protection bits are 1 by default, means not protected. Need to set to 0
3587 * each bit that belongs to a protected register.
3588 *
3589 */
gaudi2_ack_protection_bits_errors(struct hl_device * hdev)3590 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
3591 {
3592 struct asic_fixed_properties *prop = &hdev->asic_prop;
3593 u32 instance_offset;
3594 u8 i;
3595
3596 /* SFT */
3597 instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3598 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3599 gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));
3600
3601 /* HIF */
3602 instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3603 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3604 NUM_OF_HIF_PER_DCORE, instance_offset,
3605 gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3606 prop->hmmu_hif_enabled_mask);
3607
3608 /* RTR */
3609 instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3610 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3611 gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));
3612
3613 /* HMMU */
3614 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3615 NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3616 gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3617 prop->hmmu_hif_enabled_mask);
3618
3619 /* CPU.
3620 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3621 * by privileged RR.
3622 */
3623 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3624 gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));
3625 if (!hdev->asic_prop.fw_security_enabled)
3626 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3627 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));
3628
3629 /* KDMA */
3630 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3631 gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));
3632
3633 /* PDMA */
3634 instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3635 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3636 gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));
3637
3638 /* ARC PDMA */
3639 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3640 gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));
3641
3642 /* EDMA */
3643 instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3644 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3645 instance_offset, gaudi2_pb_dcr0_edma0,
3646 ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3647 prop->edma_enabled_mask);
3648
3649 /* ARC EDMA */
3650 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3651 instance_offset, gaudi2_pb_dcr0_edma0_arc,
3652 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3653 prop->edma_enabled_mask);
3654
3655 /* MME */
3656 instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3657
3658 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3659 /* MME SBTE */
3660 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3661 instance_offset, gaudi2_pb_dcr0_mme_sbte,
3662 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));
3663
3664 /* MME */
3665 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3666 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3667 gaudi2_pb_dcr0_mme_eng,
3668 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));
3669 }
3670
3671 /*
3672 * we have special iteration for case in which we would like to
3673 * configure stubbed MME's ARC/QMAN
3674 */
3675 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3676 /* MME QM */
3677 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3678 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3679 gaudi2_pb_dcr0_mme_qm,
3680 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));
3681
3682 /* ARC MME */
3683 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3684 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3685 gaudi2_pb_dcr0_mme_arc,
3686 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));
3687 }
3688
3689 /* MME QM ARC ACP ENG */
3690 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3691 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3692 gaudi2_pb_mme_qm_arc_acp_eng,
3693 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3694 (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3695
3696 /* TPC */
3697 gaudi2_ack_pb_tpc(hdev);
3698
3699 /* SRAM */
3700 instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3701 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3702 gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));
3703
3704 /* Sync Manager MSTR IF */
3705 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3706 gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3707
3708 /* Sync Manager */
3709 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3710 gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));
3711
3712 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3713 gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3714
3715 /* PSOC.
3716 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3717 * protected by privileged RR.
3718 */
3719 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3720 gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));
3721 if (!hdev->asic_prop.fw_security_enabled)
3722 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3723 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));
3724
3725 /* PMMU */
3726 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3727 gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));
3728
3729 /* PLL.
3730 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3731 * privileged RR.
3732 */
3733 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3734 gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));
3735 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3736 gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));
3737 if (!hdev->asic_prop.fw_security_enabled) {
3738 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3739 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));
3740 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3741 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));
3742 }
3743
3744 /* PCIE */
3745 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3746 gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));
3747
3748 /* Thermal Sensor.
3749 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3750 */
3751 if (!hdev->asic_prop.fw_security_enabled) {
3752 instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3753 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3754 gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));
3755 }
3756
3757 /* HBM */
3758 instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
3759 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3760 instance_offset, gaudi2_pb_hbm,
3761 ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);
3762
3763 /* Scheduler ARCs */
3764 instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3765 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
3766 instance_offset, gaudi2_pb_arc_sched,
3767 ARRAY_SIZE(gaudi2_pb_arc_sched));
3768
3769 /* XBAR MIDs */
3770 instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3771 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3772 instance_offset, gaudi2_pb_xbar_mid,
3773 ARRAY_SIZE(gaudi2_pb_xbar_mid));
3774
3775 /* XBAR EDGEs */
3776 instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3777 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3778 instance_offset, gaudi2_pb_xbar_edge,
3779 ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);
3780
3781 /* NIC */
3782 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3783 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
3784
3785 /* NIC QM and QPC */
3786 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3787 NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3788 hdev->nic_ports_mask);
3789
3790 /* NIC QM ARC */
3791 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3792 NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,
3793 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
3794
3795 /* NIC UMR */
3796 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3797 NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),
3798 hdev->nic_ports_mask);
3799
3800 /* Rotators */
3801 instance_offset = mmROT1_BASE - mmROT0_BASE;
3802 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3803 gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));
3804
3805 /* Rotators ARCS */
3806 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3807 gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));
3808 }
3809
3810 /*
3811 * Print PB security errors
3812 */
3813
gaudi2_pb_print_security_errors(struct hl_device * hdev,u32 block_addr,u32 cause,u32 offended_addr)3814 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
3815 u32 offended_addr)
3816 {
3817 int i = 0;
3818 const char *error_format =
3819 "Security error at block 0x%x, offending address 0x%x\n"
3820 "Cause 0x%x: %s %s %s %s %s %s %s %s\n";
3821 char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };
3822
3823 if (!cause)
3824 return;
3825
3826 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)
3827 mcause[i++] = "APB_PRIV_RD";
3828
3829 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)
3830 mcause[i++] = "APB_SEC_RD";
3831
3832 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)
3833 mcause[i++] = "APB_UNMAPPED_RD";
3834
3835 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)
3836 mcause[i++] = "APB_PRIV_WR";
3837
3838 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)
3839 mcause[i++] = "APB_SEC_WR";
3840
3841 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)
3842 mcause[i++] = "APB_UNMAPPED_WR";
3843
3844 if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)
3845 mcause[i++] = "EXT_SEC_WR";
3846
3847 if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)
3848 mcause[i++] = "APB_EXT_UNMAPPED_WR";
3849
3850 dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,
3851 cause, mcause[0], mcause[1], mcause[2], mcause[3],
3852 mcause[4], mcause[5], mcause[6], mcause[7]);
3853 }
3854