1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv50.h"
25 #include "channv50.h"
26
27 static void
g84_fifo_uevent_fini(struct nvkm_fifo * fifo)28 g84_fifo_uevent_fini(struct nvkm_fifo *fifo)
29 {
30 struct nvkm_device *device = fifo->engine.subdev.device;
31 nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
32 }
33
34 static void
g84_fifo_uevent_init(struct nvkm_fifo * fifo)35 g84_fifo_uevent_init(struct nvkm_fifo *fifo)
36 {
37 struct nvkm_device *device = fifo->engine.subdev.device;
38 nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
39 }
40
41 static struct nvkm_engine *
g84_fifo_id_engine(struct nvkm_fifo * fifo,int engi)42 g84_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
43 {
44 struct nvkm_device *device = fifo->engine.subdev.device;
45 struct nvkm_engine *engine;
46 enum nvkm_subdev_type type;
47
48 switch (engi) {
49 case G84_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break;
50 case G84_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break;
51 case G84_FIFO_ENGN_MPEG :
52 if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPPP, 0)))
53 return engine;
54 type = NVKM_ENGINE_MPEG;
55 break;
56 case G84_FIFO_ENGN_ME :
57 if ((engine = nvkm_device_engine(device, NVKM_ENGINE_CE, 0)))
58 return engine;
59 type = NVKM_ENGINE_ME;
60 break;
61 case G84_FIFO_ENGN_VP :
62 if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPDEC, 0)))
63 return engine;
64 type = NVKM_ENGINE_VP;
65 break;
66 case G84_FIFO_ENGN_CIPHER:
67 if ((engine = nvkm_device_engine(device, NVKM_ENGINE_VIC, 0)))
68 return engine;
69 if ((engine = nvkm_device_engine(device, NVKM_ENGINE_SEC, 0)))
70 return engine;
71 type = NVKM_ENGINE_CIPHER;
72 break;
73 case G84_FIFO_ENGN_BSP :
74 if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSVLD, 0)))
75 return engine;
76 type = NVKM_ENGINE_BSP;
77 break;
78 case G84_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break;
79 default:
80 WARN_ON(1);
81 return NULL;
82 }
83
84 return nvkm_device_engine(fifo->engine.subdev.device, type, 0);
85 }
86
87 static int
g84_fifo_engine_id(struct nvkm_fifo * base,struct nvkm_engine * engine)88 g84_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
89 {
90 switch (engine->subdev.type) {
91 case NVKM_ENGINE_SW : return G84_FIFO_ENGN_SW;
92 case NVKM_ENGINE_GR : return G84_FIFO_ENGN_GR;
93 case NVKM_ENGINE_MPEG :
94 case NVKM_ENGINE_MSPPP : return G84_FIFO_ENGN_MPEG;
95 case NVKM_ENGINE_CE : return G84_FIFO_ENGN_CE0;
96 case NVKM_ENGINE_VP :
97 case NVKM_ENGINE_MSPDEC: return G84_FIFO_ENGN_VP;
98 case NVKM_ENGINE_CIPHER:
99 case NVKM_ENGINE_SEC : return G84_FIFO_ENGN_CIPHER;
100 case NVKM_ENGINE_BSP :
101 case NVKM_ENGINE_MSVLD : return G84_FIFO_ENGN_BSP;
102 case NVKM_ENGINE_DMAOBJ: return G84_FIFO_ENGN_DMA;
103 default:
104 WARN_ON(1);
105 return -1;
106 }
107 }
108
109 static const struct nvkm_fifo_func
110 g84_fifo = {
111 .dtor = nv50_fifo_dtor,
112 .oneinit = nv50_fifo_oneinit,
113 .init = nv50_fifo_init,
114 .intr = nv04_fifo_intr,
115 .engine_id = g84_fifo_engine_id,
116 .id_engine = g84_fifo_id_engine,
117 .pause = nv04_fifo_pause,
118 .start = nv04_fifo_start,
119 .uevent_init = g84_fifo_uevent_init,
120 .uevent_fini = g84_fifo_uevent_fini,
121 .chan = {
122 &g84_fifo_gpfifo_oclass,
123 NULL
124 },
125 };
126
127 int
g84_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)128 g84_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
129 struct nvkm_fifo **pfifo)
130 {
131 return nv50_fifo_new_(&g84_fifo, device, type, inst, pfifo);
132 }
133