1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 *
5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
6 */
7
8 #include "g4x_hdmi.h"
9 #include "intel_audio.h"
10 #include "intel_connector.h"
11 #include "intel_crtc.h"
12 #include "intel_de.h"
13 #include "intel_display_power.h"
14 #include "intel_display_types.h"
15 #include "intel_dpio_phy.h"
16 #include "intel_fifo_underrun.h"
17 #include "intel_hdmi.h"
18 #include "intel_hotplug.h"
19 #include "intel_sdvo.h"
20 #include "vlv_sideband.h"
21
intel_hdmi_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)22 static void intel_hdmi_prepare(struct intel_encoder *encoder,
23 const struct intel_crtc_state *crtc_state)
24 {
25 struct drm_device *dev = encoder->base.dev;
26 struct drm_i915_private *dev_priv = to_i915(dev);
27 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
28 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
29 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
30 u32 hdmi_val;
31
32 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
33
34 hdmi_val = SDVO_ENCODING_HDMI;
35 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
36 hdmi_val |= HDMI_COLOR_RANGE_16_235;
37 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
38 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
39 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
40 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
41
42 if (crtc_state->pipe_bpp > 24)
43 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
44 else
45 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
46
47 if (crtc_state->has_hdmi_sink)
48 hdmi_val |= HDMI_MODE_SELECT_HDMI;
49
50 if (HAS_PCH_CPT(dev_priv))
51 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
52 else if (IS_CHERRYVIEW(dev_priv))
53 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
54 else
55 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
56
57 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
58 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
59 }
60
intel_hdmi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)61 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
62 enum pipe *pipe)
63 {
64 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
65 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
66 intel_wakeref_t wakeref;
67 bool ret;
68
69 wakeref = intel_display_power_get_if_enabled(dev_priv,
70 encoder->power_domain);
71 if (!wakeref)
72 return false;
73
74 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
75
76 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
77
78 return ret;
79 }
80
intel_hdmi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)81 static void intel_hdmi_get_config(struct intel_encoder *encoder,
82 struct intel_crtc_state *pipe_config)
83 {
84 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
85 struct drm_device *dev = encoder->base.dev;
86 struct drm_i915_private *dev_priv = to_i915(dev);
87 u32 tmp, flags = 0;
88 int dotclock;
89
90 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
91
92 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
93
94 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
95 flags |= DRM_MODE_FLAG_PHSYNC;
96 else
97 flags |= DRM_MODE_FLAG_NHSYNC;
98
99 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
100 flags |= DRM_MODE_FLAG_PVSYNC;
101 else
102 flags |= DRM_MODE_FLAG_NVSYNC;
103
104 if (tmp & HDMI_MODE_SELECT_HDMI)
105 pipe_config->has_hdmi_sink = true;
106
107 pipe_config->infoframes.enable |=
108 intel_hdmi_infoframes_enabled(encoder, pipe_config);
109
110 if (pipe_config->infoframes.enable)
111 pipe_config->has_infoframe = true;
112
113 if (tmp & HDMI_AUDIO_ENABLE)
114 pipe_config->has_audio = true;
115
116 if (!HAS_PCH_SPLIT(dev_priv) &&
117 tmp & HDMI_COLOR_RANGE_16_235)
118 pipe_config->limited_color_range = true;
119
120 pipe_config->hw.adjusted_mode.flags |= flags;
121
122 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
123 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3);
124 else
125 dotclock = pipe_config->port_clock;
126
127 if (pipe_config->pixel_multiplier)
128 dotclock /= pipe_config->pixel_multiplier;
129
130 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
131
132 pipe_config->lane_count = 4;
133
134 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
135
136 intel_read_infoframe(encoder, pipe_config,
137 HDMI_INFOFRAME_TYPE_AVI,
138 &pipe_config->infoframes.avi);
139 intel_read_infoframe(encoder, pipe_config,
140 HDMI_INFOFRAME_TYPE_SPD,
141 &pipe_config->infoframes.spd);
142 intel_read_infoframe(encoder, pipe_config,
143 HDMI_INFOFRAME_TYPE_VENDOR,
144 &pipe_config->infoframes.hdmi);
145 }
146
g4x_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)147 static void g4x_enable_hdmi(struct intel_atomic_state *state,
148 struct intel_encoder *encoder,
149 const struct intel_crtc_state *pipe_config,
150 const struct drm_connector_state *conn_state)
151 {
152 struct drm_device *dev = encoder->base.dev;
153 struct drm_i915_private *dev_priv = to_i915(dev);
154 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
155 u32 temp;
156
157 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
158
159 temp |= SDVO_ENABLE;
160 if (pipe_config->has_audio)
161 temp |= HDMI_AUDIO_ENABLE;
162
163 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
164 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
165
166 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
167 !pipe_config->has_hdmi_sink);
168 intel_audio_codec_enable(encoder, pipe_config, conn_state);
169 }
170
ibx_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)171 static void ibx_enable_hdmi(struct intel_atomic_state *state,
172 struct intel_encoder *encoder,
173 const struct intel_crtc_state *pipe_config,
174 const struct drm_connector_state *conn_state)
175 {
176 struct drm_device *dev = encoder->base.dev;
177 struct drm_i915_private *dev_priv = to_i915(dev);
178 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
179 u32 temp;
180
181 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
182
183 temp |= SDVO_ENABLE;
184 if (pipe_config->has_audio)
185 temp |= HDMI_AUDIO_ENABLE;
186
187 /*
188 * HW workaround, need to write this twice for issue
189 * that may result in first write getting masked.
190 */
191 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
192 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
193 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
194 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
195
196 /*
197 * HW workaround, need to toggle enable bit off and on
198 * for 12bpc with pixel repeat.
199 *
200 * FIXME: BSpec says this should be done at the end of
201 * the modeset sequence, so not sure if this isn't too soon.
202 */
203 if (pipe_config->pipe_bpp > 24 &&
204 pipe_config->pixel_multiplier > 1) {
205 intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
206 temp & ~SDVO_ENABLE);
207 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
208
209 /*
210 * HW workaround, need to write this twice for issue
211 * that may result in first write getting masked.
212 */
213 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
214 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
215 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
216 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
217 }
218
219 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
220 !pipe_config->has_hdmi_sink);
221 intel_audio_codec_enable(encoder, pipe_config, conn_state);
222 }
223
cpt_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)224 static void cpt_enable_hdmi(struct intel_atomic_state *state,
225 struct intel_encoder *encoder,
226 const struct intel_crtc_state *pipe_config,
227 const struct drm_connector_state *conn_state)
228 {
229 struct drm_device *dev = encoder->base.dev;
230 struct drm_i915_private *dev_priv = to_i915(dev);
231 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
232 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
233 enum pipe pipe = crtc->pipe;
234 u32 temp;
235
236 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
237
238 temp |= SDVO_ENABLE;
239 if (pipe_config->has_audio)
240 temp |= HDMI_AUDIO_ENABLE;
241
242 /*
243 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
244 *
245 * The procedure for 12bpc is as follows:
246 * 1. disable HDMI clock gating
247 * 2. enable HDMI with 8bpc
248 * 3. enable HDMI with 12bpc
249 * 4. enable HDMI clock gating
250 */
251
252 if (pipe_config->pipe_bpp > 24) {
253 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
254 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
255
256 temp &= ~SDVO_COLOR_FORMAT_MASK;
257 temp |= SDVO_COLOR_FORMAT_8bpc;
258 }
259
260 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
261 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
262
263 if (pipe_config->pipe_bpp > 24) {
264 temp &= ~SDVO_COLOR_FORMAT_MASK;
265 temp |= HDMI_COLOR_FORMAT_12bpc;
266
267 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
268 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
269
270 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
271 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
272 }
273
274 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
275 !pipe_config->has_hdmi_sink);
276 intel_audio_codec_enable(encoder, pipe_config, conn_state);
277 }
278
vlv_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)279 static void vlv_enable_hdmi(struct intel_atomic_state *state,
280 struct intel_encoder *encoder,
281 const struct intel_crtc_state *pipe_config,
282 const struct drm_connector_state *conn_state)
283 {
284 }
285
intel_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)286 static void intel_disable_hdmi(struct intel_atomic_state *state,
287 struct intel_encoder *encoder,
288 const struct intel_crtc_state *old_crtc_state,
289 const struct drm_connector_state *old_conn_state)
290 {
291 struct drm_device *dev = encoder->base.dev;
292 struct drm_i915_private *dev_priv = to_i915(dev);
293 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
294 struct intel_digital_port *dig_port =
295 hdmi_to_dig_port(intel_hdmi);
296 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
297 u32 temp;
298
299 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
300
301 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
302 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
303 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
304
305 /*
306 * HW workaround for IBX, we need to move the port
307 * to transcoder A after disabling it to allow the
308 * matching DP port to be enabled on transcoder A.
309 */
310 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
311 /*
312 * We get CPU/PCH FIFO underruns on the other pipe when
313 * doing the workaround. Sweep them under the rug.
314 */
315 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
316 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
317
318 temp &= ~SDVO_PIPE_SEL_MASK;
319 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
320 /*
321 * HW workaround, need to write this twice for issue
322 * that may result in first write getting masked.
323 */
324 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
325 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
326 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
327 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
328
329 temp &= ~SDVO_ENABLE;
330 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
331 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
332
333 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
334 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
335 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
336 }
337
338 dig_port->set_infoframes(encoder,
339 false,
340 old_crtc_state, old_conn_state);
341
342 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
343 }
344
g4x_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)345 static void g4x_disable_hdmi(struct intel_atomic_state *state,
346 struct intel_encoder *encoder,
347 const struct intel_crtc_state *old_crtc_state,
348 const struct drm_connector_state *old_conn_state)
349 {
350 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
351
352 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
353 }
354
pch_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)355 static void pch_disable_hdmi(struct intel_atomic_state *state,
356 struct intel_encoder *encoder,
357 const struct intel_crtc_state *old_crtc_state,
358 const struct drm_connector_state *old_conn_state)
359 {
360 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
361 }
362
pch_post_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)363 static void pch_post_disable_hdmi(struct intel_atomic_state *state,
364 struct intel_encoder *encoder,
365 const struct intel_crtc_state *old_crtc_state,
366 const struct drm_connector_state *old_conn_state)
367 {
368 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
369 }
370
intel_hdmi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)371 static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
372 struct intel_encoder *encoder,
373 const struct intel_crtc_state *pipe_config,
374 const struct drm_connector_state *conn_state)
375 {
376 struct intel_digital_port *dig_port =
377 enc_to_dig_port(encoder);
378
379 intel_hdmi_prepare(encoder, pipe_config);
380
381 dig_port->set_infoframes(encoder,
382 pipe_config->has_infoframe,
383 pipe_config, conn_state);
384 }
385
vlv_hdmi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)386 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
387 struct intel_encoder *encoder,
388 const struct intel_crtc_state *pipe_config,
389 const struct drm_connector_state *conn_state)
390 {
391 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
393
394 vlv_phy_pre_encoder_enable(encoder, pipe_config);
395
396 /* HDMI 1.0V-2dB */
397 vlv_set_phy_signal_level(encoder, pipe_config,
398 0x2b245f5f, 0x00002000,
399 0x5578b83a, 0x2b247878);
400
401 dig_port->set_infoframes(encoder,
402 pipe_config->has_infoframe,
403 pipe_config, conn_state);
404
405 g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
406
407 vlv_wait_port_ready(dev_priv, dig_port, 0x0);
408 }
409
vlv_hdmi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)410 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
411 struct intel_encoder *encoder,
412 const struct intel_crtc_state *pipe_config,
413 const struct drm_connector_state *conn_state)
414 {
415 intel_hdmi_prepare(encoder, pipe_config);
416
417 vlv_phy_pre_pll_enable(encoder, pipe_config);
418 }
419
chv_hdmi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)420 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
421 struct intel_encoder *encoder,
422 const struct intel_crtc_state *pipe_config,
423 const struct drm_connector_state *conn_state)
424 {
425 intel_hdmi_prepare(encoder, pipe_config);
426
427 chv_phy_pre_pll_enable(encoder, pipe_config);
428 }
429
chv_hdmi_post_pll_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)430 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
431 struct intel_encoder *encoder,
432 const struct intel_crtc_state *old_crtc_state,
433 const struct drm_connector_state *old_conn_state)
434 {
435 chv_phy_post_pll_disable(encoder, old_crtc_state);
436 }
437
vlv_hdmi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)438 static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
439 struct intel_encoder *encoder,
440 const struct intel_crtc_state *old_crtc_state,
441 const struct drm_connector_state *old_conn_state)
442 {
443 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
444 vlv_phy_reset_lanes(encoder, old_crtc_state);
445 }
446
chv_hdmi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)447 static void chv_hdmi_post_disable(struct intel_atomic_state *state,
448 struct intel_encoder *encoder,
449 const struct intel_crtc_state *old_crtc_state,
450 const struct drm_connector_state *old_conn_state)
451 {
452 struct drm_device *dev = encoder->base.dev;
453 struct drm_i915_private *dev_priv = to_i915(dev);
454
455 vlv_dpio_get(dev_priv);
456
457 /* Assert data lane reset */
458 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
459
460 vlv_dpio_put(dev_priv);
461 }
462
chv_hdmi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)463 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
464 struct intel_encoder *encoder,
465 const struct intel_crtc_state *pipe_config,
466 const struct drm_connector_state *conn_state)
467 {
468 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
469 struct drm_device *dev = encoder->base.dev;
470 struct drm_i915_private *dev_priv = to_i915(dev);
471
472 chv_phy_pre_encoder_enable(encoder, pipe_config);
473
474 /* FIXME: Program the support xxx V-dB */
475 /* Use 800mV-0dB */
476 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
477
478 dig_port->set_infoframes(encoder,
479 pipe_config->has_infoframe,
480 pipe_config, conn_state);
481
482 g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
483
484 vlv_wait_port_ready(dev_priv, dig_port, 0x0);
485
486 /* Second common lane will stay alive on its own now */
487 chv_phy_release_cl2_override(encoder);
488 }
489
490 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
491 .destroy = intel_encoder_destroy,
492 };
493
494 static enum intel_hotplug_state
intel_hdmi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)495 intel_hdmi_hotplug(struct intel_encoder *encoder,
496 struct intel_connector *connector)
497 {
498 enum intel_hotplug_state state;
499
500 state = intel_encoder_hotplug(encoder, connector);
501
502 /*
503 * On many platforms the HDMI live state signal is known to be
504 * unreliable, so we can't use it to detect if a sink is connected or
505 * not. Instead we detect if it's connected based on whether we can
506 * read the EDID or not. That in turn has a problem during disconnect,
507 * since the HPD interrupt may be raised before the DDC lines get
508 * disconnected (due to how the required length of DDC vs. HPD
509 * connector pins are specified) and so we'll still be able to get a
510 * valid EDID. To solve this schedule another detection cycle if this
511 * time around we didn't detect any change in the sink's connection
512 * status.
513 */
514 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
515 state = INTEL_HOTPLUG_RETRY;
516
517 return state;
518 }
519
g4x_hdmi_init(struct drm_i915_private * dev_priv,i915_reg_t hdmi_reg,enum port port)520 void g4x_hdmi_init(struct drm_i915_private *dev_priv,
521 i915_reg_t hdmi_reg, enum port port)
522 {
523 struct intel_digital_port *dig_port;
524 struct intel_encoder *intel_encoder;
525 struct intel_connector *intel_connector;
526
527 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
528 if (!dig_port)
529 return;
530
531 intel_connector = intel_connector_alloc();
532 if (!intel_connector) {
533 kfree(dig_port);
534 return;
535 }
536
537 intel_encoder = &dig_port->base;
538
539 mutex_init(&dig_port->hdcp_mutex);
540
541 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
542 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
543 "HDMI %c", port_name(port));
544
545 intel_encoder->hotplug = intel_hdmi_hotplug;
546 intel_encoder->compute_config = intel_hdmi_compute_config;
547 if (HAS_PCH_SPLIT(dev_priv)) {
548 intel_encoder->disable = pch_disable_hdmi;
549 intel_encoder->post_disable = pch_post_disable_hdmi;
550 } else {
551 intel_encoder->disable = g4x_disable_hdmi;
552 }
553 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
554 intel_encoder->get_config = intel_hdmi_get_config;
555 if (IS_CHERRYVIEW(dev_priv)) {
556 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
557 intel_encoder->pre_enable = chv_hdmi_pre_enable;
558 intel_encoder->enable = vlv_enable_hdmi;
559 intel_encoder->post_disable = chv_hdmi_post_disable;
560 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
561 } else if (IS_VALLEYVIEW(dev_priv)) {
562 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
563 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
564 intel_encoder->enable = vlv_enable_hdmi;
565 intel_encoder->post_disable = vlv_hdmi_post_disable;
566 } else {
567 intel_encoder->pre_enable = intel_hdmi_pre_enable;
568 if (HAS_PCH_CPT(dev_priv))
569 intel_encoder->enable = cpt_enable_hdmi;
570 else if (HAS_PCH_IBX(dev_priv))
571 intel_encoder->enable = ibx_enable_hdmi;
572 else
573 intel_encoder->enable = g4x_enable_hdmi;
574 }
575 intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
576
577 intel_encoder->type = INTEL_OUTPUT_HDMI;
578 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
579 intel_encoder->port = port;
580 if (IS_CHERRYVIEW(dev_priv)) {
581 if (port == PORT_D)
582 intel_encoder->pipe_mask = BIT(PIPE_C);
583 else
584 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
585 } else {
586 intel_encoder->pipe_mask = ~0;
587 }
588 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
589 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
590 /*
591 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
592 * to work on real hardware. And since g4x can send infoframes to
593 * only one port anyway, nothing is lost by allowing it.
594 */
595 if (IS_G4X(dev_priv))
596 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
597
598 dig_port->hdmi.hdmi_reg = hdmi_reg;
599 dig_port->dp.output_reg = INVALID_MMIO_REG;
600 dig_port->max_lanes = 4;
601
602 intel_infoframe_init(dig_port);
603
604 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
605 intel_hdmi_init_connector(dig_port, intel_connector);
606 }
607