1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH11K_HW_H
8 #define ATH11K_HW_H
9
10 #include "hal.h"
11 #include "wmi.h"
12
13 /* Target configuration defines */
14
15 /* Num VDEVS per radio */
16 #define TARGET_NUM_VDEVS(ab) (ab->hw_params.num_vdevs)
17
18 #define TARGET_NUM_PEERS_PDEV(ab) (ab->hw_params.num_peers + TARGET_NUM_VDEVS(ab))
19
20 /* Num of peers for Single Radio mode */
21 #define TARGET_NUM_PEERS_SINGLE(ab) (TARGET_NUM_PEERS_PDEV(ab))
22
23 /* Num of peers for DBS */
24 #define TARGET_NUM_PEERS_DBS(ab) (2 * TARGET_NUM_PEERS_PDEV(ab))
25
26 /* Num of peers for DBS_SBS */
27 #define TARGET_NUM_PEERS_DBS_SBS(ab) (3 * TARGET_NUM_PEERS_PDEV(ab))
28
29 /* Max num of stations (per radio) */
30 #define TARGET_NUM_STATIONS(ab) (ab->hw_params.num_peers)
31
32 #define TARGET_NUM_PEERS(ab, x) TARGET_NUM_PEERS_##x(ab)
33 #define TARGET_NUM_PEER_KEYS 2
34 #define TARGET_NUM_TIDS(ab, x) (2 * TARGET_NUM_PEERS(ab, x) + \
35 4 * TARGET_NUM_VDEVS(ab) + 8)
36
37 #define TARGET_AST_SKID_LIMIT 16
38 #define TARGET_NUM_OFFLD_PEERS 4
39 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
40
41 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
42 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
43 #define TARGET_RX_TIMEOUT_LO_PRI 100
44 #define TARGET_RX_TIMEOUT_HI_PRI 40
45
46 #define TARGET_DECAP_MODE_RAW 0
47 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
48 #define TARGET_DECAP_MODE_ETH 2
49
50 #define TARGET_SCAN_MAX_PENDING_REQS 4
51 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
52 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
53 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
54 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
55 #define TARGET_NUM_MCAST_GROUPS 12
56 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
57 #define TARGET_MCAST2UCAST_MODE 2
58 #define TARGET_TX_DBG_LOG_SIZE 1024
59 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
60 #define TARGET_VOW_CONFIG 0
61 #define TARGET_NUM_MSDU_DESC (2500)
62 #define TARGET_MAX_FRAG_ENTRIES 6
63 #define TARGET_MAX_BCN_OFFLD 16
64 #define TARGET_NUM_WDS_ENTRIES 32
65 #define TARGET_DMA_BURST_SIZE 1
66 #define TARGET_RX_BATCHMODE 1
67
68 #define ATH11K_HW_MAX_QUEUES 4
69 #define ATH11K_QUEUE_LEN 4096
70
71 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
72
73 #define ATH11K_FW_DIR "ath11k"
74
75 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"
76 #define ATH11K_BOARD_API2_FILE "board-2.bin"
77 #define ATH11K_DEFAULT_BOARD_FILE "board.bin"
78 #define ATH11K_DEFAULT_CAL_FILE "caldata.bin"
79 #define ATH11K_AMSS_FILE "amss.bin"
80 #define ATH11K_M3_FILE "m3.bin"
81 #define ATH11K_REGDB_FILE_NAME "regdb.bin"
82
83 enum ath11k_hw_rate_cck {
84 ATH11K_HW_RATE_CCK_LP_11M = 0,
85 ATH11K_HW_RATE_CCK_LP_5_5M,
86 ATH11K_HW_RATE_CCK_LP_2M,
87 ATH11K_HW_RATE_CCK_LP_1M,
88 ATH11K_HW_RATE_CCK_SP_11M,
89 ATH11K_HW_RATE_CCK_SP_5_5M,
90 ATH11K_HW_RATE_CCK_SP_2M,
91 };
92
93 enum ath11k_hw_rate_ofdm {
94 ATH11K_HW_RATE_OFDM_48M = 0,
95 ATH11K_HW_RATE_OFDM_24M,
96 ATH11K_HW_RATE_OFDM_12M,
97 ATH11K_HW_RATE_OFDM_6M,
98 ATH11K_HW_RATE_OFDM_54M,
99 ATH11K_HW_RATE_OFDM_36M,
100 ATH11K_HW_RATE_OFDM_18M,
101 ATH11K_HW_RATE_OFDM_9M,
102 };
103
104 enum ath11k_bus {
105 ATH11K_BUS_AHB,
106 ATH11K_BUS_PCI,
107 };
108
109 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
110
111 struct hal_rx_desc;
112 struct hal_tcl_data_cmd;
113
114 struct ath11k_hw_ring_mask {
115 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
116 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
117 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
118 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
119 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
120 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
121 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
122 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
123 };
124
125 struct ath11k_hw_hal_params {
126 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
127 };
128
129 struct ath11k_hw_params {
130 const char *name;
131 u16 hw_rev;
132 u8 max_radios;
133 u32 bdf_addr;
134
135 struct {
136 const char *dir;
137 size_t board_size;
138 size_t cal_offset;
139 } fw;
140
141 const struct ath11k_hw_ops *hw_ops;
142 const struct ath11k_hw_ring_mask *ring_mask;
143
144 bool internal_sleep_clock;
145
146 const struct ath11k_hw_regs *regs;
147 u32 qmi_service_ins_id;
148 const struct ce_attr *host_ce_config;
149 u32 ce_count;
150 const struct ce_pipe_config *target_ce_config;
151 u32 target_ce_count;
152 const struct service_to_pipe *svc_to_ce_map;
153 u32 svc_to_ce_map_len;
154
155 bool single_pdev_only;
156 u32 rfkill_pin;
157 u32 rfkill_cfg;
158 u32 rfkill_on_level;
159
160 bool rxdma1_enable;
161 int num_rxmda_per_pdev;
162 bool rx_mac_buf_ring;
163 bool vdev_start_delay;
164 bool htt_peer_map_v2;
165
166 struct {
167 u8 fft_sz;
168 u8 fft_pad_sz;
169 u8 summary_pad_sz;
170 u8 fft_hdr_len;
171 u16 max_fft_bins;
172 } spectral;
173
174 u16 interface_modes;
175 bool supports_monitor;
176 bool full_monitor_mode;
177 bool supports_shadow_regs;
178 bool idle_ps;
179 bool supports_sta_ps;
180 bool cold_boot_calib;
181 int fw_mem_mode;
182 u32 num_vdevs;
183 u32 num_peers;
184 bool supports_suspend;
185 u32 hal_desc_sz;
186 bool supports_regdb;
187 bool fix_l1ss;
188 bool credit_flow;
189 u8 max_tx_ring;
190 const struct ath11k_hw_hal_params *hal_params;
191 bool supports_dynamic_smps_6ghz;
192 bool alloc_cacheable_memory;
193 bool supports_rssi_stats;
194 bool fw_wmi_diag_event;
195 bool current_cc_support;
196 bool dbr_debug_support;
197 bool global_reset;
198 const struct cfg80211_sar_capa *bios_sar_capa;
199 bool m3_fw_support;
200 bool fixed_bdf_addr;
201 bool fixed_mem_region;
202 bool static_window_map;
203 bool hybrid_bus_type;
204 bool fixed_fw_mem;
205 bool support_off_channel_tx;
206 };
207
208 struct ath11k_hw_ops {
209 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
210 void (*wmi_init_config)(struct ath11k_base *ab,
211 struct target_resource_config *config);
212 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
213 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
214 void (*tx_mesh_enable)(struct ath11k_base *ab,
215 struct hal_tcl_data_cmd *tcl_cmd);
216 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
217 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
218 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
219 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
220 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
221 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
222 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
223 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
224 bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);
225 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
226 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
227 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
228 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
229 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
230 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
231 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
232 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
233 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
234 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
235 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
236 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
237 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
238 struct hal_rx_desc *ldesc);
239 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
240 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
241 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
242 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
243 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
244 void (*reo_setup)(struct ath11k_base *ab);
245 u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
246 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
247 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
248 };
249
250 extern const struct ath11k_hw_ops ipq8074_ops;
251 extern const struct ath11k_hw_ops ipq6018_ops;
252 extern const struct ath11k_hw_ops qca6390_ops;
253 extern const struct ath11k_hw_ops qcn9074_ops;
254 extern const struct ath11k_hw_ops wcn6855_ops;
255 extern const struct ath11k_hw_ops wcn6750_ops;
256
257 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
258 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
259 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
260
261 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074;
262 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390;
263
264 static inline
ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params * hw,int pdev_idx)265 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
266 int pdev_idx)
267 {
268 if (hw->hw_ops->get_hw_mac_from_pdev_id)
269 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
270
271 return 0;
272 }
273
ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params * hw,int mac_id)274 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,
275 int mac_id)
276 {
277 if (hw->hw_ops->mac_id_to_pdev_id)
278 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
279
280 return 0;
281 }
282
ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params * hw,int mac_id)283 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,
284 int mac_id)
285 {
286 if (hw->hw_ops->mac_id_to_srng_id)
287 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
288
289 return 0;
290 }
291
292 struct ath11k_fw_ie {
293 __le32 id;
294 __le32 len;
295 u8 data[];
296 };
297
298 enum ath11k_bd_ie_board_type {
299 ATH11K_BD_IE_BOARD_NAME = 0,
300 ATH11K_BD_IE_BOARD_DATA = 1,
301 };
302
303 enum ath11k_bd_ie_regdb_type {
304 ATH11K_BD_IE_REGDB_NAME = 0,
305 ATH11K_BD_IE_REGDB_DATA = 1,
306 };
307
308 enum ath11k_bd_ie_type {
309 /* contains sub IEs of enum ath11k_bd_ie_board_type */
310 ATH11K_BD_IE_BOARD = 0,
311 /* contains sub IEs of enum ath11k_bd_ie_regdb_type */
312 ATH11K_BD_IE_REGDB = 1,
313 };
314
315 struct ath11k_hw_regs {
316 u32 hal_tcl1_ring_base_lsb;
317 u32 hal_tcl1_ring_base_msb;
318 u32 hal_tcl1_ring_id;
319 u32 hal_tcl1_ring_misc;
320 u32 hal_tcl1_ring_tp_addr_lsb;
321 u32 hal_tcl1_ring_tp_addr_msb;
322 u32 hal_tcl1_ring_consumer_int_setup_ix0;
323 u32 hal_tcl1_ring_consumer_int_setup_ix1;
324 u32 hal_tcl1_ring_msi1_base_lsb;
325 u32 hal_tcl1_ring_msi1_base_msb;
326 u32 hal_tcl1_ring_msi1_data;
327 u32 hal_tcl2_ring_base_lsb;
328 u32 hal_tcl_ring_base_lsb;
329
330 u32 hal_tcl_status_ring_base_lsb;
331
332 u32 hal_reo1_ring_base_lsb;
333 u32 hal_reo1_ring_base_msb;
334 u32 hal_reo1_ring_id;
335 u32 hal_reo1_ring_misc;
336 u32 hal_reo1_ring_hp_addr_lsb;
337 u32 hal_reo1_ring_hp_addr_msb;
338 u32 hal_reo1_ring_producer_int_setup;
339 u32 hal_reo1_ring_msi1_base_lsb;
340 u32 hal_reo1_ring_msi1_base_msb;
341 u32 hal_reo1_ring_msi1_data;
342 u32 hal_reo2_ring_base_lsb;
343 u32 hal_reo1_aging_thresh_ix_0;
344 u32 hal_reo1_aging_thresh_ix_1;
345 u32 hal_reo1_aging_thresh_ix_2;
346 u32 hal_reo1_aging_thresh_ix_3;
347
348 u32 hal_reo1_ring_hp;
349 u32 hal_reo1_ring_tp;
350 u32 hal_reo2_ring_hp;
351
352 u32 hal_reo_tcl_ring_base_lsb;
353 u32 hal_reo_tcl_ring_hp;
354
355 u32 hal_reo_status_ring_base_lsb;
356 u32 hal_reo_status_hp;
357
358 u32 hal_reo_cmd_ring_base_lsb;
359 u32 hal_reo_cmd_ring_hp;
360
361 u32 hal_sw2reo_ring_base_lsb;
362 u32 hal_sw2reo_ring_hp;
363
364 u32 hal_seq_wcss_umac_ce0_src_reg;
365 u32 hal_seq_wcss_umac_ce0_dst_reg;
366 u32 hal_seq_wcss_umac_ce1_src_reg;
367 u32 hal_seq_wcss_umac_ce1_dst_reg;
368
369 u32 hal_wbm_idle_link_ring_base_lsb;
370 u32 hal_wbm_idle_link_ring_misc;
371
372 u32 hal_wbm_release_ring_base_lsb;
373
374 u32 hal_wbm0_release_ring_base_lsb;
375 u32 hal_wbm1_release_ring_base_lsb;
376
377 u32 pcie_qserdes_sysclk_en_sel;
378 u32 pcie_pcs_osc_dtct_config_base;
379
380 u32 hal_shadow_base_addr;
381 u32 hal_reo1_misc_ctl;
382 };
383
384 extern const struct ath11k_hw_regs ipq8074_regs;
385 extern const struct ath11k_hw_regs qca6390_regs;
386 extern const struct ath11k_hw_regs qcn9074_regs;
387 extern const struct ath11k_hw_regs wcn6855_regs;
388 extern const struct ath11k_hw_regs wcn6750_regs;
389
ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)390 static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
391 {
392 switch (type) {
393 case ATH11K_BD_IE_BOARD:
394 return "board data";
395 case ATH11K_BD_IE_REGDB:
396 return "regdb data";
397 }
398
399 return "unknown";
400 }
401
402 extern const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855;
403 #endif
404