1 /*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41 #ifndef _PM8001_SAS_H_
42 #define _PM8001_SAS_H_
43
44 #include <linux/kernel.h>
45 #include <linux/module.h>
46 #include <linux/spinlock.h>
47 #include <linux/delay.h>
48 #include <linux/types.h>
49 #include <linux/ctype.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/pci.h>
52 #include <linux/interrupt.h>
53 #include <linux/workqueue.h>
54 #include <scsi/libsas.h>
55 #include <scsi/scsi_tcq.h>
56 #include <scsi/sas_ata.h>
57 #include <linux/atomic.h>
58 #include "pm8001_defs.h"
59
60 #define DRV_NAME "pm80xx"
61 #define DRV_VERSION "0.1.40"
62 #define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
63 #define PM8001_INIT_LOGGING 0x02 /* driver init logging */
64 #define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
65 #define PM8001_IO_LOGGING 0x08 /* I/O path logging */
66 #define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
67 #define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
68 #define PM8001_MSG_LOGGING 0x40 /* misc message logging */
69 #define PM8001_DEV_LOGGING 0x80 /* development message logging */
70 #define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */
71 #define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */
72
73 #define pm8001_info(HBA, fmt, ...) \
74 pr_info("%s:: %s %d: " fmt, \
75 (HBA)->name, __func__, __LINE__, ##__VA_ARGS__)
76
77 #define pm8001_dbg(HBA, level, fmt, ...) \
78 do { \
79 if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING)) \
80 pm8001_info(HBA, fmt, ##__VA_ARGS__); \
81 } while (0)
82
83 #define PM8001_USE_TASKLET
84 #define PM8001_USE_MSIX
85 #define PM8001_READ_VPD
86
87
88 #define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
89 || (dev->device == 0X8076) \
90 || (dev->device == 0X8077) \
91 || (dev->device == 0X8070) \
92 || (dev->device == 0X8072))
93
94 #define PM8001_NAME_LENGTH 32/* generic length of strings */
95 extern struct list_head hba_list;
96 extern const struct pm8001_dispatch pm8001_8001_dispatch;
97 extern const struct pm8001_dispatch pm8001_80xx_dispatch;
98
99 struct pm8001_hba_info;
100 struct pm8001_ccb_info;
101 struct pm8001_device;
102
103 struct pm8001_ioctl_payload {
104 u32 signature;
105 u16 major_function;
106 u16 minor_function;
107 u16 status;
108 u16 offset;
109 u16 id;
110 u32 wr_length;
111 u32 rd_length;
112 u8 *func_specific;
113 };
114
115 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
116 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
117 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
118 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
119 #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
120 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
121 #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
122 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
123 #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN 0x18 /* TOTALLEN */
124 #define MPI_FATAL_EDUMP_TABLE_SIGNATURE 0x1C /* SIGNITURE */
125 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
126 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
127 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
128 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
129 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
130 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
131 #define TYPE_GSM_SPACE 1
132 #define TYPE_QUEUE 2
133 #define TYPE_FATAL 3
134 #define TYPE_NON_FATAL 4
135 #define TYPE_INBOUND 1
136 #define TYPE_OUTBOUND 2
137 struct forensic_data {
138 u32 data_type;
139 union {
140 struct {
141 u32 direct_len;
142 u32 direct_offset;
143 void *direct_data;
144 } gsm_buf;
145 struct {
146 u16 queue_type;
147 u16 queue_index;
148 u32 direct_len;
149 void *direct_data;
150 } queue_buf;
151 struct {
152 u32 direct_len;
153 u32 direct_offset;
154 u32 read_len;
155 void *direct_data;
156 } data_buf;
157 };
158 };
159
160 /* bit31-26 - mask bar */
161 #define SCRATCH_PAD0_BAR_MASK 0xFC000000
162 /* bit25-0 - offset mask */
163 #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
164 /* if AAP error state */
165 #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
166 /* Inbound doorbell bit7 */
167 #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
168 /* Inbound doorbell bit7 SPCV */
169 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
170 #define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
171
172 struct pm8001_dispatch {
173 char *name;
174 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
175 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
176 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
177 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
178 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
179 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
180 u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
181 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
182 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
183 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
184 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
185 int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
186 struct pm8001_ccb_info *ccb);
187 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
188 struct pm8001_ccb_info *ccb);
189 int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
190 struct pm8001_ccb_info *ccb);
191 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
192 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
193 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
194 struct pm8001_device *pm8001_dev, u32 flag);
195 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
196 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
197 u32 phy_id, u32 phy_op);
198 int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
199 struct pm8001_ccb_info *ccb);
200 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
201 struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf);
202 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
203 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
204 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
205 void *payload);
206 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
207 struct pm8001_device *pm8001_dev, u32 state);
208 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
209 u32 state);
210 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
211 u32 state);
212 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
213 int (*fatal_errors)(struct pm8001_hba_info *pm8001_ha);
214 void (*hw_event_ack_req)(struct pm8001_hba_info *pm8001_ha,
215 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0,
216 u32 param1);
217 };
218
219 struct pm8001_chip_info {
220 u32 encrypt;
221 u32 n_phy;
222 const struct pm8001_dispatch *dispatch;
223 };
224 #define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
225
226 struct pm8001_port {
227 struct asd_sas_port sas_port;
228 u8 port_attached;
229 u16 wide_port_phymap;
230 u8 port_state;
231 u8 port_id;
232 struct list_head list;
233 };
234
235 struct pm8001_phy {
236 struct pm8001_hba_info *pm8001_ha;
237 struct pm8001_port *port;
238 struct asd_sas_phy sas_phy;
239 struct sas_identify identify;
240 struct scsi_device *sdev;
241 u64 dev_sas_addr;
242 u32 phy_type;
243 struct completion *enable_completion;
244 u32 frame_rcvd_size;
245 u8 frame_rcvd[32];
246 u8 phy_attached;
247 u8 phy_state;
248 enum sas_linkrate minimum_linkrate;
249 enum sas_linkrate maximum_linkrate;
250 struct completion *reset_completion;
251 bool port_reset_status;
252 bool reset_success;
253 };
254
255 /* port reset status */
256 #define PORT_RESET_SUCCESS 0x00
257 #define PORT_RESET_TMO 0x01
258
259 struct pm8001_device {
260 enum sas_device_type dev_type;
261 struct domain_device *sas_device;
262 u32 attached_phy;
263 u32 id;
264 struct completion *dcompletion;
265 struct completion *setds_completion;
266 u32 device_id;
267 atomic_t running_req;
268 };
269
270 struct pm8001_prd_imt {
271 __le32 len;
272 __le32 e;
273 };
274
275 struct pm8001_prd {
276 __le64 addr; /* 64-bit buffer address */
277 struct pm8001_prd_imt im_len; /* 64-bit length */
278 } __attribute__ ((packed));
279 /*
280 * CCB(Command Control Block)
281 */
282 struct pm8001_ccb_info {
283 struct sas_task *task;
284 u32 n_elem;
285 u32 ccb_tag;
286 dma_addr_t ccb_dma_handle;
287 struct pm8001_device *device;
288 struct pm8001_prd *buf_prd;
289 struct fw_control_ex *fw_control_context;
290 u8 open_retry;
291 };
292
293 struct mpi_mem {
294 void *virt_ptr;
295 dma_addr_t phys_addr;
296 u32 phys_addr_hi;
297 u32 phys_addr_lo;
298 u32 total_len;
299 u32 num_elements;
300 u32 element_size;
301 u32 alignment;
302 };
303
304 struct mpi_mem_req {
305 /* The number of element in the mpiMemory array */
306 u32 count;
307 /* The array of structures that define memroy regions*/
308 struct mpi_mem region[USI_MAX_MEMCNT];
309 };
310
311 struct encrypt {
312 u32 cipher_mode;
313 u32 sec_mode;
314 u32 status;
315 u32 flag;
316 };
317
318 struct sas_phy_attribute_table {
319 u32 phystart1_16[16];
320 u32 outbound_hw_event_pid1_16[16];
321 };
322
323 union main_cfg_table {
324 struct {
325 u32 signature;
326 u32 interface_rev;
327 u32 firmware_rev;
328 u32 max_out_io;
329 u32 max_sgl;
330 u32 ctrl_cap_flag;
331 u32 gst_offset;
332 u32 inbound_queue_offset;
333 u32 outbound_queue_offset;
334 u32 inbound_q_nppd_hppd;
335 u32 outbound_hw_event_pid0_3;
336 u32 outbound_hw_event_pid4_7;
337 u32 outbound_ncq_event_pid0_3;
338 u32 outbound_ncq_event_pid4_7;
339 u32 outbound_tgt_ITNexus_event_pid0_3;
340 u32 outbound_tgt_ITNexus_event_pid4_7;
341 u32 outbound_tgt_ssp_event_pid0_3;
342 u32 outbound_tgt_ssp_event_pid4_7;
343 u32 outbound_tgt_smp_event_pid0_3;
344 u32 outbound_tgt_smp_event_pid4_7;
345 u32 upper_event_log_addr;
346 u32 lower_event_log_addr;
347 u32 event_log_size;
348 u32 event_log_option;
349 u32 upper_iop_event_log_addr;
350 u32 lower_iop_event_log_addr;
351 u32 iop_event_log_size;
352 u32 iop_event_log_option;
353 u32 fatal_err_interrupt;
354 u32 fatal_err_dump_offset0;
355 u32 fatal_err_dump_length0;
356 u32 fatal_err_dump_offset1;
357 u32 fatal_err_dump_length1;
358 u32 hda_mode_flag;
359 u32 anolog_setup_table_offset;
360 u32 rsvd[4];
361 } pm8001_tbl;
362
363 struct {
364 u32 signature;
365 u32 interface_rev;
366 u32 firmware_rev;
367 u32 max_out_io;
368 u32 max_sgl;
369 u32 ctrl_cap_flag;
370 u32 gst_offset;
371 u32 inbound_queue_offset;
372 u32 outbound_queue_offset;
373 u32 inbound_q_nppd_hppd;
374 u32 rsvd[8];
375 u32 crc_core_dump;
376 u32 rsvd1;
377 u32 upper_event_log_addr;
378 u32 lower_event_log_addr;
379 u32 event_log_size;
380 u32 event_log_severity;
381 u32 upper_pcs_event_log_addr;
382 u32 lower_pcs_event_log_addr;
383 u32 pcs_event_log_size;
384 u32 pcs_event_log_severity;
385 u32 fatal_err_interrupt;
386 u32 fatal_err_dump_offset0;
387 u32 fatal_err_dump_length0;
388 u32 fatal_err_dump_offset1;
389 u32 fatal_err_dump_length1;
390 u32 gpio_led_mapping;
391 u32 analog_setup_table_offset;
392 u32 int_vec_table_offset;
393 u32 phy_attr_table_offset;
394 u32 port_recovery_timer;
395 u32 interrupt_reassertion_delay;
396 u32 fatal_n_non_fatal_dump; /* 0x28 */
397 u32 ila_version;
398 u32 inc_fw_version;
399 } pm80xx_tbl;
400 };
401
402 union general_status_table {
403 struct {
404 u32 gst_len_mpistate;
405 u32 iq_freeze_state0;
406 u32 iq_freeze_state1;
407 u32 msgu_tcnt;
408 u32 iop_tcnt;
409 u32 rsvd;
410 u32 phy_state[8];
411 u32 gpio_input_val;
412 u32 rsvd1[2];
413 u32 recover_err_info[8];
414 } pm8001_tbl;
415 struct {
416 u32 gst_len_mpistate;
417 u32 iq_freeze_state0;
418 u32 iq_freeze_state1;
419 u32 msgu_tcnt;
420 u32 iop_tcnt;
421 u32 rsvd[9];
422 u32 gpio_input_val;
423 u32 rsvd1[2];
424 u32 recover_err_info[8];
425 } pm80xx_tbl;
426 };
427 struct inbound_queue_table {
428 u32 element_pri_size_cnt;
429 u32 upper_base_addr;
430 u32 lower_base_addr;
431 u32 ci_upper_base_addr;
432 u32 ci_lower_base_addr;
433 u32 pi_pci_bar;
434 u32 pi_offset;
435 u32 total_length;
436 void *base_virt;
437 void *ci_virt;
438 u32 reserved;
439 __le32 consumer_index;
440 u32 producer_idx;
441 spinlock_t iq_lock;
442 };
443 struct outbound_queue_table {
444 u32 element_size_cnt;
445 u32 upper_base_addr;
446 u32 lower_base_addr;
447 void *base_virt;
448 u32 pi_upper_base_addr;
449 u32 pi_lower_base_addr;
450 u32 ci_pci_bar;
451 u32 ci_offset;
452 u32 total_length;
453 void *pi_virt;
454 u32 interrup_vec_cnt_delay;
455 u32 dinterrup_to_pci_offset;
456 __le32 producer_index;
457 u32 consumer_idx;
458 spinlock_t oq_lock;
459 unsigned long lock_flags;
460 };
461 struct pm8001_hba_memspace {
462 void __iomem *memvirtaddr;
463 u64 membase;
464 u32 memsize;
465 };
466 struct isr_param {
467 struct pm8001_hba_info *drv_inst;
468 u32 irq_id;
469 };
470 struct pm8001_hba_info {
471 char name[PM8001_NAME_LENGTH];
472 struct list_head list;
473 unsigned long flags;
474 spinlock_t lock;/* host-wide lock */
475 spinlock_t bitmap_lock;
476 struct pci_dev *pdev;/* our device */
477 struct device *dev;
478 struct pm8001_hba_memspace io_mem[6];
479 struct mpi_mem_req memoryMap;
480 struct encrypt encrypt_info; /* support encryption */
481 struct forensic_data forensic_info;
482 u32 fatal_bar_loc;
483 u32 forensic_last_offset;
484 u32 fatal_forensic_shift_offset;
485 u32 forensic_fatal_step;
486 u32 forensic_preserved_accumulated_transfer;
487 u32 evtlog_ib_offset;
488 u32 evtlog_ob_offset;
489 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
490 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
491 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
492 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
493 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
494 void __iomem *pspa_q_tbl_addr;
495 /*MPI SAS PHY attributes Queue Config Table Addr*/
496 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
497 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
498 union main_cfg_table main_cfg_tbl;
499 union general_status_table gs_tbl;
500 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM];
501 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
502 struct sas_phy_attribute_table phy_attr_table;
503 /* MPI SAS PHY attributes */
504 u8 sas_addr[SAS_ADDR_SIZE];
505 struct sas_ha_struct *sas;/* SCSI/SAS glue */
506 struct Scsi_Host *shost;
507 u32 chip_id;
508 const struct pm8001_chip_info *chip;
509 struct completion *nvmd_completion;
510 int tags_num;
511 unsigned long *tags;
512 struct pm8001_phy phy[PM8001_MAX_PHYS];
513 struct pm8001_port port[PM8001_MAX_PHYS];
514 u32 id;
515 u32 irq;
516 u32 iomb_size; /* SPC and SPCV IOMB size */
517 struct pm8001_device *devices;
518 struct pm8001_ccb_info *ccb_info;
519 u32 ccb_count;
520 #ifdef PM8001_USE_MSIX
521 int number_of_intr;/*will be used in remove()*/
522 char intr_drvname[PM8001_MAX_MSIX_VEC]
523 [PM8001_NAME_LENGTH+1+3+1];
524 #endif
525 #ifdef PM8001_USE_TASKLET
526 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
527 #endif
528 u32 logging_level;
529 u32 link_rate;
530 u32 fw_status;
531 u32 smp_exp_mode;
532 bool controller_fatal_error;
533 const struct firmware *fw_image;
534 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
535 u32 reset_in_progress;
536 u32 non_fatal_count;
537 u32 non_fatal_read_length;
538 u32 max_q_num;
539 u32 ib_offset;
540 u32 ob_offset;
541 u32 ci_offset;
542 u32 pi_offset;
543 u32 max_memcnt;
544 };
545
546 struct pm8001_work {
547 struct work_struct work;
548 struct pm8001_hba_info *pm8001_ha;
549 void *data;
550 int handler;
551 };
552
553 struct pm8001_fw_image_header {
554 u8 vender_id[8];
555 u8 product_id;
556 u8 hardware_rev;
557 u8 dest_partition;
558 u8 reserved;
559 u8 fw_rev[4];
560 __be32 image_length;
561 __be32 image_crc;
562 __be32 startup_entry;
563 } __attribute__((packed, aligned(4)));
564
565
566 /**
567 * FW Flash Update status values
568 */
569 #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
570 #define FLASH_UPDATE_IN_PROGRESS 0x01
571 #define FLASH_UPDATE_HDR_ERR 0x02
572 #define FLASH_UPDATE_OFFSET_ERR 0x03
573 #define FLASH_UPDATE_CRC_ERR 0x04
574 #define FLASH_UPDATE_LENGTH_ERR 0x05
575 #define FLASH_UPDATE_HW_ERR 0x06
576 #define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
577 #define FLASH_UPDATE_DISABLED 0x11
578
579 #define NCQ_READ_LOG_FLAG 0x80000000
580 #define NCQ_ABORT_ALL_FLAG 0x40000000
581 #define NCQ_2ND_RLE_FLAG 0x20000000
582
583 /* Device states */
584 #define DS_OPERATIONAL 0x01
585 #define DS_PORT_IN_RESET 0x02
586 #define DS_IN_RECOVERY 0x03
587 #define DS_IN_ERROR 0x04
588 #define DS_NON_OPERATIONAL 0x07
589
590 /**
591 * brief param structure for firmware flash update.
592 */
593 struct fw_flash_updata_info {
594 u32 cur_image_offset;
595 u32 cur_image_len;
596 u32 total_image_len;
597 struct pm8001_prd sgl;
598 };
599
600 struct fw_control_info {
601 u32 retcode;/*ret code (status)*/
602 u32 phase;/*ret code phase*/
603 u32 phaseCmplt;/*percent complete for the current
604 update phase */
605 u32 version;/*Hex encoded firmware version number*/
606 u32 offset;/*Used for downloading firmware */
607 u32 len; /*len of buffer*/
608 u32 size;/* Used in OS VPD and Trace get size
609 operations.*/
610 u32 reserved;/* padding required for 64 bit
611 alignment */
612 u8 buffer[1];/* Start of buffer */
613 };
614 struct fw_control_ex {
615 struct fw_control_info *fw_control;
616 void *buffer;/* keep buffer pointer to be
617 freed when the response comes*/
618 void *virtAddr;/* keep virtual address of the data */
619 void *usrAddr;/* keep virtual address of the
620 user data */
621 dma_addr_t phys_addr;
622 u32 len; /* len of buffer */
623 void *payload; /* pointer to IOCTL Payload */
624 u8 inProgress;/*if 1 - the IOCTL request is in
625 progress */
626 void *param1;
627 void *param2;
628 void *param3;
629 };
630
631 /* pm8001 workqueue */
632 extern struct workqueue_struct *pm8001_wq;
633
634 /******************** function prototype *********************/
635 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
636 void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
637 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
638 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
639 struct pm8001_ccb_info *ccb);
640 int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
641 void *funcdata);
642 void pm8001_scan_start(struct Scsi_Host *shost);
643 int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
644 int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
645 int pm8001_abort_task(struct sas_task *task);
646 int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
647 int pm8001_dev_found(struct domain_device *dev);
648 void pm8001_dev_gone(struct domain_device *dev);
649 int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
650 int pm8001_I_T_nexus_reset(struct domain_device *dev);
651 int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
652 int pm8001_query_task(struct sas_task *task);
653 void pm8001_port_formed(struct asd_sas_phy *sas_phy);
654 void pm8001_open_reject_retry(
655 struct pm8001_hba_info *pm8001_ha,
656 struct sas_task *task_to_close,
657 struct pm8001_device *device_to_close);
658 int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
659 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
660 u32 mem_size, u32 align);
661
662 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
663 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
664 u32 q_index, u32 opCode, void *payload, size_t nb,
665 u32 responseQueue);
666 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
667 u16 messageSize, void **messagePtr);
668 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
669 struct outbound_queue_table *circularQ, u8 bc);
670 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
671 struct outbound_queue_table *circularQ,
672 void **messagePtr1, u8 *pBC);
673 int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
674 struct pm8001_device *pm8001_dev, u32 state);
675 int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
676 void *payload);
677 int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
678 void *fw_flash_updata_info, u32 tag);
679 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
680 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
681 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
682 struct pm8001_ccb_info *ccb,
683 struct sas_tmf_task *tmf);
684 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
685 struct pm8001_ccb_info *ccb);
686 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
687 void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
688 void pm8001_work_fn(struct work_struct *work);
689 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
690 void *data, int handler);
691 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
692 void *piomb);
693 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
694 void *piomb);
695 void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
696 void *piomb);
697 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
698 void *piomb);
699 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
700 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
701 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
702 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
703 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
704 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
705 void *piomb);
706 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb);
707 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
708 struct sas_task *pm8001_alloc_task(void);
709 void pm8001_task_done(struct sas_task *task);
710 void pm8001_free_task(struct sas_task *task);
711 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
712 struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
713 u32 device_id);
714 int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
715
716 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
717 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
718 u32 length, u8 *buf);
719 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
720 u32 phy, u32 length, u32 *buf);
721 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
722 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
723 struct device_attribute *attr, char *buf);
724 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
725 struct device_attribute *attr, char *buf);
726 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
727 int pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha);
728 void pm8001_free_dev(struct pm8001_device *pm8001_dev);
729 /* ctl shared API */
730 extern const struct attribute_group *pm8001_host_groups[];
731
732 #define PM8001_INVALID_TAG ((u32)-1)
733
734 /*
735 * Allocate a new tag and return the corresponding ccb after initializing it.
736 */
737 static inline struct pm8001_ccb_info *
pm8001_ccb_alloc(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * dev,struct sas_task * task)738 pm8001_ccb_alloc(struct pm8001_hba_info *pm8001_ha,
739 struct pm8001_device *dev, struct sas_task *task)
740 {
741 struct pm8001_ccb_info *ccb;
742 u32 tag;
743
744 if (pm8001_tag_alloc(pm8001_ha, &tag)) {
745 pm8001_dbg(pm8001_ha, FAIL, "Failed to allocate a tag\n");
746 return NULL;
747 }
748
749 ccb = &pm8001_ha->ccb_info[tag];
750 ccb->task = task;
751 ccb->n_elem = 0;
752 ccb->ccb_tag = tag;
753 ccb->device = dev;
754 ccb->fw_control_context = NULL;
755 ccb->open_retry = 0;
756
757 return ccb;
758 }
759
760 /*
761 * Free the tag of an initialized ccb.
762 */
pm8001_ccb_free(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)763 static inline void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha,
764 struct pm8001_ccb_info *ccb)
765 {
766 u32 tag = ccb->ccb_tag;
767
768 /*
769 * Cleanup the ccb to make sure that a manual scan of the adapter
770 * ccb_info array can detect ccb's that are in use.
771 * C.f. pm8001_open_reject_retry()
772 */
773 ccb->task = NULL;
774 ccb->ccb_tag = PM8001_INVALID_TAG;
775 ccb->device = NULL;
776 ccb->fw_control_context = NULL;
777
778 pm8001_tag_free(pm8001_ha, tag);
779 }
780
pm8001_ccb_task_free_done(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)781 static inline void pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
782 struct pm8001_ccb_info *ccb)
783 {
784 struct sas_task *task = ccb->task;
785
786 pm8001_ccb_task_free(pm8001_ha, ccb);
787 smp_mb(); /*in order to force CPU ordering*/
788 task->task_done(task);
789 }
790 void pm8001_setds_completion(struct domain_device *dev);
791 void pm8001_tmf_aborted(struct sas_task *task);
792
793 #endif
794
795