1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/export.h>
7 #include <linux/err.h>
8 #include <linux/device.h>
9 #include <linux/pci.h>
10 #include <linux/interrupt.h>
11 #include <linux/wait.h>
12 #include <linux/types.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/log2.h>
16 #include <linux/string.h>
17 
18 #include "pci_hw.h"
19 #include "pci.h"
20 #include "core.h"
21 #include "cmd.h"
22 #include "port.h"
23 #include "resources.h"
24 
25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
26 	iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
27 #define mlxsw_pci_read32(mlxsw_pci, reg) \
28 	ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
29 
30 enum mlxsw_pci_queue_type {
31 	MLXSW_PCI_QUEUE_TYPE_SDQ,
32 	MLXSW_PCI_QUEUE_TYPE_RDQ,
33 	MLXSW_PCI_QUEUE_TYPE_CQ,
34 	MLXSW_PCI_QUEUE_TYPE_EQ,
35 };
36 
37 #define MLXSW_PCI_QUEUE_TYPE_COUNT	4
38 
39 static const u16 mlxsw_pci_doorbell_type_offset[] = {
40 	MLXSW_PCI_DOORBELL_SDQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
41 	MLXSW_PCI_DOORBELL_RDQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
42 	MLXSW_PCI_DOORBELL_CQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_CQ */
43 	MLXSW_PCI_DOORBELL_EQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_EQ */
44 };
45 
46 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
47 	0, /* unused */
48 	0, /* unused */
49 	MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
50 	MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
51 };
52 
53 struct mlxsw_pci_mem_item {
54 	char *buf;
55 	dma_addr_t mapaddr;
56 	size_t size;
57 };
58 
59 struct mlxsw_pci_queue_elem_info {
60 	char *elem; /* pointer to actual dma mapped element mem chunk */
61 	union {
62 		struct {
63 			struct sk_buff *skb;
64 		} sdq;
65 		struct {
66 			struct sk_buff *skb;
67 		} rdq;
68 	} u;
69 };
70 
71 struct mlxsw_pci_queue {
72 	spinlock_t lock; /* for queue accesses */
73 	struct mlxsw_pci_mem_item mem_item;
74 	struct mlxsw_pci_queue_elem_info *elem_info;
75 	u16 producer_counter;
76 	u16 consumer_counter;
77 	u16 count; /* number of elements in queue */
78 	u8 num; /* queue number */
79 	u8 elem_size; /* size of one element */
80 	enum mlxsw_pci_queue_type type;
81 	struct tasklet_struct tasklet; /* queue processing tasklet */
82 	struct mlxsw_pci *pci;
83 	union {
84 		struct {
85 			u32 comp_sdq_count;
86 			u32 comp_rdq_count;
87 			enum mlxsw_pci_cqe_v v;
88 		} cq;
89 		struct {
90 			u32 ev_cmd_count;
91 			u32 ev_comp_count;
92 			u32 ev_other_count;
93 		} eq;
94 	} u;
95 };
96 
97 struct mlxsw_pci_queue_type_group {
98 	struct mlxsw_pci_queue *q;
99 	u8 count; /* number of queues in group */
100 };
101 
102 struct mlxsw_pci {
103 	struct pci_dev *pdev;
104 	u8 __iomem *hw_addr;
105 	u64 free_running_clock_offset;
106 	u64 utc_sec_offset;
107 	u64 utc_nsec_offset;
108 	struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
109 	u32 doorbell_offset;
110 	struct mlxsw_core *core;
111 	struct {
112 		struct mlxsw_pci_mem_item *items;
113 		unsigned int count;
114 	} fw_area;
115 	struct {
116 		struct mlxsw_pci_mem_item out_mbox;
117 		struct mlxsw_pci_mem_item in_mbox;
118 		struct mutex lock; /* Lock access to command registers */
119 		bool nopoll;
120 		wait_queue_head_t wait;
121 		bool wait_done;
122 		struct {
123 			u8 status;
124 			u64 out_param;
125 		} comp;
126 	} cmd;
127 	struct mlxsw_bus_info bus_info;
128 	const struct pci_device_id *id;
129 	enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */
130 	u8 num_sdq_cqs; /* Number of CQs used for SDQs */
131 };
132 
mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue * q)133 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
134 {
135 	tasklet_schedule(&q->tasklet);
136 }
137 
__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue * q,size_t elem_size,int elem_index)138 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
139 					size_t elem_size, int elem_index)
140 {
141 	return q->mem_item.buf + (elem_size * elem_index);
142 }
143 
144 static struct mlxsw_pci_queue_elem_info *
mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue * q,int elem_index)145 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
146 {
147 	return &q->elem_info[elem_index];
148 }
149 
150 static struct mlxsw_pci_queue_elem_info *
mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue * q)151 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
152 {
153 	int index = q->producer_counter & (q->count - 1);
154 
155 	if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
156 		return NULL;
157 	return mlxsw_pci_queue_elem_info_get(q, index);
158 }
159 
160 static struct mlxsw_pci_queue_elem_info *
mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue * q)161 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
162 {
163 	int index = q->consumer_counter & (q->count - 1);
164 
165 	return mlxsw_pci_queue_elem_info_get(q, index);
166 }
167 
mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue * q,int elem_index)168 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
169 {
170 	return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
171 }
172 
mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue * q,bool owner_bit)173 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
174 {
175 	return owner_bit != !!(q->consumer_counter & q->count);
176 }
177 
178 static struct mlxsw_pci_queue_type_group *
mlxsw_pci_queue_type_group_get(struct mlxsw_pci * mlxsw_pci,enum mlxsw_pci_queue_type q_type)179 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
180 			       enum mlxsw_pci_queue_type q_type)
181 {
182 	return &mlxsw_pci->queues[q_type];
183 }
184 
__mlxsw_pci_queue_count(struct mlxsw_pci * mlxsw_pci,enum mlxsw_pci_queue_type q_type)185 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
186 				  enum mlxsw_pci_queue_type q_type)
187 {
188 	struct mlxsw_pci_queue_type_group *queue_group;
189 
190 	queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
191 	return queue_group->count;
192 }
193 
mlxsw_pci_sdq_count(struct mlxsw_pci * mlxsw_pci)194 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
195 {
196 	return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
197 }
198 
mlxsw_pci_cq_count(struct mlxsw_pci * mlxsw_pci)199 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
200 {
201 	return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
202 }
203 
204 static struct mlxsw_pci_queue *
__mlxsw_pci_queue_get(struct mlxsw_pci * mlxsw_pci,enum mlxsw_pci_queue_type q_type,u8 q_num)205 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
206 		      enum mlxsw_pci_queue_type q_type, u8 q_num)
207 {
208 	return &mlxsw_pci->queues[q_type].q[q_num];
209 }
210 
mlxsw_pci_sdq_get(struct mlxsw_pci * mlxsw_pci,u8 q_num)211 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
212 						 u8 q_num)
213 {
214 	return __mlxsw_pci_queue_get(mlxsw_pci,
215 				     MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
216 }
217 
mlxsw_pci_rdq_get(struct mlxsw_pci * mlxsw_pci,u8 q_num)218 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
219 						 u8 q_num)
220 {
221 	return __mlxsw_pci_queue_get(mlxsw_pci,
222 				     MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
223 }
224 
mlxsw_pci_cq_get(struct mlxsw_pci * mlxsw_pci,u8 q_num)225 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
226 						u8 q_num)
227 {
228 	return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
229 }
230 
mlxsw_pci_eq_get(struct mlxsw_pci * mlxsw_pci,u8 q_num)231 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
232 						u8 q_num)
233 {
234 	return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
235 }
236 
__mlxsw_pci_queue_doorbell_set(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q,u16 val)237 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
238 					   struct mlxsw_pci_queue *q,
239 					   u16 val)
240 {
241 	mlxsw_pci_write32(mlxsw_pci,
242 			  DOORBELL(mlxsw_pci->doorbell_offset,
243 				   mlxsw_pci_doorbell_type_offset[q->type],
244 				   q->num), val);
245 }
246 
__mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q,u16 val)247 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
248 					       struct mlxsw_pci_queue *q,
249 					       u16 val)
250 {
251 	mlxsw_pci_write32(mlxsw_pci,
252 			  DOORBELL(mlxsw_pci->doorbell_offset,
253 				   mlxsw_pci_doorbell_arm_type_offset[q->type],
254 				   q->num), val);
255 }
256 
mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)257 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
258 						   struct mlxsw_pci_queue *q)
259 {
260 	wmb(); /* ensure all writes are done before we ring a bell */
261 	__mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
262 }
263 
mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)264 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
265 						   struct mlxsw_pci_queue *q)
266 {
267 	wmb(); /* ensure all writes are done before we ring a bell */
268 	__mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
269 				       q->consumer_counter + q->count);
270 }
271 
272 static void
mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)273 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
274 					   struct mlxsw_pci_queue *q)
275 {
276 	wmb(); /* ensure all writes are done before we ring a bell */
277 	__mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
278 }
279 
__mlxsw_pci_queue_page_get(struct mlxsw_pci_queue * q,int page_index)280 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
281 					     int page_index)
282 {
283 	return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
284 }
285 
mlxsw_pci_sdq_init(struct mlxsw_pci * mlxsw_pci,char * mbox,struct mlxsw_pci_queue * q)286 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
287 			      struct mlxsw_pci_queue *q)
288 {
289 	int tclass;
290 	int lp;
291 	int i;
292 	int err;
293 
294 	q->producer_counter = 0;
295 	q->consumer_counter = 0;
296 	tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC :
297 						      MLXSW_PCI_SDQ_CTL_TC;
298 	lp = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE :
299 						  MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE;
300 
301 	/* Set CQ of same number of this SDQ. */
302 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
303 	mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp);
304 	mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass);
305 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
306 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
307 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
308 
309 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
310 	}
311 
312 	err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
313 	if (err)
314 		return err;
315 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
316 	return 0;
317 }
318 
mlxsw_pci_sdq_fini(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)319 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
320 			       struct mlxsw_pci_queue *q)
321 {
322 	mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
323 }
324 
mlxsw_pci_wqe_frag_map(struct mlxsw_pci * mlxsw_pci,char * wqe,int index,char * frag_data,size_t frag_len,int direction)325 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
326 				  int index, char *frag_data, size_t frag_len,
327 				  int direction)
328 {
329 	struct pci_dev *pdev = mlxsw_pci->pdev;
330 	dma_addr_t mapaddr;
331 
332 	mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction);
333 	if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) {
334 		dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
335 		return -EIO;
336 	}
337 	mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
338 	mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
339 	return 0;
340 }
341 
mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci * mlxsw_pci,char * wqe,int index,int direction)342 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
343 				     int index, int direction)
344 {
345 	struct pci_dev *pdev = mlxsw_pci->pdev;
346 	size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
347 	dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
348 
349 	if (!frag_len)
350 		return;
351 	dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction);
352 }
353 
mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue_elem_info * elem_info)354 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
355 				   struct mlxsw_pci_queue_elem_info *elem_info)
356 {
357 	size_t buf_len = MLXSW_PORT_MAX_MTU;
358 	char *wqe = elem_info->elem;
359 	struct sk_buff *skb;
360 	int err;
361 
362 	skb = netdev_alloc_skb_ip_align(NULL, buf_len);
363 	if (!skb)
364 		return -ENOMEM;
365 
366 	err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
367 				     buf_len, DMA_FROM_DEVICE);
368 	if (err)
369 		goto err_frag_map;
370 
371 	elem_info->u.rdq.skb = skb;
372 	return 0;
373 
374 err_frag_map:
375 	dev_kfree_skb_any(skb);
376 	return err;
377 }
378 
mlxsw_pci_rdq_skb_free(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue_elem_info * elem_info)379 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
380 				   struct mlxsw_pci_queue_elem_info *elem_info)
381 {
382 	struct sk_buff *skb;
383 	char *wqe;
384 
385 	skb = elem_info->u.rdq.skb;
386 	wqe = elem_info->elem;
387 
388 	mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
389 	dev_kfree_skb_any(skb);
390 }
391 
mlxsw_pci_rdq_init(struct mlxsw_pci * mlxsw_pci,char * mbox,struct mlxsw_pci_queue * q)392 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
393 			      struct mlxsw_pci_queue *q)
394 {
395 	struct mlxsw_pci_queue_elem_info *elem_info;
396 	u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
397 	int i;
398 	int err;
399 
400 	q->producer_counter = 0;
401 	q->consumer_counter = 0;
402 
403 	/* Set CQ of same number of this RDQ with base
404 	 * above SDQ count as the lower ones are assigned to SDQs.
405 	 */
406 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
407 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
408 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
409 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
410 
411 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
412 	}
413 
414 	err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
415 	if (err)
416 		return err;
417 
418 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
419 
420 	for (i = 0; i < q->count; i++) {
421 		elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
422 		BUG_ON(!elem_info);
423 		err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
424 		if (err)
425 			goto rollback;
426 		/* Everything is set up, ring doorbell to pass elem to HW */
427 		q->producer_counter++;
428 		mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
429 	}
430 
431 	return 0;
432 
433 rollback:
434 	for (i--; i >= 0; i--) {
435 		elem_info = mlxsw_pci_queue_elem_info_get(q, i);
436 		mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
437 	}
438 	mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
439 
440 	return err;
441 }
442 
mlxsw_pci_rdq_fini(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)443 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
444 			       struct mlxsw_pci_queue *q)
445 {
446 	struct mlxsw_pci_queue_elem_info *elem_info;
447 	int i;
448 
449 	mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
450 	for (i = 0; i < q->count; i++) {
451 		elem_info = mlxsw_pci_queue_elem_info_get(q, i);
452 		mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
453 	}
454 }
455 
mlxsw_pci_cq_pre_init(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)456 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
457 				  struct mlxsw_pci_queue *q)
458 {
459 	q->u.cq.v = mlxsw_pci->max_cqe_ver;
460 
461 	if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
462 	    q->num < mlxsw_pci->num_sdq_cqs &&
463 	    !mlxsw_core_sdq_supports_cqe_v2(mlxsw_pci->core))
464 		q->u.cq.v = MLXSW_PCI_CQE_V1;
465 }
466 
mlxsw_pci_cq_init(struct mlxsw_pci * mlxsw_pci,char * mbox,struct mlxsw_pci_queue * q)467 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
468 			     struct mlxsw_pci_queue *q)
469 {
470 	int i;
471 	int err;
472 
473 	q->consumer_counter = 0;
474 
475 	for (i = 0; i < q->count; i++) {
476 		char *elem = mlxsw_pci_queue_elem_get(q, i);
477 
478 		mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
479 	}
480 
481 	if (q->u.cq.v == MLXSW_PCI_CQE_V1)
482 		mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
483 				MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
484 	else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
485 		mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
486 				MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
487 
488 	mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
489 	mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
490 	mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
491 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
492 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
493 
494 		mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
495 	}
496 	err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
497 	if (err)
498 		return err;
499 	mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
500 	mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
501 	return 0;
502 }
503 
mlxsw_pci_cq_fini(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)504 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
505 			      struct mlxsw_pci_queue *q)
506 {
507 	mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
508 }
509 
mlxsw_pci_read32_off(struct mlxsw_pci * mlxsw_pci,ptrdiff_t off)510 static unsigned int mlxsw_pci_read32_off(struct mlxsw_pci *mlxsw_pci,
511 					 ptrdiff_t off)
512 {
513 	return ioread32be(mlxsw_pci->hw_addr + off);
514 }
515 
mlxsw_pci_skb_cb_ts_set(struct mlxsw_pci * mlxsw_pci,struct sk_buff * skb,enum mlxsw_pci_cqe_v cqe_v,char * cqe)516 static void mlxsw_pci_skb_cb_ts_set(struct mlxsw_pci *mlxsw_pci,
517 				    struct sk_buff *skb,
518 				    enum mlxsw_pci_cqe_v cqe_v, char *cqe)
519 {
520 	if (cqe_v != MLXSW_PCI_CQE_V2)
521 		return;
522 
523 	if (mlxsw_pci_cqe2_time_stamp_type_get(cqe) !=
524 	    MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC)
525 		return;
526 
527 	mlxsw_skb_cb(skb)->cqe_ts.sec = mlxsw_pci_cqe2_time_stamp_sec_get(cqe);
528 	mlxsw_skb_cb(skb)->cqe_ts.nsec =
529 		mlxsw_pci_cqe2_time_stamp_nsec_get(cqe);
530 }
531 
mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q,u16 consumer_counter_limit,enum mlxsw_pci_cqe_v cqe_v,char * cqe)532 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
533 				     struct mlxsw_pci_queue *q,
534 				     u16 consumer_counter_limit,
535 				     enum mlxsw_pci_cqe_v cqe_v,
536 				     char *cqe)
537 {
538 	struct pci_dev *pdev = mlxsw_pci->pdev;
539 	struct mlxsw_pci_queue_elem_info *elem_info;
540 	struct mlxsw_tx_info tx_info;
541 	char *wqe;
542 	struct sk_buff *skb;
543 	int i;
544 
545 	spin_lock(&q->lock);
546 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
547 	tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info;
548 	skb = elem_info->u.sdq.skb;
549 	wqe = elem_info->elem;
550 	for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
551 		mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
552 
553 	if (unlikely(!tx_info.is_emad &&
554 		     skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
555 		mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe);
556 		mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb,
557 					   tx_info.local_port);
558 		skb = NULL;
559 	}
560 
561 	if (skb)
562 		dev_kfree_skb_any(skb);
563 	elem_info->u.sdq.skb = NULL;
564 
565 	if (q->consumer_counter++ != consumer_counter_limit)
566 		dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
567 	spin_unlock(&q->lock);
568 }
569 
mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff * skb,const char * cqe)570 static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb,
571 					      const char *cqe)
572 {
573 	struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb);
574 
575 	if (mlxsw_pci_cqe2_tx_lag_get(cqe)) {
576 		cb->rx_md_info.tx_port_is_lag = true;
577 		cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe);
578 		cb->rx_md_info.tx_lag_port_index =
579 			mlxsw_pci_cqe2_tx_lag_subport_get(cqe);
580 	} else {
581 		cb->rx_md_info.tx_port_is_lag = false;
582 		cb->rx_md_info.tx_sys_port =
583 			mlxsw_pci_cqe2_tx_system_port_get(cqe);
584 	}
585 
586 	if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT &&
587 	    cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID)
588 		cb->rx_md_info.tx_port_valid = 1;
589 	else
590 		cb->rx_md_info.tx_port_valid = 0;
591 }
592 
mlxsw_pci_cqe_rdq_md_init(struct sk_buff * skb,const char * cqe)593 static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe)
594 {
595 	struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb);
596 
597 	cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe);
598 	if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID)
599 		cb->rx_md_info.tx_congestion_valid = 1;
600 	else
601 		cb->rx_md_info.tx_congestion_valid = 0;
602 	cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT;
603 
604 	cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe);
605 	if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID)
606 		cb->rx_md_info.latency_valid = 1;
607 	else
608 		cb->rx_md_info.latency_valid = 0;
609 
610 	cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe);
611 	if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID)
612 		cb->rx_md_info.tx_tc_valid = 1;
613 	else
614 		cb->rx_md_info.tx_tc_valid = 0;
615 
616 	mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe);
617 }
618 
mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q,u16 consumer_counter_limit,enum mlxsw_pci_cqe_v cqe_v,char * cqe)619 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
620 				     struct mlxsw_pci_queue *q,
621 				     u16 consumer_counter_limit,
622 				     enum mlxsw_pci_cqe_v cqe_v, char *cqe)
623 {
624 	struct pci_dev *pdev = mlxsw_pci->pdev;
625 	struct mlxsw_pci_queue_elem_info *elem_info;
626 	struct mlxsw_rx_info rx_info = {};
627 	char wqe[MLXSW_PCI_WQE_SIZE];
628 	struct sk_buff *skb;
629 	u16 byte_count;
630 	int err;
631 
632 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
633 	skb = elem_info->u.rdq.skb;
634 	memcpy(wqe, elem_info->elem, MLXSW_PCI_WQE_SIZE);
635 
636 	if (q->consumer_counter++ != consumer_counter_limit)
637 		dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
638 
639 	err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
640 	if (err) {
641 		dev_err_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
642 		goto out;
643 	}
644 
645 	mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
646 
647 	if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) {
648 		rx_info.is_lag = true;
649 		rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe);
650 		rx_info.lag_port_index =
651 			mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe);
652 	} else {
653 		rx_info.is_lag = false;
654 		rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
655 	}
656 
657 	rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
658 
659 	if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL ||
660 	    rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) {
661 		u32 cookie_index = 0;
662 
663 		if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2)
664 			cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe);
665 		mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index;
666 	} else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 &&
667 		   rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 &&
668 		   mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) {
669 		rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe);
670 		mlxsw_pci_cqe_rdq_md_init(skb, cqe);
671 	} else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE &&
672 		   mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) {
673 		mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe);
674 	}
675 
676 	mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe);
677 
678 	byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
679 	if (mlxsw_pci_cqe_crc_get(cqe_v, cqe))
680 		byte_count -= ETH_FCS_LEN;
681 	skb_put(skb, byte_count);
682 	mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
683 
684 out:
685 	/* Everything is set up, ring doorbell to pass elem to HW */
686 	q->producer_counter++;
687 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
688 	return;
689 }
690 
mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue * q)691 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
692 {
693 	struct mlxsw_pci_queue_elem_info *elem_info;
694 	char *elem;
695 	bool owner_bit;
696 
697 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
698 	elem = elem_info->elem;
699 	owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
700 	if (mlxsw_pci_elem_hw_owned(q, owner_bit))
701 		return NULL;
702 	q->consumer_counter++;
703 	rmb(); /* make sure we read owned bit before the rest of elem */
704 	return elem;
705 }
706 
mlxsw_pci_cq_tasklet(struct tasklet_struct * t)707 static void mlxsw_pci_cq_tasklet(struct tasklet_struct *t)
708 {
709 	struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet);
710 	struct mlxsw_pci *mlxsw_pci = q->pci;
711 	char *cqe;
712 	int items = 0;
713 	int credits = q->count >> 1;
714 
715 	while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
716 		u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
717 		u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
718 		u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
719 		char ncqe[MLXSW_PCI_CQE_SIZE_MAX];
720 
721 		memcpy(ncqe, cqe, q->elem_size);
722 		mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
723 
724 		if (sendq) {
725 			struct mlxsw_pci_queue *sdq;
726 
727 			sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
728 			mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
729 						 wqe_counter, q->u.cq.v, ncqe);
730 			q->u.cq.comp_sdq_count++;
731 		} else {
732 			struct mlxsw_pci_queue *rdq;
733 
734 			rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
735 			mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
736 						 wqe_counter, q->u.cq.v, ncqe);
737 			q->u.cq.comp_rdq_count++;
738 		}
739 		if (++items == credits)
740 			break;
741 	}
742 	if (items)
743 		mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
744 }
745 
mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue * q)746 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
747 {
748 	return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
749 					       MLXSW_PCI_CQE01_COUNT;
750 }
751 
mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue * q)752 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
753 {
754 	return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
755 					       MLXSW_PCI_CQE01_SIZE;
756 }
757 
mlxsw_pci_eq_init(struct mlxsw_pci * mlxsw_pci,char * mbox,struct mlxsw_pci_queue * q)758 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
759 			     struct mlxsw_pci_queue *q)
760 {
761 	int i;
762 	int err;
763 
764 	q->consumer_counter = 0;
765 
766 	for (i = 0; i < q->count; i++) {
767 		char *elem = mlxsw_pci_queue_elem_get(q, i);
768 
769 		mlxsw_pci_eqe_owner_set(elem, 1);
770 	}
771 
772 	mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
773 	mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
774 	mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
775 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
776 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
777 
778 		mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
779 	}
780 	err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
781 	if (err)
782 		return err;
783 	mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
784 	mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
785 	return 0;
786 }
787 
mlxsw_pci_eq_fini(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_queue * q)788 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
789 			      struct mlxsw_pci_queue *q)
790 {
791 	mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
792 }
793 
mlxsw_pci_eq_cmd_event(struct mlxsw_pci * mlxsw_pci,char * eqe)794 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
795 {
796 	mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
797 	mlxsw_pci->cmd.comp.out_param =
798 		((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
799 		mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
800 	mlxsw_pci->cmd.wait_done = true;
801 	wake_up(&mlxsw_pci->cmd.wait);
802 }
803 
mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue * q)804 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
805 {
806 	struct mlxsw_pci_queue_elem_info *elem_info;
807 	char *elem;
808 	bool owner_bit;
809 
810 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
811 	elem = elem_info->elem;
812 	owner_bit = mlxsw_pci_eqe_owner_get(elem);
813 	if (mlxsw_pci_elem_hw_owned(q, owner_bit))
814 		return NULL;
815 	q->consumer_counter++;
816 	rmb(); /* make sure we read owned bit before the rest of elem */
817 	return elem;
818 }
819 
mlxsw_pci_eq_tasklet(struct tasklet_struct * t)820 static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t)
821 {
822 	struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet);
823 	struct mlxsw_pci *mlxsw_pci = q->pci;
824 	u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
825 	unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
826 	char *eqe;
827 	u8 cqn;
828 	bool cq_handle = false;
829 	int items = 0;
830 	int credits = q->count >> 1;
831 
832 	memset(&active_cqns, 0, sizeof(active_cqns));
833 
834 	while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
835 
836 		/* Command interface completion events are always received on
837 		 * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events
838 		 * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1).
839 		 */
840 		switch (q->num) {
841 		case MLXSW_PCI_EQ_ASYNC_NUM:
842 			mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
843 			q->u.eq.ev_cmd_count++;
844 			break;
845 		case MLXSW_PCI_EQ_COMP_NUM:
846 			cqn = mlxsw_pci_eqe_cqn_get(eqe);
847 			set_bit(cqn, active_cqns);
848 			cq_handle = true;
849 			q->u.eq.ev_comp_count++;
850 			break;
851 		default:
852 			q->u.eq.ev_other_count++;
853 		}
854 		if (++items == credits)
855 			break;
856 	}
857 	if (items) {
858 		mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
859 		mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
860 	}
861 
862 	if (!cq_handle)
863 		return;
864 	for_each_set_bit(cqn, active_cqns, cq_count) {
865 		q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
866 		mlxsw_pci_queue_tasklet_schedule(q);
867 	}
868 }
869 
870 struct mlxsw_pci_queue_ops {
871 	const char *name;
872 	enum mlxsw_pci_queue_type type;
873 	void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
874 			 struct mlxsw_pci_queue *q);
875 	int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
876 		    struct mlxsw_pci_queue *q);
877 	void (*fini)(struct mlxsw_pci *mlxsw_pci,
878 		     struct mlxsw_pci_queue *q);
879 	void (*tasklet)(struct tasklet_struct *t);
880 	u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
881 	u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
882 	u16 elem_count;
883 	u8 elem_size;
884 };
885 
886 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
887 	.type		= MLXSW_PCI_QUEUE_TYPE_SDQ,
888 	.init		= mlxsw_pci_sdq_init,
889 	.fini		= mlxsw_pci_sdq_fini,
890 	.elem_count	= MLXSW_PCI_WQE_COUNT,
891 	.elem_size	= MLXSW_PCI_WQE_SIZE,
892 };
893 
894 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
895 	.type		= MLXSW_PCI_QUEUE_TYPE_RDQ,
896 	.init		= mlxsw_pci_rdq_init,
897 	.fini		= mlxsw_pci_rdq_fini,
898 	.elem_count	= MLXSW_PCI_WQE_COUNT,
899 	.elem_size	= MLXSW_PCI_WQE_SIZE
900 };
901 
902 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
903 	.type		= MLXSW_PCI_QUEUE_TYPE_CQ,
904 	.pre_init	= mlxsw_pci_cq_pre_init,
905 	.init		= mlxsw_pci_cq_init,
906 	.fini		= mlxsw_pci_cq_fini,
907 	.tasklet	= mlxsw_pci_cq_tasklet,
908 	.elem_count_f	= mlxsw_pci_cq_elem_count,
909 	.elem_size_f	= mlxsw_pci_cq_elem_size
910 };
911 
912 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
913 	.type		= MLXSW_PCI_QUEUE_TYPE_EQ,
914 	.init		= mlxsw_pci_eq_init,
915 	.fini		= mlxsw_pci_eq_fini,
916 	.tasklet	= mlxsw_pci_eq_tasklet,
917 	.elem_count	= MLXSW_PCI_EQE_COUNT,
918 	.elem_size	= MLXSW_PCI_EQE_SIZE
919 };
920 
mlxsw_pci_queue_init(struct mlxsw_pci * mlxsw_pci,char * mbox,const struct mlxsw_pci_queue_ops * q_ops,struct mlxsw_pci_queue * q,u8 q_num)921 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
922 				const struct mlxsw_pci_queue_ops *q_ops,
923 				struct mlxsw_pci_queue *q, u8 q_num)
924 {
925 	struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
926 	int i;
927 	int err;
928 
929 	q->num = q_num;
930 	if (q_ops->pre_init)
931 		q_ops->pre_init(mlxsw_pci, q);
932 
933 	spin_lock_init(&q->lock);
934 	q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
935 					 q_ops->elem_count;
936 	q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
937 					    q_ops->elem_size;
938 	q->type = q_ops->type;
939 	q->pci = mlxsw_pci;
940 
941 	if (q_ops->tasklet)
942 		tasklet_setup(&q->tasklet, q_ops->tasklet);
943 
944 	mem_item->size = MLXSW_PCI_AQ_SIZE;
945 	mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev,
946 					   mem_item->size, &mem_item->mapaddr,
947 					   GFP_KERNEL);
948 	if (!mem_item->buf)
949 		return -ENOMEM;
950 
951 	q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
952 	if (!q->elem_info) {
953 		err = -ENOMEM;
954 		goto err_elem_info_alloc;
955 	}
956 
957 	/* Initialize dma mapped elements info elem_info for
958 	 * future easy access.
959 	 */
960 	for (i = 0; i < q->count; i++) {
961 		struct mlxsw_pci_queue_elem_info *elem_info;
962 
963 		elem_info = mlxsw_pci_queue_elem_info_get(q, i);
964 		elem_info->elem =
965 			__mlxsw_pci_queue_elem_get(q, q->elem_size, i);
966 	}
967 
968 	mlxsw_cmd_mbox_zero(mbox);
969 	err = q_ops->init(mlxsw_pci, mbox, q);
970 	if (err)
971 		goto err_q_ops_init;
972 	return 0;
973 
974 err_q_ops_init:
975 	kfree(q->elem_info);
976 err_elem_info_alloc:
977 	dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
978 			  mem_item->buf, mem_item->mapaddr);
979 	return err;
980 }
981 
mlxsw_pci_queue_fini(struct mlxsw_pci * mlxsw_pci,const struct mlxsw_pci_queue_ops * q_ops,struct mlxsw_pci_queue * q)982 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
983 				 const struct mlxsw_pci_queue_ops *q_ops,
984 				 struct mlxsw_pci_queue *q)
985 {
986 	struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
987 
988 	q_ops->fini(mlxsw_pci, q);
989 	kfree(q->elem_info);
990 	dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
991 			  mem_item->buf, mem_item->mapaddr);
992 }
993 
mlxsw_pci_queue_group_init(struct mlxsw_pci * mlxsw_pci,char * mbox,const struct mlxsw_pci_queue_ops * q_ops,u8 num_qs)994 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
995 				      const struct mlxsw_pci_queue_ops *q_ops,
996 				      u8 num_qs)
997 {
998 	struct mlxsw_pci_queue_type_group *queue_group;
999 	int i;
1000 	int err;
1001 
1002 	queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1003 	queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
1004 	if (!queue_group->q)
1005 		return -ENOMEM;
1006 
1007 	for (i = 0; i < num_qs; i++) {
1008 		err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
1009 					   &queue_group->q[i], i);
1010 		if (err)
1011 			goto err_queue_init;
1012 	}
1013 	queue_group->count = num_qs;
1014 
1015 	return 0;
1016 
1017 err_queue_init:
1018 	for (i--; i >= 0; i--)
1019 		mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1020 	kfree(queue_group->q);
1021 	return err;
1022 }
1023 
mlxsw_pci_queue_group_fini(struct mlxsw_pci * mlxsw_pci,const struct mlxsw_pci_queue_ops * q_ops)1024 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
1025 				       const struct mlxsw_pci_queue_ops *q_ops)
1026 {
1027 	struct mlxsw_pci_queue_type_group *queue_group;
1028 	int i;
1029 
1030 	queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1031 	for (i = 0; i < queue_group->count; i++)
1032 		mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1033 	kfree(queue_group->q);
1034 }
1035 
mlxsw_pci_aqs_init(struct mlxsw_pci * mlxsw_pci,char * mbox)1036 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1037 {
1038 	struct pci_dev *pdev = mlxsw_pci->pdev;
1039 	u8 num_sdqs;
1040 	u8 sdq_log2sz;
1041 	u8 num_rdqs;
1042 	u8 rdq_log2sz;
1043 	u8 num_cqs;
1044 	u8 cq_log2sz;
1045 	u8 cqv2_log2sz;
1046 	u8 num_eqs;
1047 	u8 eq_log2sz;
1048 	int err;
1049 
1050 	mlxsw_cmd_mbox_zero(mbox);
1051 	err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1052 	if (err)
1053 		return err;
1054 
1055 	num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1056 	sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1057 	num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1058 	rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1059 	num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1060 	cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1061 	cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
1062 	num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1063 	eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1064 
1065 	if (num_sdqs + num_rdqs > num_cqs ||
1066 	    num_sdqs < MLXSW_PCI_SDQS_MIN ||
1067 	    num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
1068 		dev_err(&pdev->dev, "Unsupported number of queues\n");
1069 		return -EINVAL;
1070 	}
1071 
1072 	if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1073 	    (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1074 	    (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
1075 	    (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
1076 	     (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
1077 	    (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1078 		dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1079 		return -EINVAL;
1080 	}
1081 
1082 	mlxsw_pci->num_sdq_cqs = num_sdqs;
1083 
1084 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1085 					 num_eqs);
1086 	if (err) {
1087 		dev_err(&pdev->dev, "Failed to initialize event queues\n");
1088 		return err;
1089 	}
1090 
1091 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1092 					 num_cqs);
1093 	if (err) {
1094 		dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1095 		goto err_cqs_init;
1096 	}
1097 
1098 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1099 					 num_sdqs);
1100 	if (err) {
1101 		dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1102 		goto err_sdqs_init;
1103 	}
1104 
1105 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1106 					 num_rdqs);
1107 	if (err) {
1108 		dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1109 		goto err_rdqs_init;
1110 	}
1111 
1112 	/* We have to poll in command interface until queues are initialized */
1113 	mlxsw_pci->cmd.nopoll = true;
1114 	return 0;
1115 
1116 err_rdqs_init:
1117 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1118 err_sdqs_init:
1119 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1120 err_cqs_init:
1121 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1122 	return err;
1123 }
1124 
mlxsw_pci_aqs_fini(struct mlxsw_pci * mlxsw_pci)1125 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1126 {
1127 	mlxsw_pci->cmd.nopoll = false;
1128 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1129 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1130 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1131 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1132 }
1133 
1134 static void
mlxsw_pci_config_profile_swid_config(struct mlxsw_pci * mlxsw_pci,char * mbox,int index,const struct mlxsw_swid_config * swid)1135 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1136 				     char *mbox, int index,
1137 				     const struct mlxsw_swid_config *swid)
1138 {
1139 	u8 mask = 0;
1140 
1141 	if (swid->used_type) {
1142 		mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1143 			mbox, index, swid->type);
1144 		mask |= 1;
1145 	}
1146 	if (swid->used_properties) {
1147 		mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1148 			mbox, index, swid->properties);
1149 		mask |= 2;
1150 	}
1151 	mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1152 }
1153 
1154 static int
mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci * mlxsw_pci,const struct mlxsw_config_profile * profile,struct mlxsw_res * res)1155 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1156 				const struct mlxsw_config_profile *profile,
1157 				struct mlxsw_res *res)
1158 {
1159 	u64 single_size, double_size, linear_size;
1160 	int err;
1161 
1162 	err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1163 				       &single_size, &double_size,
1164 				       &linear_size);
1165 	if (err)
1166 		return err;
1167 
1168 	MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1169 	MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1170 	MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1171 
1172 	return 0;
1173 }
1174 
mlxsw_pci_config_profile(struct mlxsw_pci * mlxsw_pci,char * mbox,const struct mlxsw_config_profile * profile,struct mlxsw_res * res)1175 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1176 				    const struct mlxsw_config_profile *profile,
1177 				    struct mlxsw_res *res)
1178 {
1179 	int i;
1180 	int err;
1181 
1182 	mlxsw_cmd_mbox_zero(mbox);
1183 
1184 	if (profile->used_max_vepa_channels) {
1185 		mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1186 			mbox, 1);
1187 		mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1188 			mbox, profile->max_vepa_channels);
1189 	}
1190 	if (profile->used_max_lag) {
1191 		mlxsw_cmd_mbox_config_profile_set_max_lag_set(mbox, 1);
1192 		mlxsw_cmd_mbox_config_profile_max_lag_set(mbox,
1193 							  profile->max_lag);
1194 	}
1195 	if (profile->used_max_mid) {
1196 		mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1197 			mbox, 1);
1198 		mlxsw_cmd_mbox_config_profile_max_mid_set(
1199 			mbox, profile->max_mid);
1200 	}
1201 	if (profile->used_max_pgt) {
1202 		mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1203 			mbox, 1);
1204 		mlxsw_cmd_mbox_config_profile_max_pgt_set(
1205 			mbox, profile->max_pgt);
1206 	}
1207 	if (profile->used_max_system_port) {
1208 		mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1209 			mbox, 1);
1210 		mlxsw_cmd_mbox_config_profile_max_system_port_set(
1211 			mbox, profile->max_system_port);
1212 	}
1213 	if (profile->used_max_vlan_groups) {
1214 		mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1215 			mbox, 1);
1216 		mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1217 			mbox, profile->max_vlan_groups);
1218 	}
1219 	if (profile->used_max_regions) {
1220 		mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1221 			mbox, 1);
1222 		mlxsw_cmd_mbox_config_profile_max_regions_set(
1223 			mbox, profile->max_regions);
1224 	}
1225 	if (profile->used_flood_tables) {
1226 		mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1227 			mbox, 1);
1228 		mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1229 			mbox, profile->max_flood_tables);
1230 		mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1231 			mbox, profile->max_vid_flood_tables);
1232 		mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1233 			mbox, profile->max_fid_offset_flood_tables);
1234 		mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1235 			mbox, profile->fid_offset_flood_table_size);
1236 		mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1237 			mbox, profile->max_fid_flood_tables);
1238 		mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1239 			mbox, profile->fid_flood_table_size);
1240 	}
1241 	if (profile->used_flood_mode) {
1242 		mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1243 			mbox, 1);
1244 		mlxsw_cmd_mbox_config_profile_flood_mode_set(
1245 			mbox, profile->flood_mode);
1246 	}
1247 	if (profile->used_max_ib_mc) {
1248 		mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1249 			mbox, 1);
1250 		mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1251 			mbox, profile->max_ib_mc);
1252 	}
1253 	if (profile->used_max_pkey) {
1254 		mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1255 			mbox, 1);
1256 		mlxsw_cmd_mbox_config_profile_max_pkey_set(
1257 			mbox, profile->max_pkey);
1258 	}
1259 	if (profile->used_ar_sec) {
1260 		mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1261 			mbox, 1);
1262 		mlxsw_cmd_mbox_config_profile_ar_sec_set(
1263 			mbox, profile->ar_sec);
1264 	}
1265 	if (profile->used_adaptive_routing_group_cap) {
1266 		mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1267 			mbox, 1);
1268 		mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1269 			mbox, profile->adaptive_routing_group_cap);
1270 	}
1271 	if (profile->used_ubridge) {
1272 		mlxsw_cmd_mbox_config_profile_set_ubridge_set(mbox, 1);
1273 		mlxsw_cmd_mbox_config_profile_ubridge_set(mbox,
1274 							  profile->ubridge);
1275 	}
1276 	if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {
1277 		err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1278 		if (err)
1279 			return err;
1280 
1281 		mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1282 		mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1283 					MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1284 		mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1285 									   1);
1286 		mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1287 					MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1288 		mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1289 								mbox, 1);
1290 		mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1291 					MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1292 	}
1293 
1294 	for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1295 		mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1296 						     &profile->swid_config[i]);
1297 
1298 	if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1299 		mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1300 		mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1301 	}
1302 
1303 	if (profile->used_cqe_time_stamp_type) {
1304 		mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox,
1305 									  1);
1306 		mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox,
1307 					profile->cqe_time_stamp_type);
1308 	}
1309 
1310 	return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1311 }
1312 
mlxsw_pci_boardinfo(struct mlxsw_pci * mlxsw_pci,char * mbox)1313 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1314 {
1315 	struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1316 	int err;
1317 
1318 	mlxsw_cmd_mbox_zero(mbox);
1319 	err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1320 	if (err)
1321 		return err;
1322 	mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1323 	mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1324 	return 0;
1325 }
1326 
mlxsw_pci_fw_area_init(struct mlxsw_pci * mlxsw_pci,char * mbox,u16 num_pages)1327 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1328 				  u16 num_pages)
1329 {
1330 	struct mlxsw_pci_mem_item *mem_item;
1331 	int nent = 0;
1332 	int i;
1333 	int err;
1334 
1335 	mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1336 					   GFP_KERNEL);
1337 	if (!mlxsw_pci->fw_area.items)
1338 		return -ENOMEM;
1339 	mlxsw_pci->fw_area.count = num_pages;
1340 
1341 	mlxsw_cmd_mbox_zero(mbox);
1342 	for (i = 0; i < num_pages; i++) {
1343 		mem_item = &mlxsw_pci->fw_area.items[i];
1344 
1345 		mem_item->size = MLXSW_PCI_PAGE_SIZE;
1346 		mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev,
1347 						   mem_item->size,
1348 						   &mem_item->mapaddr, GFP_KERNEL);
1349 		if (!mem_item->buf) {
1350 			err = -ENOMEM;
1351 			goto err_alloc;
1352 		}
1353 		mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1354 		mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1355 		if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1356 			err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1357 			if (err)
1358 				goto err_cmd_map_fa;
1359 			nent = 0;
1360 			mlxsw_cmd_mbox_zero(mbox);
1361 		}
1362 	}
1363 
1364 	if (nent) {
1365 		err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1366 		if (err)
1367 			goto err_cmd_map_fa;
1368 	}
1369 
1370 	return 0;
1371 
1372 err_cmd_map_fa:
1373 err_alloc:
1374 	for (i--; i >= 0; i--) {
1375 		mem_item = &mlxsw_pci->fw_area.items[i];
1376 
1377 		dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
1378 				  mem_item->buf, mem_item->mapaddr);
1379 	}
1380 	kfree(mlxsw_pci->fw_area.items);
1381 	return err;
1382 }
1383 
mlxsw_pci_fw_area_fini(struct mlxsw_pci * mlxsw_pci)1384 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1385 {
1386 	struct mlxsw_pci_mem_item *mem_item;
1387 	int i;
1388 
1389 	mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1390 
1391 	for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1392 		mem_item = &mlxsw_pci->fw_area.items[i];
1393 
1394 		dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size,
1395 				  mem_item->buf, mem_item->mapaddr);
1396 	}
1397 	kfree(mlxsw_pci->fw_area.items);
1398 }
1399 
mlxsw_pci_eq_irq_handler(int irq,void * dev_id)1400 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1401 {
1402 	struct mlxsw_pci *mlxsw_pci = dev_id;
1403 	struct mlxsw_pci_queue *q;
1404 	int i;
1405 
1406 	for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1407 		q = mlxsw_pci_eq_get(mlxsw_pci, i);
1408 		mlxsw_pci_queue_tasklet_schedule(q);
1409 	}
1410 	return IRQ_HANDLED;
1411 }
1412 
mlxsw_pci_mbox_alloc(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_mem_item * mbox)1413 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1414 				struct mlxsw_pci_mem_item *mbox)
1415 {
1416 	struct pci_dev *pdev = mlxsw_pci->pdev;
1417 	int err = 0;
1418 
1419 	mbox->size = MLXSW_CMD_MBOX_SIZE;
1420 	mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE,
1421 				       &mbox->mapaddr, GFP_KERNEL);
1422 	if (!mbox->buf) {
1423 		dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1424 		err = -ENOMEM;
1425 	}
1426 
1427 	return err;
1428 }
1429 
mlxsw_pci_mbox_free(struct mlxsw_pci * mlxsw_pci,struct mlxsw_pci_mem_item * mbox)1430 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1431 				struct mlxsw_pci_mem_item *mbox)
1432 {
1433 	struct pci_dev *pdev = mlxsw_pci->pdev;
1434 
1435 	dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1436 			  mbox->mapaddr);
1437 }
1438 
mlxsw_pci_sys_ready_wait(struct mlxsw_pci * mlxsw_pci,const struct pci_device_id * id,u32 * p_sys_status)1439 static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci,
1440 				    const struct pci_device_id *id,
1441 				    u32 *p_sys_status)
1442 {
1443 	unsigned long end;
1444 	u32 val;
1445 
1446 	/* We must wait for the HW to become responsive. */
1447 	msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1448 
1449 	end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1450 	do {
1451 		val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1452 		if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1453 			return 0;
1454 		cond_resched();
1455 	} while (time_before(jiffies, end));
1456 
1457 	*p_sys_status = val & MLXSW_PCI_FW_READY_MASK;
1458 
1459 	return -EBUSY;
1460 }
1461 
mlxsw_pci_sw_reset(struct mlxsw_pci * mlxsw_pci,const struct pci_device_id * id)1462 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1463 			      const struct pci_device_id *id)
1464 {
1465 	struct pci_dev *pdev = mlxsw_pci->pdev;
1466 	char mrsr_pl[MLXSW_REG_MRSR_LEN];
1467 	u32 sys_status;
1468 	int err;
1469 
1470 	err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1471 	if (err) {
1472 		dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n",
1473 			sys_status);
1474 		return err;
1475 	}
1476 
1477 	mlxsw_reg_mrsr_pack(mrsr_pl);
1478 	err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl);
1479 	if (err)
1480 		return err;
1481 
1482 	err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1483 	if (err) {
1484 		dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n",
1485 			sys_status);
1486 		return err;
1487 	}
1488 
1489 	return 0;
1490 }
1491 
mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci * mlxsw_pci)1492 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1493 {
1494 	int err;
1495 
1496 	err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1497 	if (err < 0)
1498 		dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1499 	return err;
1500 }
1501 
mlxsw_pci_free_irq_vectors(struct mlxsw_pci * mlxsw_pci)1502 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1503 {
1504 	pci_free_irq_vectors(mlxsw_pci->pdev);
1505 }
1506 
mlxsw_pci_init(void * bus_priv,struct mlxsw_core * mlxsw_core,const struct mlxsw_config_profile * profile,struct mlxsw_res * res)1507 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1508 			  const struct mlxsw_config_profile *profile,
1509 			  struct mlxsw_res *res)
1510 {
1511 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1512 	struct pci_dev *pdev = mlxsw_pci->pdev;
1513 	char *mbox;
1514 	u16 num_pages;
1515 	int err;
1516 
1517 	mlxsw_pci->core = mlxsw_core;
1518 
1519 	mbox = mlxsw_cmd_mbox_alloc();
1520 	if (!mbox)
1521 		return -ENOMEM;
1522 
1523 	err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1524 	if (err)
1525 		goto err_sw_reset;
1526 
1527 	err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1528 	if (err < 0) {
1529 		dev_err(&pdev->dev, "MSI-X init failed\n");
1530 		goto err_alloc_irq;
1531 	}
1532 
1533 	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1534 	if (err)
1535 		goto err_query_fw;
1536 
1537 	mlxsw_pci->bus_info.fw_rev.major =
1538 		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1539 	mlxsw_pci->bus_info.fw_rev.minor =
1540 		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1541 	mlxsw_pci->bus_info.fw_rev.subminor =
1542 		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1543 
1544 	if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1545 		dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1546 		err = -EINVAL;
1547 		goto err_iface_rev;
1548 	}
1549 	if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1550 		dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1551 		err = -EINVAL;
1552 		goto err_doorbell_page_bar;
1553 	}
1554 
1555 	mlxsw_pci->doorbell_offset =
1556 		mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1557 
1558 	if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {
1559 		dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n");
1560 		err = -EINVAL;
1561 		goto err_fr_rn_clk_bar;
1562 	}
1563 
1564 	mlxsw_pci->free_running_clock_offset =
1565 		mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
1566 
1567 	if (mlxsw_cmd_mbox_query_fw_utc_sec_bar_get(mbox) != 0) {
1568 		dev_err(&pdev->dev, "Unsupported UTC sec BAR queried from hw\n");
1569 		err = -EINVAL;
1570 		goto err_utc_sec_bar;
1571 	}
1572 
1573 	mlxsw_pci->utc_sec_offset =
1574 		mlxsw_cmd_mbox_query_fw_utc_sec_offset_get(mbox);
1575 
1576 	if (mlxsw_cmd_mbox_query_fw_utc_nsec_bar_get(mbox) != 0) {
1577 		dev_err(&pdev->dev, "Unsupported UTC nsec BAR queried from hw\n");
1578 		err = -EINVAL;
1579 		goto err_utc_nsec_bar;
1580 	}
1581 
1582 	mlxsw_pci->utc_nsec_offset =
1583 		mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox);
1584 
1585 	num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1586 	err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1587 	if (err)
1588 		goto err_fw_area_init;
1589 
1590 	err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1591 	if (err)
1592 		goto err_boardinfo;
1593 
1594 	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1595 	if (err)
1596 		goto err_query_resources;
1597 
1598 	if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1599 	    MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1600 		mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1601 	else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1602 		 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1603 		mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1604 	else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1605 		  MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1606 		 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1607 		mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1608 	} else {
1609 		dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1610 		goto err_cqe_v_check;
1611 	}
1612 
1613 	err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1614 	if (err)
1615 		goto err_config_profile;
1616 
1617 	/* Some resources depend on unified bridge model, which is configured
1618 	 * as part of config_profile. Query the resources again to get correct
1619 	 * values.
1620 	 */
1621 	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1622 	if (err)
1623 		goto err_requery_resources;
1624 
1625 	err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1626 	if (err)
1627 		goto err_aqs_init;
1628 
1629 	err = request_irq(pci_irq_vector(pdev, 0),
1630 			  mlxsw_pci_eq_irq_handler, 0,
1631 			  mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1632 	if (err) {
1633 		dev_err(&pdev->dev, "IRQ request failed\n");
1634 		goto err_request_eq_irq;
1635 	}
1636 
1637 	goto mbox_put;
1638 
1639 err_request_eq_irq:
1640 	mlxsw_pci_aqs_fini(mlxsw_pci);
1641 err_aqs_init:
1642 err_requery_resources:
1643 err_config_profile:
1644 err_cqe_v_check:
1645 err_query_resources:
1646 err_boardinfo:
1647 	mlxsw_pci_fw_area_fini(mlxsw_pci);
1648 err_fw_area_init:
1649 err_utc_nsec_bar:
1650 err_utc_sec_bar:
1651 err_fr_rn_clk_bar:
1652 err_doorbell_page_bar:
1653 err_iface_rev:
1654 err_query_fw:
1655 	mlxsw_pci_free_irq_vectors(mlxsw_pci);
1656 err_alloc_irq:
1657 err_sw_reset:
1658 mbox_put:
1659 	mlxsw_cmd_mbox_free(mbox);
1660 	return err;
1661 }
1662 
mlxsw_pci_fini(void * bus_priv)1663 static void mlxsw_pci_fini(void *bus_priv)
1664 {
1665 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1666 
1667 	free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1668 	mlxsw_pci_aqs_fini(mlxsw_pci);
1669 	mlxsw_pci_fw_area_fini(mlxsw_pci);
1670 	mlxsw_pci_free_irq_vectors(mlxsw_pci);
1671 }
1672 
1673 static struct mlxsw_pci_queue *
mlxsw_pci_sdq_pick(struct mlxsw_pci * mlxsw_pci,const struct mlxsw_tx_info * tx_info)1674 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1675 		   const struct mlxsw_tx_info *tx_info)
1676 {
1677 	u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1;
1678 	u8 sdqn;
1679 
1680 	if (tx_info->is_emad) {
1681 		sdqn = MLXSW_PCI_SDQ_EMAD_INDEX;
1682 	} else {
1683 		BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0);
1684 		sdqn = 1 + (tx_info->local_port % ctl_sdq_count);
1685 	}
1686 
1687 	return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1688 }
1689 
mlxsw_pci_skb_transmit_busy(void * bus_priv,const struct mlxsw_tx_info * tx_info)1690 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1691 					const struct mlxsw_tx_info *tx_info)
1692 {
1693 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1694 	struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1695 
1696 	return !mlxsw_pci_queue_elem_info_producer_get(q);
1697 }
1698 
mlxsw_pci_skb_transmit(void * bus_priv,struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)1699 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1700 				  const struct mlxsw_tx_info *tx_info)
1701 {
1702 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1703 	struct mlxsw_pci_queue *q;
1704 	struct mlxsw_pci_queue_elem_info *elem_info;
1705 	char *wqe;
1706 	int i;
1707 	int err;
1708 
1709 	if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1710 		err = skb_linearize(skb);
1711 		if (err)
1712 			return err;
1713 	}
1714 
1715 	q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1716 	spin_lock_bh(&q->lock);
1717 	elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1718 	if (!elem_info) {
1719 		/* queue is full */
1720 		err = -EAGAIN;
1721 		goto unlock;
1722 	}
1723 	mlxsw_skb_cb(skb)->tx_info = *tx_info;
1724 	elem_info->u.sdq.skb = skb;
1725 
1726 	wqe = elem_info->elem;
1727 	mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1728 	mlxsw_pci_wqe_lp_set(wqe, 0);
1729 	mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1730 
1731 	err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1732 				     skb_headlen(skb), DMA_TO_DEVICE);
1733 	if (err)
1734 		goto unlock;
1735 
1736 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1737 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1738 
1739 		err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1740 					     skb_frag_address(frag),
1741 					     skb_frag_size(frag),
1742 					     DMA_TO_DEVICE);
1743 		if (err)
1744 			goto unmap_frags;
1745 	}
1746 
1747 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
1748 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1749 
1750 	/* Set unused sq entries byte count to zero. */
1751 	for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1752 		mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1753 
1754 	/* Everything is set up, ring producer doorbell to get HW going */
1755 	q->producer_counter++;
1756 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1757 
1758 	goto unlock;
1759 
1760 unmap_frags:
1761 	for (; i >= 0; i--)
1762 		mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1763 unlock:
1764 	spin_unlock_bh(&q->lock);
1765 	return err;
1766 }
1767 
mlxsw_pci_cmd_exec(void * bus_priv,u16 opcode,u8 opcode_mod,u32 in_mod,bool out_mbox_direct,char * in_mbox,size_t in_mbox_size,char * out_mbox,size_t out_mbox_size,u8 * p_status)1768 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1769 			      u32 in_mod, bool out_mbox_direct,
1770 			      char *in_mbox, size_t in_mbox_size,
1771 			      char *out_mbox, size_t out_mbox_size,
1772 			      u8 *p_status)
1773 {
1774 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1775 	dma_addr_t in_mapaddr = 0, out_mapaddr = 0;
1776 	bool evreq = mlxsw_pci->cmd.nopoll;
1777 	unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1778 	bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1779 	int err;
1780 
1781 	*p_status = MLXSW_CMD_STATUS_OK;
1782 
1783 	err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1784 	if (err)
1785 		return err;
1786 
1787 	if (in_mbox) {
1788 		memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1789 		in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1790 	}
1791 	mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1792 	mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1793 
1794 	if (out_mbox)
1795 		out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1796 	mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1797 	mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1798 
1799 	mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1800 	mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1801 
1802 	*p_wait_done = false;
1803 
1804 	wmb(); /* all needs to be written before we write control register */
1805 	mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1806 			  MLXSW_PCI_CIR_CTRL_GO_BIT |
1807 			  (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1808 			  (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1809 			  opcode);
1810 
1811 	if (!evreq) {
1812 		unsigned long end;
1813 
1814 		end = jiffies + timeout;
1815 		do {
1816 			u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1817 
1818 			if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1819 				*p_wait_done = true;
1820 				*p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1821 				break;
1822 			}
1823 			cond_resched();
1824 		} while (time_before(jiffies, end));
1825 	} else {
1826 		wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1827 		*p_status = mlxsw_pci->cmd.comp.status;
1828 	}
1829 
1830 	err = 0;
1831 	if (*p_wait_done) {
1832 		if (*p_status)
1833 			err = -EIO;
1834 	} else {
1835 		err = -ETIMEDOUT;
1836 	}
1837 
1838 	if (!err && out_mbox && out_mbox_direct) {
1839 		/* Some commands don't use output param as address to mailbox
1840 		 * but they store output directly into registers. In that case,
1841 		 * copy registers into mbox buffer.
1842 		 */
1843 		__be32 tmp;
1844 
1845 		if (!evreq) {
1846 			tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1847 							   CIR_OUT_PARAM_HI));
1848 			memcpy(out_mbox, &tmp, sizeof(tmp));
1849 			tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1850 							   CIR_OUT_PARAM_LO));
1851 			memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1852 		}
1853 	} else if (!err && out_mbox) {
1854 		memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1855 	}
1856 
1857 	mutex_unlock(&mlxsw_pci->cmd.lock);
1858 
1859 	return err;
1860 }
1861 
mlxsw_pci_read_frc_h(void * bus_priv)1862 static u32 mlxsw_pci_read_frc_h(void *bus_priv)
1863 {
1864 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1865 	u64 frc_offset_h;
1866 
1867 	frc_offset_h = mlxsw_pci->free_running_clock_offset;
1868 	return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_h);
1869 }
1870 
mlxsw_pci_read_frc_l(void * bus_priv)1871 static u32 mlxsw_pci_read_frc_l(void *bus_priv)
1872 {
1873 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1874 	u64 frc_offset_l;
1875 
1876 	frc_offset_l = mlxsw_pci->free_running_clock_offset + 4;
1877 	return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_l);
1878 }
1879 
mlxsw_pci_read_utc_sec(void * bus_priv)1880 static u32 mlxsw_pci_read_utc_sec(void *bus_priv)
1881 {
1882 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1883 
1884 	return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_sec_offset);
1885 }
1886 
mlxsw_pci_read_utc_nsec(void * bus_priv)1887 static u32 mlxsw_pci_read_utc_nsec(void *bus_priv)
1888 {
1889 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1890 
1891 	return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_nsec_offset);
1892 }
1893 
1894 static const struct mlxsw_bus mlxsw_pci_bus = {
1895 	.kind			= "pci",
1896 	.init			= mlxsw_pci_init,
1897 	.fini			= mlxsw_pci_fini,
1898 	.skb_transmit_busy	= mlxsw_pci_skb_transmit_busy,
1899 	.skb_transmit		= mlxsw_pci_skb_transmit,
1900 	.cmd_exec		= mlxsw_pci_cmd_exec,
1901 	.read_frc_h		= mlxsw_pci_read_frc_h,
1902 	.read_frc_l		= mlxsw_pci_read_frc_l,
1903 	.read_utc_sec		= mlxsw_pci_read_utc_sec,
1904 	.read_utc_nsec		= mlxsw_pci_read_utc_nsec,
1905 	.features		= MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
1906 };
1907 
mlxsw_pci_cmd_init(struct mlxsw_pci * mlxsw_pci)1908 static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci)
1909 {
1910 	int err;
1911 
1912 	mutex_init(&mlxsw_pci->cmd.lock);
1913 	init_waitqueue_head(&mlxsw_pci->cmd.wait);
1914 
1915 	err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1916 	if (err)
1917 		goto err_in_mbox_alloc;
1918 
1919 	err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1920 	if (err)
1921 		goto err_out_mbox_alloc;
1922 
1923 	return 0;
1924 
1925 err_out_mbox_alloc:
1926 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1927 err_in_mbox_alloc:
1928 	mutex_destroy(&mlxsw_pci->cmd.lock);
1929 	return err;
1930 }
1931 
mlxsw_pci_cmd_fini(struct mlxsw_pci * mlxsw_pci)1932 static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci)
1933 {
1934 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1935 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1936 	mutex_destroy(&mlxsw_pci->cmd.lock);
1937 }
1938 
mlxsw_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1939 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1940 {
1941 	const char *driver_name = dev_driver_string(&pdev->dev);
1942 	struct mlxsw_pci *mlxsw_pci;
1943 	int err;
1944 
1945 	mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1946 	if (!mlxsw_pci)
1947 		return -ENOMEM;
1948 
1949 	err = pci_enable_device(pdev);
1950 	if (err) {
1951 		dev_err(&pdev->dev, "pci_enable_device failed\n");
1952 		goto err_pci_enable_device;
1953 	}
1954 
1955 	err = pci_request_regions(pdev, driver_name);
1956 	if (err) {
1957 		dev_err(&pdev->dev, "pci_request_regions failed\n");
1958 		goto err_pci_request_regions;
1959 	}
1960 
1961 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1962 	if (err) {
1963 		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1964 		if (err) {
1965 			dev_err(&pdev->dev, "dma_set_mask failed\n");
1966 			goto err_pci_set_dma_mask;
1967 		}
1968 	}
1969 
1970 	if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1971 		dev_err(&pdev->dev, "invalid PCI region size\n");
1972 		err = -EINVAL;
1973 		goto err_pci_resource_len_check;
1974 	}
1975 
1976 	mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1977 				     pci_resource_len(pdev, 0));
1978 	if (!mlxsw_pci->hw_addr) {
1979 		dev_err(&pdev->dev, "ioremap failed\n");
1980 		err = -EIO;
1981 		goto err_ioremap;
1982 	}
1983 	pci_set_master(pdev);
1984 
1985 	mlxsw_pci->pdev = pdev;
1986 	pci_set_drvdata(pdev, mlxsw_pci);
1987 
1988 	err = mlxsw_pci_cmd_init(mlxsw_pci);
1989 	if (err)
1990 		goto err_pci_cmd_init;
1991 
1992 	mlxsw_pci->bus_info.device_kind = driver_name;
1993 	mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1994 	mlxsw_pci->bus_info.dev = &pdev->dev;
1995 	mlxsw_pci->bus_info.read_clock_capable = true;
1996 	mlxsw_pci->id = id;
1997 
1998 	err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1999 					     &mlxsw_pci_bus, mlxsw_pci, false,
2000 					     NULL, NULL);
2001 	if (err) {
2002 		dev_err(&pdev->dev, "cannot register bus device\n");
2003 		goto err_bus_device_register;
2004 	}
2005 
2006 	return 0;
2007 
2008 err_bus_device_register:
2009 	mlxsw_pci_cmd_fini(mlxsw_pci);
2010 err_pci_cmd_init:
2011 	iounmap(mlxsw_pci->hw_addr);
2012 err_ioremap:
2013 err_pci_resource_len_check:
2014 err_pci_set_dma_mask:
2015 	pci_release_regions(pdev);
2016 err_pci_request_regions:
2017 	pci_disable_device(pdev);
2018 err_pci_enable_device:
2019 	kfree(mlxsw_pci);
2020 	return err;
2021 }
2022 
mlxsw_pci_remove(struct pci_dev * pdev)2023 static void mlxsw_pci_remove(struct pci_dev *pdev)
2024 {
2025 	struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
2026 
2027 	mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
2028 	mlxsw_pci_cmd_fini(mlxsw_pci);
2029 	iounmap(mlxsw_pci->hw_addr);
2030 	pci_release_regions(mlxsw_pci->pdev);
2031 	pci_disable_device(mlxsw_pci->pdev);
2032 	kfree(mlxsw_pci);
2033 }
2034 
mlxsw_pci_driver_register(struct pci_driver * pci_driver)2035 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
2036 {
2037 	pci_driver->probe = mlxsw_pci_probe;
2038 	pci_driver->remove = mlxsw_pci_remove;
2039 	pci_driver->shutdown = mlxsw_pci_remove;
2040 	return pci_register_driver(pci_driver);
2041 }
2042 EXPORT_SYMBOL(mlxsw_pci_driver_register);
2043 
mlxsw_pci_driver_unregister(struct pci_driver * pci_driver)2044 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
2045 {
2046 	pci_unregister_driver(pci_driver);
2047 }
2048 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
2049 
mlxsw_pci_module_init(void)2050 static int __init mlxsw_pci_module_init(void)
2051 {
2052 	return 0;
2053 }
2054 
mlxsw_pci_module_exit(void)2055 static void __exit mlxsw_pci_module_exit(void)
2056 {
2057 }
2058 
2059 module_init(mlxsw_pci_module_init);
2060 module_exit(mlxsw_pci_module_exit);
2061 
2062 MODULE_LICENSE("Dual BSD/GPL");
2063 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
2064 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
2065