1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23 /*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42 /*#define DBGTBUF(info) dump_tbufs(info)*/
43 /*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46 #include <linux/module.h>
47 #include <linux/errno.h>
48 #include <linux/signal.h>
49 #include <linux/sched.h>
50 #include <linux/timer.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55 #include <linux/serial.h>
56 #include <linux/major.h>
57 #include <linux/string.h>
58 #include <linux/fcntl.h>
59 #include <linux/ptrace.h>
60 #include <linux/ioport.h>
61 #include <linux/mm.h>
62 #include <linux/seq_file.h>
63 #include <linux/slab.h>
64 #include <linux/netdevice.h>
65 #include <linux/vmalloc.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/ioctl.h>
69 #include <linux/termios.h>
70 #include <linux/bitops.h>
71 #include <linux/workqueue.h>
72 #include <linux/hdlc.h>
73 #include <linux/synclink.h>
74
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/dma.h>
78 #include <asm/types.h>
79 #include <linux/uaccess.h>
80
81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82 #define SYNCLINK_GENERIC_HDLC 1
83 #else
84 #define SYNCLINK_GENERIC_HDLC 0
85 #endif
86
87 /*
88 * module identification
89 */
90 static char *driver_name = "SyncLink GT";
91 static char *slgt_driver_name = "synclink_gt";
92 static char *tty_dev_prefix = "ttySLG";
93 MODULE_LICENSE("GPL");
94 #define MAX_DEVICES 32
95
96 static const struct pci_device_id pci_table[] = {
97 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {0,}, /* terminate list */
102 };
103 MODULE_DEVICE_TABLE(pci, pci_table);
104
105 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
106 static void remove_one(struct pci_dev *dev);
107 static struct pci_driver pci_driver = {
108 .name = "synclink_gt",
109 .id_table = pci_table,
110 .probe = init_one,
111 .remove = remove_one,
112 };
113
114 static bool pci_registered;
115
116 /*
117 * module configuration and status
118 */
119 static struct slgt_info *slgt_device_list;
120 static int slgt_device_count;
121
122 static int ttymajor;
123 static int debug_level;
124 static int maxframe[MAX_DEVICES];
125
126 module_param(ttymajor, int, 0);
127 module_param(debug_level, int, 0);
128 module_param_array(maxframe, int, NULL, 0);
129
130 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
131 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
132 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
133
134 /*
135 * tty support and callbacks
136 */
137 static struct tty_driver *serial_driver;
138
139 static void wait_until_sent(struct tty_struct *tty, int timeout);
140 static void flush_buffer(struct tty_struct *tty);
141 static void tx_release(struct tty_struct *tty);
142
143 /*
144 * generic HDLC support
145 */
146 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
147
148
149 /*
150 * device specific structures, macros and functions
151 */
152
153 #define SLGT_MAX_PORTS 4
154 #define SLGT_REG_SIZE 256
155
156 /*
157 * conditional wait facility
158 */
159 struct cond_wait {
160 struct cond_wait *next;
161 wait_queue_head_t q;
162 wait_queue_entry_t wait;
163 unsigned int data;
164 };
165 static void flush_cond_wait(struct cond_wait **head);
166
167 /*
168 * DMA buffer descriptor and access macros
169 */
170 struct slgt_desc
171 {
172 __le16 count;
173 __le16 status;
174 __le32 pbuf; /* physical address of data buffer */
175 __le32 next; /* physical address of next descriptor */
176
177 /* driver book keeping */
178 char *buf; /* virtual address of data buffer */
179 unsigned int pdesc; /* physical address of this descriptor */
180 dma_addr_t buf_dma_addr;
181 unsigned short buf_count;
182 };
183
184 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
185 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
186 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
187 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
188 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
189 #define desc_count(a) (le16_to_cpu((a).count))
190 #define desc_status(a) (le16_to_cpu((a).status))
191 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
192 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
193 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
194 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
195 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
196
197 struct _input_signal_events {
198 int ri_up;
199 int ri_down;
200 int dsr_up;
201 int dsr_down;
202 int dcd_up;
203 int dcd_down;
204 int cts_up;
205 int cts_down;
206 };
207
208 /*
209 * device instance data structure
210 */
211 struct slgt_info {
212 void *if_ptr; /* General purpose pointer (used by SPPP) */
213 struct tty_port port;
214
215 struct slgt_info *next_device; /* device list link */
216
217 char device_name[25];
218 struct pci_dev *pdev;
219
220 int port_count; /* count of ports on adapter */
221 int adapter_num; /* adapter instance number */
222 int port_num; /* port instance number */
223
224 /* array of pointers to port contexts on this adapter */
225 struct slgt_info *port_array[SLGT_MAX_PORTS];
226
227 int line; /* tty line instance number */
228
229 struct mgsl_icount icount;
230
231 int timeout;
232 int x_char; /* xon/xoff character */
233 unsigned int read_status_mask;
234 unsigned int ignore_status_mask;
235
236 wait_queue_head_t status_event_wait_q;
237 wait_queue_head_t event_wait_q;
238 struct timer_list tx_timer;
239 struct timer_list rx_timer;
240
241 unsigned int gpio_present;
242 struct cond_wait *gpio_wait_q;
243
244 spinlock_t lock; /* spinlock for synchronizing with ISR */
245
246 struct work_struct task;
247 u32 pending_bh;
248 bool bh_requested;
249 bool bh_running;
250
251 int isr_overflow;
252 bool irq_requested; /* true if IRQ requested */
253 bool irq_occurred; /* for diagnostics use */
254
255 /* device configuration */
256
257 unsigned int bus_type;
258 unsigned int irq_level;
259 unsigned long irq_flags;
260
261 unsigned char __iomem * reg_addr; /* memory mapped registers address */
262 u32 phys_reg_addr;
263 bool reg_addr_requested;
264
265 MGSL_PARAMS params; /* communications parameters */
266 u32 idle_mode;
267 u32 max_frame_size; /* as set by device config */
268
269 unsigned int rbuf_fill_level;
270 unsigned int rx_pio;
271 unsigned int if_mode;
272 unsigned int base_clock;
273 unsigned int xsync;
274 unsigned int xctrl;
275
276 /* device status */
277
278 bool rx_enabled;
279 bool rx_restart;
280
281 bool tx_enabled;
282 bool tx_active;
283
284 unsigned char signals; /* serial signal states */
285 int init_error; /* initialization error */
286
287 unsigned char *tx_buf;
288 int tx_count;
289
290 char *flag_buf;
291 bool drop_rts_on_tx_done;
292 struct _input_signal_events input_signal_events;
293
294 int dcd_chkcount; /* check counts to prevent */
295 int cts_chkcount; /* too many IRQs if a signal */
296 int dsr_chkcount; /* is floating */
297 int ri_chkcount;
298
299 char *bufs; /* virtual address of DMA buffer lists */
300 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
301
302 unsigned int rbuf_count;
303 struct slgt_desc *rbufs;
304 unsigned int rbuf_current;
305 unsigned int rbuf_index;
306 unsigned int rbuf_fill_index;
307 unsigned short rbuf_fill_count;
308
309 unsigned int tbuf_count;
310 struct slgt_desc *tbufs;
311 unsigned int tbuf_current;
312 unsigned int tbuf_start;
313
314 unsigned char *tmp_rbuf;
315 unsigned int tmp_rbuf_count;
316
317 /* SPPP/Cisco HDLC device parts */
318
319 int netcount;
320 spinlock_t netlock;
321 #if SYNCLINK_GENERIC_HDLC
322 struct net_device *netdev;
323 #endif
324
325 };
326
327 static MGSL_PARAMS default_params = {
328 .mode = MGSL_MODE_HDLC,
329 .loopback = 0,
330 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
331 .encoding = HDLC_ENCODING_NRZI_SPACE,
332 .clock_speed = 0,
333 .addr_filter = 0xff,
334 .crc_type = HDLC_CRC_16_CCITT,
335 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
336 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
337 .data_rate = 9600,
338 .data_bits = 8,
339 .stop_bits = 1,
340 .parity = ASYNC_PARITY_NONE
341 };
342
343
344 #define BH_RECEIVE 1
345 #define BH_TRANSMIT 2
346 #define BH_STATUS 4
347 #define IO_PIN_SHUTDOWN_LIMIT 100
348
349 #define DMABUFSIZE 256
350 #define DESC_LIST_SIZE 4096
351
352 #define MASK_PARITY BIT1
353 #define MASK_FRAMING BIT0
354 #define MASK_BREAK BIT14
355 #define MASK_OVERRUN BIT4
356
357 #define GSR 0x00 /* global status */
358 #define JCR 0x04 /* JTAG control */
359 #define IODR 0x08 /* GPIO direction */
360 #define IOER 0x0c /* GPIO interrupt enable */
361 #define IOVR 0x10 /* GPIO value */
362 #define IOSR 0x14 /* GPIO interrupt status */
363 #define TDR 0x80 /* tx data */
364 #define RDR 0x80 /* rx data */
365 #define TCR 0x82 /* tx control */
366 #define TIR 0x84 /* tx idle */
367 #define TPR 0x85 /* tx preamble */
368 #define RCR 0x86 /* rx control */
369 #define VCR 0x88 /* V.24 control */
370 #define CCR 0x89 /* clock control */
371 #define BDR 0x8a /* baud divisor */
372 #define SCR 0x8c /* serial control */
373 #define SSR 0x8e /* serial status */
374 #define RDCSR 0x90 /* rx DMA control/status */
375 #define TDCSR 0x94 /* tx DMA control/status */
376 #define RDDAR 0x98 /* rx DMA descriptor address */
377 #define TDDAR 0x9c /* tx DMA descriptor address */
378 #define XSR 0x40 /* extended sync pattern */
379 #define XCR 0x44 /* extended control */
380
381 #define RXIDLE BIT14
382 #define RXBREAK BIT14
383 #define IRQ_TXDATA BIT13
384 #define IRQ_TXIDLE BIT12
385 #define IRQ_TXUNDER BIT11 /* HDLC */
386 #define IRQ_RXDATA BIT10
387 #define IRQ_RXIDLE BIT9 /* HDLC */
388 #define IRQ_RXBREAK BIT9 /* async */
389 #define IRQ_RXOVER BIT8
390 #define IRQ_DSR BIT7
391 #define IRQ_CTS BIT6
392 #define IRQ_DCD BIT5
393 #define IRQ_RI BIT4
394 #define IRQ_ALL 0x3ff0
395 #define IRQ_MASTER BIT0
396
397 #define slgt_irq_on(info, mask) \
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
399 #define slgt_irq_off(info, mask) \
400 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
401
402 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
403 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
404 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
405 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
406 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
407 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
408
409 static void msc_set_vcr(struct slgt_info *info);
410
411 static int startup(struct slgt_info *info);
412 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
413 static void shutdown(struct slgt_info *info);
414 static void program_hw(struct slgt_info *info);
415 static void change_params(struct slgt_info *info);
416
417 static int adapter_test(struct slgt_info *info);
418
419 static void reset_port(struct slgt_info *info);
420 static void async_mode(struct slgt_info *info);
421 static void sync_mode(struct slgt_info *info);
422
423 static void rx_stop(struct slgt_info *info);
424 static void rx_start(struct slgt_info *info);
425 static void reset_rbufs(struct slgt_info *info);
426 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
427 static bool rx_get_frame(struct slgt_info *info);
428 static bool rx_get_buf(struct slgt_info *info);
429
430 static void tx_start(struct slgt_info *info);
431 static void tx_stop(struct slgt_info *info);
432 static void tx_set_idle(struct slgt_info *info);
433 static unsigned int tbuf_bytes(struct slgt_info *info);
434 static void reset_tbufs(struct slgt_info *info);
435 static void tdma_reset(struct slgt_info *info);
436 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
437
438 static void get_gtsignals(struct slgt_info *info);
439 static void set_gtsignals(struct slgt_info *info);
440 static void set_rate(struct slgt_info *info, u32 data_rate);
441
442 static void bh_transmit(struct slgt_info *info);
443 static void isr_txeom(struct slgt_info *info, unsigned short status);
444
445 static void tx_timeout(struct timer_list *t);
446 static void rx_timeout(struct timer_list *t);
447
448 /*
449 * ioctl handlers
450 */
451 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
452 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
453 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
454 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
455 static int set_txidle(struct slgt_info *info, int idle_mode);
456 static int tx_enable(struct slgt_info *info, int enable);
457 static int tx_abort(struct slgt_info *info);
458 static int rx_enable(struct slgt_info *info, int enable);
459 static int modem_input_wait(struct slgt_info *info,int arg);
460 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
461 static int get_interface(struct slgt_info *info, int __user *if_mode);
462 static int set_interface(struct slgt_info *info, int if_mode);
463 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
465 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
466 static int get_xsync(struct slgt_info *info, int __user *if_mode);
467 static int set_xsync(struct slgt_info *info, int if_mode);
468 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
469 static int set_xctrl(struct slgt_info *info, int if_mode);
470
471 /*
472 * driver functions
473 */
474 static void release_resources(struct slgt_info *info);
475
476 /*
477 * DEBUG OUTPUT CODE
478 */
479 #ifndef DBGINFO
480 #define DBGINFO(fmt)
481 #endif
482 #ifndef DBGERR
483 #define DBGERR(fmt)
484 #endif
485 #ifndef DBGBH
486 #define DBGBH(fmt)
487 #endif
488 #ifndef DBGISR
489 #define DBGISR(fmt)
490 #endif
491
492 #ifdef DBGDATA
trace_block(struct slgt_info * info,const char * data,int count,const char * label)493 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
494 {
495 int i;
496 int linecount;
497 printk("%s %s data:\n",info->device_name, label);
498 while(count) {
499 linecount = (count > 16) ? 16 : count;
500 for(i=0; i < linecount; i++)
501 printk("%02X ",(unsigned char)data[i]);
502 for(;i<17;i++)
503 printk(" ");
504 for(i=0;i<linecount;i++) {
505 if (data[i]>=040 && data[i]<=0176)
506 printk("%c",data[i]);
507 else
508 printk(".");
509 }
510 printk("\n");
511 data += linecount;
512 count -= linecount;
513 }
514 }
515 #else
516 #define DBGDATA(info, buf, size, label)
517 #endif
518
519 #ifdef DBGTBUF
dump_tbufs(struct slgt_info * info)520 static void dump_tbufs(struct slgt_info *info)
521 {
522 int i;
523 printk("tbuf_current=%d\n", info->tbuf_current);
524 for (i=0 ; i < info->tbuf_count ; i++) {
525 printk("%d: count=%04X status=%04X\n",
526 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
527 }
528 }
529 #else
530 #define DBGTBUF(info)
531 #endif
532
533 #ifdef DBGRBUF
dump_rbufs(struct slgt_info * info)534 static void dump_rbufs(struct slgt_info *info)
535 {
536 int i;
537 printk("rbuf_current=%d\n", info->rbuf_current);
538 for (i=0 ; i < info->rbuf_count ; i++) {
539 printk("%d: count=%04X status=%04X\n",
540 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
541 }
542 }
543 #else
544 #define DBGRBUF(info)
545 #endif
546
sanity_check(struct slgt_info * info,char * devname,const char * name)547 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
548 {
549 #ifdef SANITY_CHECK
550 if (!info) {
551 printk("null struct slgt_info for (%s) in %s\n", devname, name);
552 return 1;
553 }
554 #else
555 if (!info)
556 return 1;
557 #endif
558 return 0;
559 }
560
561 /*
562 * line discipline callback wrappers
563 *
564 * The wrappers maintain line discipline references
565 * while calling into the line discipline.
566 *
567 * ldisc_receive_buf - pass receive data to line discipline
568 */
ldisc_receive_buf(struct tty_struct * tty,const __u8 * data,char * flags,int count)569 static void ldisc_receive_buf(struct tty_struct *tty,
570 const __u8 *data, char *flags, int count)
571 {
572 struct tty_ldisc *ld;
573 if (!tty)
574 return;
575 ld = tty_ldisc_ref(tty);
576 if (ld) {
577 if (ld->ops->receive_buf)
578 ld->ops->receive_buf(tty, data, flags, count);
579 tty_ldisc_deref(ld);
580 }
581 }
582
583 /* tty callbacks */
584
open(struct tty_struct * tty,struct file * filp)585 static int open(struct tty_struct *tty, struct file *filp)
586 {
587 struct slgt_info *info;
588 int retval, line;
589 unsigned long flags;
590
591 line = tty->index;
592 if (line >= slgt_device_count) {
593 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
594 return -ENODEV;
595 }
596
597 info = slgt_device_list;
598 while(info && info->line != line)
599 info = info->next_device;
600 if (sanity_check(info, tty->name, "open"))
601 return -ENODEV;
602 if (info->init_error) {
603 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
604 return -ENODEV;
605 }
606
607 tty->driver_data = info;
608 info->port.tty = tty;
609
610 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
611
612 mutex_lock(&info->port.mutex);
613
614 spin_lock_irqsave(&info->netlock, flags);
615 if (info->netcount) {
616 retval = -EBUSY;
617 spin_unlock_irqrestore(&info->netlock, flags);
618 mutex_unlock(&info->port.mutex);
619 goto cleanup;
620 }
621 info->port.count++;
622 spin_unlock_irqrestore(&info->netlock, flags);
623
624 if (info->port.count == 1) {
625 /* 1st open on this device, init hardware */
626 retval = startup(info);
627 if (retval < 0) {
628 mutex_unlock(&info->port.mutex);
629 goto cleanup;
630 }
631 }
632 mutex_unlock(&info->port.mutex);
633 retval = block_til_ready(tty, filp, info);
634 if (retval) {
635 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
636 goto cleanup;
637 }
638
639 retval = 0;
640
641 cleanup:
642 if (retval) {
643 if (tty->count == 1)
644 info->port.tty = NULL; /* tty layer will release tty struct */
645 if(info->port.count)
646 info->port.count--;
647 }
648
649 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
650 return retval;
651 }
652
close(struct tty_struct * tty,struct file * filp)653 static void close(struct tty_struct *tty, struct file *filp)
654 {
655 struct slgt_info *info = tty->driver_data;
656
657 if (sanity_check(info, tty->name, "close"))
658 return;
659 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
660
661 if (tty_port_close_start(&info->port, tty, filp) == 0)
662 goto cleanup;
663
664 mutex_lock(&info->port.mutex);
665 if (tty_port_initialized(&info->port))
666 wait_until_sent(tty, info->timeout);
667 flush_buffer(tty);
668 tty_ldisc_flush(tty);
669
670 shutdown(info);
671 mutex_unlock(&info->port.mutex);
672
673 tty_port_close_end(&info->port, tty);
674 info->port.tty = NULL;
675 cleanup:
676 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
677 }
678
hangup(struct tty_struct * tty)679 static void hangup(struct tty_struct *tty)
680 {
681 struct slgt_info *info = tty->driver_data;
682 unsigned long flags;
683
684 if (sanity_check(info, tty->name, "hangup"))
685 return;
686 DBGINFO(("%s hangup\n", info->device_name));
687
688 flush_buffer(tty);
689
690 mutex_lock(&info->port.mutex);
691 shutdown(info);
692
693 spin_lock_irqsave(&info->port.lock, flags);
694 info->port.count = 0;
695 info->port.tty = NULL;
696 spin_unlock_irqrestore(&info->port.lock, flags);
697 tty_port_set_active(&info->port, 0);
698 mutex_unlock(&info->port.mutex);
699
700 wake_up_interruptible(&info->port.open_wait);
701 }
702
set_termios(struct tty_struct * tty,const struct ktermios * old_termios)703 static void set_termios(struct tty_struct *tty,
704 const struct ktermios *old_termios)
705 {
706 struct slgt_info *info = tty->driver_data;
707 unsigned long flags;
708
709 DBGINFO(("%s set_termios\n", tty->driver->name));
710
711 change_params(info);
712
713 /* Handle transition to B0 status */
714 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
715 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
716 spin_lock_irqsave(&info->lock,flags);
717 set_gtsignals(info);
718 spin_unlock_irqrestore(&info->lock,flags);
719 }
720
721 /* Handle transition away from B0 status */
722 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
723 info->signals |= SerialSignal_DTR;
724 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
725 info->signals |= SerialSignal_RTS;
726 spin_lock_irqsave(&info->lock,flags);
727 set_gtsignals(info);
728 spin_unlock_irqrestore(&info->lock,flags);
729 }
730
731 /* Handle turning off CRTSCTS */
732 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
733 tty->hw_stopped = 0;
734 tx_release(tty);
735 }
736 }
737
update_tx_timer(struct slgt_info * info)738 static void update_tx_timer(struct slgt_info *info)
739 {
740 /*
741 * use worst case speed of 1200bps to calculate transmit timeout
742 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
743 */
744 if (info->params.mode == MGSL_MODE_HDLC) {
745 int timeout = (tbuf_bytes(info) * 7) + 1000;
746 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
747 }
748 }
749
write(struct tty_struct * tty,const unsigned char * buf,int count)750 static int write(struct tty_struct *tty,
751 const unsigned char *buf, int count)
752 {
753 int ret = 0;
754 struct slgt_info *info = tty->driver_data;
755 unsigned long flags;
756
757 if (sanity_check(info, tty->name, "write"))
758 return -EIO;
759
760 DBGINFO(("%s write count=%d\n", info->device_name, count));
761
762 if (!info->tx_buf || (count > info->max_frame_size))
763 return -EIO;
764
765 if (!count || tty->flow.stopped || tty->hw_stopped)
766 return 0;
767
768 spin_lock_irqsave(&info->lock, flags);
769
770 if (info->tx_count) {
771 /* send accumulated data from send_char() */
772 if (!tx_load(info, info->tx_buf, info->tx_count))
773 goto cleanup;
774 info->tx_count = 0;
775 }
776
777 if (tx_load(info, buf, count))
778 ret = count;
779
780 cleanup:
781 spin_unlock_irqrestore(&info->lock, flags);
782 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
783 return ret;
784 }
785
put_char(struct tty_struct * tty,unsigned char ch)786 static int put_char(struct tty_struct *tty, unsigned char ch)
787 {
788 struct slgt_info *info = tty->driver_data;
789 unsigned long flags;
790 int ret = 0;
791
792 if (sanity_check(info, tty->name, "put_char"))
793 return 0;
794 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
795 if (!info->tx_buf)
796 return 0;
797 spin_lock_irqsave(&info->lock,flags);
798 if (info->tx_count < info->max_frame_size) {
799 info->tx_buf[info->tx_count++] = ch;
800 ret = 1;
801 }
802 spin_unlock_irqrestore(&info->lock,flags);
803 return ret;
804 }
805
send_xchar(struct tty_struct * tty,char ch)806 static void send_xchar(struct tty_struct *tty, char ch)
807 {
808 struct slgt_info *info = tty->driver_data;
809 unsigned long flags;
810
811 if (sanity_check(info, tty->name, "send_xchar"))
812 return;
813 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
814 info->x_char = ch;
815 if (ch) {
816 spin_lock_irqsave(&info->lock,flags);
817 if (!info->tx_enabled)
818 tx_start(info);
819 spin_unlock_irqrestore(&info->lock,flags);
820 }
821 }
822
wait_until_sent(struct tty_struct * tty,int timeout)823 static void wait_until_sent(struct tty_struct *tty, int timeout)
824 {
825 struct slgt_info *info = tty->driver_data;
826 unsigned long orig_jiffies, char_time;
827
828 if (!info )
829 return;
830 if (sanity_check(info, tty->name, "wait_until_sent"))
831 return;
832 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
833 if (!tty_port_initialized(&info->port))
834 goto exit;
835
836 orig_jiffies = jiffies;
837
838 /* Set check interval to 1/5 of estimated time to
839 * send a character, and make it at least 1. The check
840 * interval should also be less than the timeout.
841 * Note: use tight timings here to satisfy the NIST-PCTS.
842 */
843
844 if (info->params.data_rate) {
845 char_time = info->timeout/(32 * 5);
846 if (!char_time)
847 char_time++;
848 } else
849 char_time = 1;
850
851 if (timeout)
852 char_time = min_t(unsigned long, char_time, timeout);
853
854 while (info->tx_active) {
855 msleep_interruptible(jiffies_to_msecs(char_time));
856 if (signal_pending(current))
857 break;
858 if (timeout && time_after(jiffies, orig_jiffies + timeout))
859 break;
860 }
861 exit:
862 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
863 }
864
write_room(struct tty_struct * tty)865 static unsigned int write_room(struct tty_struct *tty)
866 {
867 struct slgt_info *info = tty->driver_data;
868 unsigned int ret;
869
870 if (sanity_check(info, tty->name, "write_room"))
871 return 0;
872 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
873 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
874 return ret;
875 }
876
flush_chars(struct tty_struct * tty)877 static void flush_chars(struct tty_struct *tty)
878 {
879 struct slgt_info *info = tty->driver_data;
880 unsigned long flags;
881
882 if (sanity_check(info, tty->name, "flush_chars"))
883 return;
884 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
885
886 if (info->tx_count <= 0 || tty->flow.stopped ||
887 tty->hw_stopped || !info->tx_buf)
888 return;
889
890 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
891
892 spin_lock_irqsave(&info->lock,flags);
893 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
894 info->tx_count = 0;
895 spin_unlock_irqrestore(&info->lock,flags);
896 }
897
flush_buffer(struct tty_struct * tty)898 static void flush_buffer(struct tty_struct *tty)
899 {
900 struct slgt_info *info = tty->driver_data;
901 unsigned long flags;
902
903 if (sanity_check(info, tty->name, "flush_buffer"))
904 return;
905 DBGINFO(("%s flush_buffer\n", info->device_name));
906
907 spin_lock_irqsave(&info->lock, flags);
908 info->tx_count = 0;
909 spin_unlock_irqrestore(&info->lock, flags);
910
911 tty_wakeup(tty);
912 }
913
914 /*
915 * throttle (stop) transmitter
916 */
tx_hold(struct tty_struct * tty)917 static void tx_hold(struct tty_struct *tty)
918 {
919 struct slgt_info *info = tty->driver_data;
920 unsigned long flags;
921
922 if (sanity_check(info, tty->name, "tx_hold"))
923 return;
924 DBGINFO(("%s tx_hold\n", info->device_name));
925 spin_lock_irqsave(&info->lock,flags);
926 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
927 tx_stop(info);
928 spin_unlock_irqrestore(&info->lock,flags);
929 }
930
931 /*
932 * release (start) transmitter
933 */
tx_release(struct tty_struct * tty)934 static void tx_release(struct tty_struct *tty)
935 {
936 struct slgt_info *info = tty->driver_data;
937 unsigned long flags;
938
939 if (sanity_check(info, tty->name, "tx_release"))
940 return;
941 DBGINFO(("%s tx_release\n", info->device_name));
942 spin_lock_irqsave(&info->lock, flags);
943 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
944 info->tx_count = 0;
945 spin_unlock_irqrestore(&info->lock, flags);
946 }
947
948 /*
949 * Service an IOCTL request
950 *
951 * Arguments
952 *
953 * tty pointer to tty instance data
954 * cmd IOCTL command code
955 * arg command argument/context
956 *
957 * Return 0 if success, otherwise error code
958 */
ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)959 static int ioctl(struct tty_struct *tty,
960 unsigned int cmd, unsigned long arg)
961 {
962 struct slgt_info *info = tty->driver_data;
963 void __user *argp = (void __user *)arg;
964 int ret;
965
966 if (sanity_check(info, tty->name, "ioctl"))
967 return -ENODEV;
968 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
969
970 if (cmd != TIOCMIWAIT) {
971 if (tty_io_error(tty))
972 return -EIO;
973 }
974
975 switch (cmd) {
976 case MGSL_IOCWAITEVENT:
977 return wait_mgsl_event(info, argp);
978 case TIOCMIWAIT:
979 return modem_input_wait(info,(int)arg);
980 case MGSL_IOCSGPIO:
981 return set_gpio(info, argp);
982 case MGSL_IOCGGPIO:
983 return get_gpio(info, argp);
984 case MGSL_IOCWAITGPIO:
985 return wait_gpio(info, argp);
986 case MGSL_IOCGXSYNC:
987 return get_xsync(info, argp);
988 case MGSL_IOCSXSYNC:
989 return set_xsync(info, (int)arg);
990 case MGSL_IOCGXCTRL:
991 return get_xctrl(info, argp);
992 case MGSL_IOCSXCTRL:
993 return set_xctrl(info, (int)arg);
994 }
995 mutex_lock(&info->port.mutex);
996 switch (cmd) {
997 case MGSL_IOCGPARAMS:
998 ret = get_params(info, argp);
999 break;
1000 case MGSL_IOCSPARAMS:
1001 ret = set_params(info, argp);
1002 break;
1003 case MGSL_IOCGTXIDLE:
1004 ret = get_txidle(info, argp);
1005 break;
1006 case MGSL_IOCSTXIDLE:
1007 ret = set_txidle(info, (int)arg);
1008 break;
1009 case MGSL_IOCTXENABLE:
1010 ret = tx_enable(info, (int)arg);
1011 break;
1012 case MGSL_IOCRXENABLE:
1013 ret = rx_enable(info, (int)arg);
1014 break;
1015 case MGSL_IOCTXABORT:
1016 ret = tx_abort(info);
1017 break;
1018 case MGSL_IOCGSTATS:
1019 ret = get_stats(info, argp);
1020 break;
1021 case MGSL_IOCGIF:
1022 ret = get_interface(info, argp);
1023 break;
1024 case MGSL_IOCSIF:
1025 ret = set_interface(info,(int)arg);
1026 break;
1027 default:
1028 ret = -ENOIOCTLCMD;
1029 }
1030 mutex_unlock(&info->port.mutex);
1031 return ret;
1032 }
1033
get_icount(struct tty_struct * tty,struct serial_icounter_struct * icount)1034 static int get_icount(struct tty_struct *tty,
1035 struct serial_icounter_struct *icount)
1036
1037 {
1038 struct slgt_info *info = tty->driver_data;
1039 struct mgsl_icount cnow; /* kernel counter temps */
1040 unsigned long flags;
1041
1042 spin_lock_irqsave(&info->lock,flags);
1043 cnow = info->icount;
1044 spin_unlock_irqrestore(&info->lock,flags);
1045
1046 icount->cts = cnow.cts;
1047 icount->dsr = cnow.dsr;
1048 icount->rng = cnow.rng;
1049 icount->dcd = cnow.dcd;
1050 icount->rx = cnow.rx;
1051 icount->tx = cnow.tx;
1052 icount->frame = cnow.frame;
1053 icount->overrun = cnow.overrun;
1054 icount->parity = cnow.parity;
1055 icount->brk = cnow.brk;
1056 icount->buf_overrun = cnow.buf_overrun;
1057
1058 return 0;
1059 }
1060
1061 /*
1062 * support for 32 bit ioctl calls on 64 bit systems
1063 */
1064 #ifdef CONFIG_COMPAT
get_params32(struct slgt_info * info,struct MGSL_PARAMS32 __user * user_params)1065 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1066 {
1067 struct MGSL_PARAMS32 tmp_params;
1068
1069 DBGINFO(("%s get_params32\n", info->device_name));
1070 memset(&tmp_params, 0, sizeof(tmp_params));
1071 tmp_params.mode = (compat_ulong_t)info->params.mode;
1072 tmp_params.loopback = info->params.loopback;
1073 tmp_params.flags = info->params.flags;
1074 tmp_params.encoding = info->params.encoding;
1075 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1076 tmp_params.addr_filter = info->params.addr_filter;
1077 tmp_params.crc_type = info->params.crc_type;
1078 tmp_params.preamble_length = info->params.preamble_length;
1079 tmp_params.preamble = info->params.preamble;
1080 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1081 tmp_params.data_bits = info->params.data_bits;
1082 tmp_params.stop_bits = info->params.stop_bits;
1083 tmp_params.parity = info->params.parity;
1084 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1085 return -EFAULT;
1086 return 0;
1087 }
1088
set_params32(struct slgt_info * info,struct MGSL_PARAMS32 __user * new_params)1089 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1090 {
1091 struct MGSL_PARAMS32 tmp_params;
1092
1093 DBGINFO(("%s set_params32\n", info->device_name));
1094 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1095 return -EFAULT;
1096
1097 spin_lock(&info->lock);
1098 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1099 info->base_clock = tmp_params.clock_speed;
1100 } else {
1101 info->params.mode = tmp_params.mode;
1102 info->params.loopback = tmp_params.loopback;
1103 info->params.flags = tmp_params.flags;
1104 info->params.encoding = tmp_params.encoding;
1105 info->params.clock_speed = tmp_params.clock_speed;
1106 info->params.addr_filter = tmp_params.addr_filter;
1107 info->params.crc_type = tmp_params.crc_type;
1108 info->params.preamble_length = tmp_params.preamble_length;
1109 info->params.preamble = tmp_params.preamble;
1110 info->params.data_rate = tmp_params.data_rate;
1111 info->params.data_bits = tmp_params.data_bits;
1112 info->params.stop_bits = tmp_params.stop_bits;
1113 info->params.parity = tmp_params.parity;
1114 }
1115 spin_unlock(&info->lock);
1116
1117 program_hw(info);
1118
1119 return 0;
1120 }
1121
slgt_compat_ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)1122 static long slgt_compat_ioctl(struct tty_struct *tty,
1123 unsigned int cmd, unsigned long arg)
1124 {
1125 struct slgt_info *info = tty->driver_data;
1126 int rc;
1127
1128 if (sanity_check(info, tty->name, "compat_ioctl"))
1129 return -ENODEV;
1130 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1131
1132 switch (cmd) {
1133 case MGSL_IOCSPARAMS32:
1134 rc = set_params32(info, compat_ptr(arg));
1135 break;
1136
1137 case MGSL_IOCGPARAMS32:
1138 rc = get_params32(info, compat_ptr(arg));
1139 break;
1140
1141 case MGSL_IOCGPARAMS:
1142 case MGSL_IOCSPARAMS:
1143 case MGSL_IOCGTXIDLE:
1144 case MGSL_IOCGSTATS:
1145 case MGSL_IOCWAITEVENT:
1146 case MGSL_IOCGIF:
1147 case MGSL_IOCSGPIO:
1148 case MGSL_IOCGGPIO:
1149 case MGSL_IOCWAITGPIO:
1150 case MGSL_IOCGXSYNC:
1151 case MGSL_IOCGXCTRL:
1152 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1153 break;
1154 default:
1155 rc = ioctl(tty, cmd, arg);
1156 }
1157 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1158 return rc;
1159 }
1160 #else
1161 #define slgt_compat_ioctl NULL
1162 #endif /* ifdef CONFIG_COMPAT */
1163
1164 /*
1165 * proc fs support
1166 */
line_info(struct seq_file * m,struct slgt_info * info)1167 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1168 {
1169 char stat_buf[30];
1170 unsigned long flags;
1171
1172 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1173 info->device_name, info->phys_reg_addr,
1174 info->irq_level, info->max_frame_size);
1175
1176 /* output current serial signal states */
1177 spin_lock_irqsave(&info->lock,flags);
1178 get_gtsignals(info);
1179 spin_unlock_irqrestore(&info->lock,flags);
1180
1181 stat_buf[0] = 0;
1182 stat_buf[1] = 0;
1183 if (info->signals & SerialSignal_RTS)
1184 strcat(stat_buf, "|RTS");
1185 if (info->signals & SerialSignal_CTS)
1186 strcat(stat_buf, "|CTS");
1187 if (info->signals & SerialSignal_DTR)
1188 strcat(stat_buf, "|DTR");
1189 if (info->signals & SerialSignal_DSR)
1190 strcat(stat_buf, "|DSR");
1191 if (info->signals & SerialSignal_DCD)
1192 strcat(stat_buf, "|CD");
1193 if (info->signals & SerialSignal_RI)
1194 strcat(stat_buf, "|RI");
1195
1196 if (info->params.mode != MGSL_MODE_ASYNC) {
1197 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1198 info->icount.txok, info->icount.rxok);
1199 if (info->icount.txunder)
1200 seq_printf(m, " txunder:%d", info->icount.txunder);
1201 if (info->icount.txabort)
1202 seq_printf(m, " txabort:%d", info->icount.txabort);
1203 if (info->icount.rxshort)
1204 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1205 if (info->icount.rxlong)
1206 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1207 if (info->icount.rxover)
1208 seq_printf(m, " rxover:%d", info->icount.rxover);
1209 if (info->icount.rxcrc)
1210 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1211 } else {
1212 seq_printf(m, "\tASYNC tx:%d rx:%d",
1213 info->icount.tx, info->icount.rx);
1214 if (info->icount.frame)
1215 seq_printf(m, " fe:%d", info->icount.frame);
1216 if (info->icount.parity)
1217 seq_printf(m, " pe:%d", info->icount.parity);
1218 if (info->icount.brk)
1219 seq_printf(m, " brk:%d", info->icount.brk);
1220 if (info->icount.overrun)
1221 seq_printf(m, " oe:%d", info->icount.overrun);
1222 }
1223
1224 /* Append serial signal status to end */
1225 seq_printf(m, " %s\n", stat_buf+1);
1226
1227 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1228 info->tx_active,info->bh_requested,info->bh_running,
1229 info->pending_bh);
1230 }
1231
1232 /* Called to print information about devices
1233 */
synclink_gt_proc_show(struct seq_file * m,void * v)1234 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1235 {
1236 struct slgt_info *info;
1237
1238 seq_puts(m, "synclink_gt driver\n");
1239
1240 info = slgt_device_list;
1241 while( info ) {
1242 line_info(m, info);
1243 info = info->next_device;
1244 }
1245 return 0;
1246 }
1247
1248 /*
1249 * return count of bytes in transmit buffer
1250 */
chars_in_buffer(struct tty_struct * tty)1251 static unsigned int chars_in_buffer(struct tty_struct *tty)
1252 {
1253 struct slgt_info *info = tty->driver_data;
1254 unsigned int count;
1255 if (sanity_check(info, tty->name, "chars_in_buffer"))
1256 return 0;
1257 count = tbuf_bytes(info);
1258 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1259 return count;
1260 }
1261
1262 /*
1263 * signal remote device to throttle send data (our receive data)
1264 */
throttle(struct tty_struct * tty)1265 static void throttle(struct tty_struct * tty)
1266 {
1267 struct slgt_info *info = tty->driver_data;
1268 unsigned long flags;
1269
1270 if (sanity_check(info, tty->name, "throttle"))
1271 return;
1272 DBGINFO(("%s throttle\n", info->device_name));
1273 if (I_IXOFF(tty))
1274 send_xchar(tty, STOP_CHAR(tty));
1275 if (C_CRTSCTS(tty)) {
1276 spin_lock_irqsave(&info->lock,flags);
1277 info->signals &= ~SerialSignal_RTS;
1278 set_gtsignals(info);
1279 spin_unlock_irqrestore(&info->lock,flags);
1280 }
1281 }
1282
1283 /*
1284 * signal remote device to stop throttling send data (our receive data)
1285 */
unthrottle(struct tty_struct * tty)1286 static void unthrottle(struct tty_struct * tty)
1287 {
1288 struct slgt_info *info = tty->driver_data;
1289 unsigned long flags;
1290
1291 if (sanity_check(info, tty->name, "unthrottle"))
1292 return;
1293 DBGINFO(("%s unthrottle\n", info->device_name));
1294 if (I_IXOFF(tty)) {
1295 if (info->x_char)
1296 info->x_char = 0;
1297 else
1298 send_xchar(tty, START_CHAR(tty));
1299 }
1300 if (C_CRTSCTS(tty)) {
1301 spin_lock_irqsave(&info->lock,flags);
1302 info->signals |= SerialSignal_RTS;
1303 set_gtsignals(info);
1304 spin_unlock_irqrestore(&info->lock,flags);
1305 }
1306 }
1307
1308 /*
1309 * set or clear transmit break condition
1310 * break_state -1=set break condition, 0=clear
1311 */
set_break(struct tty_struct * tty,int break_state)1312 static int set_break(struct tty_struct *tty, int break_state)
1313 {
1314 struct slgt_info *info = tty->driver_data;
1315 unsigned short value;
1316 unsigned long flags;
1317
1318 if (sanity_check(info, tty->name, "set_break"))
1319 return -EINVAL;
1320 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1321
1322 spin_lock_irqsave(&info->lock,flags);
1323 value = rd_reg16(info, TCR);
1324 if (break_state == -1)
1325 value |= BIT6;
1326 else
1327 value &= ~BIT6;
1328 wr_reg16(info, TCR, value);
1329 spin_unlock_irqrestore(&info->lock,flags);
1330 return 0;
1331 }
1332
1333 #if SYNCLINK_GENERIC_HDLC
1334
1335 /**
1336 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1337 * @dev: pointer to network device structure
1338 * @encoding: serial encoding setting
1339 * @parity: FCS setting
1340 *
1341 * Set encoding and frame check sequence (FCS) options.
1342 *
1343 * Return: 0 if success, otherwise error code
1344 */
hdlcdev_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)1345 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1346 unsigned short parity)
1347 {
1348 struct slgt_info *info = dev_to_port(dev);
1349 unsigned char new_encoding;
1350 unsigned short new_crctype;
1351
1352 /* return error if TTY interface open */
1353 if (info->port.count)
1354 return -EBUSY;
1355
1356 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1357
1358 switch (encoding)
1359 {
1360 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1361 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1362 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1363 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1364 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1365 default: return -EINVAL;
1366 }
1367
1368 switch (parity)
1369 {
1370 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1371 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1372 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1373 default: return -EINVAL;
1374 }
1375
1376 info->params.encoding = new_encoding;
1377 info->params.crc_type = new_crctype;
1378
1379 /* if network interface up, reprogram hardware */
1380 if (info->netcount)
1381 program_hw(info);
1382
1383 return 0;
1384 }
1385
1386 /**
1387 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1388 * @skb: socket buffer containing HDLC frame
1389 * @dev: pointer to network device structure
1390 */
hdlcdev_xmit(struct sk_buff * skb,struct net_device * dev)1391 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1392 struct net_device *dev)
1393 {
1394 struct slgt_info *info = dev_to_port(dev);
1395 unsigned long flags;
1396
1397 DBGINFO(("%s hdlc_xmit\n", dev->name));
1398
1399 if (!skb->len)
1400 return NETDEV_TX_OK;
1401
1402 /* stop sending until this frame completes */
1403 netif_stop_queue(dev);
1404
1405 /* update network statistics */
1406 dev->stats.tx_packets++;
1407 dev->stats.tx_bytes += skb->len;
1408
1409 /* save start time for transmit timeout detection */
1410 netif_trans_update(dev);
1411
1412 spin_lock_irqsave(&info->lock, flags);
1413 tx_load(info, skb->data, skb->len);
1414 spin_unlock_irqrestore(&info->lock, flags);
1415
1416 /* done with socket buffer, so free it */
1417 dev_kfree_skb(skb);
1418
1419 return NETDEV_TX_OK;
1420 }
1421
1422 /**
1423 * hdlcdev_open - called by network layer when interface enabled
1424 * @dev: pointer to network device structure
1425 *
1426 * Claim resources and initialize hardware.
1427 *
1428 * Return: 0 if success, otherwise error code
1429 */
hdlcdev_open(struct net_device * dev)1430 static int hdlcdev_open(struct net_device *dev)
1431 {
1432 struct slgt_info *info = dev_to_port(dev);
1433 int rc;
1434 unsigned long flags;
1435
1436 if (!try_module_get(THIS_MODULE))
1437 return -EBUSY;
1438
1439 DBGINFO(("%s hdlcdev_open\n", dev->name));
1440
1441 /* generic HDLC layer open processing */
1442 rc = hdlc_open(dev);
1443 if (rc)
1444 return rc;
1445
1446 /* arbitrate between network and tty opens */
1447 spin_lock_irqsave(&info->netlock, flags);
1448 if (info->port.count != 0 || info->netcount != 0) {
1449 DBGINFO(("%s hdlc_open busy\n", dev->name));
1450 spin_unlock_irqrestore(&info->netlock, flags);
1451 return -EBUSY;
1452 }
1453 info->netcount=1;
1454 spin_unlock_irqrestore(&info->netlock, flags);
1455
1456 /* claim resources and init adapter */
1457 if ((rc = startup(info)) != 0) {
1458 spin_lock_irqsave(&info->netlock, flags);
1459 info->netcount=0;
1460 spin_unlock_irqrestore(&info->netlock, flags);
1461 return rc;
1462 }
1463
1464 /* assert RTS and DTR, apply hardware settings */
1465 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1466 program_hw(info);
1467
1468 /* enable network layer transmit */
1469 netif_trans_update(dev);
1470 netif_start_queue(dev);
1471
1472 /* inform generic HDLC layer of current DCD status */
1473 spin_lock_irqsave(&info->lock, flags);
1474 get_gtsignals(info);
1475 spin_unlock_irqrestore(&info->lock, flags);
1476 if (info->signals & SerialSignal_DCD)
1477 netif_carrier_on(dev);
1478 else
1479 netif_carrier_off(dev);
1480 return 0;
1481 }
1482
1483 /**
1484 * hdlcdev_close - called by network layer when interface is disabled
1485 * @dev: pointer to network device structure
1486 *
1487 * Shutdown hardware and release resources.
1488 *
1489 * Return: 0 if success, otherwise error code
1490 */
hdlcdev_close(struct net_device * dev)1491 static int hdlcdev_close(struct net_device *dev)
1492 {
1493 struct slgt_info *info = dev_to_port(dev);
1494 unsigned long flags;
1495
1496 DBGINFO(("%s hdlcdev_close\n", dev->name));
1497
1498 netif_stop_queue(dev);
1499
1500 /* shutdown adapter and release resources */
1501 shutdown(info);
1502
1503 hdlc_close(dev);
1504
1505 spin_lock_irqsave(&info->netlock, flags);
1506 info->netcount=0;
1507 spin_unlock_irqrestore(&info->netlock, flags);
1508
1509 module_put(THIS_MODULE);
1510 return 0;
1511 }
1512
1513 /**
1514 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1515 * @dev: pointer to network device structure
1516 * @ifr: pointer to network interface request structure
1517 * @cmd: IOCTL command code
1518 *
1519 * Return: 0 if success, otherwise error code
1520 */
hdlcdev_ioctl(struct net_device * dev,struct if_settings * ifs)1521 static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1522 {
1523 const size_t size = sizeof(sync_serial_settings);
1524 sync_serial_settings new_line;
1525 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1526 struct slgt_info *info = dev_to_port(dev);
1527 unsigned int flags;
1528
1529 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1530
1531 /* return error if TTY interface open */
1532 if (info->port.count)
1533 return -EBUSY;
1534
1535 memset(&new_line, 0, sizeof(new_line));
1536
1537 switch (ifs->type) {
1538 case IF_GET_IFACE: /* return current sync_serial_settings */
1539
1540 ifs->type = IF_IFACE_SYNC_SERIAL;
1541 if (ifs->size < size) {
1542 ifs->size = size; /* data size wanted */
1543 return -ENOBUFS;
1544 }
1545
1546 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1547 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1548 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1549 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1550
1551 switch (flags){
1552 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1553 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1554 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1555 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1556 default: new_line.clock_type = CLOCK_DEFAULT;
1557 }
1558
1559 new_line.clock_rate = info->params.clock_speed;
1560 new_line.loopback = info->params.loopback ? 1:0;
1561
1562 if (copy_to_user(line, &new_line, size))
1563 return -EFAULT;
1564 return 0;
1565
1566 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1567
1568 if(!capable(CAP_NET_ADMIN))
1569 return -EPERM;
1570 if (copy_from_user(&new_line, line, size))
1571 return -EFAULT;
1572
1573 switch (new_line.clock_type)
1574 {
1575 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1576 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1577 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1578 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1579 case CLOCK_DEFAULT: flags = info->params.flags &
1580 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1581 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1582 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1583 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1584 default: return -EINVAL;
1585 }
1586
1587 if (new_line.loopback != 0 && new_line.loopback != 1)
1588 return -EINVAL;
1589
1590 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1591 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1592 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1593 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1594 info->params.flags |= flags;
1595
1596 info->params.loopback = new_line.loopback;
1597
1598 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1599 info->params.clock_speed = new_line.clock_rate;
1600 else
1601 info->params.clock_speed = 0;
1602
1603 /* if network interface up, reprogram hardware */
1604 if (info->netcount)
1605 program_hw(info);
1606 return 0;
1607
1608 default:
1609 return hdlc_ioctl(dev, ifs);
1610 }
1611 }
1612
1613 /**
1614 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1615 * @dev: pointer to network device structure
1616 * @txqueue: unused
1617 */
hdlcdev_tx_timeout(struct net_device * dev,unsigned int txqueue)1618 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1619 {
1620 struct slgt_info *info = dev_to_port(dev);
1621 unsigned long flags;
1622
1623 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1624
1625 dev->stats.tx_errors++;
1626 dev->stats.tx_aborted_errors++;
1627
1628 spin_lock_irqsave(&info->lock,flags);
1629 tx_stop(info);
1630 spin_unlock_irqrestore(&info->lock,flags);
1631
1632 netif_wake_queue(dev);
1633 }
1634
1635 /**
1636 * hdlcdev_tx_done - called by device driver when transmit completes
1637 * @info: pointer to device instance information
1638 *
1639 * Reenable network layer transmit if stopped.
1640 */
hdlcdev_tx_done(struct slgt_info * info)1641 static void hdlcdev_tx_done(struct slgt_info *info)
1642 {
1643 if (netif_queue_stopped(info->netdev))
1644 netif_wake_queue(info->netdev);
1645 }
1646
1647 /**
1648 * hdlcdev_rx - called by device driver when frame received
1649 * @info: pointer to device instance information
1650 * @buf: pointer to buffer contianing frame data
1651 * @size: count of data bytes in buf
1652 *
1653 * Pass frame to network layer.
1654 */
hdlcdev_rx(struct slgt_info * info,char * buf,int size)1655 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1656 {
1657 struct sk_buff *skb = dev_alloc_skb(size);
1658 struct net_device *dev = info->netdev;
1659
1660 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1661
1662 if (skb == NULL) {
1663 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1664 dev->stats.rx_dropped++;
1665 return;
1666 }
1667
1668 skb_put_data(skb, buf, size);
1669
1670 skb->protocol = hdlc_type_trans(skb, dev);
1671
1672 dev->stats.rx_packets++;
1673 dev->stats.rx_bytes += size;
1674
1675 netif_rx(skb);
1676 }
1677
1678 static const struct net_device_ops hdlcdev_ops = {
1679 .ndo_open = hdlcdev_open,
1680 .ndo_stop = hdlcdev_close,
1681 .ndo_start_xmit = hdlc_start_xmit,
1682 .ndo_siocwandev = hdlcdev_ioctl,
1683 .ndo_tx_timeout = hdlcdev_tx_timeout,
1684 };
1685
1686 /**
1687 * hdlcdev_init - called by device driver when adding device instance
1688 * @info: pointer to device instance information
1689 *
1690 * Do generic HDLC initialization.
1691 *
1692 * Return: 0 if success, otherwise error code
1693 */
hdlcdev_init(struct slgt_info * info)1694 static int hdlcdev_init(struct slgt_info *info)
1695 {
1696 int rc;
1697 struct net_device *dev;
1698 hdlc_device *hdlc;
1699
1700 /* allocate and initialize network and HDLC layer objects */
1701
1702 dev = alloc_hdlcdev(info);
1703 if (!dev) {
1704 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1705 return -ENOMEM;
1706 }
1707
1708 /* for network layer reporting purposes only */
1709 dev->mem_start = info->phys_reg_addr;
1710 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1711 dev->irq = info->irq_level;
1712
1713 /* network layer callbacks and settings */
1714 dev->netdev_ops = &hdlcdev_ops;
1715 dev->watchdog_timeo = 10 * HZ;
1716 dev->tx_queue_len = 50;
1717
1718 /* generic HDLC layer callbacks and settings */
1719 hdlc = dev_to_hdlc(dev);
1720 hdlc->attach = hdlcdev_attach;
1721 hdlc->xmit = hdlcdev_xmit;
1722
1723 /* register objects with HDLC layer */
1724 rc = register_hdlc_device(dev);
1725 if (rc) {
1726 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1727 free_netdev(dev);
1728 return rc;
1729 }
1730
1731 info->netdev = dev;
1732 return 0;
1733 }
1734
1735 /**
1736 * hdlcdev_exit - called by device driver when removing device instance
1737 * @info: pointer to device instance information
1738 *
1739 * Do generic HDLC cleanup.
1740 */
hdlcdev_exit(struct slgt_info * info)1741 static void hdlcdev_exit(struct slgt_info *info)
1742 {
1743 if (!info->netdev)
1744 return;
1745 unregister_hdlc_device(info->netdev);
1746 free_netdev(info->netdev);
1747 info->netdev = NULL;
1748 }
1749
1750 #endif /* ifdef CONFIG_HDLC */
1751
1752 /*
1753 * get async data from rx DMA buffers
1754 */
rx_async(struct slgt_info * info)1755 static void rx_async(struct slgt_info *info)
1756 {
1757 struct mgsl_icount *icount = &info->icount;
1758 unsigned int start, end;
1759 unsigned char *p;
1760 unsigned char status;
1761 struct slgt_desc *bufs = info->rbufs;
1762 int i, count;
1763 int chars = 0;
1764 int stat;
1765 unsigned char ch;
1766
1767 start = end = info->rbuf_current;
1768
1769 while(desc_complete(bufs[end])) {
1770 count = desc_count(bufs[end]) - info->rbuf_index;
1771 p = bufs[end].buf + info->rbuf_index;
1772
1773 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1774 DBGDATA(info, p, count, "rx");
1775
1776 for(i=0 ; i < count; i+=2, p+=2) {
1777 ch = *p;
1778 icount->rx++;
1779
1780 stat = 0;
1781
1782 status = *(p + 1) & (BIT1 + BIT0);
1783 if (status) {
1784 if (status & BIT1)
1785 icount->parity++;
1786 else if (status & BIT0)
1787 icount->frame++;
1788 /* discard char if tty control flags say so */
1789 if (status & info->ignore_status_mask)
1790 continue;
1791 if (status & BIT1)
1792 stat = TTY_PARITY;
1793 else if (status & BIT0)
1794 stat = TTY_FRAME;
1795 }
1796 tty_insert_flip_char(&info->port, ch, stat);
1797 chars++;
1798 }
1799
1800 if (i < count) {
1801 /* receive buffer not completed */
1802 info->rbuf_index += i;
1803 mod_timer(&info->rx_timer, jiffies + 1);
1804 break;
1805 }
1806
1807 info->rbuf_index = 0;
1808 free_rbufs(info, end, end);
1809
1810 if (++end == info->rbuf_count)
1811 end = 0;
1812
1813 /* if entire list searched then no frame available */
1814 if (end == start)
1815 break;
1816 }
1817
1818 if (chars)
1819 tty_flip_buffer_push(&info->port);
1820 }
1821
1822 /*
1823 * return next bottom half action to perform
1824 */
bh_action(struct slgt_info * info)1825 static int bh_action(struct slgt_info *info)
1826 {
1827 unsigned long flags;
1828 int rc;
1829
1830 spin_lock_irqsave(&info->lock,flags);
1831
1832 if (info->pending_bh & BH_RECEIVE) {
1833 info->pending_bh &= ~BH_RECEIVE;
1834 rc = BH_RECEIVE;
1835 } else if (info->pending_bh & BH_TRANSMIT) {
1836 info->pending_bh &= ~BH_TRANSMIT;
1837 rc = BH_TRANSMIT;
1838 } else if (info->pending_bh & BH_STATUS) {
1839 info->pending_bh &= ~BH_STATUS;
1840 rc = BH_STATUS;
1841 } else {
1842 /* Mark BH routine as complete */
1843 info->bh_running = false;
1844 info->bh_requested = false;
1845 rc = 0;
1846 }
1847
1848 spin_unlock_irqrestore(&info->lock,flags);
1849
1850 return rc;
1851 }
1852
1853 /*
1854 * perform bottom half processing
1855 */
bh_handler(struct work_struct * work)1856 static void bh_handler(struct work_struct *work)
1857 {
1858 struct slgt_info *info = container_of(work, struct slgt_info, task);
1859 int action;
1860
1861 info->bh_running = true;
1862
1863 while((action = bh_action(info))) {
1864 switch (action) {
1865 case BH_RECEIVE:
1866 DBGBH(("%s bh receive\n", info->device_name));
1867 switch(info->params.mode) {
1868 case MGSL_MODE_ASYNC:
1869 rx_async(info);
1870 break;
1871 case MGSL_MODE_HDLC:
1872 while(rx_get_frame(info));
1873 break;
1874 case MGSL_MODE_RAW:
1875 case MGSL_MODE_MONOSYNC:
1876 case MGSL_MODE_BISYNC:
1877 case MGSL_MODE_XSYNC:
1878 while(rx_get_buf(info));
1879 break;
1880 }
1881 /* restart receiver if rx DMA buffers exhausted */
1882 if (info->rx_restart)
1883 rx_start(info);
1884 break;
1885 case BH_TRANSMIT:
1886 bh_transmit(info);
1887 break;
1888 case BH_STATUS:
1889 DBGBH(("%s bh status\n", info->device_name));
1890 info->ri_chkcount = 0;
1891 info->dsr_chkcount = 0;
1892 info->dcd_chkcount = 0;
1893 info->cts_chkcount = 0;
1894 break;
1895 default:
1896 DBGBH(("%s unknown action\n", info->device_name));
1897 break;
1898 }
1899 }
1900 DBGBH(("%s bh_handler exit\n", info->device_name));
1901 }
1902
bh_transmit(struct slgt_info * info)1903 static void bh_transmit(struct slgt_info *info)
1904 {
1905 struct tty_struct *tty = info->port.tty;
1906
1907 DBGBH(("%s bh_transmit\n", info->device_name));
1908 if (tty)
1909 tty_wakeup(tty);
1910 }
1911
dsr_change(struct slgt_info * info,unsigned short status)1912 static void dsr_change(struct slgt_info *info, unsigned short status)
1913 {
1914 if (status & BIT3) {
1915 info->signals |= SerialSignal_DSR;
1916 info->input_signal_events.dsr_up++;
1917 } else {
1918 info->signals &= ~SerialSignal_DSR;
1919 info->input_signal_events.dsr_down++;
1920 }
1921 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1922 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1923 slgt_irq_off(info, IRQ_DSR);
1924 return;
1925 }
1926 info->icount.dsr++;
1927 wake_up_interruptible(&info->status_event_wait_q);
1928 wake_up_interruptible(&info->event_wait_q);
1929 info->pending_bh |= BH_STATUS;
1930 }
1931
cts_change(struct slgt_info * info,unsigned short status)1932 static void cts_change(struct slgt_info *info, unsigned short status)
1933 {
1934 if (status & BIT2) {
1935 info->signals |= SerialSignal_CTS;
1936 info->input_signal_events.cts_up++;
1937 } else {
1938 info->signals &= ~SerialSignal_CTS;
1939 info->input_signal_events.cts_down++;
1940 }
1941 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1942 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1943 slgt_irq_off(info, IRQ_CTS);
1944 return;
1945 }
1946 info->icount.cts++;
1947 wake_up_interruptible(&info->status_event_wait_q);
1948 wake_up_interruptible(&info->event_wait_q);
1949 info->pending_bh |= BH_STATUS;
1950
1951 if (tty_port_cts_enabled(&info->port)) {
1952 if (info->port.tty) {
1953 if (info->port.tty->hw_stopped) {
1954 if (info->signals & SerialSignal_CTS) {
1955 info->port.tty->hw_stopped = 0;
1956 info->pending_bh |= BH_TRANSMIT;
1957 return;
1958 }
1959 } else {
1960 if (!(info->signals & SerialSignal_CTS))
1961 info->port.tty->hw_stopped = 1;
1962 }
1963 }
1964 }
1965 }
1966
dcd_change(struct slgt_info * info,unsigned short status)1967 static void dcd_change(struct slgt_info *info, unsigned short status)
1968 {
1969 if (status & BIT1) {
1970 info->signals |= SerialSignal_DCD;
1971 info->input_signal_events.dcd_up++;
1972 } else {
1973 info->signals &= ~SerialSignal_DCD;
1974 info->input_signal_events.dcd_down++;
1975 }
1976 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1977 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1978 slgt_irq_off(info, IRQ_DCD);
1979 return;
1980 }
1981 info->icount.dcd++;
1982 #if SYNCLINK_GENERIC_HDLC
1983 if (info->netcount) {
1984 if (info->signals & SerialSignal_DCD)
1985 netif_carrier_on(info->netdev);
1986 else
1987 netif_carrier_off(info->netdev);
1988 }
1989 #endif
1990 wake_up_interruptible(&info->status_event_wait_q);
1991 wake_up_interruptible(&info->event_wait_q);
1992 info->pending_bh |= BH_STATUS;
1993
1994 if (tty_port_check_carrier(&info->port)) {
1995 if (info->signals & SerialSignal_DCD)
1996 wake_up_interruptible(&info->port.open_wait);
1997 else {
1998 if (info->port.tty)
1999 tty_hangup(info->port.tty);
2000 }
2001 }
2002 }
2003
ri_change(struct slgt_info * info,unsigned short status)2004 static void ri_change(struct slgt_info *info, unsigned short status)
2005 {
2006 if (status & BIT0) {
2007 info->signals |= SerialSignal_RI;
2008 info->input_signal_events.ri_up++;
2009 } else {
2010 info->signals &= ~SerialSignal_RI;
2011 info->input_signal_events.ri_down++;
2012 }
2013 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2014 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2015 slgt_irq_off(info, IRQ_RI);
2016 return;
2017 }
2018 info->icount.rng++;
2019 wake_up_interruptible(&info->status_event_wait_q);
2020 wake_up_interruptible(&info->event_wait_q);
2021 info->pending_bh |= BH_STATUS;
2022 }
2023
isr_rxdata(struct slgt_info * info)2024 static void isr_rxdata(struct slgt_info *info)
2025 {
2026 unsigned int count = info->rbuf_fill_count;
2027 unsigned int i = info->rbuf_fill_index;
2028 unsigned short reg;
2029
2030 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2031 reg = rd_reg16(info, RDR);
2032 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2033 if (desc_complete(info->rbufs[i])) {
2034 /* all buffers full */
2035 rx_stop(info);
2036 info->rx_restart = true;
2037 continue;
2038 }
2039 info->rbufs[i].buf[count++] = (unsigned char)reg;
2040 /* async mode saves status byte to buffer for each data byte */
2041 if (info->params.mode == MGSL_MODE_ASYNC)
2042 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2043 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2044 /* buffer full or end of frame */
2045 set_desc_count(info->rbufs[i], count);
2046 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2047 info->rbuf_fill_count = count = 0;
2048 if (++i == info->rbuf_count)
2049 i = 0;
2050 info->pending_bh |= BH_RECEIVE;
2051 }
2052 }
2053
2054 info->rbuf_fill_index = i;
2055 info->rbuf_fill_count = count;
2056 }
2057
isr_serial(struct slgt_info * info)2058 static void isr_serial(struct slgt_info *info)
2059 {
2060 unsigned short status = rd_reg16(info, SSR);
2061
2062 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2063
2064 wr_reg16(info, SSR, status); /* clear pending */
2065
2066 info->irq_occurred = true;
2067
2068 if (info->params.mode == MGSL_MODE_ASYNC) {
2069 if (status & IRQ_TXIDLE) {
2070 if (info->tx_active)
2071 isr_txeom(info, status);
2072 }
2073 if (info->rx_pio && (status & IRQ_RXDATA))
2074 isr_rxdata(info);
2075 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2076 info->icount.brk++;
2077 /* process break detection if tty control allows */
2078 if (info->port.tty) {
2079 if (!(status & info->ignore_status_mask)) {
2080 if (info->read_status_mask & MASK_BREAK) {
2081 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2082 if (info->port.flags & ASYNC_SAK)
2083 do_SAK(info->port.tty);
2084 }
2085 }
2086 }
2087 }
2088 } else {
2089 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2090 isr_txeom(info, status);
2091 if (info->rx_pio && (status & IRQ_RXDATA))
2092 isr_rxdata(info);
2093 if (status & IRQ_RXIDLE) {
2094 if (status & RXIDLE)
2095 info->icount.rxidle++;
2096 else
2097 info->icount.exithunt++;
2098 wake_up_interruptible(&info->event_wait_q);
2099 }
2100
2101 if (status & IRQ_RXOVER)
2102 rx_start(info);
2103 }
2104
2105 if (status & IRQ_DSR)
2106 dsr_change(info, status);
2107 if (status & IRQ_CTS)
2108 cts_change(info, status);
2109 if (status & IRQ_DCD)
2110 dcd_change(info, status);
2111 if (status & IRQ_RI)
2112 ri_change(info, status);
2113 }
2114
isr_rdma(struct slgt_info * info)2115 static void isr_rdma(struct slgt_info *info)
2116 {
2117 unsigned int status = rd_reg32(info, RDCSR);
2118
2119 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2120
2121 /* RDCSR (rx DMA control/status)
2122 *
2123 * 31..07 reserved
2124 * 06 save status byte to DMA buffer
2125 * 05 error
2126 * 04 eol (end of list)
2127 * 03 eob (end of buffer)
2128 * 02 IRQ enable
2129 * 01 reset
2130 * 00 enable
2131 */
2132 wr_reg32(info, RDCSR, status); /* clear pending */
2133
2134 if (status & (BIT5 + BIT4)) {
2135 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2136 info->rx_restart = true;
2137 }
2138 info->pending_bh |= BH_RECEIVE;
2139 }
2140
isr_tdma(struct slgt_info * info)2141 static void isr_tdma(struct slgt_info *info)
2142 {
2143 unsigned int status = rd_reg32(info, TDCSR);
2144
2145 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2146
2147 /* TDCSR (tx DMA control/status)
2148 *
2149 * 31..06 reserved
2150 * 05 error
2151 * 04 eol (end of list)
2152 * 03 eob (end of buffer)
2153 * 02 IRQ enable
2154 * 01 reset
2155 * 00 enable
2156 */
2157 wr_reg32(info, TDCSR, status); /* clear pending */
2158
2159 if (status & (BIT5 + BIT4 + BIT3)) {
2160 // another transmit buffer has completed
2161 // run bottom half to get more send data from user
2162 info->pending_bh |= BH_TRANSMIT;
2163 }
2164 }
2165
2166 /*
2167 * return true if there are unsent tx DMA buffers, otherwise false
2168 *
2169 * if there are unsent buffers then info->tbuf_start
2170 * is set to index of first unsent buffer
2171 */
unsent_tbufs(struct slgt_info * info)2172 static bool unsent_tbufs(struct slgt_info *info)
2173 {
2174 unsigned int i = info->tbuf_current;
2175 bool rc = false;
2176
2177 /*
2178 * search backwards from last loaded buffer (precedes tbuf_current)
2179 * for first unsent buffer (desc_count > 0)
2180 */
2181
2182 do {
2183 if (i)
2184 i--;
2185 else
2186 i = info->tbuf_count - 1;
2187 if (!desc_count(info->tbufs[i]))
2188 break;
2189 info->tbuf_start = i;
2190 rc = true;
2191 } while (i != info->tbuf_current);
2192
2193 return rc;
2194 }
2195
isr_txeom(struct slgt_info * info,unsigned short status)2196 static void isr_txeom(struct slgt_info *info, unsigned short status)
2197 {
2198 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2199
2200 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2201 tdma_reset(info);
2202 if (status & IRQ_TXUNDER) {
2203 unsigned short val = rd_reg16(info, TCR);
2204 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2205 wr_reg16(info, TCR, val); /* clear reset bit */
2206 }
2207
2208 if (info->tx_active) {
2209 if (info->params.mode != MGSL_MODE_ASYNC) {
2210 if (status & IRQ_TXUNDER)
2211 info->icount.txunder++;
2212 else if (status & IRQ_TXIDLE)
2213 info->icount.txok++;
2214 }
2215
2216 if (unsent_tbufs(info)) {
2217 tx_start(info);
2218 update_tx_timer(info);
2219 return;
2220 }
2221 info->tx_active = false;
2222
2223 del_timer(&info->tx_timer);
2224
2225 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2226 info->signals &= ~SerialSignal_RTS;
2227 info->drop_rts_on_tx_done = false;
2228 set_gtsignals(info);
2229 }
2230
2231 #if SYNCLINK_GENERIC_HDLC
2232 if (info->netcount)
2233 hdlcdev_tx_done(info);
2234 else
2235 #endif
2236 {
2237 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2238 tx_stop(info);
2239 return;
2240 }
2241 info->pending_bh |= BH_TRANSMIT;
2242 }
2243 }
2244 }
2245
isr_gpio(struct slgt_info * info,unsigned int changed,unsigned int state)2246 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2247 {
2248 struct cond_wait *w, *prev;
2249
2250 /* wake processes waiting for specific transitions */
2251 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2252 if (w->data & changed) {
2253 w->data = state;
2254 wake_up_interruptible(&w->q);
2255 if (prev != NULL)
2256 prev->next = w->next;
2257 else
2258 info->gpio_wait_q = w->next;
2259 } else
2260 prev = w;
2261 }
2262 }
2263
2264 /* interrupt service routine
2265 *
2266 * irq interrupt number
2267 * dev_id device ID supplied during interrupt registration
2268 */
slgt_interrupt(int dummy,void * dev_id)2269 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2270 {
2271 struct slgt_info *info = dev_id;
2272 unsigned int gsr;
2273 unsigned int i;
2274
2275 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2276
2277 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2278 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2279 info->irq_occurred = true;
2280 for(i=0; i < info->port_count ; i++) {
2281 if (info->port_array[i] == NULL)
2282 continue;
2283 spin_lock(&info->port_array[i]->lock);
2284 if (gsr & (BIT8 << i))
2285 isr_serial(info->port_array[i]);
2286 if (gsr & (BIT16 << (i*2)))
2287 isr_rdma(info->port_array[i]);
2288 if (gsr & (BIT17 << (i*2)))
2289 isr_tdma(info->port_array[i]);
2290 spin_unlock(&info->port_array[i]->lock);
2291 }
2292 }
2293
2294 if (info->gpio_present) {
2295 unsigned int state;
2296 unsigned int changed;
2297 spin_lock(&info->lock);
2298 while ((changed = rd_reg32(info, IOSR)) != 0) {
2299 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2300 /* read latched state of GPIO signals */
2301 state = rd_reg32(info, IOVR);
2302 /* clear pending GPIO interrupt bits */
2303 wr_reg32(info, IOSR, changed);
2304 for (i=0 ; i < info->port_count ; i++) {
2305 if (info->port_array[i] != NULL)
2306 isr_gpio(info->port_array[i], changed, state);
2307 }
2308 }
2309 spin_unlock(&info->lock);
2310 }
2311
2312 for(i=0; i < info->port_count ; i++) {
2313 struct slgt_info *port = info->port_array[i];
2314 if (port == NULL)
2315 continue;
2316 spin_lock(&port->lock);
2317 if ((port->port.count || port->netcount) &&
2318 port->pending_bh && !port->bh_running &&
2319 !port->bh_requested) {
2320 DBGISR(("%s bh queued\n", port->device_name));
2321 schedule_work(&port->task);
2322 port->bh_requested = true;
2323 }
2324 spin_unlock(&port->lock);
2325 }
2326
2327 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2328 return IRQ_HANDLED;
2329 }
2330
startup(struct slgt_info * info)2331 static int startup(struct slgt_info *info)
2332 {
2333 DBGINFO(("%s startup\n", info->device_name));
2334
2335 if (tty_port_initialized(&info->port))
2336 return 0;
2337
2338 if (!info->tx_buf) {
2339 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2340 if (!info->tx_buf) {
2341 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2342 return -ENOMEM;
2343 }
2344 }
2345
2346 info->pending_bh = 0;
2347
2348 memset(&info->icount, 0, sizeof(info->icount));
2349
2350 /* program hardware for current parameters */
2351 change_params(info);
2352
2353 if (info->port.tty)
2354 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2355
2356 tty_port_set_initialized(&info->port, 1);
2357
2358 return 0;
2359 }
2360
2361 /*
2362 * called by close() and hangup() to shutdown hardware
2363 */
shutdown(struct slgt_info * info)2364 static void shutdown(struct slgt_info *info)
2365 {
2366 unsigned long flags;
2367
2368 if (!tty_port_initialized(&info->port))
2369 return;
2370
2371 DBGINFO(("%s shutdown\n", info->device_name));
2372
2373 /* clear status wait queue because status changes */
2374 /* can't happen after shutting down the hardware */
2375 wake_up_interruptible(&info->status_event_wait_q);
2376 wake_up_interruptible(&info->event_wait_q);
2377
2378 del_timer_sync(&info->tx_timer);
2379 del_timer_sync(&info->rx_timer);
2380
2381 kfree(info->tx_buf);
2382 info->tx_buf = NULL;
2383
2384 spin_lock_irqsave(&info->lock,flags);
2385
2386 tx_stop(info);
2387 rx_stop(info);
2388
2389 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2390
2391 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2392 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2393 set_gtsignals(info);
2394 }
2395
2396 flush_cond_wait(&info->gpio_wait_q);
2397
2398 spin_unlock_irqrestore(&info->lock,flags);
2399
2400 if (info->port.tty)
2401 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2402
2403 tty_port_set_initialized(&info->port, 0);
2404 }
2405
program_hw(struct slgt_info * info)2406 static void program_hw(struct slgt_info *info)
2407 {
2408 unsigned long flags;
2409
2410 spin_lock_irqsave(&info->lock,flags);
2411
2412 rx_stop(info);
2413 tx_stop(info);
2414
2415 if (info->params.mode != MGSL_MODE_ASYNC ||
2416 info->netcount)
2417 sync_mode(info);
2418 else
2419 async_mode(info);
2420
2421 set_gtsignals(info);
2422
2423 info->dcd_chkcount = 0;
2424 info->cts_chkcount = 0;
2425 info->ri_chkcount = 0;
2426 info->dsr_chkcount = 0;
2427
2428 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2429 get_gtsignals(info);
2430
2431 if (info->netcount ||
2432 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2433 rx_start(info);
2434
2435 spin_unlock_irqrestore(&info->lock,flags);
2436 }
2437
2438 /*
2439 * reconfigure adapter based on new parameters
2440 */
change_params(struct slgt_info * info)2441 static void change_params(struct slgt_info *info)
2442 {
2443 unsigned cflag;
2444 int bits_per_char;
2445
2446 if (!info->port.tty)
2447 return;
2448 DBGINFO(("%s change_params\n", info->device_name));
2449
2450 cflag = info->port.tty->termios.c_cflag;
2451
2452 /* if B0 rate (hangup) specified then negate RTS and DTR */
2453 /* otherwise assert RTS and DTR */
2454 if (cflag & CBAUD)
2455 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2456 else
2457 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2458
2459 /* byte size and parity */
2460
2461 info->params.data_bits = tty_get_char_size(cflag);
2462 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2463
2464 if (cflag & PARENB)
2465 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2466 else
2467 info->params.parity = ASYNC_PARITY_NONE;
2468
2469 /* calculate number of jiffies to transmit a full
2470 * FIFO (32 bytes) at specified data rate
2471 */
2472 bits_per_char = info->params.data_bits +
2473 info->params.stop_bits + 1;
2474
2475 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2476
2477 if (info->params.data_rate) {
2478 info->timeout = (32*HZ*bits_per_char) /
2479 info->params.data_rate;
2480 }
2481 info->timeout += HZ/50; /* Add .02 seconds of slop */
2482
2483 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2484 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2485
2486 /* process tty input control flags */
2487
2488 info->read_status_mask = IRQ_RXOVER;
2489 if (I_INPCK(info->port.tty))
2490 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2491 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2492 info->read_status_mask |= MASK_BREAK;
2493 if (I_IGNPAR(info->port.tty))
2494 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2495 if (I_IGNBRK(info->port.tty)) {
2496 info->ignore_status_mask |= MASK_BREAK;
2497 /* If ignoring parity and break indicators, ignore
2498 * overruns too. (For real raw support).
2499 */
2500 if (I_IGNPAR(info->port.tty))
2501 info->ignore_status_mask |= MASK_OVERRUN;
2502 }
2503
2504 program_hw(info);
2505 }
2506
get_stats(struct slgt_info * info,struct mgsl_icount __user * user_icount)2507 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2508 {
2509 DBGINFO(("%s get_stats\n", info->device_name));
2510 if (!user_icount) {
2511 memset(&info->icount, 0, sizeof(info->icount));
2512 } else {
2513 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2514 return -EFAULT;
2515 }
2516 return 0;
2517 }
2518
get_params(struct slgt_info * info,MGSL_PARAMS __user * user_params)2519 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2520 {
2521 DBGINFO(("%s get_params\n", info->device_name));
2522 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2523 return -EFAULT;
2524 return 0;
2525 }
2526
set_params(struct slgt_info * info,MGSL_PARAMS __user * new_params)2527 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2528 {
2529 unsigned long flags;
2530 MGSL_PARAMS tmp_params;
2531
2532 DBGINFO(("%s set_params\n", info->device_name));
2533 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2534 return -EFAULT;
2535
2536 spin_lock_irqsave(&info->lock, flags);
2537 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2538 info->base_clock = tmp_params.clock_speed;
2539 else
2540 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2541 spin_unlock_irqrestore(&info->lock, flags);
2542
2543 program_hw(info);
2544
2545 return 0;
2546 }
2547
get_txidle(struct slgt_info * info,int __user * idle_mode)2548 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2549 {
2550 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2551 if (put_user(info->idle_mode, idle_mode))
2552 return -EFAULT;
2553 return 0;
2554 }
2555
set_txidle(struct slgt_info * info,int idle_mode)2556 static int set_txidle(struct slgt_info *info, int idle_mode)
2557 {
2558 unsigned long flags;
2559 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2560 spin_lock_irqsave(&info->lock,flags);
2561 info->idle_mode = idle_mode;
2562 if (info->params.mode != MGSL_MODE_ASYNC)
2563 tx_set_idle(info);
2564 spin_unlock_irqrestore(&info->lock,flags);
2565 return 0;
2566 }
2567
tx_enable(struct slgt_info * info,int enable)2568 static int tx_enable(struct slgt_info *info, int enable)
2569 {
2570 unsigned long flags;
2571 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2572 spin_lock_irqsave(&info->lock,flags);
2573 if (enable) {
2574 if (!info->tx_enabled)
2575 tx_start(info);
2576 } else {
2577 if (info->tx_enabled)
2578 tx_stop(info);
2579 }
2580 spin_unlock_irqrestore(&info->lock,flags);
2581 return 0;
2582 }
2583
2584 /*
2585 * abort transmit HDLC frame
2586 */
tx_abort(struct slgt_info * info)2587 static int tx_abort(struct slgt_info *info)
2588 {
2589 unsigned long flags;
2590 DBGINFO(("%s tx_abort\n", info->device_name));
2591 spin_lock_irqsave(&info->lock,flags);
2592 tdma_reset(info);
2593 spin_unlock_irqrestore(&info->lock,flags);
2594 return 0;
2595 }
2596
rx_enable(struct slgt_info * info,int enable)2597 static int rx_enable(struct slgt_info *info, int enable)
2598 {
2599 unsigned long flags;
2600 unsigned int rbuf_fill_level;
2601 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2602 spin_lock_irqsave(&info->lock,flags);
2603 /*
2604 * enable[31..16] = receive DMA buffer fill level
2605 * 0 = noop (leave fill level unchanged)
2606 * fill level must be multiple of 4 and <= buffer size
2607 */
2608 rbuf_fill_level = ((unsigned int)enable) >> 16;
2609 if (rbuf_fill_level) {
2610 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2611 spin_unlock_irqrestore(&info->lock, flags);
2612 return -EINVAL;
2613 }
2614 info->rbuf_fill_level = rbuf_fill_level;
2615 if (rbuf_fill_level < 128)
2616 info->rx_pio = 1; /* PIO mode */
2617 else
2618 info->rx_pio = 0; /* DMA mode */
2619 rx_stop(info); /* restart receiver to use new fill level */
2620 }
2621
2622 /*
2623 * enable[1..0] = receiver enable command
2624 * 0 = disable
2625 * 1 = enable
2626 * 2 = enable or force hunt mode if already enabled
2627 */
2628 enable &= 3;
2629 if (enable) {
2630 if (!info->rx_enabled)
2631 rx_start(info);
2632 else if (enable == 2) {
2633 /* force hunt mode (write 1 to RCR[3]) */
2634 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2635 }
2636 } else {
2637 if (info->rx_enabled)
2638 rx_stop(info);
2639 }
2640 spin_unlock_irqrestore(&info->lock,flags);
2641 return 0;
2642 }
2643
2644 /*
2645 * wait for specified event to occur
2646 */
wait_mgsl_event(struct slgt_info * info,int __user * mask_ptr)2647 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2648 {
2649 unsigned long flags;
2650 int s;
2651 int rc=0;
2652 struct mgsl_icount cprev, cnow;
2653 int events;
2654 int mask;
2655 struct _input_signal_events oldsigs, newsigs;
2656 DECLARE_WAITQUEUE(wait, current);
2657
2658 if (get_user(mask, mask_ptr))
2659 return -EFAULT;
2660
2661 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2662
2663 spin_lock_irqsave(&info->lock,flags);
2664
2665 /* return immediately if state matches requested events */
2666 get_gtsignals(info);
2667 s = info->signals;
2668
2669 events = mask &
2670 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2671 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2672 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2673 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2674 if (events) {
2675 spin_unlock_irqrestore(&info->lock,flags);
2676 goto exit;
2677 }
2678
2679 /* save current irq counts */
2680 cprev = info->icount;
2681 oldsigs = info->input_signal_events;
2682
2683 /* enable hunt and idle irqs if needed */
2684 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2685 unsigned short val = rd_reg16(info, SCR);
2686 if (!(val & IRQ_RXIDLE))
2687 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2688 }
2689
2690 set_current_state(TASK_INTERRUPTIBLE);
2691 add_wait_queue(&info->event_wait_q, &wait);
2692
2693 spin_unlock_irqrestore(&info->lock,flags);
2694
2695 for(;;) {
2696 schedule();
2697 if (signal_pending(current)) {
2698 rc = -ERESTARTSYS;
2699 break;
2700 }
2701
2702 /* get current irq counts */
2703 spin_lock_irqsave(&info->lock,flags);
2704 cnow = info->icount;
2705 newsigs = info->input_signal_events;
2706 set_current_state(TASK_INTERRUPTIBLE);
2707 spin_unlock_irqrestore(&info->lock,flags);
2708
2709 /* if no change, wait aborted for some reason */
2710 if (newsigs.dsr_up == oldsigs.dsr_up &&
2711 newsigs.dsr_down == oldsigs.dsr_down &&
2712 newsigs.dcd_up == oldsigs.dcd_up &&
2713 newsigs.dcd_down == oldsigs.dcd_down &&
2714 newsigs.cts_up == oldsigs.cts_up &&
2715 newsigs.cts_down == oldsigs.cts_down &&
2716 newsigs.ri_up == oldsigs.ri_up &&
2717 newsigs.ri_down == oldsigs.ri_down &&
2718 cnow.exithunt == cprev.exithunt &&
2719 cnow.rxidle == cprev.rxidle) {
2720 rc = -EIO;
2721 break;
2722 }
2723
2724 events = mask &
2725 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2726 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2727 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2728 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2729 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2730 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2731 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2732 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2733 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2734 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2735 if (events)
2736 break;
2737
2738 cprev = cnow;
2739 oldsigs = newsigs;
2740 }
2741
2742 remove_wait_queue(&info->event_wait_q, &wait);
2743 set_current_state(TASK_RUNNING);
2744
2745
2746 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2747 spin_lock_irqsave(&info->lock,flags);
2748 if (!waitqueue_active(&info->event_wait_q)) {
2749 /* disable enable exit hunt mode/idle rcvd IRQs */
2750 wr_reg16(info, SCR,
2751 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2752 }
2753 spin_unlock_irqrestore(&info->lock,flags);
2754 }
2755 exit:
2756 if (rc == 0)
2757 rc = put_user(events, mask_ptr);
2758 return rc;
2759 }
2760
get_interface(struct slgt_info * info,int __user * if_mode)2761 static int get_interface(struct slgt_info *info, int __user *if_mode)
2762 {
2763 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2764 if (put_user(info->if_mode, if_mode))
2765 return -EFAULT;
2766 return 0;
2767 }
2768
set_interface(struct slgt_info * info,int if_mode)2769 static int set_interface(struct slgt_info *info, int if_mode)
2770 {
2771 unsigned long flags;
2772 unsigned short val;
2773
2774 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2775 spin_lock_irqsave(&info->lock,flags);
2776 info->if_mode = if_mode;
2777
2778 msc_set_vcr(info);
2779
2780 /* TCR (tx control) 07 1=RTS driver control */
2781 val = rd_reg16(info, TCR);
2782 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2783 val |= BIT7;
2784 else
2785 val &= ~BIT7;
2786 wr_reg16(info, TCR, val);
2787
2788 spin_unlock_irqrestore(&info->lock,flags);
2789 return 0;
2790 }
2791
get_xsync(struct slgt_info * info,int __user * xsync)2792 static int get_xsync(struct slgt_info *info, int __user *xsync)
2793 {
2794 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2795 if (put_user(info->xsync, xsync))
2796 return -EFAULT;
2797 return 0;
2798 }
2799
2800 /*
2801 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2802 *
2803 * sync pattern is contained in least significant bytes of value
2804 * most significant byte of sync pattern is oldest (1st sent/detected)
2805 */
set_xsync(struct slgt_info * info,int xsync)2806 static int set_xsync(struct slgt_info *info, int xsync)
2807 {
2808 unsigned long flags;
2809
2810 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2811 spin_lock_irqsave(&info->lock, flags);
2812 info->xsync = xsync;
2813 wr_reg32(info, XSR, xsync);
2814 spin_unlock_irqrestore(&info->lock, flags);
2815 return 0;
2816 }
2817
get_xctrl(struct slgt_info * info,int __user * xctrl)2818 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2819 {
2820 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2821 if (put_user(info->xctrl, xctrl))
2822 return -EFAULT;
2823 return 0;
2824 }
2825
2826 /*
2827 * set extended control options
2828 *
2829 * xctrl[31:19] reserved, must be zero
2830 * xctrl[18:17] extended sync pattern length in bytes
2831 * 00 = 1 byte in xsr[7:0]
2832 * 01 = 2 bytes in xsr[15:0]
2833 * 10 = 3 bytes in xsr[23:0]
2834 * 11 = 4 bytes in xsr[31:0]
2835 * xctrl[16] 1 = enable terminal count, 0=disabled
2836 * xctrl[15:0] receive terminal count for fixed length packets
2837 * value is count minus one (0 = 1 byte packet)
2838 * when terminal count is reached, receiver
2839 * automatically returns to hunt mode and receive
2840 * FIFO contents are flushed to DMA buffers with
2841 * end of frame (EOF) status
2842 */
set_xctrl(struct slgt_info * info,int xctrl)2843 static int set_xctrl(struct slgt_info *info, int xctrl)
2844 {
2845 unsigned long flags;
2846
2847 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2848 spin_lock_irqsave(&info->lock, flags);
2849 info->xctrl = xctrl;
2850 wr_reg32(info, XCR, xctrl);
2851 spin_unlock_irqrestore(&info->lock, flags);
2852 return 0;
2853 }
2854
2855 /*
2856 * set general purpose IO pin state and direction
2857 *
2858 * user_gpio fields:
2859 * state each bit indicates a pin state
2860 * smask set bit indicates pin state to set
2861 * dir each bit indicates a pin direction (0=input, 1=output)
2862 * dmask set bit indicates pin direction to set
2863 */
set_gpio(struct slgt_info * info,struct gpio_desc __user * user_gpio)2864 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2865 {
2866 unsigned long flags;
2867 struct gpio_desc gpio;
2868 __u32 data;
2869
2870 if (!info->gpio_present)
2871 return -EINVAL;
2872 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2873 return -EFAULT;
2874 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2875 info->device_name, gpio.state, gpio.smask,
2876 gpio.dir, gpio.dmask));
2877
2878 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2879 if (gpio.dmask) {
2880 data = rd_reg32(info, IODR);
2881 data |= gpio.dmask & gpio.dir;
2882 data &= ~(gpio.dmask & ~gpio.dir);
2883 wr_reg32(info, IODR, data);
2884 }
2885 if (gpio.smask) {
2886 data = rd_reg32(info, IOVR);
2887 data |= gpio.smask & gpio.state;
2888 data &= ~(gpio.smask & ~gpio.state);
2889 wr_reg32(info, IOVR, data);
2890 }
2891 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2892
2893 return 0;
2894 }
2895
2896 /*
2897 * get general purpose IO pin state and direction
2898 */
get_gpio(struct slgt_info * info,struct gpio_desc __user * user_gpio)2899 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2900 {
2901 struct gpio_desc gpio;
2902 if (!info->gpio_present)
2903 return -EINVAL;
2904 gpio.state = rd_reg32(info, IOVR);
2905 gpio.smask = 0xffffffff;
2906 gpio.dir = rd_reg32(info, IODR);
2907 gpio.dmask = 0xffffffff;
2908 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2909 return -EFAULT;
2910 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2911 info->device_name, gpio.state, gpio.dir));
2912 return 0;
2913 }
2914
2915 /*
2916 * conditional wait facility
2917 */
init_cond_wait(struct cond_wait * w,unsigned int data)2918 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2919 {
2920 init_waitqueue_head(&w->q);
2921 init_waitqueue_entry(&w->wait, current);
2922 w->data = data;
2923 }
2924
add_cond_wait(struct cond_wait ** head,struct cond_wait * w)2925 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2926 {
2927 set_current_state(TASK_INTERRUPTIBLE);
2928 add_wait_queue(&w->q, &w->wait);
2929 w->next = *head;
2930 *head = w;
2931 }
2932
remove_cond_wait(struct cond_wait ** head,struct cond_wait * cw)2933 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2934 {
2935 struct cond_wait *w, *prev;
2936 remove_wait_queue(&cw->q, &cw->wait);
2937 set_current_state(TASK_RUNNING);
2938 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2939 if (w == cw) {
2940 if (prev != NULL)
2941 prev->next = w->next;
2942 else
2943 *head = w->next;
2944 break;
2945 }
2946 }
2947 }
2948
flush_cond_wait(struct cond_wait ** head)2949 static void flush_cond_wait(struct cond_wait **head)
2950 {
2951 while (*head != NULL) {
2952 wake_up_interruptible(&(*head)->q);
2953 *head = (*head)->next;
2954 }
2955 }
2956
2957 /*
2958 * wait for general purpose I/O pin(s) to enter specified state
2959 *
2960 * user_gpio fields:
2961 * state - bit indicates target pin state
2962 * smask - set bit indicates watched pin
2963 *
2964 * The wait ends when at least one watched pin enters the specified
2965 * state. When 0 (no error) is returned, user_gpio->state is set to the
2966 * state of all GPIO pins when the wait ends.
2967 *
2968 * Note: Each pin may be a dedicated input, dedicated output, or
2969 * configurable input/output. The number and configuration of pins
2970 * varies with the specific adapter model. Only input pins (dedicated
2971 * or configured) can be monitored with this function.
2972 */
wait_gpio(struct slgt_info * info,struct gpio_desc __user * user_gpio)2973 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2974 {
2975 unsigned long flags;
2976 int rc = 0;
2977 struct gpio_desc gpio;
2978 struct cond_wait wait;
2979 u32 state;
2980
2981 if (!info->gpio_present)
2982 return -EINVAL;
2983 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2984 return -EFAULT;
2985 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2986 info->device_name, gpio.state, gpio.smask));
2987 /* ignore output pins identified by set IODR bit */
2988 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2989 return -EINVAL;
2990 init_cond_wait(&wait, gpio.smask);
2991
2992 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2993 /* enable interrupts for watched pins */
2994 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2995 /* get current pin states */
2996 state = rd_reg32(info, IOVR);
2997
2998 if (gpio.smask & ~(state ^ gpio.state)) {
2999 /* already in target state */
3000 gpio.state = state;
3001 } else {
3002 /* wait for target state */
3003 add_cond_wait(&info->gpio_wait_q, &wait);
3004 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3005 schedule();
3006 if (signal_pending(current))
3007 rc = -ERESTARTSYS;
3008 else
3009 gpio.state = wait.data;
3010 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3011 remove_cond_wait(&info->gpio_wait_q, &wait);
3012 }
3013
3014 /* disable all GPIO interrupts if no waiting processes */
3015 if (info->gpio_wait_q == NULL)
3016 wr_reg32(info, IOER, 0);
3017 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3018
3019 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3020 rc = -EFAULT;
3021 return rc;
3022 }
3023
modem_input_wait(struct slgt_info * info,int arg)3024 static int modem_input_wait(struct slgt_info *info,int arg)
3025 {
3026 unsigned long flags;
3027 int rc;
3028 struct mgsl_icount cprev, cnow;
3029 DECLARE_WAITQUEUE(wait, current);
3030
3031 /* save current irq counts */
3032 spin_lock_irqsave(&info->lock,flags);
3033 cprev = info->icount;
3034 add_wait_queue(&info->status_event_wait_q, &wait);
3035 set_current_state(TASK_INTERRUPTIBLE);
3036 spin_unlock_irqrestore(&info->lock,flags);
3037
3038 for(;;) {
3039 schedule();
3040 if (signal_pending(current)) {
3041 rc = -ERESTARTSYS;
3042 break;
3043 }
3044
3045 /* get new irq counts */
3046 spin_lock_irqsave(&info->lock,flags);
3047 cnow = info->icount;
3048 set_current_state(TASK_INTERRUPTIBLE);
3049 spin_unlock_irqrestore(&info->lock,flags);
3050
3051 /* if no change, wait aborted for some reason */
3052 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3053 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3054 rc = -EIO;
3055 break;
3056 }
3057
3058 /* check for change in caller specified modem input */
3059 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3060 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3061 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3062 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3063 rc = 0;
3064 break;
3065 }
3066
3067 cprev = cnow;
3068 }
3069 remove_wait_queue(&info->status_event_wait_q, &wait);
3070 set_current_state(TASK_RUNNING);
3071 return rc;
3072 }
3073
3074 /*
3075 * return state of serial control and status signals
3076 */
tiocmget(struct tty_struct * tty)3077 static int tiocmget(struct tty_struct *tty)
3078 {
3079 struct slgt_info *info = tty->driver_data;
3080 unsigned int result;
3081 unsigned long flags;
3082
3083 spin_lock_irqsave(&info->lock,flags);
3084 get_gtsignals(info);
3085 spin_unlock_irqrestore(&info->lock,flags);
3086
3087 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3088 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3089 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3090 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3091 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3092 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3093
3094 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3095 return result;
3096 }
3097
3098 /*
3099 * set modem control signals (DTR/RTS)
3100 *
3101 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3102 * TIOCMSET = set/clear signal values
3103 * value bit mask for command
3104 */
tiocmset(struct tty_struct * tty,unsigned int set,unsigned int clear)3105 static int tiocmset(struct tty_struct *tty,
3106 unsigned int set, unsigned int clear)
3107 {
3108 struct slgt_info *info = tty->driver_data;
3109 unsigned long flags;
3110
3111 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3112
3113 if (set & TIOCM_RTS)
3114 info->signals |= SerialSignal_RTS;
3115 if (set & TIOCM_DTR)
3116 info->signals |= SerialSignal_DTR;
3117 if (clear & TIOCM_RTS)
3118 info->signals &= ~SerialSignal_RTS;
3119 if (clear & TIOCM_DTR)
3120 info->signals &= ~SerialSignal_DTR;
3121
3122 spin_lock_irqsave(&info->lock,flags);
3123 set_gtsignals(info);
3124 spin_unlock_irqrestore(&info->lock,flags);
3125 return 0;
3126 }
3127
carrier_raised(struct tty_port * port)3128 static int carrier_raised(struct tty_port *port)
3129 {
3130 unsigned long flags;
3131 struct slgt_info *info = container_of(port, struct slgt_info, port);
3132
3133 spin_lock_irqsave(&info->lock,flags);
3134 get_gtsignals(info);
3135 spin_unlock_irqrestore(&info->lock,flags);
3136 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3137 }
3138
dtr_rts(struct tty_port * port,int on)3139 static void dtr_rts(struct tty_port *port, int on)
3140 {
3141 unsigned long flags;
3142 struct slgt_info *info = container_of(port, struct slgt_info, port);
3143
3144 spin_lock_irqsave(&info->lock,flags);
3145 if (on)
3146 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3147 else
3148 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3149 set_gtsignals(info);
3150 spin_unlock_irqrestore(&info->lock,flags);
3151 }
3152
3153
3154 /*
3155 * block current process until the device is ready to open
3156 */
block_til_ready(struct tty_struct * tty,struct file * filp,struct slgt_info * info)3157 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3158 struct slgt_info *info)
3159 {
3160 DECLARE_WAITQUEUE(wait, current);
3161 int retval;
3162 bool do_clocal = false;
3163 unsigned long flags;
3164 int cd;
3165 struct tty_port *port = &info->port;
3166
3167 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3168
3169 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3170 /* nonblock mode is set or port is not enabled */
3171 tty_port_set_active(port, 1);
3172 return 0;
3173 }
3174
3175 if (C_CLOCAL(tty))
3176 do_clocal = true;
3177
3178 /* Wait for carrier detect and the line to become
3179 * free (i.e., not in use by the callout). While we are in
3180 * this loop, port->count is dropped by one, so that
3181 * close() knows when to free things. We restore it upon
3182 * exit, either normal or abnormal.
3183 */
3184
3185 retval = 0;
3186 add_wait_queue(&port->open_wait, &wait);
3187
3188 spin_lock_irqsave(&info->lock, flags);
3189 port->count--;
3190 spin_unlock_irqrestore(&info->lock, flags);
3191 port->blocked_open++;
3192
3193 while (1) {
3194 if (C_BAUD(tty) && tty_port_initialized(port))
3195 tty_port_raise_dtr_rts(port);
3196
3197 set_current_state(TASK_INTERRUPTIBLE);
3198
3199 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3200 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3201 -EAGAIN : -ERESTARTSYS;
3202 break;
3203 }
3204
3205 cd = tty_port_carrier_raised(port);
3206 if (do_clocal || cd)
3207 break;
3208
3209 if (signal_pending(current)) {
3210 retval = -ERESTARTSYS;
3211 break;
3212 }
3213
3214 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3215 tty_unlock(tty);
3216 schedule();
3217 tty_lock(tty);
3218 }
3219
3220 set_current_state(TASK_RUNNING);
3221 remove_wait_queue(&port->open_wait, &wait);
3222
3223 if (!tty_hung_up_p(filp))
3224 port->count++;
3225 port->blocked_open--;
3226
3227 if (!retval)
3228 tty_port_set_active(port, 1);
3229
3230 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3231 return retval;
3232 }
3233
3234 /*
3235 * allocate buffers used for calling line discipline receive_buf
3236 * directly in synchronous mode
3237 * note: add 5 bytes to max frame size to allow appending
3238 * 32-bit CRC and status byte when configured to do so
3239 */
alloc_tmp_rbuf(struct slgt_info * info)3240 static int alloc_tmp_rbuf(struct slgt_info *info)
3241 {
3242 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3243 if (info->tmp_rbuf == NULL)
3244 return -ENOMEM;
3245 /* unused flag buffer to satisfy receive_buf calling interface */
3246 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3247 if (!info->flag_buf) {
3248 kfree(info->tmp_rbuf);
3249 info->tmp_rbuf = NULL;
3250 return -ENOMEM;
3251 }
3252 return 0;
3253 }
3254
free_tmp_rbuf(struct slgt_info * info)3255 static void free_tmp_rbuf(struct slgt_info *info)
3256 {
3257 kfree(info->tmp_rbuf);
3258 info->tmp_rbuf = NULL;
3259 kfree(info->flag_buf);
3260 info->flag_buf = NULL;
3261 }
3262
3263 /*
3264 * allocate DMA descriptor lists.
3265 */
alloc_desc(struct slgt_info * info)3266 static int alloc_desc(struct slgt_info *info)
3267 {
3268 unsigned int i;
3269 unsigned int pbufs;
3270
3271 /* allocate memory to hold descriptor lists */
3272 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3273 &info->bufs_dma_addr, GFP_KERNEL);
3274 if (info->bufs == NULL)
3275 return -ENOMEM;
3276
3277 info->rbufs = (struct slgt_desc*)info->bufs;
3278 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3279
3280 pbufs = (unsigned int)info->bufs_dma_addr;
3281
3282 /*
3283 * Build circular lists of descriptors
3284 */
3285
3286 for (i=0; i < info->rbuf_count; i++) {
3287 /* physical address of this descriptor */
3288 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3289
3290 /* physical address of next descriptor */
3291 if (i == info->rbuf_count - 1)
3292 info->rbufs[i].next = cpu_to_le32(pbufs);
3293 else
3294 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3295 set_desc_count(info->rbufs[i], DMABUFSIZE);
3296 }
3297
3298 for (i=0; i < info->tbuf_count; i++) {
3299 /* physical address of this descriptor */
3300 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3301
3302 /* physical address of next descriptor */
3303 if (i == info->tbuf_count - 1)
3304 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3305 else
3306 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3307 }
3308
3309 return 0;
3310 }
3311
free_desc(struct slgt_info * info)3312 static void free_desc(struct slgt_info *info)
3313 {
3314 if (info->bufs != NULL) {
3315 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3316 info->bufs, info->bufs_dma_addr);
3317 info->bufs = NULL;
3318 info->rbufs = NULL;
3319 info->tbufs = NULL;
3320 }
3321 }
3322
alloc_bufs(struct slgt_info * info,struct slgt_desc * bufs,int count)3323 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3324 {
3325 int i;
3326 for (i=0; i < count; i++) {
3327 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3328 &bufs[i].buf_dma_addr, GFP_KERNEL);
3329 if (!bufs[i].buf)
3330 return -ENOMEM;
3331 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3332 }
3333 return 0;
3334 }
3335
free_bufs(struct slgt_info * info,struct slgt_desc * bufs,int count)3336 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3337 {
3338 int i;
3339 for (i=0; i < count; i++) {
3340 if (bufs[i].buf == NULL)
3341 continue;
3342 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3343 bufs[i].buf_dma_addr);
3344 bufs[i].buf = NULL;
3345 }
3346 }
3347
alloc_dma_bufs(struct slgt_info * info)3348 static int alloc_dma_bufs(struct slgt_info *info)
3349 {
3350 info->rbuf_count = 32;
3351 info->tbuf_count = 32;
3352
3353 if (alloc_desc(info) < 0 ||
3354 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3355 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3356 alloc_tmp_rbuf(info) < 0) {
3357 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3358 return -ENOMEM;
3359 }
3360 reset_rbufs(info);
3361 return 0;
3362 }
3363
free_dma_bufs(struct slgt_info * info)3364 static void free_dma_bufs(struct slgt_info *info)
3365 {
3366 if (info->bufs) {
3367 free_bufs(info, info->rbufs, info->rbuf_count);
3368 free_bufs(info, info->tbufs, info->tbuf_count);
3369 free_desc(info);
3370 }
3371 free_tmp_rbuf(info);
3372 }
3373
claim_resources(struct slgt_info * info)3374 static int claim_resources(struct slgt_info *info)
3375 {
3376 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3377 DBGERR(("%s reg addr conflict, addr=%08X\n",
3378 info->device_name, info->phys_reg_addr));
3379 info->init_error = DiagStatus_AddressConflict;
3380 goto errout;
3381 }
3382 else
3383 info->reg_addr_requested = true;
3384
3385 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3386 if (!info->reg_addr) {
3387 DBGERR(("%s can't map device registers, addr=%08X\n",
3388 info->device_name, info->phys_reg_addr));
3389 info->init_error = DiagStatus_CantAssignPciResources;
3390 goto errout;
3391 }
3392 return 0;
3393
3394 errout:
3395 release_resources(info);
3396 return -ENODEV;
3397 }
3398
release_resources(struct slgt_info * info)3399 static void release_resources(struct slgt_info *info)
3400 {
3401 if (info->irq_requested) {
3402 free_irq(info->irq_level, info);
3403 info->irq_requested = false;
3404 }
3405
3406 if (info->reg_addr_requested) {
3407 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3408 info->reg_addr_requested = false;
3409 }
3410
3411 if (info->reg_addr) {
3412 iounmap(info->reg_addr);
3413 info->reg_addr = NULL;
3414 }
3415 }
3416
3417 /* Add the specified device instance data structure to the
3418 * global linked list of devices and increment the device count.
3419 */
add_device(struct slgt_info * info)3420 static void add_device(struct slgt_info *info)
3421 {
3422 char *devstr;
3423
3424 info->next_device = NULL;
3425 info->line = slgt_device_count;
3426 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3427
3428 if (info->line < MAX_DEVICES) {
3429 if (maxframe[info->line])
3430 info->max_frame_size = maxframe[info->line];
3431 }
3432
3433 slgt_device_count++;
3434
3435 if (!slgt_device_list)
3436 slgt_device_list = info;
3437 else {
3438 struct slgt_info *current_dev = slgt_device_list;
3439 while(current_dev->next_device)
3440 current_dev = current_dev->next_device;
3441 current_dev->next_device = info;
3442 }
3443
3444 if (info->max_frame_size < 4096)
3445 info->max_frame_size = 4096;
3446 else if (info->max_frame_size > 65535)
3447 info->max_frame_size = 65535;
3448
3449 switch(info->pdev->device) {
3450 case SYNCLINK_GT_DEVICE_ID:
3451 devstr = "GT";
3452 break;
3453 case SYNCLINK_GT2_DEVICE_ID:
3454 devstr = "GT2";
3455 break;
3456 case SYNCLINK_GT4_DEVICE_ID:
3457 devstr = "GT4";
3458 break;
3459 case SYNCLINK_AC_DEVICE_ID:
3460 devstr = "AC";
3461 info->params.mode = MGSL_MODE_ASYNC;
3462 break;
3463 default:
3464 devstr = "(unknown model)";
3465 }
3466 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3467 devstr, info->device_name, info->phys_reg_addr,
3468 info->irq_level, info->max_frame_size);
3469
3470 #if SYNCLINK_GENERIC_HDLC
3471 hdlcdev_init(info);
3472 #endif
3473 }
3474
3475 static const struct tty_port_operations slgt_port_ops = {
3476 .carrier_raised = carrier_raised,
3477 .dtr_rts = dtr_rts,
3478 };
3479
3480 /*
3481 * allocate device instance structure, return NULL on failure
3482 */
alloc_dev(int adapter_num,int port_num,struct pci_dev * pdev)3483 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3484 {
3485 struct slgt_info *info;
3486
3487 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3488
3489 if (!info) {
3490 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3491 driver_name, adapter_num, port_num));
3492 } else {
3493 tty_port_init(&info->port);
3494 info->port.ops = &slgt_port_ops;
3495 INIT_WORK(&info->task, bh_handler);
3496 info->max_frame_size = 4096;
3497 info->base_clock = 14745600;
3498 info->rbuf_fill_level = DMABUFSIZE;
3499 init_waitqueue_head(&info->status_event_wait_q);
3500 init_waitqueue_head(&info->event_wait_q);
3501 spin_lock_init(&info->netlock);
3502 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3503 info->idle_mode = HDLC_TXIDLE_FLAGS;
3504 info->adapter_num = adapter_num;
3505 info->port_num = port_num;
3506
3507 timer_setup(&info->tx_timer, tx_timeout, 0);
3508 timer_setup(&info->rx_timer, rx_timeout, 0);
3509
3510 /* Copy configuration info to device instance data */
3511 info->pdev = pdev;
3512 info->irq_level = pdev->irq;
3513 info->phys_reg_addr = pci_resource_start(pdev,0);
3514
3515 info->bus_type = MGSL_BUS_TYPE_PCI;
3516 info->irq_flags = IRQF_SHARED;
3517
3518 info->init_error = -1; /* assume error, set to 0 on successful init */
3519 }
3520
3521 return info;
3522 }
3523
device_init(int adapter_num,struct pci_dev * pdev)3524 static void device_init(int adapter_num, struct pci_dev *pdev)
3525 {
3526 struct slgt_info *port_array[SLGT_MAX_PORTS];
3527 int i;
3528 int port_count = 1;
3529
3530 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3531 port_count = 2;
3532 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3533 port_count = 4;
3534
3535 /* allocate device instances for all ports */
3536 for (i=0; i < port_count; ++i) {
3537 port_array[i] = alloc_dev(adapter_num, i, pdev);
3538 if (port_array[i] == NULL) {
3539 for (--i; i >= 0; --i) {
3540 tty_port_destroy(&port_array[i]->port);
3541 kfree(port_array[i]);
3542 }
3543 return;
3544 }
3545 }
3546
3547 /* give copy of port_array to all ports and add to device list */
3548 for (i=0; i < port_count; ++i) {
3549 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3550 add_device(port_array[i]);
3551 port_array[i]->port_count = port_count;
3552 spin_lock_init(&port_array[i]->lock);
3553 }
3554
3555 /* Allocate and claim adapter resources */
3556 if (!claim_resources(port_array[0])) {
3557
3558 alloc_dma_bufs(port_array[0]);
3559
3560 /* copy resource information from first port to others */
3561 for (i = 1; i < port_count; ++i) {
3562 port_array[i]->irq_level = port_array[0]->irq_level;
3563 port_array[i]->reg_addr = port_array[0]->reg_addr;
3564 alloc_dma_bufs(port_array[i]);
3565 }
3566
3567 if (request_irq(port_array[0]->irq_level,
3568 slgt_interrupt,
3569 port_array[0]->irq_flags,
3570 port_array[0]->device_name,
3571 port_array[0]) < 0) {
3572 DBGERR(("%s request_irq failed IRQ=%d\n",
3573 port_array[0]->device_name,
3574 port_array[0]->irq_level));
3575 } else {
3576 port_array[0]->irq_requested = true;
3577 adapter_test(port_array[0]);
3578 for (i=1 ; i < port_count ; i++) {
3579 port_array[i]->init_error = port_array[0]->init_error;
3580 port_array[i]->gpio_present = port_array[0]->gpio_present;
3581 }
3582 }
3583 }
3584
3585 for (i = 0; i < port_count; ++i) {
3586 struct slgt_info *info = port_array[i];
3587 tty_port_register_device(&info->port, serial_driver, info->line,
3588 &info->pdev->dev);
3589 }
3590 }
3591
init_one(struct pci_dev * dev,const struct pci_device_id * ent)3592 static int init_one(struct pci_dev *dev,
3593 const struct pci_device_id *ent)
3594 {
3595 if (pci_enable_device(dev)) {
3596 printk("error enabling pci device %p\n", dev);
3597 return -EIO;
3598 }
3599 pci_set_master(dev);
3600 device_init(slgt_device_count, dev);
3601 return 0;
3602 }
3603
remove_one(struct pci_dev * dev)3604 static void remove_one(struct pci_dev *dev)
3605 {
3606 }
3607
3608 static const struct tty_operations ops = {
3609 .open = open,
3610 .close = close,
3611 .write = write,
3612 .put_char = put_char,
3613 .flush_chars = flush_chars,
3614 .write_room = write_room,
3615 .chars_in_buffer = chars_in_buffer,
3616 .flush_buffer = flush_buffer,
3617 .ioctl = ioctl,
3618 .compat_ioctl = slgt_compat_ioctl,
3619 .throttle = throttle,
3620 .unthrottle = unthrottle,
3621 .send_xchar = send_xchar,
3622 .break_ctl = set_break,
3623 .wait_until_sent = wait_until_sent,
3624 .set_termios = set_termios,
3625 .stop = tx_hold,
3626 .start = tx_release,
3627 .hangup = hangup,
3628 .tiocmget = tiocmget,
3629 .tiocmset = tiocmset,
3630 .get_icount = get_icount,
3631 .proc_show = synclink_gt_proc_show,
3632 };
3633
slgt_cleanup(void)3634 static void slgt_cleanup(void)
3635 {
3636 struct slgt_info *info;
3637 struct slgt_info *tmp;
3638
3639 printk(KERN_INFO "unload %s\n", driver_name);
3640
3641 if (serial_driver) {
3642 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3643 tty_unregister_device(serial_driver, info->line);
3644 tty_unregister_driver(serial_driver);
3645 tty_driver_kref_put(serial_driver);
3646 }
3647
3648 /* reset devices */
3649 info = slgt_device_list;
3650 while(info) {
3651 reset_port(info);
3652 info = info->next_device;
3653 }
3654
3655 /* release devices */
3656 info = slgt_device_list;
3657 while(info) {
3658 #if SYNCLINK_GENERIC_HDLC
3659 hdlcdev_exit(info);
3660 #endif
3661 free_dma_bufs(info);
3662 free_tmp_rbuf(info);
3663 if (info->port_num == 0)
3664 release_resources(info);
3665 tmp = info;
3666 info = info->next_device;
3667 tty_port_destroy(&tmp->port);
3668 kfree(tmp);
3669 }
3670
3671 if (pci_registered)
3672 pci_unregister_driver(&pci_driver);
3673 }
3674
3675 /*
3676 * Driver initialization entry point.
3677 */
slgt_init(void)3678 static int __init slgt_init(void)
3679 {
3680 int rc;
3681
3682 printk(KERN_INFO "%s\n", driver_name);
3683
3684 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3685 TTY_DRIVER_DYNAMIC_DEV);
3686 if (IS_ERR(serial_driver)) {
3687 printk("%s can't allocate tty driver\n", driver_name);
3688 return PTR_ERR(serial_driver);
3689 }
3690
3691 /* Initialize the tty_driver structure */
3692
3693 serial_driver->driver_name = slgt_driver_name;
3694 serial_driver->name = tty_dev_prefix;
3695 serial_driver->major = ttymajor;
3696 serial_driver->minor_start = 64;
3697 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3698 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3699 serial_driver->init_termios = tty_std_termios;
3700 serial_driver->init_termios.c_cflag =
3701 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3702 serial_driver->init_termios.c_ispeed = 9600;
3703 serial_driver->init_termios.c_ospeed = 9600;
3704 tty_set_operations(serial_driver, &ops);
3705 if ((rc = tty_register_driver(serial_driver)) < 0) {
3706 DBGERR(("%s can't register serial driver\n", driver_name));
3707 tty_driver_kref_put(serial_driver);
3708 serial_driver = NULL;
3709 goto error;
3710 }
3711
3712 printk(KERN_INFO "%s, tty major#%d\n",
3713 driver_name, serial_driver->major);
3714
3715 slgt_device_count = 0;
3716 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3717 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3718 goto error;
3719 }
3720 pci_registered = true;
3721
3722 if (!slgt_device_list)
3723 printk("%s no devices found\n",driver_name);
3724
3725 return 0;
3726
3727 error:
3728 slgt_cleanup();
3729 return rc;
3730 }
3731
slgt_exit(void)3732 static void __exit slgt_exit(void)
3733 {
3734 slgt_cleanup();
3735 }
3736
3737 module_init(slgt_init);
3738 module_exit(slgt_exit);
3739
3740 /*
3741 * register access routines
3742 */
3743
3744 #define CALC_REGADDR() \
3745 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3746 if (addr >= 0x80) \
3747 reg_addr += (info->port_num) * 32; \
3748 else if (addr >= 0x40) \
3749 reg_addr += (info->port_num) * 16;
3750
rd_reg8(struct slgt_info * info,unsigned int addr)3751 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3752 {
3753 CALC_REGADDR();
3754 return readb((void __iomem *)reg_addr);
3755 }
3756
wr_reg8(struct slgt_info * info,unsigned int addr,__u8 value)3757 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3758 {
3759 CALC_REGADDR();
3760 writeb(value, (void __iomem *)reg_addr);
3761 }
3762
rd_reg16(struct slgt_info * info,unsigned int addr)3763 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3764 {
3765 CALC_REGADDR();
3766 return readw((void __iomem *)reg_addr);
3767 }
3768
wr_reg16(struct slgt_info * info,unsigned int addr,__u16 value)3769 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3770 {
3771 CALC_REGADDR();
3772 writew(value, (void __iomem *)reg_addr);
3773 }
3774
rd_reg32(struct slgt_info * info,unsigned int addr)3775 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3776 {
3777 CALC_REGADDR();
3778 return readl((void __iomem *)reg_addr);
3779 }
3780
wr_reg32(struct slgt_info * info,unsigned int addr,__u32 value)3781 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3782 {
3783 CALC_REGADDR();
3784 writel(value, (void __iomem *)reg_addr);
3785 }
3786
rdma_reset(struct slgt_info * info)3787 static void rdma_reset(struct slgt_info *info)
3788 {
3789 unsigned int i;
3790
3791 /* set reset bit */
3792 wr_reg32(info, RDCSR, BIT1);
3793
3794 /* wait for enable bit cleared */
3795 for(i=0 ; i < 1000 ; i++)
3796 if (!(rd_reg32(info, RDCSR) & BIT0))
3797 break;
3798 }
3799
tdma_reset(struct slgt_info * info)3800 static void tdma_reset(struct slgt_info *info)
3801 {
3802 unsigned int i;
3803
3804 /* set reset bit */
3805 wr_reg32(info, TDCSR, BIT1);
3806
3807 /* wait for enable bit cleared */
3808 for(i=0 ; i < 1000 ; i++)
3809 if (!(rd_reg32(info, TDCSR) & BIT0))
3810 break;
3811 }
3812
3813 /*
3814 * enable internal loopback
3815 * TxCLK and RxCLK are generated from BRG
3816 * and TxD is looped back to RxD internally.
3817 */
enable_loopback(struct slgt_info * info)3818 static void enable_loopback(struct slgt_info *info)
3819 {
3820 /* SCR (serial control) BIT2=loopback enable */
3821 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3822
3823 if (info->params.mode != MGSL_MODE_ASYNC) {
3824 /* CCR (clock control)
3825 * 07..05 tx clock source (010 = BRG)
3826 * 04..02 rx clock source (010 = BRG)
3827 * 01 auxclk enable (0 = disable)
3828 * 00 BRG enable (1 = enable)
3829 *
3830 * 0100 1001
3831 */
3832 wr_reg8(info, CCR, 0x49);
3833
3834 /* set speed if available, otherwise use default */
3835 if (info->params.clock_speed)
3836 set_rate(info, info->params.clock_speed);
3837 else
3838 set_rate(info, 3686400);
3839 }
3840 }
3841
3842 /*
3843 * set baud rate generator to specified rate
3844 */
set_rate(struct slgt_info * info,u32 rate)3845 static void set_rate(struct slgt_info *info, u32 rate)
3846 {
3847 unsigned int div;
3848 unsigned int osc = info->base_clock;
3849
3850 /* div = osc/rate - 1
3851 *
3852 * Round div up if osc/rate is not integer to
3853 * force to next slowest rate.
3854 */
3855
3856 if (rate) {
3857 div = osc/rate;
3858 if (!(osc % rate) && div)
3859 div--;
3860 wr_reg16(info, BDR, (unsigned short)div);
3861 }
3862 }
3863
rx_stop(struct slgt_info * info)3864 static void rx_stop(struct slgt_info *info)
3865 {
3866 unsigned short val;
3867
3868 /* disable and reset receiver */
3869 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3870 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3871 wr_reg16(info, RCR, val); /* clear reset bit */
3872
3873 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3874
3875 /* clear pending rx interrupts */
3876 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3877
3878 rdma_reset(info);
3879
3880 info->rx_enabled = false;
3881 info->rx_restart = false;
3882 }
3883
rx_start(struct slgt_info * info)3884 static void rx_start(struct slgt_info *info)
3885 {
3886 unsigned short val;
3887
3888 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3889
3890 /* clear pending rx overrun IRQ */
3891 wr_reg16(info, SSR, IRQ_RXOVER);
3892
3893 /* reset and disable receiver */
3894 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3895 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3896 wr_reg16(info, RCR, val); /* clear reset bit */
3897
3898 rdma_reset(info);
3899 reset_rbufs(info);
3900
3901 if (info->rx_pio) {
3902 /* rx request when rx FIFO not empty */
3903 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3904 slgt_irq_on(info, IRQ_RXDATA);
3905 if (info->params.mode == MGSL_MODE_ASYNC) {
3906 /* enable saving of rx status */
3907 wr_reg32(info, RDCSR, BIT6);
3908 }
3909 } else {
3910 /* rx request when rx FIFO half full */
3911 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3912 /* set 1st descriptor address */
3913 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3914
3915 if (info->params.mode != MGSL_MODE_ASYNC) {
3916 /* enable rx DMA and DMA interrupt */
3917 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3918 } else {
3919 /* enable saving of rx status, rx DMA and DMA interrupt */
3920 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3921 }
3922 }
3923
3924 slgt_irq_on(info, IRQ_RXOVER);
3925
3926 /* enable receiver */
3927 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3928
3929 info->rx_restart = false;
3930 info->rx_enabled = true;
3931 }
3932
tx_start(struct slgt_info * info)3933 static void tx_start(struct slgt_info *info)
3934 {
3935 if (!info->tx_enabled) {
3936 wr_reg16(info, TCR,
3937 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3938 info->tx_enabled = true;
3939 }
3940
3941 if (desc_count(info->tbufs[info->tbuf_start])) {
3942 info->drop_rts_on_tx_done = false;
3943
3944 if (info->params.mode != MGSL_MODE_ASYNC) {
3945 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3946 get_gtsignals(info);
3947 if (!(info->signals & SerialSignal_RTS)) {
3948 info->signals |= SerialSignal_RTS;
3949 set_gtsignals(info);
3950 info->drop_rts_on_tx_done = true;
3951 }
3952 }
3953
3954 slgt_irq_off(info, IRQ_TXDATA);
3955 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3956 /* clear tx idle and underrun status bits */
3957 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3958 } else {
3959 slgt_irq_off(info, IRQ_TXDATA);
3960 slgt_irq_on(info, IRQ_TXIDLE);
3961 /* clear tx idle status bit */
3962 wr_reg16(info, SSR, IRQ_TXIDLE);
3963 }
3964 /* set 1st descriptor address and start DMA */
3965 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3966 wr_reg32(info, TDCSR, BIT2 + BIT0);
3967 info->tx_active = true;
3968 }
3969 }
3970
tx_stop(struct slgt_info * info)3971 static void tx_stop(struct slgt_info *info)
3972 {
3973 unsigned short val;
3974
3975 del_timer(&info->tx_timer);
3976
3977 tdma_reset(info);
3978
3979 /* reset and disable transmitter */
3980 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3981 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3982
3983 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3984
3985 /* clear tx idle and underrun status bit */
3986 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3987
3988 reset_tbufs(info);
3989
3990 info->tx_enabled = false;
3991 info->tx_active = false;
3992 }
3993
reset_port(struct slgt_info * info)3994 static void reset_port(struct slgt_info *info)
3995 {
3996 if (!info->reg_addr)
3997 return;
3998
3999 tx_stop(info);
4000 rx_stop(info);
4001
4002 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4003 set_gtsignals(info);
4004
4005 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4006 }
4007
reset_adapter(struct slgt_info * info)4008 static void reset_adapter(struct slgt_info *info)
4009 {
4010 int i;
4011 for (i=0; i < info->port_count; ++i) {
4012 if (info->port_array[i])
4013 reset_port(info->port_array[i]);
4014 }
4015 }
4016
async_mode(struct slgt_info * info)4017 static void async_mode(struct slgt_info *info)
4018 {
4019 unsigned short val;
4020
4021 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4022 tx_stop(info);
4023 rx_stop(info);
4024
4025 /* TCR (tx control)
4026 *
4027 * 15..13 mode, 010=async
4028 * 12..10 encoding, 000=NRZ
4029 * 09 parity enable
4030 * 08 1=odd parity, 0=even parity
4031 * 07 1=RTS driver control
4032 * 06 1=break enable
4033 * 05..04 character length
4034 * 00=5 bits
4035 * 01=6 bits
4036 * 10=7 bits
4037 * 11=8 bits
4038 * 03 0=1 stop bit, 1=2 stop bits
4039 * 02 reset
4040 * 01 enable
4041 * 00 auto-CTS enable
4042 */
4043 val = 0x4000;
4044
4045 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4046 val |= BIT7;
4047
4048 if (info->params.parity != ASYNC_PARITY_NONE) {
4049 val |= BIT9;
4050 if (info->params.parity == ASYNC_PARITY_ODD)
4051 val |= BIT8;
4052 }
4053
4054 switch (info->params.data_bits)
4055 {
4056 case 6: val |= BIT4; break;
4057 case 7: val |= BIT5; break;
4058 case 8: val |= BIT5 + BIT4; break;
4059 }
4060
4061 if (info->params.stop_bits != 1)
4062 val |= BIT3;
4063
4064 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4065 val |= BIT0;
4066
4067 wr_reg16(info, TCR, val);
4068
4069 /* RCR (rx control)
4070 *
4071 * 15..13 mode, 010=async
4072 * 12..10 encoding, 000=NRZ
4073 * 09 parity enable
4074 * 08 1=odd parity, 0=even parity
4075 * 07..06 reserved, must be 0
4076 * 05..04 character length
4077 * 00=5 bits
4078 * 01=6 bits
4079 * 10=7 bits
4080 * 11=8 bits
4081 * 03 reserved, must be zero
4082 * 02 reset
4083 * 01 enable
4084 * 00 auto-DCD enable
4085 */
4086 val = 0x4000;
4087
4088 if (info->params.parity != ASYNC_PARITY_NONE) {
4089 val |= BIT9;
4090 if (info->params.parity == ASYNC_PARITY_ODD)
4091 val |= BIT8;
4092 }
4093
4094 switch (info->params.data_bits)
4095 {
4096 case 6: val |= BIT4; break;
4097 case 7: val |= BIT5; break;
4098 case 8: val |= BIT5 + BIT4; break;
4099 }
4100
4101 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4102 val |= BIT0;
4103
4104 wr_reg16(info, RCR, val);
4105
4106 /* CCR (clock control)
4107 *
4108 * 07..05 011 = tx clock source is BRG/16
4109 * 04..02 010 = rx clock source is BRG
4110 * 01 0 = auxclk disabled
4111 * 00 1 = BRG enabled
4112 *
4113 * 0110 1001
4114 */
4115 wr_reg8(info, CCR, 0x69);
4116
4117 msc_set_vcr(info);
4118
4119 /* SCR (serial control)
4120 *
4121 * 15 1=tx req on FIFO half empty
4122 * 14 1=rx req on FIFO half full
4123 * 13 tx data IRQ enable
4124 * 12 tx idle IRQ enable
4125 * 11 rx break on IRQ enable
4126 * 10 rx data IRQ enable
4127 * 09 rx break off IRQ enable
4128 * 08 overrun IRQ enable
4129 * 07 DSR IRQ enable
4130 * 06 CTS IRQ enable
4131 * 05 DCD IRQ enable
4132 * 04 RI IRQ enable
4133 * 03 0=16x sampling, 1=8x sampling
4134 * 02 1=txd->rxd internal loopback enable
4135 * 01 reserved, must be zero
4136 * 00 1=master IRQ enable
4137 */
4138 val = BIT15 + BIT14 + BIT0;
4139 /* JCR[8] : 1 = x8 async mode feature available */
4140 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4141 ((info->base_clock < (info->params.data_rate * 16)) ||
4142 (info->base_clock % (info->params.data_rate * 16)))) {
4143 /* use 8x sampling */
4144 val |= BIT3;
4145 set_rate(info, info->params.data_rate * 8);
4146 } else {
4147 /* use 16x sampling */
4148 set_rate(info, info->params.data_rate * 16);
4149 }
4150 wr_reg16(info, SCR, val);
4151
4152 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4153
4154 if (info->params.loopback)
4155 enable_loopback(info);
4156 }
4157
sync_mode(struct slgt_info * info)4158 static void sync_mode(struct slgt_info *info)
4159 {
4160 unsigned short val;
4161
4162 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4163 tx_stop(info);
4164 rx_stop(info);
4165
4166 /* TCR (tx control)
4167 *
4168 * 15..13 mode
4169 * 000=HDLC/SDLC
4170 * 001=raw bit synchronous
4171 * 010=asynchronous/isochronous
4172 * 011=monosync byte synchronous
4173 * 100=bisync byte synchronous
4174 * 101=xsync byte synchronous
4175 * 12..10 encoding
4176 * 09 CRC enable
4177 * 08 CRC32
4178 * 07 1=RTS driver control
4179 * 06 preamble enable
4180 * 05..04 preamble length
4181 * 03 share open/close flag
4182 * 02 reset
4183 * 01 enable
4184 * 00 auto-CTS enable
4185 */
4186 val = BIT2;
4187
4188 switch(info->params.mode) {
4189 case MGSL_MODE_XSYNC:
4190 val |= BIT15 + BIT13;
4191 break;
4192 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4193 case MGSL_MODE_BISYNC: val |= BIT15; break;
4194 case MGSL_MODE_RAW: val |= BIT13; break;
4195 }
4196 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4197 val |= BIT7;
4198
4199 switch(info->params.encoding)
4200 {
4201 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4202 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4203 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4204 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4205 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4206 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4207 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4208 }
4209
4210 switch (info->params.crc_type & HDLC_CRC_MASK)
4211 {
4212 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4213 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4214 }
4215
4216 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4217 val |= BIT6;
4218
4219 switch (info->params.preamble_length)
4220 {
4221 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4222 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4223 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4224 }
4225
4226 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4227 val |= BIT0;
4228
4229 wr_reg16(info, TCR, val);
4230
4231 /* TPR (transmit preamble) */
4232
4233 switch (info->params.preamble)
4234 {
4235 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4236 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4237 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4238 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4239 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4240 default: val = 0x7e; break;
4241 }
4242 wr_reg8(info, TPR, (unsigned char)val);
4243
4244 /* RCR (rx control)
4245 *
4246 * 15..13 mode
4247 * 000=HDLC/SDLC
4248 * 001=raw bit synchronous
4249 * 010=asynchronous/isochronous
4250 * 011=monosync byte synchronous
4251 * 100=bisync byte synchronous
4252 * 101=xsync byte synchronous
4253 * 12..10 encoding
4254 * 09 CRC enable
4255 * 08 CRC32
4256 * 07..03 reserved, must be 0
4257 * 02 reset
4258 * 01 enable
4259 * 00 auto-DCD enable
4260 */
4261 val = 0;
4262
4263 switch(info->params.mode) {
4264 case MGSL_MODE_XSYNC:
4265 val |= BIT15 + BIT13;
4266 break;
4267 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4268 case MGSL_MODE_BISYNC: val |= BIT15; break;
4269 case MGSL_MODE_RAW: val |= BIT13; break;
4270 }
4271
4272 switch(info->params.encoding)
4273 {
4274 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4275 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4276 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4277 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4278 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4279 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4280 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4281 }
4282
4283 switch (info->params.crc_type & HDLC_CRC_MASK)
4284 {
4285 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4286 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4287 }
4288
4289 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4290 val |= BIT0;
4291
4292 wr_reg16(info, RCR, val);
4293
4294 /* CCR (clock control)
4295 *
4296 * 07..05 tx clock source
4297 * 04..02 rx clock source
4298 * 01 auxclk enable
4299 * 00 BRG enable
4300 */
4301 val = 0;
4302
4303 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4304 {
4305 // when RxC source is DPLL, BRG generates 16X DPLL
4306 // reference clock, so take TxC from BRG/16 to get
4307 // transmit clock at actual data rate
4308 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4309 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4310 else
4311 val |= BIT6; /* 010, txclk = BRG */
4312 }
4313 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4314 val |= BIT7; /* 100, txclk = DPLL Input */
4315 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4316 val |= BIT5; /* 001, txclk = RXC Input */
4317
4318 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4319 val |= BIT3; /* 010, rxclk = BRG */
4320 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4321 val |= BIT4; /* 100, rxclk = DPLL */
4322 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4323 val |= BIT2; /* 001, rxclk = TXC Input */
4324
4325 if (info->params.clock_speed)
4326 val |= BIT1 + BIT0;
4327
4328 wr_reg8(info, CCR, (unsigned char)val);
4329
4330 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4331 {
4332 // program DPLL mode
4333 switch(info->params.encoding)
4334 {
4335 case HDLC_ENCODING_BIPHASE_MARK:
4336 case HDLC_ENCODING_BIPHASE_SPACE:
4337 val = BIT7; break;
4338 case HDLC_ENCODING_BIPHASE_LEVEL:
4339 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4340 val = BIT7 + BIT6; break;
4341 default: val = BIT6; // NRZ encodings
4342 }
4343 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4344
4345 // DPLL requires a 16X reference clock from BRG
4346 set_rate(info, info->params.clock_speed * 16);
4347 }
4348 else
4349 set_rate(info, info->params.clock_speed);
4350
4351 tx_set_idle(info);
4352
4353 msc_set_vcr(info);
4354
4355 /* SCR (serial control)
4356 *
4357 * 15 1=tx req on FIFO half empty
4358 * 14 1=rx req on FIFO half full
4359 * 13 tx data IRQ enable
4360 * 12 tx idle IRQ enable
4361 * 11 underrun IRQ enable
4362 * 10 rx data IRQ enable
4363 * 09 rx idle IRQ enable
4364 * 08 overrun IRQ enable
4365 * 07 DSR IRQ enable
4366 * 06 CTS IRQ enable
4367 * 05 DCD IRQ enable
4368 * 04 RI IRQ enable
4369 * 03 reserved, must be zero
4370 * 02 1=txd->rxd internal loopback enable
4371 * 01 reserved, must be zero
4372 * 00 1=master IRQ enable
4373 */
4374 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4375
4376 if (info->params.loopback)
4377 enable_loopback(info);
4378 }
4379
4380 /*
4381 * set transmit idle mode
4382 */
tx_set_idle(struct slgt_info * info)4383 static void tx_set_idle(struct slgt_info *info)
4384 {
4385 unsigned char val;
4386 unsigned short tcr;
4387
4388 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4389 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4390 */
4391 tcr = rd_reg16(info, TCR);
4392 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4393 /* disable preamble, set idle size to 16 bits */
4394 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4395 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4396 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4397 } else if (!(tcr & BIT6)) {
4398 /* preamble is disabled, set idle size to 8 bits */
4399 tcr &= ~(BIT5 + BIT4);
4400 }
4401 wr_reg16(info, TCR, tcr);
4402
4403 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4404 /* LSB of custom tx idle specified in tx idle register */
4405 val = (unsigned char)(info->idle_mode & 0xff);
4406 } else {
4407 /* standard 8 bit idle patterns */
4408 switch(info->idle_mode)
4409 {
4410 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4411 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4412 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4413 case HDLC_TXIDLE_ZEROS:
4414 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4415 default: val = 0xff;
4416 }
4417 }
4418
4419 wr_reg8(info, TIR, val);
4420 }
4421
4422 /*
4423 * get state of V24 status (input) signals
4424 */
get_gtsignals(struct slgt_info * info)4425 static void get_gtsignals(struct slgt_info *info)
4426 {
4427 unsigned short status = rd_reg16(info, SSR);
4428
4429 /* clear all serial signals except RTS and DTR */
4430 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4431
4432 if (status & BIT3)
4433 info->signals |= SerialSignal_DSR;
4434 if (status & BIT2)
4435 info->signals |= SerialSignal_CTS;
4436 if (status & BIT1)
4437 info->signals |= SerialSignal_DCD;
4438 if (status & BIT0)
4439 info->signals |= SerialSignal_RI;
4440 }
4441
4442 /*
4443 * set V.24 Control Register based on current configuration
4444 */
msc_set_vcr(struct slgt_info * info)4445 static void msc_set_vcr(struct slgt_info *info)
4446 {
4447 unsigned char val = 0;
4448
4449 /* VCR (V.24 control)
4450 *
4451 * 07..04 serial IF select
4452 * 03 DTR
4453 * 02 RTS
4454 * 01 LL
4455 * 00 RL
4456 */
4457
4458 switch(info->if_mode & MGSL_INTERFACE_MASK)
4459 {
4460 case MGSL_INTERFACE_RS232:
4461 val |= BIT5; /* 0010 */
4462 break;
4463 case MGSL_INTERFACE_V35:
4464 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4465 break;
4466 case MGSL_INTERFACE_RS422:
4467 val |= BIT6; /* 0100 */
4468 break;
4469 }
4470
4471 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4472 val |= BIT4;
4473 if (info->signals & SerialSignal_DTR)
4474 val |= BIT3;
4475 if (info->signals & SerialSignal_RTS)
4476 val |= BIT2;
4477 if (info->if_mode & MGSL_INTERFACE_LL)
4478 val |= BIT1;
4479 if (info->if_mode & MGSL_INTERFACE_RL)
4480 val |= BIT0;
4481 wr_reg8(info, VCR, val);
4482 }
4483
4484 /*
4485 * set state of V24 control (output) signals
4486 */
set_gtsignals(struct slgt_info * info)4487 static void set_gtsignals(struct slgt_info *info)
4488 {
4489 unsigned char val = rd_reg8(info, VCR);
4490 if (info->signals & SerialSignal_DTR)
4491 val |= BIT3;
4492 else
4493 val &= ~BIT3;
4494 if (info->signals & SerialSignal_RTS)
4495 val |= BIT2;
4496 else
4497 val &= ~BIT2;
4498 wr_reg8(info, VCR, val);
4499 }
4500
4501 /*
4502 * free range of receive DMA buffers (i to last)
4503 */
free_rbufs(struct slgt_info * info,unsigned int i,unsigned int last)4504 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4505 {
4506 int done = 0;
4507
4508 while(!done) {
4509 /* reset current buffer for reuse */
4510 info->rbufs[i].status = 0;
4511 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4512 if (i == last)
4513 done = 1;
4514 if (++i == info->rbuf_count)
4515 i = 0;
4516 }
4517 info->rbuf_current = i;
4518 }
4519
4520 /*
4521 * mark all receive DMA buffers as free
4522 */
reset_rbufs(struct slgt_info * info)4523 static void reset_rbufs(struct slgt_info *info)
4524 {
4525 free_rbufs(info, 0, info->rbuf_count - 1);
4526 info->rbuf_fill_index = 0;
4527 info->rbuf_fill_count = 0;
4528 }
4529
4530 /*
4531 * pass receive HDLC frame to upper layer
4532 *
4533 * return true if frame available, otherwise false
4534 */
rx_get_frame(struct slgt_info * info)4535 static bool rx_get_frame(struct slgt_info *info)
4536 {
4537 unsigned int start, end;
4538 unsigned short status;
4539 unsigned int framesize = 0;
4540 unsigned long flags;
4541 struct tty_struct *tty = info->port.tty;
4542 unsigned char addr_field = 0xff;
4543 unsigned int crc_size = 0;
4544
4545 switch (info->params.crc_type & HDLC_CRC_MASK) {
4546 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4547 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4548 }
4549
4550 check_again:
4551
4552 framesize = 0;
4553 addr_field = 0xff;
4554 start = end = info->rbuf_current;
4555
4556 for (;;) {
4557 if (!desc_complete(info->rbufs[end]))
4558 goto cleanup;
4559
4560 if (framesize == 0 && info->params.addr_filter != 0xff)
4561 addr_field = info->rbufs[end].buf[0];
4562
4563 framesize += desc_count(info->rbufs[end]);
4564
4565 if (desc_eof(info->rbufs[end]))
4566 break;
4567
4568 if (++end == info->rbuf_count)
4569 end = 0;
4570
4571 if (end == info->rbuf_current) {
4572 if (info->rx_enabled){
4573 spin_lock_irqsave(&info->lock,flags);
4574 rx_start(info);
4575 spin_unlock_irqrestore(&info->lock,flags);
4576 }
4577 goto cleanup;
4578 }
4579 }
4580
4581 /* status
4582 *
4583 * 15 buffer complete
4584 * 14..06 reserved
4585 * 05..04 residue
4586 * 02 eof (end of frame)
4587 * 01 CRC error
4588 * 00 abort
4589 */
4590 status = desc_status(info->rbufs[end]);
4591
4592 /* ignore CRC bit if not using CRC (bit is undefined) */
4593 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4594 status &= ~BIT1;
4595
4596 if (framesize == 0 ||
4597 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4598 free_rbufs(info, start, end);
4599 goto check_again;
4600 }
4601
4602 if (framesize < (2 + crc_size) || status & BIT0) {
4603 info->icount.rxshort++;
4604 framesize = 0;
4605 } else if (status & BIT1) {
4606 info->icount.rxcrc++;
4607 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4608 framesize = 0;
4609 }
4610
4611 #if SYNCLINK_GENERIC_HDLC
4612 if (framesize == 0) {
4613 info->netdev->stats.rx_errors++;
4614 info->netdev->stats.rx_frame_errors++;
4615 }
4616 #endif
4617
4618 DBGBH(("%s rx frame status=%04X size=%d\n",
4619 info->device_name, status, framesize));
4620 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4621
4622 if (framesize) {
4623 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4624 framesize -= crc_size;
4625 crc_size = 0;
4626 }
4627
4628 if (framesize > info->max_frame_size + crc_size)
4629 info->icount.rxlong++;
4630 else {
4631 /* copy dma buffer(s) to contiguous temp buffer */
4632 int copy_count = framesize;
4633 int i = start;
4634 unsigned char *p = info->tmp_rbuf;
4635 info->tmp_rbuf_count = framesize;
4636
4637 info->icount.rxok++;
4638
4639 while(copy_count) {
4640 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4641 memcpy(p, info->rbufs[i].buf, partial_count);
4642 p += partial_count;
4643 copy_count -= partial_count;
4644 if (++i == info->rbuf_count)
4645 i = 0;
4646 }
4647
4648 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4649 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4650 framesize++;
4651 }
4652
4653 #if SYNCLINK_GENERIC_HDLC
4654 if (info->netcount)
4655 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4656 else
4657 #endif
4658 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4659 }
4660 }
4661 free_rbufs(info, start, end);
4662 return true;
4663
4664 cleanup:
4665 return false;
4666 }
4667
4668 /*
4669 * pass receive buffer (RAW synchronous mode) to tty layer
4670 * return true if buffer available, otherwise false
4671 */
rx_get_buf(struct slgt_info * info)4672 static bool rx_get_buf(struct slgt_info *info)
4673 {
4674 unsigned int i = info->rbuf_current;
4675 unsigned int count;
4676
4677 if (!desc_complete(info->rbufs[i]))
4678 return false;
4679 count = desc_count(info->rbufs[i]);
4680 switch(info->params.mode) {
4681 case MGSL_MODE_MONOSYNC:
4682 case MGSL_MODE_BISYNC:
4683 case MGSL_MODE_XSYNC:
4684 /* ignore residue in byte synchronous modes */
4685 if (desc_residue(info->rbufs[i]))
4686 count--;
4687 break;
4688 }
4689 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4690 DBGINFO(("rx_get_buf size=%d\n", count));
4691 if (count)
4692 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4693 info->flag_buf, count);
4694 free_rbufs(info, i, i);
4695 return true;
4696 }
4697
reset_tbufs(struct slgt_info * info)4698 static void reset_tbufs(struct slgt_info *info)
4699 {
4700 unsigned int i;
4701 info->tbuf_current = 0;
4702 for (i=0 ; i < info->tbuf_count ; i++) {
4703 info->tbufs[i].status = 0;
4704 info->tbufs[i].count = 0;
4705 }
4706 }
4707
4708 /*
4709 * return number of free transmit DMA buffers
4710 */
free_tbuf_count(struct slgt_info * info)4711 static unsigned int free_tbuf_count(struct slgt_info *info)
4712 {
4713 unsigned int count = 0;
4714 unsigned int i = info->tbuf_current;
4715
4716 do
4717 {
4718 if (desc_count(info->tbufs[i]))
4719 break; /* buffer in use */
4720 ++count;
4721 if (++i == info->tbuf_count)
4722 i=0;
4723 } while (i != info->tbuf_current);
4724
4725 /* if tx DMA active, last zero count buffer is in use */
4726 if (count && (rd_reg32(info, TDCSR) & BIT0))
4727 --count;
4728
4729 return count;
4730 }
4731
4732 /*
4733 * return number of bytes in unsent transmit DMA buffers
4734 * and the serial controller tx FIFO
4735 */
tbuf_bytes(struct slgt_info * info)4736 static unsigned int tbuf_bytes(struct slgt_info *info)
4737 {
4738 unsigned int total_count = 0;
4739 unsigned int i = info->tbuf_current;
4740 unsigned int reg_value;
4741 unsigned int count;
4742 unsigned int active_buf_count = 0;
4743
4744 /*
4745 * Add descriptor counts for all tx DMA buffers.
4746 * If count is zero (cleared by DMA controller after read),
4747 * the buffer is complete or is actively being read from.
4748 *
4749 * Record buf_count of last buffer with zero count starting
4750 * from current ring position. buf_count is mirror
4751 * copy of count and is not cleared by serial controller.
4752 * If DMA controller is active, that buffer is actively
4753 * being read so add to total.
4754 */
4755 do {
4756 count = desc_count(info->tbufs[i]);
4757 if (count)
4758 total_count += count;
4759 else if (!total_count)
4760 active_buf_count = info->tbufs[i].buf_count;
4761 if (++i == info->tbuf_count)
4762 i = 0;
4763 } while (i != info->tbuf_current);
4764
4765 /* read tx DMA status register */
4766 reg_value = rd_reg32(info, TDCSR);
4767
4768 /* if tx DMA active, last zero count buffer is in use */
4769 if (reg_value & BIT0)
4770 total_count += active_buf_count;
4771
4772 /* add tx FIFO count = reg_value[15..8] */
4773 total_count += (reg_value >> 8) & 0xff;
4774
4775 /* if transmitter active add one byte for shift register */
4776 if (info->tx_active)
4777 total_count++;
4778
4779 return total_count;
4780 }
4781
4782 /*
4783 * load data into transmit DMA buffer ring and start transmitter if needed
4784 * return true if data accepted, otherwise false (buffers full)
4785 */
tx_load(struct slgt_info * info,const char * buf,unsigned int size)4786 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4787 {
4788 unsigned short count;
4789 unsigned int i;
4790 struct slgt_desc *d;
4791
4792 /* check required buffer space */
4793 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4794 return false;
4795
4796 DBGDATA(info, buf, size, "tx");
4797
4798 /*
4799 * copy data to one or more DMA buffers in circular ring
4800 * tbuf_start = first buffer for this data
4801 * tbuf_current = next free buffer
4802 *
4803 * Copy all data before making data visible to DMA controller by
4804 * setting descriptor count of the first buffer.
4805 * This prevents an active DMA controller from reading the first DMA
4806 * buffers of a frame and stopping before the final buffers are filled.
4807 */
4808
4809 info->tbuf_start = i = info->tbuf_current;
4810
4811 while (size) {
4812 d = &info->tbufs[i];
4813
4814 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4815 memcpy(d->buf, buf, count);
4816
4817 size -= count;
4818 buf += count;
4819
4820 /*
4821 * set EOF bit for last buffer of HDLC frame or
4822 * for every buffer in raw mode
4823 */
4824 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4825 info->params.mode == MGSL_MODE_RAW)
4826 set_desc_eof(*d, 1);
4827 else
4828 set_desc_eof(*d, 0);
4829
4830 /* set descriptor count for all but first buffer */
4831 if (i != info->tbuf_start)
4832 set_desc_count(*d, count);
4833 d->buf_count = count;
4834
4835 if (++i == info->tbuf_count)
4836 i = 0;
4837 }
4838
4839 info->tbuf_current = i;
4840
4841 /* set first buffer count to make new data visible to DMA controller */
4842 d = &info->tbufs[info->tbuf_start];
4843 set_desc_count(*d, d->buf_count);
4844
4845 /* start transmitter if needed and update transmit timeout */
4846 if (!info->tx_active)
4847 tx_start(info);
4848 update_tx_timer(info);
4849
4850 return true;
4851 }
4852
register_test(struct slgt_info * info)4853 static int register_test(struct slgt_info *info)
4854 {
4855 static unsigned short patterns[] =
4856 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4857 static unsigned int count = ARRAY_SIZE(patterns);
4858 unsigned int i;
4859 int rc = 0;
4860
4861 for (i=0 ; i < count ; i++) {
4862 wr_reg16(info, TIR, patterns[i]);
4863 wr_reg16(info, BDR, patterns[(i+1)%count]);
4864 if ((rd_reg16(info, TIR) != patterns[i]) ||
4865 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4866 rc = -ENODEV;
4867 break;
4868 }
4869 }
4870 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4871 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4872 return rc;
4873 }
4874
irq_test(struct slgt_info * info)4875 static int irq_test(struct slgt_info *info)
4876 {
4877 unsigned long timeout;
4878 unsigned long flags;
4879 struct tty_struct *oldtty = info->port.tty;
4880 u32 speed = info->params.data_rate;
4881
4882 info->params.data_rate = 921600;
4883 info->port.tty = NULL;
4884
4885 spin_lock_irqsave(&info->lock, flags);
4886 async_mode(info);
4887 slgt_irq_on(info, IRQ_TXIDLE);
4888
4889 /* enable transmitter */
4890 wr_reg16(info, TCR,
4891 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4892
4893 /* write one byte and wait for tx idle */
4894 wr_reg16(info, TDR, 0);
4895
4896 /* assume failure */
4897 info->init_error = DiagStatus_IrqFailure;
4898 info->irq_occurred = false;
4899
4900 spin_unlock_irqrestore(&info->lock, flags);
4901
4902 timeout=100;
4903 while(timeout-- && !info->irq_occurred)
4904 msleep_interruptible(10);
4905
4906 spin_lock_irqsave(&info->lock,flags);
4907 reset_port(info);
4908 spin_unlock_irqrestore(&info->lock,flags);
4909
4910 info->params.data_rate = speed;
4911 info->port.tty = oldtty;
4912
4913 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4914 return info->irq_occurred ? 0 : -ENODEV;
4915 }
4916
loopback_test_rx(struct slgt_info * info)4917 static int loopback_test_rx(struct slgt_info *info)
4918 {
4919 unsigned char *src, *dest;
4920 int count;
4921
4922 if (desc_complete(info->rbufs[0])) {
4923 count = desc_count(info->rbufs[0]);
4924 src = info->rbufs[0].buf;
4925 dest = info->tmp_rbuf;
4926
4927 for( ; count ; count-=2, src+=2) {
4928 /* src=data byte (src+1)=status byte */
4929 if (!(*(src+1) & (BIT9 + BIT8))) {
4930 *dest = *src;
4931 dest++;
4932 info->tmp_rbuf_count++;
4933 }
4934 }
4935 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4936 return 1;
4937 }
4938 return 0;
4939 }
4940
loopback_test(struct slgt_info * info)4941 static int loopback_test(struct slgt_info *info)
4942 {
4943 #define TESTFRAMESIZE 20
4944
4945 unsigned long timeout;
4946 u16 count;
4947 unsigned char buf[TESTFRAMESIZE];
4948 int rc = -ENODEV;
4949 unsigned long flags;
4950
4951 struct tty_struct *oldtty = info->port.tty;
4952 MGSL_PARAMS params;
4953
4954 memcpy(¶ms, &info->params, sizeof(params));
4955
4956 info->params.mode = MGSL_MODE_ASYNC;
4957 info->params.data_rate = 921600;
4958 info->params.loopback = 1;
4959 info->port.tty = NULL;
4960
4961 /* build and send transmit frame */
4962 for (count = 0; count < TESTFRAMESIZE; ++count)
4963 buf[count] = (unsigned char)count;
4964
4965 info->tmp_rbuf_count = 0;
4966 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4967
4968 /* program hardware for HDLC and enabled receiver */
4969 spin_lock_irqsave(&info->lock,flags);
4970 async_mode(info);
4971 rx_start(info);
4972 tx_load(info, buf, count);
4973 spin_unlock_irqrestore(&info->lock, flags);
4974
4975 /* wait for receive complete */
4976 for (timeout = 100; timeout; --timeout) {
4977 msleep_interruptible(10);
4978 if (loopback_test_rx(info)) {
4979 rc = 0;
4980 break;
4981 }
4982 }
4983
4984 /* verify received frame length and contents */
4985 if (!rc && (info->tmp_rbuf_count != count ||
4986 memcmp(buf, info->tmp_rbuf, count))) {
4987 rc = -ENODEV;
4988 }
4989
4990 spin_lock_irqsave(&info->lock,flags);
4991 reset_adapter(info);
4992 spin_unlock_irqrestore(&info->lock,flags);
4993
4994 memcpy(&info->params, ¶ms, sizeof(info->params));
4995 info->port.tty = oldtty;
4996
4997 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4998 return rc;
4999 }
5000
adapter_test(struct slgt_info * info)5001 static int adapter_test(struct slgt_info *info)
5002 {
5003 DBGINFO(("testing %s\n", info->device_name));
5004 if (register_test(info) < 0) {
5005 printk("register test failure %s addr=%08X\n",
5006 info->device_name, info->phys_reg_addr);
5007 } else if (irq_test(info) < 0) {
5008 printk("IRQ test failure %s IRQ=%d\n",
5009 info->device_name, info->irq_level);
5010 } else if (loopback_test(info) < 0) {
5011 printk("loopback test failure %s\n", info->device_name);
5012 }
5013 return info->init_error;
5014 }
5015
5016 /*
5017 * transmit timeout handler
5018 */
tx_timeout(struct timer_list * t)5019 static void tx_timeout(struct timer_list *t)
5020 {
5021 struct slgt_info *info = from_timer(info, t, tx_timer);
5022 unsigned long flags;
5023
5024 DBGINFO(("%s tx_timeout\n", info->device_name));
5025 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5026 info->icount.txtimeout++;
5027 }
5028 spin_lock_irqsave(&info->lock,flags);
5029 tx_stop(info);
5030 spin_unlock_irqrestore(&info->lock,flags);
5031
5032 #if SYNCLINK_GENERIC_HDLC
5033 if (info->netcount)
5034 hdlcdev_tx_done(info);
5035 else
5036 #endif
5037 bh_transmit(info);
5038 }
5039
5040 /*
5041 * receive buffer polling timer
5042 */
rx_timeout(struct timer_list * t)5043 static void rx_timeout(struct timer_list *t)
5044 {
5045 struct slgt_info *info = from_timer(info, t, rx_timer);
5046 unsigned long flags;
5047
5048 DBGINFO(("%s rx_timeout\n", info->device_name));
5049 spin_lock_irqsave(&info->lock, flags);
5050 info->pending_bh |= BH_RECEIVE;
5051 spin_unlock_irqrestore(&info->lock, flags);
5052 bh_handler(&info->task);
5053 }
5054
5055