1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 */
9 #include <asm/fpu/api.h>
10 #include <asm/fpu/regset.h>
11 #include <asm/fpu/sched.h>
12 #include <asm/fpu/signal.h>
13 #include <asm/fpu/types.h>
14 #include <asm/traps.h>
15 #include <asm/irq_regs.h>
16
17 #include <uapi/asm/kvm.h>
18
19 #include <linux/hardirq.h>
20 #include <linux/pkeys.h>
21 #include <linux/vmalloc.h>
22
23 #include "context.h"
24 #include "internal.h"
25 #include "legacy.h"
26 #include "xstate.h"
27
28 #define CREATE_TRACE_POINTS
29 #include <asm/trace/fpu.h>
30
31 #ifdef CONFIG_X86_64
32 DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic);
33 DEFINE_PER_CPU(u64, xfd_state);
34 #endif
35
36 /* The FPU state configuration data for kernel and user space */
37 struct fpu_state_config fpu_kernel_cfg __ro_after_init;
38 struct fpu_state_config fpu_user_cfg __ro_after_init;
39
40 /*
41 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
42 * depending on the FPU hardware format:
43 */
44 struct fpstate init_fpstate __ro_after_init;
45
46 /* Track in-kernel FPU usage */
47 static DEFINE_PER_CPU(bool, in_kernel_fpu);
48
49 /*
50 * Track which context is using the FPU on the CPU:
51 */
52 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
53
54 /*
55 * Can we use the FPU in kernel mode with the
56 * whole "kernel_fpu_begin/end()" sequence?
57 */
irq_fpu_usable(void)58 bool irq_fpu_usable(void)
59 {
60 if (WARN_ON_ONCE(in_nmi()))
61 return false;
62
63 /* In kernel FPU usage already active? */
64 if (this_cpu_read(in_kernel_fpu))
65 return false;
66
67 /*
68 * When not in NMI or hard interrupt context, FPU can be used in:
69 *
70 * - Task context except from within fpregs_lock()'ed critical
71 * regions.
72 *
73 * - Soft interrupt processing context which cannot happen
74 * while in a fpregs_lock()'ed critical region.
75 */
76 if (!in_hardirq())
77 return true;
78
79 /*
80 * In hard interrupt context it's safe when soft interrupts
81 * are enabled, which means the interrupt did not hit in
82 * a fpregs_lock()'ed critical region.
83 */
84 return !softirq_count();
85 }
86 EXPORT_SYMBOL(irq_fpu_usable);
87
88 /*
89 * Track AVX512 state use because it is known to slow the max clock
90 * speed of the core.
91 */
update_avx_timestamp(struct fpu * fpu)92 static void update_avx_timestamp(struct fpu *fpu)
93 {
94
95 #define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
96
97 if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK)
98 fpu->avx512_timestamp = jiffies;
99 }
100
101 /*
102 * Save the FPU register state in fpu->fpstate->regs. The register state is
103 * preserved.
104 *
105 * Must be called with fpregs_lock() held.
106 *
107 * The legacy FNSAVE instruction clears all FPU state unconditionally, so
108 * register state has to be reloaded. That might be a pointless exercise
109 * when the FPU is going to be used by another task right after that. But
110 * this only affects 20+ years old 32bit systems and avoids conditionals all
111 * over the place.
112 *
113 * FXSAVE and all XSAVE variants preserve the FPU register state.
114 */
save_fpregs_to_fpstate(struct fpu * fpu)115 void save_fpregs_to_fpstate(struct fpu *fpu)
116 {
117 if (likely(use_xsave())) {
118 os_xsave(fpu->fpstate);
119 update_avx_timestamp(fpu);
120 return;
121 }
122
123 if (likely(use_fxsr())) {
124 fxsave(&fpu->fpstate->regs.fxsave);
125 return;
126 }
127
128 /*
129 * Legacy FPU register saving, FNSAVE always clears FPU registers,
130 * so we have to reload them from the memory state.
131 */
132 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->fpstate->regs.fsave));
133 frstor(&fpu->fpstate->regs.fsave);
134 }
135
restore_fpregs_from_fpstate(struct fpstate * fpstate,u64 mask)136 void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask)
137 {
138 /*
139 * AMD K7/K8 and later CPUs up to Zen don't save/restore
140 * FDP/FIP/FOP unless an exception is pending. Clear the x87 state
141 * here by setting it to fixed values. "m" is a random variable
142 * that should be in L1.
143 */
144 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
145 asm volatile(
146 "fnclex\n\t"
147 "emms\n\t"
148 "fildl %P[addr]" /* set F?P to defined value */
149 : : [addr] "m" (fpstate));
150 }
151
152 if (use_xsave()) {
153 /*
154 * Dynamically enabled features are enabled in XCR0, but
155 * usage requires also that the corresponding bits in XFD
156 * are cleared. If the bits are set then using a related
157 * instruction will raise #NM. This allows to do the
158 * allocation of the larger FPU buffer lazy from #NM or if
159 * the task has no permission to kill it which would happen
160 * via #UD if the feature is disabled in XCR0.
161 *
162 * XFD state is following the same life time rules as
163 * XSTATE and to restore state correctly XFD has to be
164 * updated before XRSTORS otherwise the component would
165 * stay in or go into init state even if the bits are set
166 * in fpstate::regs::xsave::xfeatures.
167 */
168 xfd_update_state(fpstate);
169
170 /*
171 * Restoring state always needs to modify all features
172 * which are in @mask even if the current task cannot use
173 * extended features.
174 *
175 * So fpstate->xfeatures cannot be used here, because then
176 * a feature for which the task has no permission but was
177 * used by the previous task would not go into init state.
178 */
179 mask = fpu_kernel_cfg.max_features & mask;
180
181 os_xrstor(fpstate, mask);
182 } else {
183 if (use_fxsr())
184 fxrstor(&fpstate->regs.fxsave);
185 else
186 frstor(&fpstate->regs.fsave);
187 }
188 }
189
fpu_reset_from_exception_fixup(void)190 void fpu_reset_from_exception_fixup(void)
191 {
192 restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_FPSTATE);
193 }
194
195 #if IS_ENABLED(CONFIG_KVM)
196 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd);
197
fpu_init_guest_permissions(struct fpu_guest * gfpu)198 static void fpu_init_guest_permissions(struct fpu_guest *gfpu)
199 {
200 struct fpu_state_perm *fpuperm;
201 u64 perm;
202
203 if (!IS_ENABLED(CONFIG_X86_64))
204 return;
205
206 spin_lock_irq(¤t->sighand->siglock);
207 fpuperm = ¤t->group_leader->thread.fpu.guest_perm;
208 perm = fpuperm->__state_perm;
209
210 /* First fpstate allocation locks down permissions. */
211 WRITE_ONCE(fpuperm->__state_perm, perm | FPU_GUEST_PERM_LOCKED);
212
213 spin_unlock_irq(¤t->sighand->siglock);
214
215 gfpu->perm = perm & ~FPU_GUEST_PERM_LOCKED;
216 }
217
fpu_alloc_guest_fpstate(struct fpu_guest * gfpu)218 bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu)
219 {
220 struct fpstate *fpstate;
221 unsigned int size;
222
223 size = fpu_user_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64);
224 fpstate = vzalloc(size);
225 if (!fpstate)
226 return false;
227
228 /* Leave xfd to 0 (the reset value defined by spec) */
229 __fpstate_reset(fpstate, 0);
230 fpstate_init_user(fpstate);
231 fpstate->is_valloc = true;
232 fpstate->is_guest = true;
233
234 gfpu->fpstate = fpstate;
235 gfpu->xfeatures = fpu_user_cfg.default_features;
236 gfpu->perm = fpu_user_cfg.default_features;
237
238 /*
239 * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state
240 * to userspace, even when XSAVE is unsupported, so that restoring FPU
241 * state on a different CPU that does support XSAVE can cleanly load
242 * the incoming state using its natural XSAVE. In other words, KVM's
243 * uABI size may be larger than this host's default size. Conversely,
244 * the default size should never be larger than KVM's base uABI size;
245 * all features that can expand the uABI size must be opt-in.
246 */
247 gfpu->uabi_size = sizeof(struct kvm_xsave);
248 if (WARN_ON_ONCE(fpu_user_cfg.default_size > gfpu->uabi_size))
249 gfpu->uabi_size = fpu_user_cfg.default_size;
250
251 fpu_init_guest_permissions(gfpu);
252
253 return true;
254 }
255 EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate);
256
fpu_free_guest_fpstate(struct fpu_guest * gfpu)257 void fpu_free_guest_fpstate(struct fpu_guest *gfpu)
258 {
259 struct fpstate *fps = gfpu->fpstate;
260
261 if (!fps)
262 return;
263
264 if (WARN_ON_ONCE(!fps->is_valloc || !fps->is_guest || fps->in_use))
265 return;
266
267 gfpu->fpstate = NULL;
268 vfree(fps);
269 }
270 EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate);
271
272 /*
273 * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
274 * @guest_fpu: Pointer to the guest FPU container
275 * @xfeatures: Features requested by guest CPUID
276 *
277 * Enable all dynamic xfeatures according to guest perm and requested CPUID.
278 *
279 * Return: 0 on success, error code otherwise
280 */
fpu_enable_guest_xfd_features(struct fpu_guest * guest_fpu,u64 xfeatures)281 int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures)
282 {
283 lockdep_assert_preemption_enabled();
284
285 /* Nothing to do if all requested features are already enabled. */
286 xfeatures &= ~guest_fpu->xfeatures;
287 if (!xfeatures)
288 return 0;
289
290 return __xfd_enable_feature(xfeatures, guest_fpu);
291 }
292 EXPORT_SYMBOL_GPL(fpu_enable_guest_xfd_features);
293
294 #ifdef CONFIG_X86_64
fpu_update_guest_xfd(struct fpu_guest * guest_fpu,u64 xfd)295 void fpu_update_guest_xfd(struct fpu_guest *guest_fpu, u64 xfd)
296 {
297 fpregs_lock();
298 guest_fpu->fpstate->xfd = xfd;
299 if (guest_fpu->fpstate->in_use)
300 xfd_update_state(guest_fpu->fpstate);
301 fpregs_unlock();
302 }
303 EXPORT_SYMBOL_GPL(fpu_update_guest_xfd);
304
305 /**
306 * fpu_sync_guest_vmexit_xfd_state - Synchronize XFD MSR and software state
307 *
308 * Must be invoked from KVM after a VMEXIT before enabling interrupts when
309 * XFD write emulation is disabled. This is required because the guest can
310 * freely modify XFD and the state at VMEXIT is not guaranteed to be the
311 * same as the state on VMENTER. So software state has to be udpated before
312 * any operation which depends on it can take place.
313 *
314 * Note: It can be invoked unconditionally even when write emulation is
315 * enabled for the price of a then pointless MSR read.
316 */
fpu_sync_guest_vmexit_xfd_state(void)317 void fpu_sync_guest_vmexit_xfd_state(void)
318 {
319 struct fpstate *fps = current->thread.fpu.fpstate;
320
321 lockdep_assert_irqs_disabled();
322 if (fpu_state_size_dynamic()) {
323 rdmsrl(MSR_IA32_XFD, fps->xfd);
324 __this_cpu_write(xfd_state, fps->xfd);
325 }
326 }
327 EXPORT_SYMBOL_GPL(fpu_sync_guest_vmexit_xfd_state);
328 #endif /* CONFIG_X86_64 */
329
fpu_swap_kvm_fpstate(struct fpu_guest * guest_fpu,bool enter_guest)330 int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest)
331 {
332 struct fpstate *guest_fps = guest_fpu->fpstate;
333 struct fpu *fpu = ¤t->thread.fpu;
334 struct fpstate *cur_fps = fpu->fpstate;
335
336 fpregs_lock();
337 if (!cur_fps->is_confidential && !test_thread_flag(TIF_NEED_FPU_LOAD))
338 save_fpregs_to_fpstate(fpu);
339
340 /* Swap fpstate */
341 if (enter_guest) {
342 fpu->__task_fpstate = cur_fps;
343 fpu->fpstate = guest_fps;
344 guest_fps->in_use = true;
345 } else {
346 guest_fps->in_use = false;
347 fpu->fpstate = fpu->__task_fpstate;
348 fpu->__task_fpstate = NULL;
349 }
350
351 cur_fps = fpu->fpstate;
352
353 if (!cur_fps->is_confidential) {
354 /* Includes XFD update */
355 restore_fpregs_from_fpstate(cur_fps, XFEATURE_MASK_FPSTATE);
356 } else {
357 /*
358 * XSTATE is restored by firmware from encrypted
359 * memory. Make sure XFD state is correct while
360 * running with guest fpstate
361 */
362 xfd_update_state(cur_fps);
363 }
364
365 fpregs_mark_activate();
366 fpregs_unlock();
367 return 0;
368 }
369 EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate);
370
fpu_copy_guest_fpstate_to_uabi(struct fpu_guest * gfpu,void * buf,unsigned int size,u32 pkru)371 void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf,
372 unsigned int size, u32 pkru)
373 {
374 struct fpstate *kstate = gfpu->fpstate;
375 union fpregs_state *ustate = buf;
376 struct membuf mb = { .p = buf, .left = size };
377
378 if (cpu_feature_enabled(X86_FEATURE_XSAVE)) {
379 __copy_xstate_to_uabi_buf(mb, kstate, pkru, XSTATE_COPY_XSAVE);
380 } else {
381 memcpy(&ustate->fxsave, &kstate->regs.fxsave,
382 sizeof(ustate->fxsave));
383 /* Make it restorable on a XSAVE enabled host */
384 ustate->xsave.header.xfeatures = XFEATURE_MASK_FPSSE;
385 }
386 }
387 EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi);
388
fpu_copy_uabi_to_guest_fpstate(struct fpu_guest * gfpu,const void * buf,u64 xcr0,u32 * vpkru)389 int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf,
390 u64 xcr0, u32 *vpkru)
391 {
392 struct fpstate *kstate = gfpu->fpstate;
393 const union fpregs_state *ustate = buf;
394
395 if (!cpu_feature_enabled(X86_FEATURE_XSAVE)) {
396 if (ustate->xsave.header.xfeatures & ~XFEATURE_MASK_FPSSE)
397 return -EINVAL;
398 if (ustate->fxsave.mxcsr & ~mxcsr_feature_mask)
399 return -EINVAL;
400 memcpy(&kstate->regs.fxsave, &ustate->fxsave, sizeof(ustate->fxsave));
401 return 0;
402 }
403
404 if (ustate->xsave.header.xfeatures & ~xcr0)
405 return -EINVAL;
406
407 /*
408 * Nullify @vpkru to preserve its current value if PKRU's bit isn't set
409 * in the header. KVM's odd ABI is to leave PKRU untouched in this
410 * case (all other components are eventually re-initialized).
411 */
412 if (!(ustate->xsave.header.xfeatures & XFEATURE_MASK_PKRU))
413 vpkru = NULL;
414
415 return copy_uabi_from_kernel_to_xstate(kstate, ustate, vpkru);
416 }
417 EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate);
418 #endif /* CONFIG_KVM */
419
kernel_fpu_begin_mask(unsigned int kfpu_mask)420 void kernel_fpu_begin_mask(unsigned int kfpu_mask)
421 {
422 preempt_disable();
423
424 WARN_ON_FPU(!irq_fpu_usable());
425 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
426
427 this_cpu_write(in_kernel_fpu, true);
428
429 if (!(current->flags & PF_KTHREAD) &&
430 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
431 set_thread_flag(TIF_NEED_FPU_LOAD);
432 save_fpregs_to_fpstate(¤t->thread.fpu);
433 }
434 __cpu_invalidate_fpregs_state();
435
436 /* Put sane initial values into the control registers. */
437 if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM))
438 ldmxcsr(MXCSR_DEFAULT);
439
440 if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU))
441 asm volatile ("fninit");
442 }
443 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask);
444
kernel_fpu_end(void)445 void kernel_fpu_end(void)
446 {
447 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
448
449 this_cpu_write(in_kernel_fpu, false);
450 preempt_enable();
451 }
452 EXPORT_SYMBOL_GPL(kernel_fpu_end);
453
454 /*
455 * Sync the FPU register state to current's memory register state when the
456 * current task owns the FPU. The hardware register state is preserved.
457 */
fpu_sync_fpstate(struct fpu * fpu)458 void fpu_sync_fpstate(struct fpu *fpu)
459 {
460 WARN_ON_FPU(fpu != ¤t->thread.fpu);
461
462 fpregs_lock();
463 trace_x86_fpu_before_save(fpu);
464
465 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
466 save_fpregs_to_fpstate(fpu);
467
468 trace_x86_fpu_after_save(fpu);
469 fpregs_unlock();
470 }
471
init_fpstate_copy_size(void)472 static inline unsigned int init_fpstate_copy_size(void)
473 {
474 if (!use_xsave())
475 return fpu_kernel_cfg.default_size;
476
477 /* XSAVE(S) just needs the legacy and the xstate header part */
478 return sizeof(init_fpstate.regs.xsave);
479 }
480
fpstate_init_fxstate(struct fpstate * fpstate)481 static inline void fpstate_init_fxstate(struct fpstate *fpstate)
482 {
483 fpstate->regs.fxsave.cwd = 0x37f;
484 fpstate->regs.fxsave.mxcsr = MXCSR_DEFAULT;
485 }
486
487 /*
488 * Legacy x87 fpstate state init:
489 */
fpstate_init_fstate(struct fpstate * fpstate)490 static inline void fpstate_init_fstate(struct fpstate *fpstate)
491 {
492 fpstate->regs.fsave.cwd = 0xffff037fu;
493 fpstate->regs.fsave.swd = 0xffff0000u;
494 fpstate->regs.fsave.twd = 0xffffffffu;
495 fpstate->regs.fsave.fos = 0xffff0000u;
496 }
497
498 /*
499 * Used in two places:
500 * 1) Early boot to setup init_fpstate for non XSAVE systems
501 * 2) fpu_init_fpstate_user() which is invoked from KVM
502 */
fpstate_init_user(struct fpstate * fpstate)503 void fpstate_init_user(struct fpstate *fpstate)
504 {
505 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
506 fpstate_init_soft(&fpstate->regs.soft);
507 return;
508 }
509
510 xstate_init_xcomp_bv(&fpstate->regs.xsave, fpstate->xfeatures);
511
512 if (cpu_feature_enabled(X86_FEATURE_FXSR))
513 fpstate_init_fxstate(fpstate);
514 else
515 fpstate_init_fstate(fpstate);
516 }
517
__fpstate_reset(struct fpstate * fpstate,u64 xfd)518 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd)
519 {
520 /* Initialize sizes and feature masks */
521 fpstate->size = fpu_kernel_cfg.default_size;
522 fpstate->user_size = fpu_user_cfg.default_size;
523 fpstate->xfeatures = fpu_kernel_cfg.default_features;
524 fpstate->user_xfeatures = fpu_user_cfg.default_features;
525 fpstate->xfd = xfd;
526 }
527
fpstate_reset(struct fpu * fpu)528 void fpstate_reset(struct fpu *fpu)
529 {
530 /* Set the fpstate pointer to the default fpstate */
531 fpu->fpstate = &fpu->__fpstate;
532 __fpstate_reset(fpu->fpstate, init_fpstate.xfd);
533
534 /* Initialize the permission related info in fpu */
535 fpu->perm.__state_perm = fpu_kernel_cfg.default_features;
536 fpu->perm.__state_size = fpu_kernel_cfg.default_size;
537 fpu->perm.__user_state_size = fpu_user_cfg.default_size;
538 /* Same defaults for guests */
539 fpu->guest_perm = fpu->perm;
540 }
541
fpu_inherit_perms(struct fpu * dst_fpu)542 static inline void fpu_inherit_perms(struct fpu *dst_fpu)
543 {
544 if (fpu_state_size_dynamic()) {
545 struct fpu *src_fpu = ¤t->group_leader->thread.fpu;
546
547 spin_lock_irq(¤t->sighand->siglock);
548 /* Fork also inherits the permissions of the parent */
549 dst_fpu->perm = src_fpu->perm;
550 dst_fpu->guest_perm = src_fpu->guest_perm;
551 spin_unlock_irq(¤t->sighand->siglock);
552 }
553 }
554
555 /* Clone current's FPU state on fork */
fpu_clone(struct task_struct * dst,unsigned long clone_flags,bool minimal)556 int fpu_clone(struct task_struct *dst, unsigned long clone_flags, bool minimal)
557 {
558 struct fpu *src_fpu = ¤t->thread.fpu;
559 struct fpu *dst_fpu = &dst->thread.fpu;
560
561 /* The new task's FPU state cannot be valid in the hardware. */
562 dst_fpu->last_cpu = -1;
563
564 fpstate_reset(dst_fpu);
565
566 if (!cpu_feature_enabled(X86_FEATURE_FPU))
567 return 0;
568
569 /*
570 * Enforce reload for user space tasks and prevent kernel threads
571 * from trying to save the FPU registers on context switch.
572 */
573 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
574
575 /*
576 * No FPU state inheritance for kernel threads and IO
577 * worker threads.
578 */
579 if (minimal) {
580 /* Clear out the minimal state */
581 memcpy(&dst_fpu->fpstate->regs, &init_fpstate.regs,
582 init_fpstate_copy_size());
583 return 0;
584 }
585
586 /*
587 * If a new feature is added, ensure all dynamic features are
588 * caller-saved from here!
589 */
590 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
591
592 /*
593 * Save the default portion of the current FPU state into the
594 * clone. Assume all dynamic features to be defined as caller-
595 * saved, which enables skipping both the expansion of fpstate
596 * and the copying of any dynamic state.
597 *
598 * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because
599 * copying is not valid when current uses non-default states.
600 */
601 fpregs_lock();
602 if (test_thread_flag(TIF_NEED_FPU_LOAD))
603 fpregs_restore_userregs();
604 save_fpregs_to_fpstate(dst_fpu);
605 fpregs_unlock();
606 if (!(clone_flags & CLONE_THREAD))
607 fpu_inherit_perms(dst_fpu);
608
609 /*
610 * Children never inherit PASID state.
611 * Force it to have its init value:
612 */
613 if (use_xsave())
614 dst_fpu->fpstate->regs.xsave.header.xfeatures &= ~XFEATURE_MASK_PASID;
615
616 trace_x86_fpu_copy_src(src_fpu);
617 trace_x86_fpu_copy_dst(dst_fpu);
618
619 return 0;
620 }
621
622 /*
623 * Whitelist the FPU register state embedded into task_struct for hardened
624 * usercopy.
625 */
fpu_thread_struct_whitelist(unsigned long * offset,unsigned long * size)626 void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size)
627 {
628 *offset = offsetof(struct thread_struct, fpu.__fpstate.regs);
629 *size = fpu_kernel_cfg.default_size;
630 }
631
632 /*
633 * Drops current FPU state: deactivates the fpregs and
634 * the fpstate. NOTE: it still leaves previous contents
635 * in the fpregs in the eager-FPU case.
636 *
637 * This function can be used in cases where we know that
638 * a state-restore is coming: either an explicit one,
639 * or a reschedule.
640 */
fpu__drop(struct fpu * fpu)641 void fpu__drop(struct fpu *fpu)
642 {
643 preempt_disable();
644
645 if (fpu == ¤t->thread.fpu) {
646 /* Ignore delayed exceptions from user space */
647 asm volatile("1: fwait\n"
648 "2:\n"
649 _ASM_EXTABLE(1b, 2b));
650 fpregs_deactivate(fpu);
651 }
652
653 trace_x86_fpu_dropped(fpu);
654
655 preempt_enable();
656 }
657
658 /*
659 * Clear FPU registers by setting them up from the init fpstate.
660 * Caller must do fpregs_[un]lock() around it.
661 */
restore_fpregs_from_init_fpstate(u64 features_mask)662 static inline void restore_fpregs_from_init_fpstate(u64 features_mask)
663 {
664 if (use_xsave())
665 os_xrstor(&init_fpstate, features_mask);
666 else if (use_fxsr())
667 fxrstor(&init_fpstate.regs.fxsave);
668 else
669 frstor(&init_fpstate.regs.fsave);
670
671 pkru_write_default();
672 }
673
674 /*
675 * Reset current->fpu memory state to the init values.
676 */
fpu_reset_fpregs(void)677 static void fpu_reset_fpregs(void)
678 {
679 struct fpu *fpu = ¤t->thread.fpu;
680
681 fpregs_lock();
682 fpu__drop(fpu);
683 /*
684 * This does not change the actual hardware registers. It just
685 * resets the memory image and sets TIF_NEED_FPU_LOAD so a
686 * subsequent return to usermode will reload the registers from the
687 * task's memory image.
688 *
689 * Do not use fpstate_init() here. Just copy init_fpstate which has
690 * the correct content already except for PKRU.
691 *
692 * PKRU handling does not rely on the xstate when restoring for
693 * user space as PKRU is eagerly written in switch_to() and
694 * flush_thread().
695 */
696 memcpy(&fpu->fpstate->regs, &init_fpstate.regs, init_fpstate_copy_size());
697 set_thread_flag(TIF_NEED_FPU_LOAD);
698 fpregs_unlock();
699 }
700
701 /*
702 * Reset current's user FPU states to the init states. current's
703 * supervisor states, if any, are not modified by this function. The
704 * caller guarantees that the XSTATE header in memory is intact.
705 */
fpu__clear_user_states(struct fpu * fpu)706 void fpu__clear_user_states(struct fpu *fpu)
707 {
708 WARN_ON_FPU(fpu != ¤t->thread.fpu);
709
710 fpregs_lock();
711 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
712 fpu_reset_fpregs();
713 fpregs_unlock();
714 return;
715 }
716
717 /*
718 * Ensure that current's supervisor states are loaded into their
719 * corresponding registers.
720 */
721 if (xfeatures_mask_supervisor() &&
722 !fpregs_state_valid(fpu, smp_processor_id()))
723 os_xrstor_supervisor(fpu->fpstate);
724
725 /* Reset user states in registers. */
726 restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE);
727
728 /*
729 * Now all FPU registers have their desired values. Inform the FPU
730 * state machine that current's FPU registers are in the hardware
731 * registers. The memory image does not need to be updated because
732 * any operation relying on it has to save the registers first when
733 * current's FPU is marked active.
734 */
735 fpregs_mark_activate();
736 fpregs_unlock();
737 }
738
fpu_flush_thread(void)739 void fpu_flush_thread(void)
740 {
741 fpstate_reset(¤t->thread.fpu);
742 fpu_reset_fpregs();
743 }
744 /*
745 * Load FPU context before returning to userspace.
746 */
switch_fpu_return(void)747 void switch_fpu_return(void)
748 {
749 if (!static_cpu_has(X86_FEATURE_FPU))
750 return;
751
752 fpregs_restore_userregs();
753 }
754 EXPORT_SYMBOL_GPL(switch_fpu_return);
755
756 #ifdef CONFIG_X86_DEBUG_FPU
757 /*
758 * If current FPU state according to its tracking (loaded FPU context on this
759 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
760 * loaded on return to userland.
761 */
fpregs_assert_state_consistent(void)762 void fpregs_assert_state_consistent(void)
763 {
764 struct fpu *fpu = ¤t->thread.fpu;
765
766 if (test_thread_flag(TIF_NEED_FPU_LOAD))
767 return;
768
769 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
770 }
771 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
772 #endif
773
fpregs_mark_activate(void)774 void fpregs_mark_activate(void)
775 {
776 struct fpu *fpu = ¤t->thread.fpu;
777
778 fpregs_activate(fpu);
779 fpu->last_cpu = smp_processor_id();
780 clear_thread_flag(TIF_NEED_FPU_LOAD);
781 }
782
783 /*
784 * x87 math exception handling:
785 */
786
fpu__exception_code(struct fpu * fpu,int trap_nr)787 int fpu__exception_code(struct fpu *fpu, int trap_nr)
788 {
789 int err;
790
791 if (trap_nr == X86_TRAP_MF) {
792 unsigned short cwd, swd;
793 /*
794 * (~cwd & swd) will mask out exceptions that are not set to unmasked
795 * status. 0x3f is the exception bits in these regs, 0x200 is the
796 * C1 reg you need in case of a stack fault, 0x040 is the stack
797 * fault bit. We should only be taking one exception at a time,
798 * so if this combination doesn't produce any single exception,
799 * then we have a bad program that isn't synchronizing its FPU usage
800 * and it will suffer the consequences since we won't be able to
801 * fully reproduce the context of the exception.
802 */
803 if (boot_cpu_has(X86_FEATURE_FXSR)) {
804 cwd = fpu->fpstate->regs.fxsave.cwd;
805 swd = fpu->fpstate->regs.fxsave.swd;
806 } else {
807 cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd;
808 swd = (unsigned short)fpu->fpstate->regs.fsave.swd;
809 }
810
811 err = swd & ~cwd;
812 } else {
813 /*
814 * The SIMD FPU exceptions are handled a little differently, as there
815 * is only a single status/control register. Thus, to determine which
816 * unmasked exception was caught we must mask the exception mask bits
817 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
818 */
819 unsigned short mxcsr = MXCSR_DEFAULT;
820
821 if (boot_cpu_has(X86_FEATURE_XMM))
822 mxcsr = fpu->fpstate->regs.fxsave.mxcsr;
823
824 err = ~(mxcsr >> 7) & mxcsr;
825 }
826
827 if (err & 0x001) { /* Invalid op */
828 /*
829 * swd & 0x240 == 0x040: Stack Underflow
830 * swd & 0x240 == 0x240: Stack Overflow
831 * User must clear the SF bit (0x40) if set
832 */
833 return FPE_FLTINV;
834 } else if (err & 0x004) { /* Divide by Zero */
835 return FPE_FLTDIV;
836 } else if (err & 0x008) { /* Overflow */
837 return FPE_FLTOVF;
838 } else if (err & 0x012) { /* Denormal, Underflow */
839 return FPE_FLTUND;
840 } else if (err & 0x020) { /* Precision */
841 return FPE_FLTRES;
842 }
843
844 /*
845 * If we're using IRQ 13, or supposedly even some trap
846 * X86_TRAP_MF implementations, it's possible
847 * we get a spurious trap, which is not an error.
848 */
849 return 0;
850 }
851
852 /*
853 * Initialize register state that may prevent from entering low-power idle.
854 * This function will be invoked from the cpuidle driver only when needed.
855 */
fpu_idle_fpregs(void)856 void fpu_idle_fpregs(void)
857 {
858 /* Note: AMX_TILE being enabled implies XGETBV1 support */
859 if (cpu_feature_enabled(X86_FEATURE_AMX_TILE) &&
860 (xfeatures_in_use() & XFEATURE_MASK_XTILE)) {
861 tile_release();
862 fpregs_deactivate(¤t->thread.fpu);
863 }
864 }
865