1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * FP/SIMD context switching and fault handling
4  *
5  * Copyright (C) 2012 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/bottom_half.h>
12 #include <linux/bug.h>
13 #include <linux/cache.h>
14 #include <linux/compat.h>
15 #include <linux/compiler.h>
16 #include <linux/cpu.h>
17 #include <linux/cpu_pm.h>
18 #include <linux/ctype.h>
19 #include <linux/kernel.h>
20 #include <linux/linkage.h>
21 #include <linux/irqflags.h>
22 #include <linux/init.h>
23 #include <linux/percpu.h>
24 #include <linux/prctl.h>
25 #include <linux/preempt.h>
26 #include <linux/ptrace.h>
27 #include <linux/sched/signal.h>
28 #include <linux/sched/task_stack.h>
29 #include <linux/signal.h>
30 #include <linux/slab.h>
31 #include <linux/stddef.h>
32 #include <linux/sysctl.h>
33 #include <linux/swab.h>
34 
35 #include <asm/esr.h>
36 #include <asm/exception.h>
37 #include <asm/fpsimd.h>
38 #include <asm/cpufeature.h>
39 #include <asm/cputype.h>
40 #include <asm/neon.h>
41 #include <asm/processor.h>
42 #include <asm/simd.h>
43 #include <asm/sigcontext.h>
44 #include <asm/sysreg.h>
45 #include <asm/traps.h>
46 #include <asm/virt.h>
47 
48 #define FPEXC_IOF	(1 << 0)
49 #define FPEXC_DZF	(1 << 1)
50 #define FPEXC_OFF	(1 << 2)
51 #define FPEXC_UFF	(1 << 3)
52 #define FPEXC_IXF	(1 << 4)
53 #define FPEXC_IDF	(1 << 7)
54 
55 /*
56  * (Note: in this discussion, statements about FPSIMD apply equally to SVE.)
57  *
58  * In order to reduce the number of times the FPSIMD state is needlessly saved
59  * and restored, we need to keep track of two things:
60  * (a) for each task, we need to remember which CPU was the last one to have
61  *     the task's FPSIMD state loaded into its FPSIMD registers;
62  * (b) for each CPU, we need to remember which task's userland FPSIMD state has
63  *     been loaded into its FPSIMD registers most recently, or whether it has
64  *     been used to perform kernel mode NEON in the meantime.
65  *
66  * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to
67  * the id of the current CPU every time the state is loaded onto a CPU. For (b),
68  * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
69  * address of the userland FPSIMD state of the task that was loaded onto the CPU
70  * the most recently, or NULL if kernel mode NEON has been performed after that.
71  *
72  * With this in place, we no longer have to restore the next FPSIMD state right
73  * when switching between tasks. Instead, we can defer this check to userland
74  * resume, at which time we verify whether the CPU's fpsimd_last_state and the
75  * task's fpsimd_cpu are still mutually in sync. If this is the case, we
76  * can omit the FPSIMD restore.
77  *
78  * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to
79  * indicate whether or not the userland FPSIMD state of the current task is
80  * present in the registers. The flag is set unless the FPSIMD registers of this
81  * CPU currently contain the most recent userland FPSIMD state of the current
82  * task. If the task is behaving as a VMM, then this is will be managed by
83  * KVM which will clear it to indicate that the vcpu FPSIMD state is currently
84  * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware
85  * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and
86  * flag the register state as invalid.
87  *
88  * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may
89  * save the task's FPSIMD context back to task_struct from softirq context.
90  * To prevent this from racing with the manipulation of the task's FPSIMD state
91  * from task context and thereby corrupting the state, it is necessary to
92  * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE
93  * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to
94  * run but prevent them to use FPSIMD.
95  *
96  * For a certain task, the sequence may look something like this:
97  * - the task gets scheduled in; if both the task's fpsimd_cpu field
98  *   contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
99  *   variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is
100  *   cleared, otherwise it is set;
101  *
102  * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
103  *   userland FPSIMD state is copied from memory to the registers, the task's
104  *   fpsimd_cpu field is set to the id of the current CPU, the current
105  *   CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the
106  *   TIF_FOREIGN_FPSTATE flag is cleared;
107  *
108  * - the task executes an ordinary syscall; upon return to userland, the
109  *   TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is
110  *   restored;
111  *
112  * - the task executes a syscall which executes some NEON instructions; this is
113  *   preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD
114  *   register contents to memory, clears the fpsimd_last_state per-cpu variable
115  *   and sets the TIF_FOREIGN_FPSTATE flag;
116  *
117  * - the task gets preempted after kernel_neon_end() is called; as we have not
118  *   returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so
119  *   whatever is in the FPSIMD registers is not saved to memory, but discarded.
120  */
121 struct fpsimd_last_state_struct {
122 	struct user_fpsimd_state *st;
123 	void *sve_state;
124 	void *za_state;
125 	u64 *svcr;
126 	unsigned int sve_vl;
127 	unsigned int sme_vl;
128 };
129 
130 static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state);
131 
132 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = {
133 #ifdef CONFIG_ARM64_SVE
134 	[ARM64_VEC_SVE] = {
135 		.type			= ARM64_VEC_SVE,
136 		.name			= "SVE",
137 		.min_vl			= SVE_VL_MIN,
138 		.max_vl			= SVE_VL_MIN,
139 		.max_virtualisable_vl	= SVE_VL_MIN,
140 	},
141 #endif
142 #ifdef CONFIG_ARM64_SME
143 	[ARM64_VEC_SME] = {
144 		.type			= ARM64_VEC_SME,
145 		.name			= "SME",
146 	},
147 #endif
148 };
149 
vec_vl_inherit_flag(enum vec_type type)150 static unsigned int vec_vl_inherit_flag(enum vec_type type)
151 {
152 	switch (type) {
153 	case ARM64_VEC_SVE:
154 		return TIF_SVE_VL_INHERIT;
155 	case ARM64_VEC_SME:
156 		return TIF_SME_VL_INHERIT;
157 	default:
158 		WARN_ON_ONCE(1);
159 		return 0;
160 	}
161 }
162 
163 struct vl_config {
164 	int __default_vl;		/* Default VL for tasks */
165 };
166 
167 static struct vl_config vl_config[ARM64_VEC_MAX];
168 
get_default_vl(enum vec_type type)169 static inline int get_default_vl(enum vec_type type)
170 {
171 	return READ_ONCE(vl_config[type].__default_vl);
172 }
173 
174 #ifdef CONFIG_ARM64_SVE
175 
get_sve_default_vl(void)176 static inline int get_sve_default_vl(void)
177 {
178 	return get_default_vl(ARM64_VEC_SVE);
179 }
180 
set_default_vl(enum vec_type type,int val)181 static inline void set_default_vl(enum vec_type type, int val)
182 {
183 	WRITE_ONCE(vl_config[type].__default_vl, val);
184 }
185 
set_sve_default_vl(int val)186 static inline void set_sve_default_vl(int val)
187 {
188 	set_default_vl(ARM64_VEC_SVE, val);
189 }
190 
191 static void __percpu *efi_sve_state;
192 
193 #else /* ! CONFIG_ARM64_SVE */
194 
195 /* Dummy declaration for code that will be optimised out: */
196 extern void __percpu *efi_sve_state;
197 
198 #endif /* ! CONFIG_ARM64_SVE */
199 
200 #ifdef CONFIG_ARM64_SME
201 
get_sme_default_vl(void)202 static int get_sme_default_vl(void)
203 {
204 	return get_default_vl(ARM64_VEC_SME);
205 }
206 
set_sme_default_vl(int val)207 static void set_sme_default_vl(int val)
208 {
209 	set_default_vl(ARM64_VEC_SME, val);
210 }
211 
212 static void sme_free(struct task_struct *);
213 
214 #else
215 
sme_free(struct task_struct * t)216 static inline void sme_free(struct task_struct *t) { }
217 
218 #endif
219 
220 DEFINE_PER_CPU(bool, fpsimd_context_busy);
221 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy);
222 
223 static void fpsimd_bind_task_to_cpu(void);
224 
__get_cpu_fpsimd_context(void)225 static void __get_cpu_fpsimd_context(void)
226 {
227 	bool busy = __this_cpu_xchg(fpsimd_context_busy, true);
228 
229 	WARN_ON(busy);
230 }
231 
232 /*
233  * Claim ownership of the CPU FPSIMD context for use by the calling context.
234  *
235  * The caller may freely manipulate the FPSIMD context metadata until
236  * put_cpu_fpsimd_context() is called.
237  *
238  * The double-underscore version must only be called if you know the task
239  * can't be preempted.
240  *
241  * On RT kernels local_bh_disable() is not sufficient because it only
242  * serializes soft interrupt related sections via a local lock, but stays
243  * preemptible. Disabling preemption is the right choice here as bottom
244  * half processing is always in thread context on RT kernels so it
245  * implicitly prevents bottom half processing as well.
246  */
get_cpu_fpsimd_context(void)247 static void get_cpu_fpsimd_context(void)
248 {
249 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
250 		local_bh_disable();
251 	else
252 		preempt_disable();
253 	__get_cpu_fpsimd_context();
254 }
255 
__put_cpu_fpsimd_context(void)256 static void __put_cpu_fpsimd_context(void)
257 {
258 	bool busy = __this_cpu_xchg(fpsimd_context_busy, false);
259 
260 	WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */
261 }
262 
263 /*
264  * Release the CPU FPSIMD context.
265  *
266  * Must be called from a context in which get_cpu_fpsimd_context() was
267  * previously called, with no call to put_cpu_fpsimd_context() in the
268  * meantime.
269  */
put_cpu_fpsimd_context(void)270 static void put_cpu_fpsimd_context(void)
271 {
272 	__put_cpu_fpsimd_context();
273 	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
274 		local_bh_enable();
275 	else
276 		preempt_enable();
277 }
278 
have_cpu_fpsimd_context(void)279 static bool have_cpu_fpsimd_context(void)
280 {
281 	return !preemptible() && __this_cpu_read(fpsimd_context_busy);
282 }
283 
task_get_vl(const struct task_struct * task,enum vec_type type)284 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type)
285 {
286 	return task->thread.vl[type];
287 }
288 
task_set_vl(struct task_struct * task,enum vec_type type,unsigned long vl)289 void task_set_vl(struct task_struct *task, enum vec_type type,
290 		 unsigned long vl)
291 {
292 	task->thread.vl[type] = vl;
293 }
294 
task_get_vl_onexec(const struct task_struct * task,enum vec_type type)295 unsigned int task_get_vl_onexec(const struct task_struct *task,
296 				enum vec_type type)
297 {
298 	return task->thread.vl_onexec[type];
299 }
300 
task_set_vl_onexec(struct task_struct * task,enum vec_type type,unsigned long vl)301 void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
302 			unsigned long vl)
303 {
304 	task->thread.vl_onexec[type] = vl;
305 }
306 
307 /*
308  * TIF_SME controls whether a task can use SME without trapping while
309  * in userspace, when TIF_SME is set then we must have storage
310  * alocated in sve_state and za_state to store the contents of both ZA
311  * and the SVE registers for both streaming and non-streaming modes.
312  *
313  * If both SVCR.ZA and SVCR.SM are disabled then at any point we
314  * may disable TIF_SME and reenable traps.
315  */
316 
317 
318 /*
319  * TIF_SVE controls whether a task can use SVE without trapping while
320  * in userspace, and also (together with TIF_SME) the way a task's
321  * FPSIMD/SVE state is stored in thread_struct.
322  *
323  * The kernel uses this flag to track whether a user task is actively
324  * using SVE, and therefore whether full SVE register state needs to
325  * be tracked.  If not, the cheaper FPSIMD context handling code can
326  * be used instead of the more costly SVE equivalents.
327  *
328  *  * TIF_SVE or SVCR.SM set:
329  *
330  *    The task can execute SVE instructions while in userspace without
331  *    trapping to the kernel.
332  *
333  *    When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the
334  *    corresponding Zn), P0-P15 and FFR are encoded in
335  *    task->thread.sve_state, formatted appropriately for vector
336  *    length task->thread.sve_vl or, if SVCR.SM is set,
337  *    task->thread.sme_vl.
338  *
339  *    task->thread.sve_state must point to a valid buffer at least
340  *    sve_state_size(task) bytes in size.
341  *
342  *    During any syscall, the kernel may optionally clear TIF_SVE and
343  *    discard the vector state except for the FPSIMD subset.
344  *
345  *  * TIF_SVE clear:
346  *
347  *    An attempt by the user task to execute an SVE instruction causes
348  *    do_sve_acc() to be called, which does some preparation and then
349  *    sets TIF_SVE.
350  *
351  *    When stored, FPSIMD registers V0-V31 are encoded in
352  *    task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are
353  *    logically zero but not stored anywhere; P0-P15 and FFR are not
354  *    stored and have unspecified values from userspace's point of
355  *    view.  For hygiene purposes, the kernel zeroes them on next use,
356  *    but userspace is discouraged from relying on this.
357  *
358  *    task->thread.sve_state does not need to be non-NULL, valid or any
359  *    particular size: it must not be dereferenced.
360  *
361  *  * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state
362  *    irrespective of whether TIF_SVE is clear or set, since these are
363  *    not vector length dependent.
364  */
365 
366 /*
367  * Update current's FPSIMD/SVE registers from thread_struct.
368  *
369  * This function should be called only when the FPSIMD/SVE state in
370  * thread_struct is known to be up to date, when preparing to enter
371  * userspace.
372  */
task_fpsimd_load(void)373 static void task_fpsimd_load(void)
374 {
375 	bool restore_sve_regs = false;
376 	bool restore_ffr;
377 
378 	WARN_ON(!system_supports_fpsimd());
379 	WARN_ON(!have_cpu_fpsimd_context());
380 
381 	/* Check if we should restore SVE first */
382 	if (IS_ENABLED(CONFIG_ARM64_SVE) && test_thread_flag(TIF_SVE)) {
383 		sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1);
384 		restore_sve_regs = true;
385 		restore_ffr = true;
386 	}
387 
388 	/* Restore SME, override SVE register configuration if needed */
389 	if (system_supports_sme()) {
390 		unsigned long sme_vl = task_get_sme_vl(current);
391 
392 		/* Ensure VL is set up for restoring data */
393 		if (test_thread_flag(TIF_SME))
394 			sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
395 
396 		write_sysreg_s(current->thread.svcr, SYS_SVCR);
397 
398 		if (thread_za_enabled(&current->thread))
399 			za_load_state(current->thread.za_state);
400 
401 		if (thread_sm_enabled(&current->thread)) {
402 			restore_sve_regs = true;
403 			restore_ffr = system_supports_fa64();
404 		}
405 	}
406 
407 	if (restore_sve_regs)
408 		sve_load_state(sve_pffr(&current->thread),
409 			       &current->thread.uw.fpsimd_state.fpsr,
410 			       restore_ffr);
411 	else
412 		fpsimd_load_state(&current->thread.uw.fpsimd_state);
413 }
414 
415 /*
416  * Ensure FPSIMD/SVE storage in memory for the loaded context is up to
417  * date with respect to the CPU registers. Note carefully that the
418  * current context is the context last bound to the CPU stored in
419  * last, if KVM is involved this may be the guest VM context rather
420  * than the host thread for the VM pointed to by current. This means
421  * that we must always reference the state storage via last rather
422  * than via current, other than the TIF_ flags which KVM will
423  * carefully maintain for us.
424  */
fpsimd_save(void)425 static void fpsimd_save(void)
426 {
427 	struct fpsimd_last_state_struct const *last =
428 		this_cpu_ptr(&fpsimd_last_state);
429 	/* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */
430 	bool save_sve_regs = false;
431 	bool save_ffr;
432 	unsigned int vl;
433 
434 	WARN_ON(!system_supports_fpsimd());
435 	WARN_ON(!have_cpu_fpsimd_context());
436 
437 	if (test_thread_flag(TIF_FOREIGN_FPSTATE))
438 		return;
439 
440 	if (test_thread_flag(TIF_SVE)) {
441 		save_sve_regs = true;
442 		save_ffr = true;
443 		vl = last->sve_vl;
444 	}
445 
446 	if (system_supports_sme()) {
447 		u64 *svcr = last->svcr;
448 
449 		*svcr = read_sysreg_s(SYS_SVCR);
450 
451 		if (*svcr & SVCR_ZA_MASK)
452 			za_save_state(last->za_state);
453 
454 		/* If we are in streaming mode override regular SVE. */
455 		if (*svcr & SVCR_SM_MASK) {
456 			save_sve_regs = true;
457 			save_ffr = system_supports_fa64();
458 			vl = last->sme_vl;
459 		}
460 	}
461 
462 	if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) {
463 		/* Get the configured VL from RDVL, will account for SM */
464 		if (WARN_ON(sve_get_vl() != vl)) {
465 			/*
466 			 * Can't save the user regs, so current would
467 			 * re-enter user with corrupt state.
468 			 * There's no way to recover, so kill it:
469 			 */
470 			force_signal_inject(SIGKILL, SI_KERNEL, 0, 0);
471 			return;
472 		}
473 
474 		sve_save_state((char *)last->sve_state +
475 					sve_ffr_offset(vl),
476 			       &last->st->fpsr, save_ffr);
477 	} else {
478 		fpsimd_save_state(last->st);
479 	}
480 }
481 
482 /*
483  * All vector length selection from userspace comes through here.
484  * We're on a slow path, so some sanity-checks are included.
485  * If things go wrong there's a bug somewhere, but try to fall back to a
486  * safe choice.
487  */
find_supported_vector_length(enum vec_type type,unsigned int vl)488 static unsigned int find_supported_vector_length(enum vec_type type,
489 						 unsigned int vl)
490 {
491 	struct vl_info *info = &vl_info[type];
492 	int bit;
493 	int max_vl = info->max_vl;
494 
495 	if (WARN_ON(!sve_vl_valid(vl)))
496 		vl = info->min_vl;
497 
498 	if (WARN_ON(!sve_vl_valid(max_vl)))
499 		max_vl = info->min_vl;
500 
501 	if (vl > max_vl)
502 		vl = max_vl;
503 	if (vl < info->min_vl)
504 		vl = info->min_vl;
505 
506 	bit = find_next_bit(info->vq_map, SVE_VQ_MAX,
507 			    __vq_to_bit(sve_vq_from_vl(vl)));
508 	return sve_vl_from_vq(__bit_to_vq(bit));
509 }
510 
511 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL)
512 
vec_proc_do_default_vl(struct ctl_table * table,int write,void * buffer,size_t * lenp,loff_t * ppos)513 static int vec_proc_do_default_vl(struct ctl_table *table, int write,
514 				  void *buffer, size_t *lenp, loff_t *ppos)
515 {
516 	struct vl_info *info = table->extra1;
517 	enum vec_type type = info->type;
518 	int ret;
519 	int vl = get_default_vl(type);
520 	struct ctl_table tmp_table = {
521 		.data = &vl,
522 		.maxlen = sizeof(vl),
523 	};
524 
525 	ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos);
526 	if (ret || !write)
527 		return ret;
528 
529 	/* Writing -1 has the special meaning "set to max": */
530 	if (vl == -1)
531 		vl = info->max_vl;
532 
533 	if (!sve_vl_valid(vl))
534 		return -EINVAL;
535 
536 	set_default_vl(type, find_supported_vector_length(type, vl));
537 	return 0;
538 }
539 
540 static struct ctl_table sve_default_vl_table[] = {
541 	{
542 		.procname	= "sve_default_vector_length",
543 		.mode		= 0644,
544 		.proc_handler	= vec_proc_do_default_vl,
545 		.extra1		= &vl_info[ARM64_VEC_SVE],
546 	},
547 	{ }
548 };
549 
sve_sysctl_init(void)550 static int __init sve_sysctl_init(void)
551 {
552 	if (system_supports_sve())
553 		if (!register_sysctl("abi", sve_default_vl_table))
554 			return -EINVAL;
555 
556 	return 0;
557 }
558 
559 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
sve_sysctl_init(void)560 static int __init sve_sysctl_init(void) { return 0; }
561 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
562 
563 #if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL)
564 static struct ctl_table sme_default_vl_table[] = {
565 	{
566 		.procname	= "sme_default_vector_length",
567 		.mode		= 0644,
568 		.proc_handler	= vec_proc_do_default_vl,
569 		.extra1		= &vl_info[ARM64_VEC_SME],
570 	},
571 	{ }
572 };
573 
sme_sysctl_init(void)574 static int __init sme_sysctl_init(void)
575 {
576 	if (system_supports_sme())
577 		if (!register_sysctl("abi", sme_default_vl_table))
578 			return -EINVAL;
579 
580 	return 0;
581 }
582 
583 #else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
sme_sysctl_init(void)584 static int __init sme_sysctl_init(void) { return 0; }
585 #endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
586 
587 #define ZREG(sve_state, vq, n) ((char *)(sve_state) +		\
588 	(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
589 
590 #ifdef CONFIG_CPU_BIG_ENDIAN
arm64_cpu_to_le128(__uint128_t x)591 static __uint128_t arm64_cpu_to_le128(__uint128_t x)
592 {
593 	u64 a = swab64(x);
594 	u64 b = swab64(x >> 64);
595 
596 	return ((__uint128_t)a << 64) | b;
597 }
598 #else
arm64_cpu_to_le128(__uint128_t x)599 static __uint128_t arm64_cpu_to_le128(__uint128_t x)
600 {
601 	return x;
602 }
603 #endif
604 
605 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x)
606 
__fpsimd_to_sve(void * sst,struct user_fpsimd_state const * fst,unsigned int vq)607 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst,
608 			    unsigned int vq)
609 {
610 	unsigned int i;
611 	__uint128_t *p;
612 
613 	for (i = 0; i < SVE_NUM_ZREGS; ++i) {
614 		p = (__uint128_t *)ZREG(sst, vq, i);
615 		*p = arm64_cpu_to_le128(fst->vregs[i]);
616 	}
617 }
618 
619 /*
620  * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
621  * task->thread.sve_state.
622  *
623  * Task can be a non-runnable task, or current.  In the latter case,
624  * the caller must have ownership of the cpu FPSIMD context before calling
625  * this function.
626  * task->thread.sve_state must point to at least sve_state_size(task)
627  * bytes of allocated kernel memory.
628  * task->thread.uw.fpsimd_state must be up to date before calling this
629  * function.
630  */
fpsimd_to_sve(struct task_struct * task)631 static void fpsimd_to_sve(struct task_struct *task)
632 {
633 	unsigned int vq;
634 	void *sst = task->thread.sve_state;
635 	struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
636 
637 	if (!system_supports_sve())
638 		return;
639 
640 	vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
641 	__fpsimd_to_sve(sst, fst, vq);
642 }
643 
644 /*
645  * Transfer the SVE state in task->thread.sve_state to
646  * task->thread.uw.fpsimd_state.
647  *
648  * Task can be a non-runnable task, or current.  In the latter case,
649  * the caller must have ownership of the cpu FPSIMD context before calling
650  * this function.
651  * task->thread.sve_state must point to at least sve_state_size(task)
652  * bytes of allocated kernel memory.
653  * task->thread.sve_state must be up to date before calling this function.
654  */
sve_to_fpsimd(struct task_struct * task)655 static void sve_to_fpsimd(struct task_struct *task)
656 {
657 	unsigned int vq, vl;
658 	void const *sst = task->thread.sve_state;
659 	struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
660 	unsigned int i;
661 	__uint128_t const *p;
662 
663 	if (!system_supports_sve())
664 		return;
665 
666 	vl = thread_get_cur_vl(&task->thread);
667 	vq = sve_vq_from_vl(vl);
668 	for (i = 0; i < SVE_NUM_ZREGS; ++i) {
669 		p = (__uint128_t const *)ZREG(sst, vq, i);
670 		fst->vregs[i] = arm64_le128_to_cpu(*p);
671 	}
672 }
673 
674 #ifdef CONFIG_ARM64_SVE
675 /*
676  * Call __sve_free() directly only if you know task can't be scheduled
677  * or preempted.
678  */
__sve_free(struct task_struct * task)679 static void __sve_free(struct task_struct *task)
680 {
681 	kfree(task->thread.sve_state);
682 	task->thread.sve_state = NULL;
683 }
684 
sve_free(struct task_struct * task)685 static void sve_free(struct task_struct *task)
686 {
687 	WARN_ON(test_tsk_thread_flag(task, TIF_SVE));
688 
689 	__sve_free(task);
690 }
691 
692 /*
693  * Return how many bytes of memory are required to store the full SVE
694  * state for task, given task's currently configured vector length.
695  */
sve_state_size(struct task_struct const * task)696 size_t sve_state_size(struct task_struct const *task)
697 {
698 	unsigned int vl = 0;
699 
700 	if (system_supports_sve())
701 		vl = task_get_sve_vl(task);
702 	if (system_supports_sme())
703 		vl = max(vl, task_get_sme_vl(task));
704 
705 	return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl));
706 }
707 
708 /*
709  * Ensure that task->thread.sve_state is allocated and sufficiently large.
710  *
711  * This function should be used only in preparation for replacing
712  * task->thread.sve_state with new data.  The memory is always zeroed
713  * here to prevent stale data from showing through: this is done in
714  * the interest of testability and predictability: except in the
715  * do_sve_acc() case, there is no ABI requirement to hide stale data
716  * written previously be task.
717  */
sve_alloc(struct task_struct * task,bool flush)718 void sve_alloc(struct task_struct *task, bool flush)
719 {
720 	if (task->thread.sve_state) {
721 		if (flush)
722 			memset(task->thread.sve_state, 0,
723 			       sve_state_size(task));
724 		return;
725 	}
726 
727 	/* This is a small allocation (maximum ~8KB) and Should Not Fail. */
728 	task->thread.sve_state =
729 		kzalloc(sve_state_size(task), GFP_KERNEL);
730 }
731 
732 
733 /*
734  * Force the FPSIMD state shared with SVE to be updated in the SVE state
735  * even if the SVE state is the current active state.
736  *
737  * This should only be called by ptrace.  task must be non-runnable.
738  * task->thread.sve_state must point to at least sve_state_size(task)
739  * bytes of allocated kernel memory.
740  */
fpsimd_force_sync_to_sve(struct task_struct * task)741 void fpsimd_force_sync_to_sve(struct task_struct *task)
742 {
743 	fpsimd_to_sve(task);
744 }
745 
746 /*
747  * Ensure that task->thread.sve_state is up to date with respect to
748  * the user task, irrespective of when SVE is in use or not.
749  *
750  * This should only be called by ptrace.  task must be non-runnable.
751  * task->thread.sve_state must point to at least sve_state_size(task)
752  * bytes of allocated kernel memory.
753  */
fpsimd_sync_to_sve(struct task_struct * task)754 void fpsimd_sync_to_sve(struct task_struct *task)
755 {
756 	if (!test_tsk_thread_flag(task, TIF_SVE) &&
757 	    !thread_sm_enabled(&task->thread))
758 		fpsimd_to_sve(task);
759 }
760 
761 /*
762  * Ensure that task->thread.uw.fpsimd_state is up to date with respect to
763  * the user task, irrespective of whether SVE is in use or not.
764  *
765  * This should only be called by ptrace.  task must be non-runnable.
766  * task->thread.sve_state must point to at least sve_state_size(task)
767  * bytes of allocated kernel memory.
768  */
sve_sync_to_fpsimd(struct task_struct * task)769 void sve_sync_to_fpsimd(struct task_struct *task)
770 {
771 	if (test_tsk_thread_flag(task, TIF_SVE) ||
772 	    thread_sm_enabled(&task->thread))
773 		sve_to_fpsimd(task);
774 }
775 
776 /*
777  * Ensure that task->thread.sve_state is up to date with respect to
778  * the task->thread.uw.fpsimd_state.
779  *
780  * This should only be called by ptrace to merge new FPSIMD register
781  * values into a task for which SVE is currently active.
782  * task must be non-runnable.
783  * task->thread.sve_state must point to at least sve_state_size(task)
784  * bytes of allocated kernel memory.
785  * task->thread.uw.fpsimd_state must already have been initialised with
786  * the new FPSIMD register values to be merged in.
787  */
sve_sync_from_fpsimd_zeropad(struct task_struct * task)788 void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
789 {
790 	unsigned int vq;
791 	void *sst = task->thread.sve_state;
792 	struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
793 
794 	if (!test_tsk_thread_flag(task, TIF_SVE))
795 		return;
796 
797 	vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
798 
799 	memset(sst, 0, SVE_SIG_REGS_SIZE(vq));
800 	__fpsimd_to_sve(sst, fst, vq);
801 }
802 
vec_set_vector_length(struct task_struct * task,enum vec_type type,unsigned long vl,unsigned long flags)803 int vec_set_vector_length(struct task_struct *task, enum vec_type type,
804 			  unsigned long vl, unsigned long flags)
805 {
806 	if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |
807 				     PR_SVE_SET_VL_ONEXEC))
808 		return -EINVAL;
809 
810 	if (!sve_vl_valid(vl))
811 		return -EINVAL;
812 
813 	/*
814 	 * Clamp to the maximum vector length that VL-agnostic code
815 	 * can work with.  A flag may be assigned in the future to
816 	 * allow setting of larger vector lengths without confusing
817 	 * older software.
818 	 */
819 	if (vl > VL_ARCH_MAX)
820 		vl = VL_ARCH_MAX;
821 
822 	vl = find_supported_vector_length(type, vl);
823 
824 	if (flags & (PR_SVE_VL_INHERIT |
825 		     PR_SVE_SET_VL_ONEXEC))
826 		task_set_vl_onexec(task, type, vl);
827 	else
828 		/* Reset VL to system default on next exec: */
829 		task_set_vl_onexec(task, type, 0);
830 
831 	/* Only actually set the VL if not deferred: */
832 	if (flags & PR_SVE_SET_VL_ONEXEC)
833 		goto out;
834 
835 	if (vl == task_get_vl(task, type))
836 		goto out;
837 
838 	/*
839 	 * To ensure the FPSIMD bits of the SVE vector registers are preserved,
840 	 * write any live register state back to task_struct, and convert to a
841 	 * regular FPSIMD thread.
842 	 */
843 	if (task == current) {
844 		get_cpu_fpsimd_context();
845 
846 		fpsimd_save();
847 	}
848 
849 	fpsimd_flush_task_state(task);
850 	if (test_and_clear_tsk_thread_flag(task, TIF_SVE) ||
851 	    thread_sm_enabled(&task->thread))
852 		sve_to_fpsimd(task);
853 
854 	if (system_supports_sme() && type == ARM64_VEC_SME) {
855 		task->thread.svcr &= ~(SVCR_SM_MASK |
856 				       SVCR_ZA_MASK);
857 		clear_thread_flag(TIF_SME);
858 	}
859 
860 	if (task == current)
861 		put_cpu_fpsimd_context();
862 
863 	/*
864 	 * Force reallocation of task SVE and SME state to the correct
865 	 * size on next use:
866 	 */
867 	sve_free(task);
868 	if (system_supports_sme() && type == ARM64_VEC_SME)
869 		sme_free(task);
870 
871 	task_set_vl(task, type, vl);
872 
873 out:
874 	update_tsk_thread_flag(task, vec_vl_inherit_flag(type),
875 			       flags & PR_SVE_VL_INHERIT);
876 
877 	return 0;
878 }
879 
880 /*
881  * Encode the current vector length and flags for return.
882  * This is only required for prctl(): ptrace has separate fields.
883  * SVE and SME use the same bits for _ONEXEC and _INHERIT.
884  *
885  * flags are as for vec_set_vector_length().
886  */
vec_prctl_status(enum vec_type type,unsigned long flags)887 static int vec_prctl_status(enum vec_type type, unsigned long flags)
888 {
889 	int ret;
890 
891 	if (flags & PR_SVE_SET_VL_ONEXEC)
892 		ret = task_get_vl_onexec(current, type);
893 	else
894 		ret = task_get_vl(current, type);
895 
896 	if (test_thread_flag(vec_vl_inherit_flag(type)))
897 		ret |= PR_SVE_VL_INHERIT;
898 
899 	return ret;
900 }
901 
902 /* PR_SVE_SET_VL */
sve_set_current_vl(unsigned long arg)903 int sve_set_current_vl(unsigned long arg)
904 {
905 	unsigned long vl, flags;
906 	int ret;
907 
908 	vl = arg & PR_SVE_VL_LEN_MASK;
909 	flags = arg & ~vl;
910 
911 	if (!system_supports_sve() || is_compat_task())
912 		return -EINVAL;
913 
914 	ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags);
915 	if (ret)
916 		return ret;
917 
918 	return vec_prctl_status(ARM64_VEC_SVE, flags);
919 }
920 
921 /* PR_SVE_GET_VL */
sve_get_current_vl(void)922 int sve_get_current_vl(void)
923 {
924 	if (!system_supports_sve() || is_compat_task())
925 		return -EINVAL;
926 
927 	return vec_prctl_status(ARM64_VEC_SVE, 0);
928 }
929 
930 #ifdef CONFIG_ARM64_SME
931 /* PR_SME_SET_VL */
sme_set_current_vl(unsigned long arg)932 int sme_set_current_vl(unsigned long arg)
933 {
934 	unsigned long vl, flags;
935 	int ret;
936 
937 	vl = arg & PR_SME_VL_LEN_MASK;
938 	flags = arg & ~vl;
939 
940 	if (!system_supports_sme() || is_compat_task())
941 		return -EINVAL;
942 
943 	ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags);
944 	if (ret)
945 		return ret;
946 
947 	return vec_prctl_status(ARM64_VEC_SME, flags);
948 }
949 
950 /* PR_SME_GET_VL */
sme_get_current_vl(void)951 int sme_get_current_vl(void)
952 {
953 	if (!system_supports_sme() || is_compat_task())
954 		return -EINVAL;
955 
956 	return vec_prctl_status(ARM64_VEC_SME, 0);
957 }
958 #endif /* CONFIG_ARM64_SME */
959 
vec_probe_vqs(struct vl_info * info,DECLARE_BITMAP (map,SVE_VQ_MAX))960 static void vec_probe_vqs(struct vl_info *info,
961 			  DECLARE_BITMAP(map, SVE_VQ_MAX))
962 {
963 	unsigned int vq, vl;
964 
965 	bitmap_zero(map, SVE_VQ_MAX);
966 
967 	for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) {
968 		write_vl(info->type, vq - 1); /* self-syncing */
969 
970 		switch (info->type) {
971 		case ARM64_VEC_SVE:
972 			vl = sve_get_vl();
973 			break;
974 		case ARM64_VEC_SME:
975 			vl = sme_get_vl();
976 			break;
977 		default:
978 			vl = 0;
979 			break;
980 		}
981 
982 		/* Minimum VL identified? */
983 		if (sve_vq_from_vl(vl) > vq)
984 			break;
985 
986 		vq = sve_vq_from_vl(vl); /* skip intervening lengths */
987 		set_bit(__vq_to_bit(vq), map);
988 	}
989 }
990 
991 /*
992  * Initialise the set of known supported VQs for the boot CPU.
993  * This is called during kernel boot, before secondary CPUs are brought up.
994  */
vec_init_vq_map(enum vec_type type)995 void __init vec_init_vq_map(enum vec_type type)
996 {
997 	struct vl_info *info = &vl_info[type];
998 	vec_probe_vqs(info, info->vq_map);
999 	bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX);
1000 }
1001 
1002 /*
1003  * If we haven't committed to the set of supported VQs yet, filter out
1004  * those not supported by the current CPU.
1005  * This function is called during the bring-up of early secondary CPUs only.
1006  */
vec_update_vq_map(enum vec_type type)1007 void vec_update_vq_map(enum vec_type type)
1008 {
1009 	struct vl_info *info = &vl_info[type];
1010 	DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1011 
1012 	vec_probe_vqs(info, tmp_map);
1013 	bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX);
1014 	bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map,
1015 		  SVE_VQ_MAX);
1016 }
1017 
1018 /*
1019  * Check whether the current CPU supports all VQs in the committed set.
1020  * This function is called during the bring-up of late secondary CPUs only.
1021  */
vec_verify_vq_map(enum vec_type type)1022 int vec_verify_vq_map(enum vec_type type)
1023 {
1024 	struct vl_info *info = &vl_info[type];
1025 	DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1026 	unsigned long b;
1027 
1028 	vec_probe_vqs(info, tmp_map);
1029 
1030 	bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1031 	if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) {
1032 		pr_warn("%s: cpu%d: Required vector length(s) missing\n",
1033 			info->name, smp_processor_id());
1034 		return -EINVAL;
1035 	}
1036 
1037 	if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available())
1038 		return 0;
1039 
1040 	/*
1041 	 * For KVM, it is necessary to ensure that this CPU doesn't
1042 	 * support any vector length that guests may have probed as
1043 	 * unsupported.
1044 	 */
1045 
1046 	/* Recover the set of supported VQs: */
1047 	bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1048 	/* Find VQs supported that are not globally supported: */
1049 	bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX);
1050 
1051 	/* Find the lowest such VQ, if any: */
1052 	b = find_last_bit(tmp_map, SVE_VQ_MAX);
1053 	if (b >= SVE_VQ_MAX)
1054 		return 0; /* no mismatches */
1055 
1056 	/*
1057 	 * Mismatches above sve_max_virtualisable_vl are fine, since
1058 	 * no guest is allowed to configure ZCR_EL2.LEN to exceed this:
1059 	 */
1060 	if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) {
1061 		pr_warn("%s: cpu%d: Unsupported vector length(s) present\n",
1062 			info->name, smp_processor_id());
1063 		return -EINVAL;
1064 	}
1065 
1066 	return 0;
1067 }
1068 
sve_efi_setup(void)1069 static void __init sve_efi_setup(void)
1070 {
1071 	int max_vl = 0;
1072 	int i;
1073 
1074 	if (!IS_ENABLED(CONFIG_EFI))
1075 		return;
1076 
1077 	for (i = 0; i < ARRAY_SIZE(vl_info); i++)
1078 		max_vl = max(vl_info[i].max_vl, max_vl);
1079 
1080 	/*
1081 	 * alloc_percpu() warns and prints a backtrace if this goes wrong.
1082 	 * This is evidence of a crippled system and we are returning void,
1083 	 * so no attempt is made to handle this situation here.
1084 	 */
1085 	if (!sve_vl_valid(max_vl))
1086 		goto fail;
1087 
1088 	efi_sve_state = __alloc_percpu(
1089 		SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES);
1090 	if (!efi_sve_state)
1091 		goto fail;
1092 
1093 	return;
1094 
1095 fail:
1096 	panic("Cannot allocate percpu memory for EFI SVE save/restore");
1097 }
1098 
1099 /*
1100  * Enable SVE for EL1.
1101  * Intended for use by the cpufeatures code during CPU boot.
1102  */
sve_kernel_enable(const struct arm64_cpu_capabilities * __always_unused p)1103 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1104 {
1105 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
1106 	isb();
1107 }
1108 
1109 /*
1110  * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE
1111  * vector length.
1112  *
1113  * Use only if SVE is present.
1114  * This function clobbers the SVE vector length.
1115  */
read_zcr_features(void)1116 u64 read_zcr_features(void)
1117 {
1118 	u64 zcr;
1119 	unsigned int vq_max;
1120 
1121 	/*
1122 	 * Set the maximum possible VL, and write zeroes to all other
1123 	 * bits to see if they stick.
1124 	 */
1125 	sve_kernel_enable(NULL);
1126 	write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1);
1127 
1128 	zcr = read_sysreg_s(SYS_ZCR_EL1);
1129 	zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */
1130 	vq_max = sve_vq_from_vl(sve_get_vl());
1131 	zcr |= vq_max - 1; /* set LEN field to maximum effective value */
1132 
1133 	return zcr;
1134 }
1135 
sve_setup(void)1136 void __init sve_setup(void)
1137 {
1138 	struct vl_info *info = &vl_info[ARM64_VEC_SVE];
1139 	u64 zcr;
1140 	DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1141 	unsigned long b;
1142 
1143 	if (!system_supports_sve())
1144 		return;
1145 
1146 	/*
1147 	 * The SVE architecture mandates support for 128-bit vectors,
1148 	 * so sve_vq_map must have at least SVE_VQ_MIN set.
1149 	 * If something went wrong, at least try to patch it up:
1150 	 */
1151 	if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map)))
1152 		set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map);
1153 
1154 	zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1155 	info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1);
1156 
1157 	/*
1158 	 * Sanity-check that the max VL we determined through CPU features
1159 	 * corresponds properly to sve_vq_map.  If not, do our best:
1160 	 */
1161 	if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE,
1162 								 info->max_vl)))
1163 		info->max_vl = find_supported_vector_length(ARM64_VEC_SVE,
1164 							    info->max_vl);
1165 
1166 	/*
1167 	 * For the default VL, pick the maximum supported value <= 64.
1168 	 * VL == 64 is guaranteed not to grow the signal frame.
1169 	 */
1170 	set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64));
1171 
1172 	bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map,
1173 		      SVE_VQ_MAX);
1174 
1175 	b = find_last_bit(tmp_map, SVE_VQ_MAX);
1176 	if (b >= SVE_VQ_MAX)
1177 		/* No non-virtualisable VLs found */
1178 		info->max_virtualisable_vl = SVE_VQ_MAX;
1179 	else if (WARN_ON(b == SVE_VQ_MAX - 1))
1180 		/* No virtualisable VLs?  This is architecturally forbidden. */
1181 		info->max_virtualisable_vl = SVE_VQ_MIN;
1182 	else /* b + 1 < SVE_VQ_MAX */
1183 		info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1));
1184 
1185 	if (info->max_virtualisable_vl > info->max_vl)
1186 		info->max_virtualisable_vl = info->max_vl;
1187 
1188 	pr_info("%s: maximum available vector length %u bytes per vector\n",
1189 		info->name, info->max_vl);
1190 	pr_info("%s: default vector length %u bytes per vector\n",
1191 		info->name, get_sve_default_vl());
1192 
1193 	/* KVM decides whether to support mismatched systems. Just warn here: */
1194 	if (sve_max_virtualisable_vl() < sve_max_vl())
1195 		pr_warn("%s: unvirtualisable vector lengths present\n",
1196 			info->name);
1197 
1198 	sve_efi_setup();
1199 }
1200 
1201 /*
1202  * Called from the put_task_struct() path, which cannot get here
1203  * unless dead_task is really dead and not schedulable.
1204  */
fpsimd_release_task(struct task_struct * dead_task)1205 void fpsimd_release_task(struct task_struct *dead_task)
1206 {
1207 	__sve_free(dead_task);
1208 	sme_free(dead_task);
1209 }
1210 
1211 #endif /* CONFIG_ARM64_SVE */
1212 
1213 #ifdef CONFIG_ARM64_SME
1214 
1215 /*
1216  * Ensure that task->thread.za_state is allocated and sufficiently large.
1217  *
1218  * This function should be used only in preparation for replacing
1219  * task->thread.za_state with new data.  The memory is always zeroed
1220  * here to prevent stale data from showing through: this is done in
1221  * the interest of testability and predictability, the architecture
1222  * guarantees that when ZA is enabled it will be zeroed.
1223  */
sme_alloc(struct task_struct * task)1224 void sme_alloc(struct task_struct *task)
1225 {
1226 	if (task->thread.za_state) {
1227 		memset(task->thread.za_state, 0, za_state_size(task));
1228 		return;
1229 	}
1230 
1231 	/* This could potentially be up to 64K. */
1232 	task->thread.za_state =
1233 		kzalloc(za_state_size(task), GFP_KERNEL);
1234 }
1235 
sme_free(struct task_struct * task)1236 static void sme_free(struct task_struct *task)
1237 {
1238 	kfree(task->thread.za_state);
1239 	task->thread.za_state = NULL;
1240 }
1241 
sme_kernel_enable(const struct arm64_cpu_capabilities * __always_unused p)1242 void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1243 {
1244 	/* Set priority for all PEs to architecturally defined minimum */
1245 	write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK,
1246 		       SYS_SMPRI_EL1);
1247 
1248 	/* Allow SME in kernel */
1249 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
1250 	isb();
1251 
1252 	/* Allow EL0 to access TPIDR2 */
1253 	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
1254 	isb();
1255 }
1256 
1257 /*
1258  * This must be called after sme_kernel_enable(), we rely on the
1259  * feature table being sorted to ensure this.
1260  */
fa64_kernel_enable(const struct arm64_cpu_capabilities * __always_unused p)1261 void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1262 {
1263 	/* Allow use of FA64 */
1264 	write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK,
1265 		       SYS_SMCR_EL1);
1266 }
1267 
1268 /*
1269  * Read the pseudo-SMCR used by cpufeatures to identify the supported
1270  * vector length.
1271  *
1272  * Use only if SME is present.
1273  * This function clobbers the SME vector length.
1274  */
read_smcr_features(void)1275 u64 read_smcr_features(void)
1276 {
1277 	u64 smcr;
1278 	unsigned int vq_max;
1279 
1280 	sme_kernel_enable(NULL);
1281 	sme_smstart_sm();
1282 
1283 	/*
1284 	 * Set the maximum possible VL.
1285 	 */
1286 	write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK,
1287 		       SYS_SMCR_EL1);
1288 
1289 	smcr = read_sysreg_s(SYS_SMCR_EL1);
1290 	smcr &= ~(u64)SMCR_ELx_LEN_MASK; /* Only the LEN field */
1291 	vq_max = sve_vq_from_vl(sve_get_vl());
1292 	smcr |= vq_max - 1; /* set LEN field to maximum effective value */
1293 
1294 	sme_smstop_sm();
1295 
1296 	return smcr;
1297 }
1298 
sme_setup(void)1299 void __init sme_setup(void)
1300 {
1301 	struct vl_info *info = &vl_info[ARM64_VEC_SME];
1302 	u64 smcr;
1303 	int min_bit;
1304 
1305 	if (!system_supports_sme())
1306 		return;
1307 
1308 	/*
1309 	 * SME doesn't require any particular vector length be
1310 	 * supported but it does require at least one.  We should have
1311 	 * disabled the feature entirely while bringing up CPUs but
1312 	 * let's double check here.
1313 	 */
1314 	WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX));
1315 
1316 	min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);
1317 	info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit));
1318 
1319 	smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
1320 	info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1);
1321 
1322 	/*
1323 	 * Sanity-check that the max VL we determined through CPU features
1324 	 * corresponds properly to sme_vq_map.  If not, do our best:
1325 	 */
1326 	if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME,
1327 								 info->max_vl)))
1328 		info->max_vl = find_supported_vector_length(ARM64_VEC_SME,
1329 							    info->max_vl);
1330 
1331 	WARN_ON(info->min_vl > info->max_vl);
1332 
1333 	/*
1334 	 * For the default VL, pick the maximum supported value <= 32
1335 	 * (256 bits) if there is one since this is guaranteed not to
1336 	 * grow the signal frame when in streaming mode, otherwise the
1337 	 * minimum available VL will be used.
1338 	 */
1339 	set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32));
1340 
1341 	pr_info("SME: minimum available vector length %u bytes per vector\n",
1342 		info->min_vl);
1343 	pr_info("SME: maximum available vector length %u bytes per vector\n",
1344 		info->max_vl);
1345 	pr_info("SME: default vector length %u bytes per vector\n",
1346 		get_sme_default_vl());
1347 }
1348 
1349 #endif /* CONFIG_ARM64_SME */
1350 
sve_init_regs(void)1351 static void sve_init_regs(void)
1352 {
1353 	/*
1354 	 * Convert the FPSIMD state to SVE, zeroing all the state that
1355 	 * is not shared with FPSIMD. If (as is likely) the current
1356 	 * state is live in the registers then do this there and
1357 	 * update our metadata for the current task including
1358 	 * disabling the trap, otherwise update our in-memory copy.
1359 	 * We are guaranteed to not be in streaming mode, we can only
1360 	 * take a SVE trap when not in streaming mode and we can't be
1361 	 * in streaming mode when taking a SME trap.
1362 	 */
1363 	if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1364 		unsigned long vq_minus_one =
1365 			sve_vq_from_vl(task_get_sve_vl(current)) - 1;
1366 		sve_set_vq(vq_minus_one);
1367 		sve_flush_live(true, vq_minus_one);
1368 		fpsimd_bind_task_to_cpu();
1369 	} else {
1370 		fpsimd_to_sve(current);
1371 	}
1372 }
1373 
1374 /*
1375  * Trapped SVE access
1376  *
1377  * Storage is allocated for the full SVE state, the current FPSIMD
1378  * register contents are migrated across, and the access trap is
1379  * disabled.
1380  *
1381  * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state()
1382  * would have disabled the SVE access trap for userspace during
1383  * ret_to_user, making an SVE access trap impossible in that case.
1384  */
do_sve_acc(unsigned long esr,struct pt_regs * regs)1385 void do_sve_acc(unsigned long esr, struct pt_regs *regs)
1386 {
1387 	/* Even if we chose not to use SVE, the hardware could still trap: */
1388 	if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) {
1389 		force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1390 		return;
1391 	}
1392 
1393 	sve_alloc(current, true);
1394 	if (!current->thread.sve_state) {
1395 		force_sig(SIGKILL);
1396 		return;
1397 	}
1398 
1399 	get_cpu_fpsimd_context();
1400 
1401 	if (test_and_set_thread_flag(TIF_SVE))
1402 		WARN_ON(1); /* SVE access shouldn't have trapped */
1403 
1404 	/*
1405 	 * Even if the task can have used streaming mode we can only
1406 	 * generate SVE access traps in normal SVE mode and
1407 	 * transitioning out of streaming mode may discard any
1408 	 * streaming mode state.  Always clear the high bits to avoid
1409 	 * any potential errors tracking what is properly initialised.
1410 	 */
1411 	sve_init_regs();
1412 
1413 	put_cpu_fpsimd_context();
1414 }
1415 
1416 /*
1417  * Trapped SME access
1418  *
1419  * Storage is allocated for the full SVE and SME state, the current
1420  * FPSIMD register contents are migrated to SVE if SVE is not already
1421  * active, and the access trap is disabled.
1422  *
1423  * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state()
1424  * would have disabled the SME access trap for userspace during
1425  * ret_to_user, making an SVE access trap impossible in that case.
1426  */
do_sme_acc(unsigned long esr,struct pt_regs * regs)1427 void do_sme_acc(unsigned long esr, struct pt_regs *regs)
1428 {
1429 	/* Even if we chose not to use SME, the hardware could still trap: */
1430 	if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) {
1431 		force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1432 		return;
1433 	}
1434 
1435 	/*
1436 	 * If this not a trap due to SME being disabled then something
1437 	 * is being used in the wrong mode, report as SIGILL.
1438 	 */
1439 	if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) {
1440 		force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1441 		return;
1442 	}
1443 
1444 	sve_alloc(current, false);
1445 	sme_alloc(current);
1446 	if (!current->thread.sve_state || !current->thread.za_state) {
1447 		force_sig(SIGKILL);
1448 		return;
1449 	}
1450 
1451 	get_cpu_fpsimd_context();
1452 
1453 	/* With TIF_SME userspace shouldn't generate any traps */
1454 	if (test_and_set_thread_flag(TIF_SME))
1455 		WARN_ON(1);
1456 
1457 	if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1458 		unsigned long vq_minus_one =
1459 			sve_vq_from_vl(task_get_sme_vl(current)) - 1;
1460 		sme_set_vq(vq_minus_one);
1461 
1462 		fpsimd_bind_task_to_cpu();
1463 	}
1464 
1465 	put_cpu_fpsimd_context();
1466 }
1467 
1468 /*
1469  * Trapped FP/ASIMD access.
1470  */
do_fpsimd_acc(unsigned long esr,struct pt_regs * regs)1471 void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs)
1472 {
1473 	/* TODO: implement lazy context saving/restoring */
1474 	WARN_ON(1);
1475 }
1476 
1477 /*
1478  * Raise a SIGFPE for the current process.
1479  */
do_fpsimd_exc(unsigned long esr,struct pt_regs * regs)1480 void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs)
1481 {
1482 	unsigned int si_code = FPE_FLTUNK;
1483 
1484 	if (esr & ESR_ELx_FP_EXC_TFV) {
1485 		if (esr & FPEXC_IOF)
1486 			si_code = FPE_FLTINV;
1487 		else if (esr & FPEXC_DZF)
1488 			si_code = FPE_FLTDIV;
1489 		else if (esr & FPEXC_OFF)
1490 			si_code = FPE_FLTOVF;
1491 		else if (esr & FPEXC_UFF)
1492 			si_code = FPE_FLTUND;
1493 		else if (esr & FPEXC_IXF)
1494 			si_code = FPE_FLTRES;
1495 	}
1496 
1497 	send_sig_fault(SIGFPE, si_code,
1498 		       (void __user *)instruction_pointer(regs),
1499 		       current);
1500 }
1501 
fpsimd_thread_switch(struct task_struct * next)1502 void fpsimd_thread_switch(struct task_struct *next)
1503 {
1504 	bool wrong_task, wrong_cpu;
1505 
1506 	if (!system_supports_fpsimd())
1507 		return;
1508 
1509 	__get_cpu_fpsimd_context();
1510 
1511 	/* Save unsaved fpsimd state, if any: */
1512 	fpsimd_save();
1513 
1514 	/*
1515 	 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's
1516 	 * state.  For kernel threads, FPSIMD registers are never loaded
1517 	 * and wrong_task and wrong_cpu will always be true.
1518 	 */
1519 	wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
1520 					&next->thread.uw.fpsimd_state;
1521 	wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
1522 
1523 	update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
1524 			       wrong_task || wrong_cpu);
1525 
1526 	__put_cpu_fpsimd_context();
1527 }
1528 
fpsimd_flush_thread_vl(enum vec_type type)1529 static void fpsimd_flush_thread_vl(enum vec_type type)
1530 {
1531 	int vl, supported_vl;
1532 
1533 	/*
1534 	 * Reset the task vector length as required.  This is where we
1535 	 * ensure that all user tasks have a valid vector length
1536 	 * configured: no kernel task can become a user task without
1537 	 * an exec and hence a call to this function.  By the time the
1538 	 * first call to this function is made, all early hardware
1539 	 * probing is complete, so __sve_default_vl should be valid.
1540 	 * If a bug causes this to go wrong, we make some noise and
1541 	 * try to fudge thread.sve_vl to a safe value here.
1542 	 */
1543 	vl = task_get_vl_onexec(current, type);
1544 	if (!vl)
1545 		vl = get_default_vl(type);
1546 
1547 	if (WARN_ON(!sve_vl_valid(vl)))
1548 		vl = vl_info[type].min_vl;
1549 
1550 	supported_vl = find_supported_vector_length(type, vl);
1551 	if (WARN_ON(supported_vl != vl))
1552 		vl = supported_vl;
1553 
1554 	task_set_vl(current, type, vl);
1555 
1556 	/*
1557 	 * If the task is not set to inherit, ensure that the vector
1558 	 * length will be reset by a subsequent exec:
1559 	 */
1560 	if (!test_thread_flag(vec_vl_inherit_flag(type)))
1561 		task_set_vl_onexec(current, type, 0);
1562 }
1563 
fpsimd_flush_thread(void)1564 void fpsimd_flush_thread(void)
1565 {
1566 	void *sve_state = NULL;
1567 	void *za_state = NULL;
1568 
1569 	if (!system_supports_fpsimd())
1570 		return;
1571 
1572 	get_cpu_fpsimd_context();
1573 
1574 	fpsimd_flush_task_state(current);
1575 	memset(&current->thread.uw.fpsimd_state, 0,
1576 	       sizeof(current->thread.uw.fpsimd_state));
1577 
1578 	if (system_supports_sve()) {
1579 		clear_thread_flag(TIF_SVE);
1580 
1581 		/* Defer kfree() while in atomic context */
1582 		sve_state = current->thread.sve_state;
1583 		current->thread.sve_state = NULL;
1584 
1585 		fpsimd_flush_thread_vl(ARM64_VEC_SVE);
1586 	}
1587 
1588 	if (system_supports_sme()) {
1589 		clear_thread_flag(TIF_SME);
1590 
1591 		/* Defer kfree() while in atomic context */
1592 		za_state = current->thread.za_state;
1593 		current->thread.za_state = NULL;
1594 
1595 		fpsimd_flush_thread_vl(ARM64_VEC_SME);
1596 		current->thread.svcr = 0;
1597 	}
1598 
1599 	put_cpu_fpsimd_context();
1600 	kfree(sve_state);
1601 	kfree(za_state);
1602 }
1603 
1604 /*
1605  * Save the userland FPSIMD state of 'current' to memory, but only if the state
1606  * currently held in the registers does in fact belong to 'current'
1607  */
fpsimd_preserve_current_state(void)1608 void fpsimd_preserve_current_state(void)
1609 {
1610 	if (!system_supports_fpsimd())
1611 		return;
1612 
1613 	get_cpu_fpsimd_context();
1614 	fpsimd_save();
1615 	put_cpu_fpsimd_context();
1616 }
1617 
1618 /*
1619  * Like fpsimd_preserve_current_state(), but ensure that
1620  * current->thread.uw.fpsimd_state is updated so that it can be copied to
1621  * the signal frame.
1622  */
fpsimd_signal_preserve_current_state(void)1623 void fpsimd_signal_preserve_current_state(void)
1624 {
1625 	fpsimd_preserve_current_state();
1626 	if (test_thread_flag(TIF_SVE))
1627 		sve_to_fpsimd(current);
1628 }
1629 
1630 /*
1631  * Associate current's FPSIMD context with this cpu
1632  * The caller must have ownership of the cpu FPSIMD context before calling
1633  * this function.
1634  */
fpsimd_bind_task_to_cpu(void)1635 static void fpsimd_bind_task_to_cpu(void)
1636 {
1637 	struct fpsimd_last_state_struct *last =
1638 		this_cpu_ptr(&fpsimd_last_state);
1639 
1640 	WARN_ON(!system_supports_fpsimd());
1641 	last->st = &current->thread.uw.fpsimd_state;
1642 	last->sve_state = current->thread.sve_state;
1643 	last->za_state = current->thread.za_state;
1644 	last->sve_vl = task_get_sve_vl(current);
1645 	last->sme_vl = task_get_sme_vl(current);
1646 	last->svcr = &current->thread.svcr;
1647 	current->thread.fpsimd_cpu = smp_processor_id();
1648 
1649 	/*
1650 	 * Toggle SVE and SME trapping for userspace if needed, these
1651 	 * are serialsied by ret_to_user().
1652 	 */
1653 	if (system_supports_sme()) {
1654 		if (test_thread_flag(TIF_SME))
1655 			sme_user_enable();
1656 		else
1657 			sme_user_disable();
1658 	}
1659 
1660 	if (system_supports_sve()) {
1661 		if (test_thread_flag(TIF_SVE))
1662 			sve_user_enable();
1663 		else
1664 			sve_user_disable();
1665 	}
1666 }
1667 
fpsimd_bind_state_to_cpu(struct user_fpsimd_state * st,void * sve_state,unsigned int sve_vl,void * za_state,unsigned int sme_vl,u64 * svcr)1668 void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state,
1669 			      unsigned int sve_vl, void *za_state,
1670 			      unsigned int sme_vl, u64 *svcr)
1671 {
1672 	struct fpsimd_last_state_struct *last =
1673 		this_cpu_ptr(&fpsimd_last_state);
1674 
1675 	WARN_ON(!system_supports_fpsimd());
1676 	WARN_ON(!in_softirq() && !irqs_disabled());
1677 
1678 	last->st = st;
1679 	last->svcr = svcr;
1680 	last->sve_state = sve_state;
1681 	last->za_state = za_state;
1682 	last->sve_vl = sve_vl;
1683 	last->sme_vl = sme_vl;
1684 }
1685 
1686 /*
1687  * Load the userland FPSIMD state of 'current' from memory, but only if the
1688  * FPSIMD state already held in the registers is /not/ the most recent FPSIMD
1689  * state of 'current'.  This is called when we are preparing to return to
1690  * userspace to ensure that userspace sees a good register state.
1691  */
fpsimd_restore_current_state(void)1692 void fpsimd_restore_current_state(void)
1693 {
1694 	/*
1695 	 * For the tasks that were created before we detected the absence of
1696 	 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(),
1697 	 * e.g, init. This could be then inherited by the children processes.
1698 	 * If we later detect that the system doesn't support FP/SIMD,
1699 	 * we must clear the flag for  all the tasks to indicate that the
1700 	 * FPSTATE is clean (as we can't have one) to avoid looping for ever in
1701 	 * do_notify_resume().
1702 	 */
1703 	if (!system_supports_fpsimd()) {
1704 		clear_thread_flag(TIF_FOREIGN_FPSTATE);
1705 		return;
1706 	}
1707 
1708 	get_cpu_fpsimd_context();
1709 
1710 	if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
1711 		task_fpsimd_load();
1712 		fpsimd_bind_task_to_cpu();
1713 	}
1714 
1715 	put_cpu_fpsimd_context();
1716 }
1717 
1718 /*
1719  * Load an updated userland FPSIMD state for 'current' from memory and set the
1720  * flag that indicates that the FPSIMD register contents are the most recent
1721  * FPSIMD state of 'current'. This is used by the signal code to restore the
1722  * register state when returning from a signal handler in FPSIMD only cases,
1723  * any SVE context will be discarded.
1724  */
fpsimd_update_current_state(struct user_fpsimd_state const * state)1725 void fpsimd_update_current_state(struct user_fpsimd_state const *state)
1726 {
1727 	if (WARN_ON(!system_supports_fpsimd()))
1728 		return;
1729 
1730 	get_cpu_fpsimd_context();
1731 
1732 	current->thread.uw.fpsimd_state = *state;
1733 	if (test_thread_flag(TIF_SVE))
1734 		fpsimd_to_sve(current);
1735 
1736 	task_fpsimd_load();
1737 	fpsimd_bind_task_to_cpu();
1738 
1739 	clear_thread_flag(TIF_FOREIGN_FPSTATE);
1740 
1741 	put_cpu_fpsimd_context();
1742 }
1743 
1744 /*
1745  * Invalidate live CPU copies of task t's FPSIMD state
1746  *
1747  * This function may be called with preemption enabled.  The barrier()
1748  * ensures that the assignment to fpsimd_cpu is visible to any
1749  * preemption/softirq that could race with set_tsk_thread_flag(), so
1750  * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared.
1751  *
1752  * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any
1753  * subsequent code.
1754  */
fpsimd_flush_task_state(struct task_struct * t)1755 void fpsimd_flush_task_state(struct task_struct *t)
1756 {
1757 	t->thread.fpsimd_cpu = NR_CPUS;
1758 	/*
1759 	 * If we don't support fpsimd, bail out after we have
1760 	 * reset the fpsimd_cpu for this task and clear the
1761 	 * FPSTATE.
1762 	 */
1763 	if (!system_supports_fpsimd())
1764 		return;
1765 	barrier();
1766 	set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE);
1767 
1768 	barrier();
1769 }
1770 
1771 /*
1772  * Invalidate any task's FPSIMD state that is present on this cpu.
1773  * The FPSIMD context should be acquired with get_cpu_fpsimd_context()
1774  * before calling this function.
1775  */
fpsimd_flush_cpu_state(void)1776 static void fpsimd_flush_cpu_state(void)
1777 {
1778 	WARN_ON(!system_supports_fpsimd());
1779 	__this_cpu_write(fpsimd_last_state.st, NULL);
1780 
1781 	/*
1782 	 * Leaving streaming mode enabled will cause issues for any kernel
1783 	 * NEON and leaving streaming mode or ZA enabled may increase power
1784 	 * consumption.
1785 	 */
1786 	if (system_supports_sme())
1787 		sme_smstop();
1788 
1789 	set_thread_flag(TIF_FOREIGN_FPSTATE);
1790 }
1791 
1792 /*
1793  * Save the FPSIMD state to memory and invalidate cpu view.
1794  * This function must be called with preemption disabled.
1795  */
fpsimd_save_and_flush_cpu_state(void)1796 void fpsimd_save_and_flush_cpu_state(void)
1797 {
1798 	if (!system_supports_fpsimd())
1799 		return;
1800 	WARN_ON(preemptible());
1801 	__get_cpu_fpsimd_context();
1802 	fpsimd_save();
1803 	fpsimd_flush_cpu_state();
1804 	__put_cpu_fpsimd_context();
1805 }
1806 
1807 #ifdef CONFIG_KERNEL_MODE_NEON
1808 
1809 /*
1810  * Kernel-side NEON support functions
1811  */
1812 
1813 /*
1814  * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling
1815  * context
1816  *
1817  * Must not be called unless may_use_simd() returns true.
1818  * Task context in the FPSIMD registers is saved back to memory as necessary.
1819  *
1820  * A matching call to kernel_neon_end() must be made before returning from the
1821  * calling context.
1822  *
1823  * The caller may freely use the FPSIMD registers until kernel_neon_end() is
1824  * called.
1825  */
kernel_neon_begin(void)1826 void kernel_neon_begin(void)
1827 {
1828 	if (WARN_ON(!system_supports_fpsimd()))
1829 		return;
1830 
1831 	BUG_ON(!may_use_simd());
1832 
1833 	get_cpu_fpsimd_context();
1834 
1835 	/* Save unsaved fpsimd state, if any: */
1836 	fpsimd_save();
1837 
1838 	/* Invalidate any task state remaining in the fpsimd regs: */
1839 	fpsimd_flush_cpu_state();
1840 }
1841 EXPORT_SYMBOL(kernel_neon_begin);
1842 
1843 /*
1844  * kernel_neon_end(): give the CPU FPSIMD registers back to the current task
1845  *
1846  * Must be called from a context in which kernel_neon_begin() was previously
1847  * called, with no call to kernel_neon_end() in the meantime.
1848  *
1849  * The caller must not use the FPSIMD registers after this function is called,
1850  * unless kernel_neon_begin() is called again in the meantime.
1851  */
kernel_neon_end(void)1852 void kernel_neon_end(void)
1853 {
1854 	if (!system_supports_fpsimd())
1855 		return;
1856 
1857 	put_cpu_fpsimd_context();
1858 }
1859 EXPORT_SYMBOL(kernel_neon_end);
1860 
1861 #ifdef CONFIG_EFI
1862 
1863 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state);
1864 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used);
1865 static DEFINE_PER_CPU(bool, efi_sve_state_used);
1866 static DEFINE_PER_CPU(bool, efi_sm_state);
1867 
1868 /*
1869  * EFI runtime services support functions
1870  *
1871  * The ABI for EFI runtime services allows EFI to use FPSIMD during the call.
1872  * This means that for EFI (and only for EFI), we have to assume that FPSIMD
1873  * is always used rather than being an optional accelerator.
1874  *
1875  * These functions provide the necessary support for ensuring FPSIMD
1876  * save/restore in the contexts from which EFI is used.
1877  *
1878  * Do not use them for any other purpose -- if tempted to do so, you are
1879  * either doing something wrong or you need to propose some refactoring.
1880  */
1881 
1882 /*
1883  * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call
1884  */
__efi_fpsimd_begin(void)1885 void __efi_fpsimd_begin(void)
1886 {
1887 	if (!system_supports_fpsimd())
1888 		return;
1889 
1890 	WARN_ON(preemptible());
1891 
1892 	if (may_use_simd()) {
1893 		kernel_neon_begin();
1894 	} else {
1895 		/*
1896 		 * If !efi_sve_state, SVE can't be in use yet and doesn't need
1897 		 * preserving:
1898 		 */
1899 		if (system_supports_sve() && likely(efi_sve_state)) {
1900 			char *sve_state = this_cpu_ptr(efi_sve_state);
1901 			bool ffr = true;
1902 			u64 svcr;
1903 
1904 			__this_cpu_write(efi_sve_state_used, true);
1905 
1906 			if (system_supports_sme()) {
1907 				svcr = read_sysreg_s(SYS_SVCR);
1908 
1909 				__this_cpu_write(efi_sm_state,
1910 						 svcr & SVCR_SM_MASK);
1911 
1912 				/*
1913 				 * Unless we have FA64 FFR does not
1914 				 * exist in streaming mode.
1915 				 */
1916 				if (!system_supports_fa64())
1917 					ffr = !(svcr & SVCR_SM_MASK);
1918 			}
1919 
1920 			sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()),
1921 				       &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
1922 				       ffr);
1923 
1924 			if (system_supports_sme())
1925 				sysreg_clear_set_s(SYS_SVCR,
1926 						   SVCR_SM_MASK, 0);
1927 
1928 		} else {
1929 			fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
1930 		}
1931 
1932 		__this_cpu_write(efi_fpsimd_state_used, true);
1933 	}
1934 }
1935 
1936 /*
1937  * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call
1938  */
__efi_fpsimd_end(void)1939 void __efi_fpsimd_end(void)
1940 {
1941 	if (!system_supports_fpsimd())
1942 		return;
1943 
1944 	if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) {
1945 		kernel_neon_end();
1946 	} else {
1947 		if (system_supports_sve() &&
1948 		    likely(__this_cpu_read(efi_sve_state_used))) {
1949 			char const *sve_state = this_cpu_ptr(efi_sve_state);
1950 			bool ffr = true;
1951 
1952 			/*
1953 			 * Restore streaming mode; EFI calls are
1954 			 * normal function calls so should not return in
1955 			 * streaming mode.
1956 			 */
1957 			if (system_supports_sme()) {
1958 				if (__this_cpu_read(efi_sm_state)) {
1959 					sysreg_clear_set_s(SYS_SVCR,
1960 							   0,
1961 							   SVCR_SM_MASK);
1962 
1963 					/*
1964 					 * Unless we have FA64 FFR does not
1965 					 * exist in streaming mode.
1966 					 */
1967 					if (!system_supports_fa64())
1968 						ffr = false;
1969 				}
1970 			}
1971 
1972 			sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()),
1973 				       &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
1974 				       ffr);
1975 
1976 			__this_cpu_write(efi_sve_state_used, false);
1977 		} else {
1978 			fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state));
1979 		}
1980 	}
1981 }
1982 
1983 #endif /* CONFIG_EFI */
1984 
1985 #endif /* CONFIG_KERNEL_MODE_NEON */
1986 
1987 #ifdef CONFIG_CPU_PM
fpsimd_cpu_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)1988 static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
1989 				  unsigned long cmd, void *v)
1990 {
1991 	switch (cmd) {
1992 	case CPU_PM_ENTER:
1993 		fpsimd_save_and_flush_cpu_state();
1994 		break;
1995 	case CPU_PM_EXIT:
1996 		break;
1997 	case CPU_PM_ENTER_FAILED:
1998 	default:
1999 		return NOTIFY_DONE;
2000 	}
2001 	return NOTIFY_OK;
2002 }
2003 
2004 static struct notifier_block fpsimd_cpu_pm_notifier_block = {
2005 	.notifier_call = fpsimd_cpu_pm_notifier,
2006 };
2007 
fpsimd_pm_init(void)2008 static void __init fpsimd_pm_init(void)
2009 {
2010 	cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block);
2011 }
2012 
2013 #else
fpsimd_pm_init(void)2014 static inline void fpsimd_pm_init(void) { }
2015 #endif /* CONFIG_CPU_PM */
2016 
2017 #ifdef CONFIG_HOTPLUG_CPU
fpsimd_cpu_dead(unsigned int cpu)2018 static int fpsimd_cpu_dead(unsigned int cpu)
2019 {
2020 	per_cpu(fpsimd_last_state.st, cpu) = NULL;
2021 	return 0;
2022 }
2023 
fpsimd_hotplug_init(void)2024 static inline void fpsimd_hotplug_init(void)
2025 {
2026 	cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead",
2027 				  NULL, fpsimd_cpu_dead);
2028 }
2029 
2030 #else
fpsimd_hotplug_init(void)2031 static inline void fpsimd_hotplug_init(void) { }
2032 #endif
2033 
2034 /*
2035  * FP/SIMD support code initialisation.
2036  */
fpsimd_init(void)2037 static int __init fpsimd_init(void)
2038 {
2039 	if (cpu_have_named_feature(FP)) {
2040 		fpsimd_pm_init();
2041 		fpsimd_hotplug_init();
2042 	} else {
2043 		pr_notice("Floating-point is not implemented\n");
2044 	}
2045 
2046 	if (!cpu_have_named_feature(ASIMD))
2047 		pr_notice("Advanced SIMD is not implemented\n");
2048 
2049 
2050 	if (cpu_have_named_feature(SME) && !cpu_have_named_feature(SVE))
2051 		pr_notice("SME is implemented but not SVE\n");
2052 
2053 	sve_sysctl_init();
2054 	sme_sysctl_init();
2055 
2056 	return 0;
2057 }
2058 core_initcall(fpsimd_init);
2059