1 /*
2  *  linux/arch/m68k/kernel/traps.c
3  *
4  *  Copyright (C) 1993, 1994 by Hamish Macdonald
5  *
6  *  68040 fixes by Michael Rausch
7  *  68040 fixes by Martin Apel
8  *  68040 fixes and writeback by Richard Zidlicky
9  *  68060 fixes by Roman Hodek
10  *  68060 fixes by Jesper Skov
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive
14  * for more details.
15  */
16 
17 /*
18  * Sets up all exception vectors
19  */
20 
21 #include <linux/sched.h>
22 #include <linux/sched/debug.h>
23 #include <linux/signal.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/module.h>
27 #include <linux/user.h>
28 #include <linux/string.h>
29 #include <linux/linkage.h>
30 #include <linux/init.h>
31 #include <linux/ptrace.h>
32 #include <linux/kallsyms.h>
33 
34 #include <asm/setup.h>
35 #include <asm/fpu.h>
36 #include <linux/uaccess.h>
37 #include <asm/traps.h>
38 #include <asm/machdep.h>
39 #include <asm/processor.h>
40 #include <asm/siginfo.h>
41 #include <asm/tlbflush.h>
42 
43 static const char *vec_names[] = {
44 	[VEC_RESETSP]	= "RESET SP",
45 	[VEC_RESETPC]	= "RESET PC",
46 	[VEC_BUSERR]	= "BUS ERROR",
47 	[VEC_ADDRERR]	= "ADDRESS ERROR",
48 	[VEC_ILLEGAL]	= "ILLEGAL INSTRUCTION",
49 	[VEC_ZERODIV]	= "ZERO DIVIDE",
50 	[VEC_CHK]	= "CHK",
51 	[VEC_TRAP]	= "TRAPcc",
52 	[VEC_PRIV]	= "PRIVILEGE VIOLATION",
53 	[VEC_TRACE]	= "TRACE",
54 	[VEC_LINE10]	= "LINE 1010",
55 	[VEC_LINE11]	= "LINE 1111",
56 	[VEC_RESV12]	= "UNASSIGNED RESERVED 12",
57 	[VEC_COPROC]	= "COPROCESSOR PROTOCOL VIOLATION",
58 	[VEC_FORMAT]	= "FORMAT ERROR",
59 	[VEC_UNINT]	= "UNINITIALIZED INTERRUPT",
60 	[VEC_RESV16]	= "UNASSIGNED RESERVED 16",
61 	[VEC_RESV17]	= "UNASSIGNED RESERVED 17",
62 	[VEC_RESV18]	= "UNASSIGNED RESERVED 18",
63 	[VEC_RESV19]	= "UNASSIGNED RESERVED 19",
64 	[VEC_RESV20]	= "UNASSIGNED RESERVED 20",
65 	[VEC_RESV21]	= "UNASSIGNED RESERVED 21",
66 	[VEC_RESV22]	= "UNASSIGNED RESERVED 22",
67 	[VEC_RESV23]	= "UNASSIGNED RESERVED 23",
68 	[VEC_SPUR]	= "SPURIOUS INTERRUPT",
69 	[VEC_INT1]	= "LEVEL 1 INT",
70 	[VEC_INT2]	= "LEVEL 2 INT",
71 	[VEC_INT3]	= "LEVEL 3 INT",
72 	[VEC_INT4]	= "LEVEL 4 INT",
73 	[VEC_INT5]	= "LEVEL 5 INT",
74 	[VEC_INT6]	= "LEVEL 6 INT",
75 	[VEC_INT7]	= "LEVEL 7 INT",
76 	[VEC_SYS]	= "SYSCALL",
77 	[VEC_TRAP1]	= "TRAP #1",
78 	[VEC_TRAP2]	= "TRAP #2",
79 	[VEC_TRAP3]	= "TRAP #3",
80 	[VEC_TRAP4]	= "TRAP #4",
81 	[VEC_TRAP5]	= "TRAP #5",
82 	[VEC_TRAP6]	= "TRAP #6",
83 	[VEC_TRAP7]	= "TRAP #7",
84 	[VEC_TRAP8]	= "TRAP #8",
85 	[VEC_TRAP9]	= "TRAP #9",
86 	[VEC_TRAP10]	= "TRAP #10",
87 	[VEC_TRAP11]	= "TRAP #11",
88 	[VEC_TRAP12]	= "TRAP #12",
89 	[VEC_TRAP13]	= "TRAP #13",
90 	[VEC_TRAP14]	= "TRAP #14",
91 	[VEC_TRAP15]	= "TRAP #15",
92 	[VEC_FPBRUC]	= "FPCP BSUN",
93 	[VEC_FPIR]	= "FPCP INEXACT",
94 	[VEC_FPDIVZ]	= "FPCP DIV BY 0",
95 	[VEC_FPUNDER]	= "FPCP UNDERFLOW",
96 	[VEC_FPOE]	= "FPCP OPERAND ERROR",
97 	[VEC_FPOVER]	= "FPCP OVERFLOW",
98 	[VEC_FPNAN]	= "FPCP SNAN",
99 	[VEC_FPUNSUP]	= "FPCP UNSUPPORTED OPERATION",
100 	[VEC_MMUCFG]	= "MMU CONFIGURATION ERROR",
101 	[VEC_MMUILL]	= "MMU ILLEGAL OPERATION ERROR",
102 	[VEC_MMUACC]	= "MMU ACCESS LEVEL VIOLATION ERROR",
103 	[VEC_RESV59]	= "UNASSIGNED RESERVED 59",
104 	[VEC_UNIMPEA]	= "UNASSIGNED RESERVED 60",
105 	[VEC_UNIMPII]	= "UNASSIGNED RESERVED 61",
106 	[VEC_RESV62]	= "UNASSIGNED RESERVED 62",
107 	[VEC_RESV63]	= "UNASSIGNED RESERVED 63",
108 };
109 
110 static const char *space_names[] = {
111 	[0]		= "Space 0",
112 	[USER_DATA]	= "User Data",
113 	[USER_PROGRAM]	= "User Program",
114 #ifndef CONFIG_SUN3
115 	[3]		= "Space 3",
116 #else
117 	[FC_CONTROL]	= "Control",
118 #endif
119 	[4]		= "Space 4",
120 	[SUPER_DATA]	= "Super Data",
121 	[SUPER_PROGRAM]	= "Super Program",
122 	[CPU_SPACE]	= "CPU"
123 };
124 
125 void die_if_kernel(char *,struct pt_regs *,int);
126 asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
127                              unsigned long error_code);
128 int send_fault_sig(struct pt_regs *regs);
129 
130 asmlinkage void trap_c(struct frame *fp);
131 
132 #if defined (CONFIG_M68060)
access_error060(struct frame * fp)133 static inline void access_error060 (struct frame *fp)
134 {
135 	unsigned long fslw = fp->un.fmt4.pc; /* is really FSLW for access error */
136 
137 	pr_debug("fslw=%#lx, fa=%#lx\n", fslw, fp->un.fmt4.effaddr);
138 
139 	if (fslw & MMU060_BPE) {
140 		/* branch prediction error -> clear branch cache */
141 		__asm__ __volatile__ ("movec %/cacr,%/d0\n\t"
142 				      "orl   #0x00400000,%/d0\n\t"
143 				      "movec %/d0,%/cacr"
144 				      : : : "d0" );
145 		/* return if there's no other error */
146 		if (!(fslw & MMU060_ERR_BITS) && !(fslw & MMU060_SEE))
147 			return;
148 	}
149 
150 	if (fslw & (MMU060_DESC_ERR | MMU060_WP | MMU060_SP)) {
151 		unsigned long errorcode;
152 		unsigned long addr = fp->un.fmt4.effaddr;
153 
154 		if (fslw & MMU060_MA)
155 			addr = (addr + PAGE_SIZE - 1) & PAGE_MASK;
156 
157 		errorcode = 1;
158 		if (fslw & MMU060_DESC_ERR) {
159 			__flush_tlb040_one(addr);
160 			errorcode = 0;
161 		}
162 		if (fslw & MMU060_W)
163 			errorcode |= 2;
164 		pr_debug("errorcode = %ld\n", errorcode);
165 		do_page_fault(&fp->ptregs, addr, errorcode);
166 	} else if (fslw & (MMU060_SEE)){
167 		/* Software Emulation Error.
168 		 * fault during mem_read/mem_write in ifpsp060/os.S
169 		 */
170 		send_fault_sig(&fp->ptregs);
171 	} else if (!(fslw & (MMU060_RE|MMU060_WE)) ||
172 		   send_fault_sig(&fp->ptregs) > 0) {
173 		pr_err("pc=%#lx, fa=%#lx\n", fp->ptregs.pc,
174 		       fp->un.fmt4.effaddr);
175 		pr_err("68060 access error, fslw=%lx\n", fslw);
176 		trap_c( fp );
177 	}
178 }
179 #endif /* CONFIG_M68060 */
180 
181 #if defined (CONFIG_M68040)
probe040(int iswrite,unsigned long addr,int wbs)182 static inline unsigned long probe040(int iswrite, unsigned long addr, int wbs)
183 {
184 	unsigned long mmusr;
185 
186 	set_fc(wbs);
187 
188 	if (iswrite)
189 		asm volatile (".chip 68040; ptestw (%0); .chip 68k" : : "a" (addr));
190 	else
191 		asm volatile (".chip 68040; ptestr (%0); .chip 68k" : : "a" (addr));
192 
193 	asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr));
194 
195 	set_fc(USER_DATA);
196 
197 	return mmusr;
198 }
199 
do_040writeback1(unsigned short wbs,unsigned long wba,unsigned long wbd)200 static inline int do_040writeback1(unsigned short wbs, unsigned long wba,
201 				   unsigned long wbd)
202 {
203 	int res = 0;
204 
205 	set_fc(wbs);
206 
207 	switch (wbs & WBSIZ_040) {
208 	case BA_SIZE_BYTE:
209 		res = put_user(wbd & 0xff, (char __user *)wba);
210 		break;
211 	case BA_SIZE_WORD:
212 		res = put_user(wbd & 0xffff, (short __user *)wba);
213 		break;
214 	case BA_SIZE_LONG:
215 		res = put_user(wbd, (int __user *)wba);
216 		break;
217 	}
218 
219 	set_fc(USER_DATA);
220 
221 	pr_debug("do_040writeback1, res=%d\n", res);
222 
223 	return res;
224 }
225 
226 /* after an exception in a writeback the stack frame corresponding
227  * to that exception is discarded, set a few bits in the old frame
228  * to simulate what it should look like
229  */
fix_xframe040(struct frame * fp,unsigned long wba,unsigned short wbs)230 static inline void fix_xframe040(struct frame *fp, unsigned long wba, unsigned short wbs)
231 {
232 	fp->un.fmt7.faddr = wba;
233 	fp->un.fmt7.ssw = wbs & 0xff;
234 	if (wba != current->thread.faddr)
235 	    fp->un.fmt7.ssw |= MA_040;
236 }
237 
do_040writebacks(struct frame * fp)238 static inline void do_040writebacks(struct frame *fp)
239 {
240 	int res = 0;
241 #if 0
242 	if (fp->un.fmt7.wb1s & WBV_040)
243 		pr_err("access_error040: cannot handle 1st writeback. oops.\n");
244 #endif
245 
246 	if ((fp->un.fmt7.wb2s & WBV_040) &&
247 	    !(fp->un.fmt7.wb2s & WBTT_040)) {
248 		res = do_040writeback1(fp->un.fmt7.wb2s, fp->un.fmt7.wb2a,
249 				       fp->un.fmt7.wb2d);
250 		if (res)
251 			fix_xframe040(fp, fp->un.fmt7.wb2a, fp->un.fmt7.wb2s);
252 		else
253 			fp->un.fmt7.wb2s = 0;
254 	}
255 
256 	/* do the 2nd wb only if the first one was successful (except for a kernel wb) */
257 	if (fp->un.fmt7.wb3s & WBV_040 && (!res || fp->un.fmt7.wb3s & 4)) {
258 		res = do_040writeback1(fp->un.fmt7.wb3s, fp->un.fmt7.wb3a,
259 				       fp->un.fmt7.wb3d);
260 		if (res)
261 		    {
262 			fix_xframe040(fp, fp->un.fmt7.wb3a, fp->un.fmt7.wb3s);
263 
264 			fp->un.fmt7.wb2s = fp->un.fmt7.wb3s;
265 			fp->un.fmt7.wb3s &= (~WBV_040);
266 			fp->un.fmt7.wb2a = fp->un.fmt7.wb3a;
267 			fp->un.fmt7.wb2d = fp->un.fmt7.wb3d;
268 		    }
269 		else
270 			fp->un.fmt7.wb3s = 0;
271 	}
272 
273 	if (res)
274 		send_fault_sig(&fp->ptregs);
275 }
276 
277 /*
278  * called from sigreturn(), must ensure userspace code didn't
279  * manipulate exception frame to circumvent protection, then complete
280  * pending writebacks
281  * we just clear TM2 to turn it into a userspace access
282  */
berr_040cleanup(struct frame * fp)283 asmlinkage void berr_040cleanup(struct frame *fp)
284 {
285 	fp->un.fmt7.wb2s &= ~4;
286 	fp->un.fmt7.wb3s &= ~4;
287 
288 	do_040writebacks(fp);
289 }
290 
access_error040(struct frame * fp)291 static inline void access_error040(struct frame *fp)
292 {
293 	unsigned short ssw = fp->un.fmt7.ssw;
294 	unsigned long mmusr;
295 
296 	pr_debug("ssw=%#x, fa=%#lx\n", ssw, fp->un.fmt7.faddr);
297 	pr_debug("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s,
298 		fp->un.fmt7.wb2s, fp->un.fmt7.wb3s);
299 	pr_debug("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n",
300 		fp->un.fmt7.wb2a, fp->un.fmt7.wb3a,
301 		fp->un.fmt7.wb2d, fp->un.fmt7.wb3d);
302 
303 	if (ssw & ATC_040) {
304 		unsigned long addr = fp->un.fmt7.faddr;
305 		unsigned long errorcode;
306 
307 		/*
308 		 * The MMU status has to be determined AFTER the address
309 		 * has been corrected if there was a misaligned access (MA).
310 		 */
311 		if (ssw & MA_040)
312 			addr = (addr + 7) & -8;
313 
314 		/* MMU error, get the MMUSR info for this access */
315 		mmusr = probe040(!(ssw & RW_040), addr, ssw);
316 		pr_debug("mmusr = %lx\n", mmusr);
317 		errorcode = 1;
318 		if (!(mmusr & MMU_R_040)) {
319 			/* clear the invalid atc entry */
320 			__flush_tlb040_one(addr);
321 			errorcode = 0;
322 		}
323 
324 		/* despite what documentation seems to say, RMW
325 		 * accesses have always both the LK and RW bits set */
326 		if (!(ssw & RW_040) || (ssw & LK_040))
327 			errorcode |= 2;
328 
329 		if (do_page_fault(&fp->ptregs, addr, errorcode)) {
330 			pr_debug("do_page_fault() !=0\n");
331 			if (user_mode(&fp->ptregs)){
332 				/* delay writebacks after signal delivery */
333 				pr_debug(".. was usermode - return\n");
334 				return;
335 			}
336 			/* disable writeback into user space from kernel
337 			 * (if do_page_fault didn't fix the mapping,
338                          * the writeback won't do good)
339 			 */
340 disable_wb:
341 			pr_debug(".. disabling wb2\n");
342 			if (fp->un.fmt7.wb2a == fp->un.fmt7.faddr)
343 				fp->un.fmt7.wb2s &= ~WBV_040;
344 			if (fp->un.fmt7.wb3a == fp->un.fmt7.faddr)
345 				fp->un.fmt7.wb3s &= ~WBV_040;
346 		}
347 	} else {
348 		/* In case of a bus error we either kill the process or expect
349 		 * the kernel to catch the fault, which then is also responsible
350 		 * for cleaning up the mess.
351 		 */
352 		current->thread.signo = SIGBUS;
353 		current->thread.faddr = fp->un.fmt7.faddr;
354 		if (send_fault_sig(&fp->ptregs) >= 0)
355 			pr_err("68040 bus error (ssw=%x, faddr=%lx)\n", ssw,
356 			       fp->un.fmt7.faddr);
357 		goto disable_wb;
358 	}
359 
360 	do_040writebacks(fp);
361 }
362 #endif /* CONFIG_M68040 */
363 
364 #if defined(CONFIG_SUN3)
365 #include <asm/sun3mmu.h>
366 
367 extern int mmu_emu_handle_fault (unsigned long, int, int);
368 
369 /* sun3 version of bus_error030 */
370 
bus_error030(struct frame * fp)371 static inline void bus_error030 (struct frame *fp)
372 {
373 	unsigned char buserr_type = sun3_get_buserr ();
374 	unsigned long addr, errorcode;
375 	unsigned short ssw = fp->un.fmtb.ssw;
376 	extern unsigned long _sun3_map_test_start, _sun3_map_test_end;
377 
378 	if (ssw & (FC | FB))
379 		pr_debug("Instruction fault at %#010lx\n",
380 			ssw & FC ?
381 			fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
382 			:
383 			fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
384 	if (ssw & DF)
385 		pr_debug("Data %s fault at %#010lx in %s (pc=%#lx)\n",
386 			ssw & RW ? "read" : "write",
387 			fp->un.fmtb.daddr,
388 			space_names[ssw & DFC], fp->ptregs.pc);
389 
390 	/*
391 	 * Check if this page should be demand-mapped. This needs to go before
392 	 * the testing for a bad kernel-space access (demand-mapping applies
393 	 * to kernel accesses too).
394 	 */
395 
396 	if ((ssw & DF)
397 	    && (buserr_type & (SUN3_BUSERR_PROTERR | SUN3_BUSERR_INVALID))) {
398 		if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 0))
399 			return;
400 	}
401 
402 	/* Check for kernel-space pagefault (BAD). */
403 	if (fp->ptregs.sr & PS_S) {
404 		/* kernel fault must be a data fault to user space */
405 		if (! ((ssw & DF) && ((ssw & DFC) == USER_DATA))) {
406 		     // try checking the kernel mappings before surrender
407 		     if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 1))
408 			  return;
409 			/* instruction fault or kernel data fault! */
410 			if (ssw & (FC | FB))
411 				pr_err("Instruction fault at %#010lx\n",
412 					fp->ptregs.pc);
413 			if (ssw & DF) {
414 				/* was this fault incurred testing bus mappings? */
415 				if((fp->ptregs.pc >= (unsigned long)&_sun3_map_test_start) &&
416 				   (fp->ptregs.pc <= (unsigned long)&_sun3_map_test_end)) {
417 					send_fault_sig(&fp->ptregs);
418 					return;
419 				}
420 
421 				pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n",
422 					ssw & RW ? "read" : "write",
423 					fp->un.fmtb.daddr,
424 					space_names[ssw & DFC], fp->ptregs.pc);
425 			}
426 			pr_err("BAD KERNEL BUSERR\n");
427 
428 			die_if_kernel("Oops", &fp->ptregs,0);
429 			force_sig(SIGKILL);
430 			return;
431 		}
432 	} else {
433 		/* user fault */
434 		if (!(ssw & (FC | FB)) && !(ssw & DF))
435 			/* not an instruction fault or data fault! BAD */
436 			panic ("USER BUSERR w/o instruction or data fault");
437 	}
438 
439 
440 	/* First handle the data fault, if any.  */
441 	if (ssw & DF) {
442 		addr = fp->un.fmtb.daddr;
443 
444 // errorcode bit 0:	0 -> no page		1 -> protection fault
445 // errorcode bit 1:	0 -> read fault		1 -> write fault
446 
447 // (buserr_type & SUN3_BUSERR_PROTERR)	-> protection fault
448 // (buserr_type & SUN3_BUSERR_INVALID)	-> invalid page fault
449 
450 		if (buserr_type & SUN3_BUSERR_PROTERR)
451 			errorcode = 0x01;
452 		else if (buserr_type & SUN3_BUSERR_INVALID)
453 			errorcode = 0x00;
454 		else {
455 			pr_debug("*** unexpected busfault type=%#04x\n",
456 				 buserr_type);
457 			pr_debug("invalid %s access at %#lx from pc %#lx\n",
458 				 !(ssw & RW) ? "write" : "read", addr,
459 				 fp->ptregs.pc);
460 			die_if_kernel ("Oops", &fp->ptregs, buserr_type);
461 			force_sig (SIGBUS);
462 			return;
463 		}
464 
465 //todo: wtf is RM bit? --m
466 		if (!(ssw & RW) || ssw & RM)
467 			errorcode |= 0x02;
468 
469 		/* Handle page fault. */
470 		do_page_fault (&fp->ptregs, addr, errorcode);
471 
472 		/* Retry the data fault now. */
473 		return;
474 	}
475 
476 	/* Now handle the instruction fault. */
477 
478 	/* Get the fault address. */
479 	if (fp->ptregs.format == 0xA)
480 		addr = fp->ptregs.pc + 4;
481 	else
482 		addr = fp->un.fmtb.baddr;
483 	if (ssw & FC)
484 		addr -= 2;
485 
486 	if (buserr_type & SUN3_BUSERR_INVALID) {
487 		if (!mmu_emu_handle_fault(addr, 1, 0))
488 			do_page_fault (&fp->ptregs, addr, 0);
489        } else {
490 		pr_debug("protection fault on insn access (segv).\n");
491 		force_sig (SIGSEGV);
492        }
493 }
494 #else
495 #if defined(CPU_M68020_OR_M68030)
bus_error030(struct frame * fp)496 static inline void bus_error030 (struct frame *fp)
497 {
498 	volatile unsigned short temp;
499 	unsigned short mmusr;
500 	unsigned long addr, errorcode;
501 	unsigned short ssw = fp->un.fmtb.ssw;
502 #ifdef DEBUG
503 	unsigned long desc;
504 #endif
505 
506 	pr_debug("pid = %x  ", current->pid);
507 	pr_debug("SSW=%#06x  ", ssw);
508 
509 	if (ssw & (FC | FB))
510 		pr_debug("Instruction fault at %#010lx\n",
511 			ssw & FC ?
512 			fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
513 			:
514 			fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
515 	if (ssw & DF)
516 		pr_debug("Data %s fault at %#010lx in %s (pc=%#lx)\n",
517 			ssw & RW ? "read" : "write",
518 			fp->un.fmtb.daddr,
519 			space_names[ssw & DFC], fp->ptregs.pc);
520 
521 	/* ++andreas: If a data fault and an instruction fault happen
522 	   at the same time map in both pages.  */
523 
524 	/* First handle the data fault, if any.  */
525 	if (ssw & DF) {
526 		addr = fp->un.fmtb.daddr;
527 
528 #ifdef DEBUG
529 		asm volatile ("ptestr %3,%2@,#7,%0\n\t"
530 			      "pmove %%psr,%1"
531 			      : "=a&" (desc), "=m" (temp)
532 			      : "a" (addr), "d" (ssw));
533 		pr_debug("mmusr is %#x for addr %#lx in task %p\n",
534 			 temp, addr, current);
535 		pr_debug("descriptor address is 0x%p, contents %#lx\n",
536 			 __va(desc), *(unsigned long *)__va(desc));
537 #else
538 		asm volatile ("ptestr %2,%1@,#7\n\t"
539 			      "pmove %%psr,%0"
540 			      : "=m" (temp) : "a" (addr), "d" (ssw));
541 #endif
542 		mmusr = temp;
543 		errorcode = (mmusr & MMU_I) ? 0 : 1;
544 		if (!(ssw & RW) || (ssw & RM))
545 			errorcode |= 2;
546 
547 		if (mmusr & (MMU_I | MMU_WP)) {
548 			if (ssw & 4) {
549 				pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n",
550 				       ssw & RW ? "read" : "write",
551 				       fp->un.fmtb.daddr,
552 				       space_names[ssw & DFC], fp->ptregs.pc);
553 				goto buserr;
554 			}
555 			/* Don't try to do anything further if an exception was
556 			   handled. */
557 			if (do_page_fault (&fp->ptregs, addr, errorcode) < 0)
558 				return;
559 		} else if (!(mmusr & MMU_I)) {
560 			/* probably a 020 cas fault */
561 			if (!(ssw & RM) && send_fault_sig(&fp->ptregs) > 0)
562 				pr_err("unexpected bus error (%#x,%#x)\n", ssw,
563 				       mmusr);
564 		} else if (mmusr & (MMU_B|MMU_L|MMU_S)) {
565 			pr_err("invalid %s access at %#lx from pc %#lx\n",
566 			       !(ssw & RW) ? "write" : "read", addr,
567 			       fp->ptregs.pc);
568 			die_if_kernel("Oops",&fp->ptregs,mmusr);
569 			force_sig(SIGSEGV);
570 			return;
571 		} else {
572 #if 0
573 			static volatile long tlong;
574 #endif
575 
576 			pr_err("weird %s access at %#lx from pc %#lx (ssw is %#x)\n",
577 			       !(ssw & RW) ? "write" : "read", addr,
578 			       fp->ptregs.pc, ssw);
579 			asm volatile ("ptestr #1,%1@,#0\n\t"
580 				      "pmove %%psr,%0"
581 				      : "=m" (temp)
582 				      : "a" (addr));
583 			mmusr = temp;
584 
585 			pr_err("level 0 mmusr is %#x\n", mmusr);
586 #if 0
587 			asm volatile ("pmove %%tt0,%0"
588 				      : "=m" (tlong));
589 			pr_debug("tt0 is %#lx, ", tlong);
590 			asm volatile ("pmove %%tt1,%0"
591 				      : "=m" (tlong));
592 			pr_debug("tt1 is %#lx\n", tlong);
593 #endif
594 			pr_debug("Unknown SIGSEGV - 1\n");
595 			die_if_kernel("Oops",&fp->ptregs,mmusr);
596 			force_sig(SIGSEGV);
597 			return;
598 		}
599 
600 		/* setup an ATC entry for the access about to be retried */
601 		if (!(ssw & RW) || (ssw & RM))
602 			asm volatile ("ploadw %1,%0@" : /* no outputs */
603 				      : "a" (addr), "d" (ssw));
604 		else
605 			asm volatile ("ploadr %1,%0@" : /* no outputs */
606 				      : "a" (addr), "d" (ssw));
607 	}
608 
609 	/* Now handle the instruction fault. */
610 
611 	if (!(ssw & (FC|FB)))
612 		return;
613 
614 	if (fp->ptregs.sr & PS_S) {
615 		pr_err("Instruction fault at %#010lx\n", fp->ptregs.pc);
616 	buserr:
617 		pr_err("BAD KERNEL BUSERR\n");
618 		die_if_kernel("Oops",&fp->ptregs,0);
619 		force_sig(SIGKILL);
620 		return;
621 	}
622 
623 	/* get the fault address */
624 	if (fp->ptregs.format == 10)
625 		addr = fp->ptregs.pc + 4;
626 	else
627 		addr = fp->un.fmtb.baddr;
628 	if (ssw & FC)
629 		addr -= 2;
630 
631 	if ((ssw & DF) && ((addr ^ fp->un.fmtb.daddr) & PAGE_MASK) == 0)
632 		/* Insn fault on same page as data fault.  But we
633 		   should still create the ATC entry.  */
634 		goto create_atc_entry;
635 
636 #ifdef DEBUG
637 	asm volatile ("ptestr #1,%2@,#7,%0\n\t"
638 		      "pmove %%psr,%1"
639 		      : "=a&" (desc), "=m" (temp)
640 		      : "a" (addr));
641 	pr_debug("mmusr is %#x for addr %#lx in task %p\n",
642 		temp, addr, current);
643 	pr_debug("descriptor address is 0x%p, contents %#lx\n",
644 		__va(desc), *(unsigned long *)__va(desc));
645 #else
646 	asm volatile ("ptestr #1,%1@,#7\n\t"
647 		      "pmove %%psr,%0"
648 		      : "=m" (temp) : "a" (addr));
649 #endif
650 	mmusr = temp;
651 	if (mmusr & MMU_I)
652 		do_page_fault (&fp->ptregs, addr, 0);
653 	else if (mmusr & (MMU_B|MMU_L|MMU_S)) {
654 		pr_err("invalid insn access at %#lx from pc %#lx\n",
655 			addr, fp->ptregs.pc);
656 		pr_debug("Unknown SIGSEGV - 2\n");
657 		die_if_kernel("Oops",&fp->ptregs,mmusr);
658 		force_sig(SIGSEGV);
659 		return;
660 	}
661 
662 create_atc_entry:
663 	/* setup an ATC entry for the access about to be retried */
664 	asm volatile ("ploadr #2,%0@" : /* no outputs */
665 		      : "a" (addr));
666 }
667 #endif /* CPU_M68020_OR_M68030 */
668 #endif /* !CONFIG_SUN3 */
669 
670 #if defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
671 #include <asm/mcfmmu.h>
672 
673 /*
674  *	The following table converts the FS encoding of a ColdFire
675  *	exception stack frame into the error_code value needed by
676  *	do_fault.
677 */
678 static const unsigned char fs_err_code[] = {
679 	0,  /* 0000 */
680 	0,  /* 0001 */
681 	0,  /* 0010 */
682 	0,  /* 0011 */
683 	1,  /* 0100 */
684 	0,  /* 0101 */
685 	0,  /* 0110 */
686 	0,  /* 0111 */
687 	2,  /* 1000 */
688 	3,  /* 1001 */
689 	2,  /* 1010 */
690 	0,  /* 1011 */
691 	1,  /* 1100 */
692 	1,  /* 1101 */
693 	0,  /* 1110 */
694 	0   /* 1111 */
695 };
696 
access_errorcf(unsigned int fs,struct frame * fp)697 static inline void access_errorcf(unsigned int fs, struct frame *fp)
698 {
699 	unsigned long mmusr, addr;
700 	unsigned int err_code;
701 	int need_page_fault;
702 
703 	mmusr = mmu_read(MMUSR);
704 	addr = mmu_read(MMUAR);
705 
706 	/*
707 	 * error_code:
708 	 *	bit 0 == 0 means no page found, 1 means protection fault
709 	 *	bit 1 == 0 means read, 1 means write
710 	 */
711 	switch (fs) {
712 	case  5:  /* 0101 TLB opword X miss */
713 		need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 0);
714 		addr = fp->ptregs.pc;
715 		break;
716 	case  6:  /* 0110 TLB extension word X miss */
717 		need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 1);
718 		addr = fp->ptregs.pc + sizeof(long);
719 		break;
720 	case 10:  /* 1010 TLB W miss */
721 		need_page_fault = cf_tlb_miss(&fp->ptregs, 1, 1, 0);
722 		break;
723 	case 14: /* 1110 TLB R miss */
724 		need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 1, 0);
725 		break;
726 	default:
727 		/* 0000 Normal  */
728 		/* 0001 Reserved */
729 		/* 0010 Interrupt during debug service routine */
730 		/* 0011 Reserved */
731 		/* 0100 X Protection */
732 		/* 0111 IFP in emulator mode */
733 		/* 1000 W Protection*/
734 		/* 1001 Write error*/
735 		/* 1011 Reserved*/
736 		/* 1100 R Protection*/
737 		/* 1101 R Protection*/
738 		/* 1111 OEP in emulator mode*/
739 		need_page_fault = 1;
740 		break;
741 	}
742 
743 	if (need_page_fault) {
744 		err_code = fs_err_code[fs];
745 		if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */
746 			err_code |= 2; /* bit1 - write, bit0 - protection */
747 		do_page_fault(&fp->ptregs, addr, err_code);
748 	}
749 }
750 #endif /* CONFIG_COLDFIRE CONFIG_MMU */
751 
buserr_c(struct frame * fp)752 asmlinkage void buserr_c(struct frame *fp)
753 {
754 	/* Only set esp0 if coming from user mode */
755 	if (user_mode(&fp->ptregs))
756 		current->thread.esp0 = (unsigned long) fp;
757 
758 	pr_debug("*** Bus Error *** Format is %x\n", fp->ptregs.format);
759 
760 #if defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
761 	if (CPU_IS_COLDFIRE) {
762 		unsigned int fs;
763 		fs = (fp->ptregs.vector & 0x3) |
764 			((fp->ptregs.vector & 0xc00) >> 8);
765 		switch (fs) {
766 		case 0x5:
767 		case 0x6:
768 		case 0x7:
769 		case 0x9:
770 		case 0xa:
771 		case 0xd:
772 		case 0xe:
773 		case 0xf:
774 			access_errorcf(fs, fp);
775 			return;
776 		default:
777 			break;
778 		}
779 	}
780 #endif /* CONFIG_COLDFIRE && CONFIG_MMU */
781 
782 	switch (fp->ptregs.format) {
783 #if defined (CONFIG_M68060)
784 	case 4:				/* 68060 access error */
785 	  access_error060 (fp);
786 	  break;
787 #endif
788 #if defined (CONFIG_M68040)
789 	case 0x7:			/* 68040 access error */
790 	  access_error040 (fp);
791 	  break;
792 #endif
793 #if defined (CPU_M68020_OR_M68030)
794 	case 0xa:
795 	case 0xb:
796 	  bus_error030 (fp);
797 	  break;
798 #endif
799 	default:
800 	  die_if_kernel("bad frame format",&fp->ptregs,0);
801 	  pr_debug("Unknown SIGSEGV - 4\n");
802 	  force_sig(SIGSEGV);
803 	}
804 }
805 
806 
807 static int kstack_depth_to_print = 48;
808 
show_trace(unsigned long * stack,const char * loglvl)809 static void show_trace(unsigned long *stack, const char *loglvl)
810 {
811 	unsigned long *endstack;
812 	unsigned long addr;
813 	int i;
814 
815 	printk("%sCall Trace:", loglvl);
816 	addr = (unsigned long)stack + THREAD_SIZE - 1;
817 	endstack = (unsigned long *)(addr & -THREAD_SIZE);
818 	i = 0;
819 	while (stack + 1 <= endstack) {
820 		addr = *stack++;
821 		/*
822 		 * If the address is either in the text segment of the
823 		 * kernel, or in the region which contains vmalloc'ed
824 		 * memory, it *may* be the address of a calling
825 		 * routine; if so, print it so that someone tracing
826 		 * down the cause of the crash will be able to figure
827 		 * out the call path that was taken.
828 		 */
829 		if (__kernel_text_address(addr)) {
830 #ifndef CONFIG_KALLSYMS
831 			if (i % 5 == 0)
832 				pr_cont("\n       ");
833 #endif
834 			pr_cont(" [<%08lx>] %pS\n", addr, (void *)addr);
835 			i++;
836 		}
837 	}
838 	pr_cont("\n");
839 }
840 
show_registers(struct pt_regs * regs)841 void show_registers(struct pt_regs *regs)
842 {
843 	struct frame *fp = (struct frame *)regs;
844 	u16 c, *cp;
845 	unsigned long addr;
846 	int i;
847 
848 	print_modules();
849 	pr_info("PC: [<%08lx>] %pS\n", regs->pc, (void *)regs->pc);
850 	pr_info("SR: %04x  SP: %p  a2: %08lx\n", regs->sr, regs, regs->a2);
851 	pr_info("d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
852 	       regs->d0, regs->d1, regs->d2, regs->d3);
853 	pr_info("d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
854 	       regs->d4, regs->d5, regs->a0, regs->a1);
855 
856 	pr_info("Process %s (pid: %d, task=%p)\n",
857 		current->comm, task_pid_nr(current), current);
858 	addr = (unsigned long)&fp->un;
859 	pr_info("Frame format=%X ", regs->format);
860 	switch (regs->format) {
861 	case 0x2:
862 		pr_cont("instr addr=%08lx\n", fp->un.fmt2.iaddr);
863 		addr += sizeof(fp->un.fmt2);
864 		break;
865 	case 0x3:
866 		pr_cont("eff addr=%08lx\n", fp->un.fmt3.effaddr);
867 		addr += sizeof(fp->un.fmt3);
868 		break;
869 	case 0x4:
870 		if (CPU_IS_060)
871 			pr_cont("fault addr=%08lx fslw=%08lx\n",
872 				fp->un.fmt4.effaddr, fp->un.fmt4.pc);
873 		else
874 			pr_cont("eff addr=%08lx pc=%08lx\n",
875 				fp->un.fmt4.effaddr, fp->un.fmt4.pc);
876 		addr += sizeof(fp->un.fmt4);
877 		break;
878 	case 0x7:
879 		pr_cont("eff addr=%08lx ssw=%04x faddr=%08lx\n",
880 			fp->un.fmt7.effaddr, fp->un.fmt7.ssw, fp->un.fmt7.faddr);
881 		pr_info("wb 1 stat/addr/data: %04x %08lx %08lx\n",
882 			fp->un.fmt7.wb1s, fp->un.fmt7.wb1a, fp->un.fmt7.wb1dpd0);
883 		pr_info("wb 2 stat/addr/data: %04x %08lx %08lx\n",
884 			fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, fp->un.fmt7.wb2d);
885 		pr_info("wb 3 stat/addr/data: %04x %08lx %08lx\n",
886 			fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, fp->un.fmt7.wb3d);
887 		pr_info("push data: %08lx %08lx %08lx %08lx\n",
888 			fp->un.fmt7.wb1dpd0, fp->un.fmt7.pd1, fp->un.fmt7.pd2,
889 			fp->un.fmt7.pd3);
890 		addr += sizeof(fp->un.fmt7);
891 		break;
892 	case 0x9:
893 		pr_cont("instr addr=%08lx\n", fp->un.fmt9.iaddr);
894 		addr += sizeof(fp->un.fmt9);
895 		break;
896 	case 0xa:
897 		pr_cont("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n",
898 			fp->un.fmta.ssw, fp->un.fmta.isc, fp->un.fmta.isb,
899 			fp->un.fmta.daddr, fp->un.fmta.dobuf);
900 		addr += sizeof(fp->un.fmta);
901 		break;
902 	case 0xb:
903 		pr_cont("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n",
904 			fp->un.fmtb.ssw, fp->un.fmtb.isc, fp->un.fmtb.isb,
905 			fp->un.fmtb.daddr, fp->un.fmtb.dobuf);
906 		pr_info("baddr=%08lx dibuf=%08lx ver=%x\n",
907 			fp->un.fmtb.baddr, fp->un.fmtb.dibuf, fp->un.fmtb.ver);
908 		addr += sizeof(fp->un.fmtb);
909 		break;
910 	default:
911 		pr_cont("\n");
912 	}
913 	show_stack(NULL, (unsigned long *)addr, KERN_INFO);
914 
915 	pr_info("Code:");
916 	cp = (u16 *)regs->pc;
917 	for (i = -8; i < 16; i++) {
918 		if (get_kernel_nofault(c, cp + i) && i >= 0) {
919 			pr_cont(" Bad PC value.");
920 			break;
921 		}
922 		if (i)
923 			pr_cont(" %04x", c);
924 		else
925 			pr_cont(" <%04x>", c);
926 	}
927 	pr_cont("\n");
928 }
929 
show_stack(struct task_struct * task,unsigned long * stack,const char * loglvl)930 void show_stack(struct task_struct *task, unsigned long *stack,
931 		const char *loglvl)
932 {
933 	unsigned long *p;
934 	unsigned long *endstack;
935 	int i;
936 
937 	if (!stack) {
938 		if (task)
939 			stack = (unsigned long *)task->thread.esp0;
940 		else
941 			stack = (unsigned long *)&stack;
942 	}
943 	endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) & -THREAD_SIZE);
944 
945 	printk("%sStack from %08lx:", loglvl, (unsigned long)stack);
946 	p = stack;
947 	for (i = 0; i < kstack_depth_to_print; i++) {
948 		if (p + 1 > endstack)
949 			break;
950 		if (i % 8 == 0)
951 			pr_cont("\n       ");
952 		pr_cont(" %08lx", *p++);
953 	}
954 	pr_cont("\n");
955 	show_trace(stack, loglvl);
956 }
957 
958 /*
959  * The vector number returned in the frame pointer may also contain
960  * the "fs" (Fault Status) bits on ColdFire. These are in the bottom
961  * 2 bits, and upper 2 bits. So we need to mask out the real vector
962  * number before using it in comparisons. You don't need to do this on
963  * real 68k parts, but it won't hurt either.
964  */
965 
bad_super_trap(struct frame * fp)966 void bad_super_trap (struct frame *fp)
967 {
968 	int vector = (fp->ptregs.vector >> 2) & 0xff;
969 
970 	console_verbose();
971 	if (vector < ARRAY_SIZE(vec_names))
972 		pr_err("*** %s ***   FORMAT=%X\n",
973 			vec_names[vector],
974 			fp->ptregs.format);
975 	else
976 		pr_err("*** Exception %d ***   FORMAT=%X\n",
977 			vector, fp->ptregs.format);
978 	if (vector == VEC_ADDRERR && CPU_IS_020_OR_030) {
979 		unsigned short ssw = fp->un.fmtb.ssw;
980 
981 		pr_err("SSW=%#06x  ", ssw);
982 
983 		if (ssw & RC)
984 			pr_err("Pipe stage C instruction fault at %#010lx\n",
985 				(fp->ptregs.format) == 0xA ?
986 				fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2);
987 		if (ssw & RB)
988 			pr_err("Pipe stage B instruction fault at %#010lx\n",
989 				(fp->ptregs.format) == 0xA ?
990 				fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
991 		if (ssw & DF)
992 			pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n",
993 				ssw & RW ? "read" : "write",
994 				fp->un.fmtb.daddr, space_names[ssw & DFC],
995 				fp->ptregs.pc);
996 	}
997 	pr_err("Current process id is %d\n", task_pid_nr(current));
998 	die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
999 }
1000 
trap_c(struct frame * fp)1001 asmlinkage void trap_c(struct frame *fp)
1002 {
1003 	int sig, si_code;
1004 	void __user *addr;
1005 	int vector = (fp->ptregs.vector >> 2) & 0xff;
1006 
1007 	if (fp->ptregs.sr & PS_S) {
1008 		if (vector == VEC_TRACE) {
1009 			/* traced a trapping instruction on a 68020/30,
1010 			 * real exception will be executed afterwards.
1011 			 */
1012 			return;
1013 		}
1014 #ifdef CONFIG_MMU
1015 		if (fixup_exception(&fp->ptregs))
1016 			return;
1017 #endif
1018 		bad_super_trap(fp);
1019 		return;
1020 	}
1021 
1022 	/* send the appropriate signal to the user program */
1023 	switch (vector) {
1024 	    case VEC_ADDRERR:
1025 		si_code = BUS_ADRALN;
1026 		sig = SIGBUS;
1027 		break;
1028 	    case VEC_ILLEGAL:
1029 	    case VEC_LINE10:
1030 	    case VEC_LINE11:
1031 		si_code = ILL_ILLOPC;
1032 		sig = SIGILL;
1033 		break;
1034 	    case VEC_PRIV:
1035 		si_code = ILL_PRVOPC;
1036 		sig = SIGILL;
1037 		break;
1038 	    case VEC_COPROC:
1039 		si_code = ILL_COPROC;
1040 		sig = SIGILL;
1041 		break;
1042 	    case VEC_TRAP1:
1043 	    case VEC_TRAP2:
1044 	    case VEC_TRAP3:
1045 	    case VEC_TRAP4:
1046 	    case VEC_TRAP5:
1047 	    case VEC_TRAP6:
1048 	    case VEC_TRAP7:
1049 	    case VEC_TRAP8:
1050 	    case VEC_TRAP9:
1051 	    case VEC_TRAP10:
1052 	    case VEC_TRAP11:
1053 	    case VEC_TRAP12:
1054 	    case VEC_TRAP13:
1055 	    case VEC_TRAP14:
1056 		si_code = ILL_ILLTRP;
1057 		sig = SIGILL;
1058 		break;
1059 	    case VEC_FPBRUC:
1060 	    case VEC_FPOE:
1061 	    case VEC_FPNAN:
1062 		si_code = FPE_FLTINV;
1063 		sig = SIGFPE;
1064 		break;
1065 	    case VEC_FPIR:
1066 		si_code = FPE_FLTRES;
1067 		sig = SIGFPE;
1068 		break;
1069 	    case VEC_FPDIVZ:
1070 		si_code = FPE_FLTDIV;
1071 		sig = SIGFPE;
1072 		break;
1073 	    case VEC_FPUNDER:
1074 		si_code = FPE_FLTUND;
1075 		sig = SIGFPE;
1076 		break;
1077 	    case VEC_FPOVER:
1078 		si_code = FPE_FLTOVF;
1079 		sig = SIGFPE;
1080 		break;
1081 	    case VEC_ZERODIV:
1082 		si_code = FPE_INTDIV;
1083 		sig = SIGFPE;
1084 		break;
1085 	    case VEC_CHK:
1086 	    case VEC_TRAP:
1087 		si_code = FPE_INTOVF;
1088 		sig = SIGFPE;
1089 		break;
1090 	    case VEC_TRACE:		/* ptrace single step */
1091 		si_code = TRAP_TRACE;
1092 		sig = SIGTRAP;
1093 		break;
1094 	    case VEC_TRAP15:		/* breakpoint */
1095 		si_code = TRAP_BRKPT;
1096 		sig = SIGTRAP;
1097 		break;
1098 	    default:
1099 		si_code = ILL_ILLOPC;
1100 		sig = SIGILL;
1101 		break;
1102 	}
1103 	switch (fp->ptregs.format) {
1104 	    default:
1105 		addr = (void __user *) fp->ptregs.pc;
1106 		break;
1107 	    case 2:
1108 		addr = (void __user *) fp->un.fmt2.iaddr;
1109 		break;
1110 	    case 7:
1111 		addr = (void __user *) fp->un.fmt7.effaddr;
1112 		break;
1113 	    case 9:
1114 		addr = (void __user *) fp->un.fmt9.iaddr;
1115 		break;
1116 	    case 10:
1117 		addr = (void __user *) fp->un.fmta.daddr;
1118 		break;
1119 	    case 11:
1120 		addr = (void __user*) fp->un.fmtb.daddr;
1121 		break;
1122 	}
1123 	force_sig_fault(sig, si_code, addr);
1124 }
1125 
die_if_kernel(char * str,struct pt_regs * fp,int nr)1126 void die_if_kernel (char *str, struct pt_regs *fp, int nr)
1127 {
1128 	if (!(fp->sr & PS_S))
1129 		return;
1130 
1131 	console_verbose();
1132 	pr_crit("%s: %08x\n", str, nr);
1133 	show_registers(fp);
1134 	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
1135 	make_task_dead(SIGSEGV);
1136 }
1137 
set_esp0(unsigned long ssp)1138 asmlinkage void set_esp0(unsigned long ssp)
1139 {
1140 	current->thread.esp0 = ssp;
1141 }
1142 
1143 /*
1144  * This function is called if an error occur while accessing
1145  * user-space from the fpsp040 code.
1146  */
fpsp040_die(void)1147 asmlinkage void fpsp040_die(void)
1148 {
1149 	force_exit_sig(SIGSEGV);
1150 }
1151 
1152 #ifdef CONFIG_M68KFPU_EMU
fpemu_signal(int signal,int code,void * addr)1153 asmlinkage void fpemu_signal(int signal, int code, void *addr)
1154 {
1155 	force_sig_fault(signal, code, addr);
1156 }
1157 #endif
1158