1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
4
5 #include <linux/device.h>
6 #include <linux/irq.h>
7 #include <linux/irqchip/chained_irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/lockdep.h>
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/property.h>
13 #include <linux/types.h>
14
15 struct gpio_desc;
16 struct of_phandle_args;
17 struct device_node;
18 struct seq_file;
19 struct gpio_device;
20 struct module;
21 enum gpiod_flags;
22 enum gpio_lookup_flags;
23
24 struct gpio_chip;
25
26 #define GPIO_LINE_DIRECTION_IN 1
27 #define GPIO_LINE_DIRECTION_OUT 0
28
29 /**
30 * struct gpio_irq_chip - GPIO interrupt controller
31 */
32 struct gpio_irq_chip {
33 /**
34 * @chip:
35 *
36 * GPIO IRQ chip implementation, provided by GPIO driver.
37 */
38 struct irq_chip *chip;
39
40 /**
41 * @domain:
42 *
43 * Interrupt translation domain; responsible for mapping between GPIO
44 * hwirq number and Linux IRQ number.
45 */
46 struct irq_domain *domain;
47
48 /**
49 * @domain_ops:
50 *
51 * Table of interrupt domain operations for this IRQ chip.
52 */
53 const struct irq_domain_ops *domain_ops;
54
55 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
56 /**
57 * @fwnode:
58 *
59 * Firmware node corresponding to this gpiochip/irqchip, necessary
60 * for hierarchical irqdomain support.
61 */
62 struct fwnode_handle *fwnode;
63
64 /**
65 * @parent_domain:
66 *
67 * If non-NULL, will be set as the parent of this GPIO interrupt
68 * controller's IRQ domain to establish a hierarchical interrupt
69 * domain. The presence of this will activate the hierarchical
70 * interrupt support.
71 */
72 struct irq_domain *parent_domain;
73
74 /**
75 * @child_to_parent_hwirq:
76 *
77 * This callback translates a child hardware IRQ offset to a parent
78 * hardware IRQ offset on a hierarchical interrupt chip. The child
79 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
80 * ngpio field of struct gpio_chip) and the corresponding parent
81 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
82 * the driver. The driver can calculate this from an offset or using
83 * a lookup table or whatever method is best for this chip. Return
84 * 0 on successful translation in the driver.
85 *
86 * If some ranges of hardware IRQs do not have a corresponding parent
87 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
88 * @need_valid_mask to make these GPIO lines unavailable for
89 * translation.
90 */
91 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
92 unsigned int child_hwirq,
93 unsigned int child_type,
94 unsigned int *parent_hwirq,
95 unsigned int *parent_type);
96
97 /**
98 * @populate_parent_alloc_arg :
99 *
100 * This optional callback allocates and populates the specific struct
101 * for the parent's IRQ domain. If this is not specified, then
102 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
103 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
104 * available.
105 */
106 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
107 unsigned int parent_hwirq,
108 unsigned int parent_type);
109
110 /**
111 * @child_offset_to_irq:
112 *
113 * This optional callback is used to translate the child's GPIO line
114 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
115 * callback. If this is not specified, then a default callback will be
116 * provided that returns the line offset.
117 */
118 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
119 unsigned int pin);
120
121 /**
122 * @child_irq_domain_ops:
123 *
124 * The IRQ domain operations that will be used for this GPIO IRQ
125 * chip. If no operations are provided, then default callbacks will
126 * be populated to setup the IRQ hierarchy. Some drivers need to
127 * supply their own translate function.
128 */
129 struct irq_domain_ops child_irq_domain_ops;
130 #endif
131
132 /**
133 * @handler:
134 *
135 * The IRQ handler to use (often a predefined IRQ core function) for
136 * GPIO IRQs, provided by GPIO driver.
137 */
138 irq_flow_handler_t handler;
139
140 /**
141 * @default_type:
142 *
143 * Default IRQ triggering type applied during GPIO driver
144 * initialization, provided by GPIO driver.
145 */
146 unsigned int default_type;
147
148 /**
149 * @lock_key:
150 *
151 * Per GPIO IRQ chip lockdep class for IRQ lock.
152 */
153 struct lock_class_key *lock_key;
154
155 /**
156 * @request_key:
157 *
158 * Per GPIO IRQ chip lockdep class for IRQ request.
159 */
160 struct lock_class_key *request_key;
161
162 /**
163 * @parent_handler:
164 *
165 * The interrupt handler for the GPIO chip's parent interrupts, may be
166 * NULL if the parent interrupts are nested rather than cascaded.
167 */
168 irq_flow_handler_t parent_handler;
169
170 union {
171 /**
172 * @parent_handler_data:
173 *
174 * If @per_parent_data is false, @parent_handler_data is a
175 * single pointer used as the data associated with every
176 * parent interrupt.
177 */
178 void *parent_handler_data;
179
180 /**
181 * @parent_handler_data_array:
182 *
183 * If @per_parent_data is true, @parent_handler_data_array is
184 * an array of @num_parents pointers, and is used to associate
185 * different data for each parent. This cannot be NULL if
186 * @per_parent_data is true.
187 */
188 void **parent_handler_data_array;
189 };
190
191 /**
192 * @num_parents:
193 *
194 * The number of interrupt parents of a GPIO chip.
195 */
196 unsigned int num_parents;
197
198 /**
199 * @parents:
200 *
201 * A list of interrupt parents of a GPIO chip. This is owned by the
202 * driver, so the core will only reference this list, not modify it.
203 */
204 unsigned int *parents;
205
206 /**
207 * @map:
208 *
209 * A list of interrupt parents for each line of a GPIO chip.
210 */
211 unsigned int *map;
212
213 /**
214 * @threaded:
215 *
216 * True if set the interrupt handling uses nested threads.
217 */
218 bool threaded;
219
220 /**
221 * @per_parent_data:
222 *
223 * True if parent_handler_data_array describes a @num_parents
224 * sized array to be used as parent data.
225 */
226 bool per_parent_data;
227
228 /**
229 * @initialized:
230 *
231 * Flag to track GPIO chip irq member's initialization.
232 * This flag will make sure GPIO chip irq members are not used
233 * before they are initialized.
234 */
235 bool initialized;
236
237 /**
238 * @init_hw: optional routine to initialize hardware before
239 * an IRQ chip will be added. This is quite useful when
240 * a particular driver wants to clear IRQ related registers
241 * in order to avoid undesired events.
242 */
243 int (*init_hw)(struct gpio_chip *gc);
244
245 /**
246 * @init_valid_mask: optional routine to initialize @valid_mask, to be
247 * used if not all GPIO lines are valid interrupts. Sometimes some
248 * lines just cannot fire interrupts, and this routine, when defined,
249 * is passed a bitmap in "valid_mask" and it will have ngpios
250 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
251 * then directly set some bits to "0" if they cannot be used for
252 * interrupts.
253 */
254 void (*init_valid_mask)(struct gpio_chip *gc,
255 unsigned long *valid_mask,
256 unsigned int ngpios);
257
258 /**
259 * @valid_mask:
260 *
261 * If not %NULL, holds bitmask of GPIOs which are valid to be included
262 * in IRQ domain of the chip.
263 */
264 unsigned long *valid_mask;
265
266 /**
267 * @first:
268 *
269 * Required for static IRQ allocation. If set, irq_domain_add_simple()
270 * will allocate and map all IRQs during initialization.
271 */
272 unsigned int first;
273
274 /**
275 * @irq_enable:
276 *
277 * Store old irq_chip irq_enable callback
278 */
279 void (*irq_enable)(struct irq_data *data);
280
281 /**
282 * @irq_disable:
283 *
284 * Store old irq_chip irq_disable callback
285 */
286 void (*irq_disable)(struct irq_data *data);
287 /**
288 * @irq_unmask:
289 *
290 * Store old irq_chip irq_unmask callback
291 */
292 void (*irq_unmask)(struct irq_data *data);
293
294 /**
295 * @irq_mask:
296 *
297 * Store old irq_chip irq_mask callback
298 */
299 void (*irq_mask)(struct irq_data *data);
300 };
301
302 /**
303 * struct gpio_chip - abstract a GPIO controller
304 * @label: a functional name for the GPIO device, such as a part
305 * number or the name of the SoC IP-block implementing it.
306 * @gpiodev: the internal state holder, opaque struct
307 * @parent: optional parent device providing the GPIOs
308 * @fwnode: optional fwnode providing this controller's properties
309 * @owner: helps prevent removal of modules exporting active GPIOs
310 * @request: optional hook for chip-specific activation, such as
311 * enabling module power and clock; may sleep
312 * @free: optional hook for chip-specific deactivation, such as
313 * disabling module power and clock; may sleep
314 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
315 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
316 * or negative error. It is recommended to always implement this
317 * function, even on input-only or output-only gpio chips.
318 * @direction_input: configures signal "offset" as input, or returns error
319 * This can be omitted on input-only or output-only gpio chips.
320 * @direction_output: configures signal "offset" as output, or returns error
321 * This can be omitted on input-only or output-only gpio chips.
322 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
323 * @get_multiple: reads values for multiple signals defined by "mask" and
324 * stores them in "bits", returns 0 on success or negative error
325 * @set: assigns output value for signal "offset"
326 * @set_multiple: assigns output values for multiple signals defined by "mask"
327 * @set_config: optional hook for all kinds of settings. Uses the same
328 * packed config format as generic pinconf.
329 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
330 * implementation may not sleep
331 * @dbg_show: optional routine to show contents in debugfs; default code
332 * will be used when this is omitted, but custom code can show extra
333 * state (such as pullup/pulldown configuration).
334 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
335 * not all GPIOs are valid.
336 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
337 * requires special mapping of the pins that provides GPIO functionality.
338 * It is called after adding GPIO chip and before adding IRQ chip.
339 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
340 * enable hardware timestamp.
341 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
342 * disable hardware timestamp.
343 * @base: identifies the first GPIO number handled by this chip;
344 * or, if negative during registration, requests dynamic ID allocation.
345 * DEPRECATION: providing anything non-negative and nailing the base
346 * offset of GPIO chips is deprecated. Please pass -1 as base to
347 * let gpiolib select the chip base in all possible cases. We want to
348 * get rid of the static GPIO number space in the long run.
349 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
350 * handled is (base + ngpio - 1).
351 * @offset: when multiple gpio chips belong to the same device this
352 * can be used as offset within the device so friendly names can
353 * be properly assigned.
354 * @names: if set, must be an array of strings to use as alternative
355 * names for the GPIOs in this chip. Any entry in the array
356 * may be NULL if there is no alias for the GPIO, however the
357 * array must be @ngpio entries long. A name can include a single printk
358 * format specifier for an unsigned int. It is substituted by the actual
359 * number of the gpio.
360 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
361 * must while accessing GPIO expander chips over I2C or SPI. This
362 * implies that if the chip supports IRQs, these IRQs need to be threaded
363 * as the chip access may sleep when e.g. reading out the IRQ status
364 * registers.
365 * @read_reg: reader function for generic GPIO
366 * @write_reg: writer function for generic GPIO
367 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
368 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
369 * generic GPIO core. It is for internal housekeeping only.
370 * @reg_dat: data (in) register for generic GPIO
371 * @reg_set: output set register (out=high) for generic GPIO
372 * @reg_clr: output clear register (out=low) for generic GPIO
373 * @reg_dir_out: direction out setting register for generic GPIO
374 * @reg_dir_in: direction in setting register for generic GPIO
375 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
376 * be read and we need to rely on out internal state tracking.
377 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
378 * <register width> * 8
379 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
380 * shadowed and real data registers writes together.
381 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
382 * safely.
383 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
384 * direction safely. A "1" in this word means the line is set as
385 * output.
386 *
387 * A gpio_chip can help platforms abstract various sources of GPIOs so
388 * they can all be accessed through a common programming interface.
389 * Example sources would be SOC controllers, FPGAs, multifunction
390 * chips, dedicated GPIO expanders, and so on.
391 *
392 * Each chip controls a number of signals, identified in method calls
393 * by "offset" values in the range 0..(@ngpio - 1). When those signals
394 * are referenced through calls like gpio_get_value(gpio), the offset
395 * is calculated by subtracting @base from the gpio number.
396 */
397 struct gpio_chip {
398 const char *label;
399 struct gpio_device *gpiodev;
400 struct device *parent;
401 struct fwnode_handle *fwnode;
402 struct module *owner;
403
404 int (*request)(struct gpio_chip *gc,
405 unsigned int offset);
406 void (*free)(struct gpio_chip *gc,
407 unsigned int offset);
408 int (*get_direction)(struct gpio_chip *gc,
409 unsigned int offset);
410 int (*direction_input)(struct gpio_chip *gc,
411 unsigned int offset);
412 int (*direction_output)(struct gpio_chip *gc,
413 unsigned int offset, int value);
414 int (*get)(struct gpio_chip *gc,
415 unsigned int offset);
416 int (*get_multiple)(struct gpio_chip *gc,
417 unsigned long *mask,
418 unsigned long *bits);
419 void (*set)(struct gpio_chip *gc,
420 unsigned int offset, int value);
421 void (*set_multiple)(struct gpio_chip *gc,
422 unsigned long *mask,
423 unsigned long *bits);
424 int (*set_config)(struct gpio_chip *gc,
425 unsigned int offset,
426 unsigned long config);
427 int (*to_irq)(struct gpio_chip *gc,
428 unsigned int offset);
429
430 void (*dbg_show)(struct seq_file *s,
431 struct gpio_chip *gc);
432
433 int (*init_valid_mask)(struct gpio_chip *gc,
434 unsigned long *valid_mask,
435 unsigned int ngpios);
436
437 int (*add_pin_ranges)(struct gpio_chip *gc);
438
439 int (*en_hw_timestamp)(struct gpio_chip *gc,
440 u32 offset,
441 unsigned long flags);
442 int (*dis_hw_timestamp)(struct gpio_chip *gc,
443 u32 offset,
444 unsigned long flags);
445 int base;
446 u16 ngpio;
447 u16 offset;
448 const char *const *names;
449 bool can_sleep;
450
451 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
452 unsigned long (*read_reg)(void __iomem *reg);
453 void (*write_reg)(void __iomem *reg, unsigned long data);
454 bool be_bits;
455 void __iomem *reg_dat;
456 void __iomem *reg_set;
457 void __iomem *reg_clr;
458 void __iomem *reg_dir_out;
459 void __iomem *reg_dir_in;
460 bool bgpio_dir_unreadable;
461 int bgpio_bits;
462 raw_spinlock_t bgpio_lock;
463 unsigned long bgpio_data;
464 unsigned long bgpio_dir;
465 #endif /* CONFIG_GPIO_GENERIC */
466
467 #ifdef CONFIG_GPIOLIB_IRQCHIP
468 /*
469 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
470 * to handle IRQs for most practical cases.
471 */
472
473 /**
474 * @irq:
475 *
476 * Integrates interrupt chip functionality with the GPIO chip. Can be
477 * used to handle IRQs for most practical cases.
478 */
479 struct gpio_irq_chip irq;
480 #endif /* CONFIG_GPIOLIB_IRQCHIP */
481
482 /**
483 * @valid_mask:
484 *
485 * If not %NULL, holds bitmask of GPIOs which are valid to be used
486 * from the chip.
487 */
488 unsigned long *valid_mask;
489
490 #if defined(CONFIG_OF_GPIO)
491 /*
492 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
493 * the device tree automatically may have an OF translation
494 */
495
496 /**
497 * @of_node:
498 *
499 * Pointer to a device tree node representing this GPIO controller.
500 */
501 struct device_node *of_node;
502
503 /**
504 * @of_gpio_n_cells:
505 *
506 * Number of cells used to form the GPIO specifier.
507 */
508 unsigned int of_gpio_n_cells;
509
510 /**
511 * @of_xlate:
512 *
513 * Callback to translate a device tree GPIO specifier into a chip-
514 * relative GPIO number and flags.
515 */
516 int (*of_xlate)(struct gpio_chip *gc,
517 const struct of_phandle_args *gpiospec, u32 *flags);
518
519 /**
520 * @of_gpio_ranges_fallback:
521 *
522 * Optional hook for the case that no gpio-ranges property is defined
523 * within the device tree node "np" (usually DT before introduction
524 * of gpio-ranges). So this callback is helpful to provide the
525 * necessary backward compatibility for the pin ranges.
526 */
527 int (*of_gpio_ranges_fallback)(struct gpio_chip *gc,
528 struct device_node *np);
529
530 #endif /* CONFIG_OF_GPIO */
531 };
532
533 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
534 unsigned int offset);
535
536 /**
537 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
538 * @chip: the chip to query
539 * @i: loop variable
540 * @base: first GPIO in the range
541 * @size: amount of GPIOs to check starting from @base
542 * @label: label of current GPIO
543 */
544 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \
545 for (i = 0; i < size; i++) \
546 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
547
548 /* Iterates over all requested GPIO of the given @chip */
549 #define for_each_requested_gpio(chip, i, label) \
550 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
551
552 /* add/remove chips */
553 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
554 struct lock_class_key *lock_key,
555 struct lock_class_key *request_key);
556
557 /**
558 * gpiochip_add_data() - register a gpio_chip
559 * @gc: the chip to register, with gc->base initialized
560 * @data: driver-private data associated with this chip
561 *
562 * Context: potentially before irqs will work
563 *
564 * When gpiochip_add_data() is called very early during boot, so that GPIOs
565 * can be freely used, the gc->parent device must be registered before
566 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
567 * for GPIOs will fail rudely.
568 *
569 * gpiochip_add_data() must only be called after gpiolib initialization,
570 * i.e. after core_initcall().
571 *
572 * If gc->base is negative, this requests dynamic assignment of
573 * a range of valid GPIOs.
574 *
575 * Returns:
576 * A negative errno if the chip can't be registered, such as because the
577 * gc->base is invalid or already associated with a different chip.
578 * Otherwise it returns zero as a success code.
579 */
580 #ifdef CONFIG_LOCKDEP
581 #define gpiochip_add_data(gc, data) ({ \
582 static struct lock_class_key lock_key; \
583 static struct lock_class_key request_key; \
584 gpiochip_add_data_with_key(gc, data, &lock_key, \
585 &request_key); \
586 })
587 #define devm_gpiochip_add_data(dev, gc, data) ({ \
588 static struct lock_class_key lock_key; \
589 static struct lock_class_key request_key; \
590 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
591 &request_key); \
592 })
593 #else
594 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
595 #define devm_gpiochip_add_data(dev, gc, data) \
596 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
597 #endif /* CONFIG_LOCKDEP */
598
gpiochip_add(struct gpio_chip * gc)599 static inline int gpiochip_add(struct gpio_chip *gc)
600 {
601 return gpiochip_add_data(gc, NULL);
602 }
603 extern void gpiochip_remove(struct gpio_chip *gc);
604 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
605 struct lock_class_key *lock_key,
606 struct lock_class_key *request_key);
607
608 extern struct gpio_chip *gpiochip_find(void *data,
609 int (*match)(struct gpio_chip *gc, void *data));
610
611 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
612 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
613 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
614 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
615 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
616
617 /* irq_data versions of the above */
618 int gpiochip_irq_reqres(struct irq_data *data);
619 void gpiochip_irq_relres(struct irq_data *data);
620
621 /* Paste this in your irq_chip structure */
622 #define GPIOCHIP_IRQ_RESOURCE_HELPERS \
623 .irq_request_resources = gpiochip_irq_reqres, \
624 .irq_release_resources = gpiochip_irq_relres
625
gpio_irq_chip_set_chip(struct gpio_irq_chip * girq,const struct irq_chip * chip)626 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
627 const struct irq_chip *chip)
628 {
629 /* Yes, dropping const is ugly, but it isn't like we have a choice */
630 girq->chip = (struct irq_chip *)chip;
631 }
632
633 /* Line status inquiry for drivers */
634 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
635 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
636
637 /* Sleep persistence inquiry for drivers */
638 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
639 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
640
641 /* get driver data */
642 void *gpiochip_get_data(struct gpio_chip *gc);
643
644 struct bgpio_pdata {
645 const char *label;
646 int base;
647 int ngpio;
648 };
649
650 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
651
652 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
653 unsigned int parent_hwirq,
654 unsigned int parent_type);
655 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
656 unsigned int parent_hwirq,
657 unsigned int parent_type);
658
659 #else
660
gpiochip_populate_parent_fwspec_twocell(struct gpio_chip * gc,unsigned int parent_hwirq,unsigned int parent_type)661 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
662 unsigned int parent_hwirq,
663 unsigned int parent_type)
664 {
665 return NULL;
666 }
667
gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip * gc,unsigned int parent_hwirq,unsigned int parent_type)668 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
669 unsigned int parent_hwirq,
670 unsigned int parent_type)
671 {
672 return NULL;
673 }
674
675 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
676
677 int bgpio_init(struct gpio_chip *gc, struct device *dev,
678 unsigned long sz, void __iomem *dat, void __iomem *set,
679 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
680 unsigned long flags);
681
682 #define BGPIOF_BIG_ENDIAN BIT(0)
683 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
684 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
685 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
686 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
687 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
688 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
689
690 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
691 irq_hw_number_t hwirq);
692 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
693
694 int gpiochip_irq_domain_activate(struct irq_domain *domain,
695 struct irq_data *data, bool reserve);
696 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
697 struct irq_data *data);
698
699 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
700 unsigned int offset);
701
702 #ifdef CONFIG_GPIOLIB_IRQCHIP
703 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
704 struct irq_domain *domain);
705 #else
gpiochip_irqchip_add_domain(struct gpio_chip * gc,struct irq_domain * domain)706 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
707 struct irq_domain *domain)
708 {
709 WARN_ON(1);
710 return -EINVAL;
711 }
712 #endif
713
714 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
715 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
716 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
717 unsigned long config);
718
719 /**
720 * struct gpio_pin_range - pin range controlled by a gpio chip
721 * @node: list for maintaining set of pin ranges, used internally
722 * @pctldev: pinctrl device which handles corresponding pins
723 * @range: actual range of pins controlled by a gpio controller
724 */
725 struct gpio_pin_range {
726 struct list_head node;
727 struct pinctrl_dev *pctldev;
728 struct pinctrl_gpio_range range;
729 };
730
731 #ifdef CONFIG_PINCTRL
732
733 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
734 unsigned int gpio_offset, unsigned int pin_offset,
735 unsigned int npins);
736 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
737 struct pinctrl_dev *pctldev,
738 unsigned int gpio_offset, const char *pin_group);
739 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
740
741 #else /* ! CONFIG_PINCTRL */
742
743 static inline int
gpiochip_add_pin_range(struct gpio_chip * gc,const char * pinctl_name,unsigned int gpio_offset,unsigned int pin_offset,unsigned int npins)744 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
745 unsigned int gpio_offset, unsigned int pin_offset,
746 unsigned int npins)
747 {
748 return 0;
749 }
750 static inline int
gpiochip_add_pingroup_range(struct gpio_chip * gc,struct pinctrl_dev * pctldev,unsigned int gpio_offset,const char * pin_group)751 gpiochip_add_pingroup_range(struct gpio_chip *gc,
752 struct pinctrl_dev *pctldev,
753 unsigned int gpio_offset, const char *pin_group)
754 {
755 return 0;
756 }
757
758 static inline void
gpiochip_remove_pin_ranges(struct gpio_chip * gc)759 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
760 {
761 }
762
763 #endif /* CONFIG_PINCTRL */
764
765 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
766 unsigned int hwnum,
767 const char *label,
768 enum gpio_lookup_flags lflags,
769 enum gpiod_flags dflags);
770 void gpiochip_free_own_desc(struct gpio_desc *desc);
771
772 #ifdef CONFIG_GPIOLIB
773
774 /* lock/unlock as IRQ */
775 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
776 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
777
778
779 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
780
781 #else /* CONFIG_GPIOLIB */
782
gpiod_to_chip(const struct gpio_desc * desc)783 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
784 {
785 /* GPIO can never have been requested */
786 WARN_ON(1);
787 return ERR_PTR(-ENODEV);
788 }
789
gpiochip_lock_as_irq(struct gpio_chip * gc,unsigned int offset)790 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
791 unsigned int offset)
792 {
793 WARN_ON(1);
794 return -EINVAL;
795 }
796
gpiochip_unlock_as_irq(struct gpio_chip * gc,unsigned int offset)797 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
798 unsigned int offset)
799 {
800 WARN_ON(1);
801 }
802 #endif /* CONFIG_GPIOLIB */
803
804 #define for_each_gpiochip_node(dev, child) \
805 device_for_each_child_node(dev, child) \
806 if (!fwnode_property_present(child, "gpio-controller")) {} else
807
gpiochip_node_count(struct device * dev)808 static inline unsigned int gpiochip_node_count(struct device *dev)
809 {
810 struct fwnode_handle *child;
811 unsigned int count = 0;
812
813 for_each_gpiochip_node(dev, child)
814 count++;
815
816 return count;
817 }
818
gpiochip_node_get_first(struct device * dev)819 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
820 {
821 struct fwnode_handle *fwnode;
822
823 for_each_gpiochip_node(dev, fwnode)
824 return fwnode;
825
826 return NULL;
827 }
828
829 #endif /* __LINUX_GPIO_DRIVER_H */
830