1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36
37 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/mmu.h>
40 #include <asm/mmu_context.h>
41 #include <asm/page.h>
42 #include <asm/types.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
45 #include <asm/prom.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
48 #include <asm/io.h>
49 #include <asm/eeh.h>
50 #include <asm/tlb.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/spu.h>
55 #include <asm/udbg.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
59
60 #ifdef DEBUG
61 #define DBG(fmt...) udbg_printf(fmt)
62 #else
63 #define DBG(fmt...)
64 #endif
65
66 #ifdef DEBUG_LOW
67 #define DBG_LOW(fmt...) udbg_printf(fmt)
68 #else
69 #define DBG_LOW(fmt...)
70 #endif
71
72 #define KB (1024)
73 #define MB (1024*KB)
74 #define GB (1024L*MB)
75
76 /*
77 * Note: pte --> Linux PTE
78 * HPTE --> PowerPC Hashed Page Table Entry
79 *
80 * Execution context:
81 * htab_initialize is called with the MMU off (of course), but
82 * the kernel has been copied down to zero so it can directly
83 * reference global data. At this point it is very difficult
84 * to print debug info.
85 *
86 */
87
88 #ifdef CONFIG_U3_DART
89 extern unsigned long dart_tablebase;
90 #endif /* CONFIG_U3_DART */
91
92 static unsigned long _SDR1;
93 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
94
95 struct hash_pte *htab_address;
96 unsigned long htab_size_bytes;
97 unsigned long htab_hash_mask;
98 EXPORT_SYMBOL_GPL(htab_hash_mask);
99 int mmu_linear_psize = MMU_PAGE_4K;
100 int mmu_virtual_psize = MMU_PAGE_4K;
101 int mmu_vmalloc_psize = MMU_PAGE_4K;
102 #ifdef CONFIG_SPARSEMEM_VMEMMAP
103 int mmu_vmemmap_psize = MMU_PAGE_4K;
104 #endif
105 int mmu_io_psize = MMU_PAGE_4K;
106 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
107 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
108 u16 mmu_slb_size = 64;
109 EXPORT_SYMBOL_GPL(mmu_slb_size);
110 #ifdef CONFIG_PPC_64K_PAGES
111 int mmu_ci_restrictions;
112 #endif
113 #ifdef CONFIG_DEBUG_PAGEALLOC
114 static u8 *linear_map_hash_slots;
115 static unsigned long linear_map_hash_count;
116 static DEFINE_SPINLOCK(linear_map_hash_lock);
117 #endif /* CONFIG_DEBUG_PAGEALLOC */
118
119 /* There are definitions of page sizes arrays to be used when none
120 * is provided by the firmware.
121 */
122
123 /* Pre-POWER4 CPUs (4k pages only)
124 */
125 static struct mmu_psize_def mmu_psize_defaults_old[] = {
126 [MMU_PAGE_4K] = {
127 .shift = 12,
128 .sllp = 0,
129 .penc = 0,
130 .avpnm = 0,
131 .tlbiel = 0,
132 },
133 };
134
135 /* POWER4, GPUL, POWER5
136 *
137 * Support for 16Mb large pages
138 */
139 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
140 [MMU_PAGE_4K] = {
141 .shift = 12,
142 .sllp = 0,
143 .penc = 0,
144 .avpnm = 0,
145 .tlbiel = 1,
146 },
147 [MMU_PAGE_16M] = {
148 .shift = 24,
149 .sllp = SLB_VSID_L,
150 .penc = 0,
151 .avpnm = 0x1UL,
152 .tlbiel = 0,
153 },
154 };
155
htab_convert_pte_flags(unsigned long pteflags)156 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
157 {
158 unsigned long rflags = pteflags & 0x1fa;
159
160 /* _PAGE_EXEC -> NOEXEC */
161 if ((pteflags & _PAGE_EXEC) == 0)
162 rflags |= HPTE_R_N;
163
164 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
165 * need to add in 0x1 if it's a read-only user page
166 */
167 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
168 (pteflags & _PAGE_DIRTY)))
169 rflags |= 1;
170
171 /* Always add C */
172 return rflags | HPTE_R_C;
173 }
174
htab_bolt_mapping(unsigned long vstart,unsigned long vend,unsigned long pstart,unsigned long prot,int psize,int ssize)175 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
176 unsigned long pstart, unsigned long prot,
177 int psize, int ssize)
178 {
179 unsigned long vaddr, paddr;
180 unsigned int step, shift;
181 int ret = 0;
182
183 shift = mmu_psize_defs[psize].shift;
184 step = 1 << shift;
185
186 prot = htab_convert_pte_flags(prot);
187
188 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
189 vstart, vend, pstart, prot, psize, ssize);
190
191 for (vaddr = vstart, paddr = pstart; vaddr < vend;
192 vaddr += step, paddr += step) {
193 unsigned long hash, hpteg;
194 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
195 unsigned long va = hpt_va(vaddr, vsid, ssize);
196 unsigned long tprot = prot;
197
198 /* Make kernel text executable */
199 if (overlaps_kernel_text(vaddr, vaddr + step))
200 tprot &= ~HPTE_R_N;
201
202 hash = hpt_hash(va, shift, ssize);
203 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
204
205 BUG_ON(!ppc_md.hpte_insert);
206 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
207 HPTE_V_BOLTED, psize, ssize);
208
209 if (ret < 0)
210 break;
211 #ifdef CONFIG_DEBUG_PAGEALLOC
212 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
213 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
214 #endif /* CONFIG_DEBUG_PAGEALLOC */
215 }
216 return ret < 0 ? ret : 0;
217 }
218
219 #ifdef CONFIG_MEMORY_HOTPLUG
htab_remove_mapping(unsigned long vstart,unsigned long vend,int psize,int ssize)220 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
221 int psize, int ssize)
222 {
223 unsigned long vaddr;
224 unsigned int step, shift;
225
226 shift = mmu_psize_defs[psize].shift;
227 step = 1 << shift;
228
229 if (!ppc_md.hpte_removebolted) {
230 printk(KERN_WARNING "Platform doesn't implement "
231 "hpte_removebolted\n");
232 return -EINVAL;
233 }
234
235 for (vaddr = vstart; vaddr < vend; vaddr += step)
236 ppc_md.hpte_removebolted(vaddr, psize, ssize);
237
238 return 0;
239 }
240 #endif /* CONFIG_MEMORY_HOTPLUG */
241
htab_dt_scan_seg_sizes(unsigned long node,const char * uname,int depth,void * data)242 static int __init htab_dt_scan_seg_sizes(unsigned long node,
243 const char *uname, int depth,
244 void *data)
245 {
246 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
247 u32 *prop;
248 unsigned long size = 0;
249
250 /* We are scanning "cpu" nodes only */
251 if (type == NULL || strcmp(type, "cpu") != 0)
252 return 0;
253
254 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
255 &size);
256 if (prop == NULL)
257 return 0;
258 for (; size >= 4; size -= 4, ++prop) {
259 if (prop[0] == 40) {
260 DBG("1T segment support detected\n");
261 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
262 return 1;
263 }
264 }
265 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
266 return 0;
267 }
268
htab_init_seg_sizes(void)269 static void __init htab_init_seg_sizes(void)
270 {
271 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
272 }
273
htab_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)274 static int __init htab_dt_scan_page_sizes(unsigned long node,
275 const char *uname, int depth,
276 void *data)
277 {
278 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
279 u32 *prop;
280 unsigned long size = 0;
281
282 /* We are scanning "cpu" nodes only */
283 if (type == NULL || strcmp(type, "cpu") != 0)
284 return 0;
285
286 prop = (u32 *)of_get_flat_dt_prop(node,
287 "ibm,segment-page-sizes", &size);
288 if (prop != NULL) {
289 DBG("Page sizes from device-tree:\n");
290 size /= 4;
291 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
292 while(size > 0) {
293 unsigned int shift = prop[0];
294 unsigned int slbenc = prop[1];
295 unsigned int lpnum = prop[2];
296 unsigned int lpenc = 0;
297 struct mmu_psize_def *def;
298 int idx = -1;
299
300 size -= 3; prop += 3;
301 while(size > 0 && lpnum) {
302 if (prop[0] == shift)
303 lpenc = prop[1];
304 prop += 2; size -= 2;
305 lpnum--;
306 }
307 switch(shift) {
308 case 0xc:
309 idx = MMU_PAGE_4K;
310 break;
311 case 0x10:
312 idx = MMU_PAGE_64K;
313 break;
314 case 0x14:
315 idx = MMU_PAGE_1M;
316 break;
317 case 0x18:
318 idx = MMU_PAGE_16M;
319 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
320 break;
321 case 0x22:
322 idx = MMU_PAGE_16G;
323 break;
324 }
325 if (idx < 0)
326 continue;
327 def = &mmu_psize_defs[idx];
328 def->shift = shift;
329 if (shift <= 23)
330 def->avpnm = 0;
331 else
332 def->avpnm = (1 << (shift - 23)) - 1;
333 def->sllp = slbenc;
334 def->penc = lpenc;
335 /* We don't know for sure what's up with tlbiel, so
336 * for now we only set it for 4K and 64K pages
337 */
338 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
339 def->tlbiel = 1;
340 else
341 def->tlbiel = 0;
342
343 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
344 "tlbiel=%d, penc=%d\n",
345 idx, shift, def->sllp, def->avpnm, def->tlbiel,
346 def->penc);
347 }
348 return 1;
349 }
350 return 0;
351 }
352
353 #ifdef CONFIG_HUGETLB_PAGE
354 /* Scan for 16G memory blocks that have been set aside for huge pages
355 * and reserve those blocks for 16G huge pages.
356 */
htab_dt_scan_hugepage_blocks(unsigned long node,const char * uname,int depth,void * data)357 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
358 const char *uname, int depth,
359 void *data) {
360 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
361 unsigned long *addr_prop;
362 u32 *page_count_prop;
363 unsigned int expected_pages;
364 long unsigned int phys_addr;
365 long unsigned int block_size;
366
367 /* We are scanning "memory" nodes only */
368 if (type == NULL || strcmp(type, "memory") != 0)
369 return 0;
370
371 /* This property is the log base 2 of the number of virtual pages that
372 * will represent this memory block. */
373 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
374 if (page_count_prop == NULL)
375 return 0;
376 expected_pages = (1 << page_count_prop[0]);
377 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
378 if (addr_prop == NULL)
379 return 0;
380 phys_addr = addr_prop[0];
381 block_size = addr_prop[1];
382 if (block_size != (16 * GB))
383 return 0;
384 printk(KERN_INFO "Huge page(16GB) memory: "
385 "addr = 0x%lX size = 0x%lX pages = %d\n",
386 phys_addr, block_size, expected_pages);
387 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
388 memblock_reserve(phys_addr, block_size * expected_pages);
389 add_gpage(phys_addr, block_size, expected_pages);
390 }
391 return 0;
392 }
393 #endif /* CONFIG_HUGETLB_PAGE */
394
htab_init_page_sizes(void)395 static void __init htab_init_page_sizes(void)
396 {
397 int rc;
398
399 /* Default to 4K pages only */
400 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
401 sizeof(mmu_psize_defaults_old));
402
403 /*
404 * Try to find the available page sizes in the device-tree
405 */
406 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
407 if (rc != 0) /* Found */
408 goto found;
409
410 /*
411 * Not in the device-tree, let's fallback on known size
412 * list for 16M capable GP & GR
413 */
414 if (mmu_has_feature(MMU_FTR_16M_PAGE))
415 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
416 sizeof(mmu_psize_defaults_gp));
417 found:
418 #ifndef CONFIG_DEBUG_PAGEALLOC
419 /*
420 * Pick a size for the linear mapping. Currently, we only support
421 * 16M, 1M and 4K which is the default
422 */
423 if (mmu_psize_defs[MMU_PAGE_16M].shift)
424 mmu_linear_psize = MMU_PAGE_16M;
425 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
426 mmu_linear_psize = MMU_PAGE_1M;
427 #endif /* CONFIG_DEBUG_PAGEALLOC */
428
429 #ifdef CONFIG_PPC_64K_PAGES
430 /*
431 * Pick a size for the ordinary pages. Default is 4K, we support
432 * 64K for user mappings and vmalloc if supported by the processor.
433 * We only use 64k for ioremap if the processor
434 * (and firmware) support cache-inhibited large pages.
435 * If not, we use 4k and set mmu_ci_restrictions so that
436 * hash_page knows to switch processes that use cache-inhibited
437 * mappings to 4k pages.
438 */
439 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
440 mmu_virtual_psize = MMU_PAGE_64K;
441 mmu_vmalloc_psize = MMU_PAGE_64K;
442 if (mmu_linear_psize == MMU_PAGE_4K)
443 mmu_linear_psize = MMU_PAGE_64K;
444 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
445 /*
446 * Don't use 64k pages for ioremap on pSeries, since
447 * that would stop us accessing the HEA ethernet.
448 */
449 if (!machine_is(pseries))
450 mmu_io_psize = MMU_PAGE_64K;
451 } else
452 mmu_ci_restrictions = 1;
453 }
454 #endif /* CONFIG_PPC_64K_PAGES */
455
456 #ifdef CONFIG_SPARSEMEM_VMEMMAP
457 /* We try to use 16M pages for vmemmap if that is supported
458 * and we have at least 1G of RAM at boot
459 */
460 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
461 memblock_phys_mem_size() >= 0x40000000)
462 mmu_vmemmap_psize = MMU_PAGE_16M;
463 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
464 mmu_vmemmap_psize = MMU_PAGE_64K;
465 else
466 mmu_vmemmap_psize = MMU_PAGE_4K;
467 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
468
469 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
470 "virtual = %d, io = %d"
471 #ifdef CONFIG_SPARSEMEM_VMEMMAP
472 ", vmemmap = %d"
473 #endif
474 "\n",
475 mmu_psize_defs[mmu_linear_psize].shift,
476 mmu_psize_defs[mmu_virtual_psize].shift,
477 mmu_psize_defs[mmu_io_psize].shift
478 #ifdef CONFIG_SPARSEMEM_VMEMMAP
479 ,mmu_psize_defs[mmu_vmemmap_psize].shift
480 #endif
481 );
482
483 #ifdef CONFIG_HUGETLB_PAGE
484 /* Reserve 16G huge page memory sections for huge pages */
485 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
486 #endif /* CONFIG_HUGETLB_PAGE */
487 }
488
htab_dt_scan_pftsize(unsigned long node,const char * uname,int depth,void * data)489 static int __init htab_dt_scan_pftsize(unsigned long node,
490 const char *uname, int depth,
491 void *data)
492 {
493 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
494 u32 *prop;
495
496 /* We are scanning "cpu" nodes only */
497 if (type == NULL || strcmp(type, "cpu") != 0)
498 return 0;
499
500 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
501 if (prop != NULL) {
502 /* pft_size[0] is the NUMA CEC cookie */
503 ppc64_pft_size = prop[1];
504 return 1;
505 }
506 return 0;
507 }
508
htab_get_table_size(void)509 static unsigned long __init htab_get_table_size(void)
510 {
511 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
512
513 /* If hash size isn't already provided by the platform, we try to
514 * retrieve it from the device-tree. If it's not there neither, we
515 * calculate it now based on the total RAM size
516 */
517 if (ppc64_pft_size == 0)
518 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
519 if (ppc64_pft_size)
520 return 1UL << ppc64_pft_size;
521
522 /* round mem_size up to next power of 2 */
523 mem_size = memblock_phys_mem_size();
524 rnd_mem_size = 1UL << __ilog2(mem_size);
525 if (rnd_mem_size < mem_size)
526 rnd_mem_size <<= 1;
527
528 /* # pages / 2 */
529 psize = mmu_psize_defs[mmu_virtual_psize].shift;
530 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
531
532 return pteg_count << 7;
533 }
534
535 #ifdef CONFIG_MEMORY_HOTPLUG
create_section_mapping(unsigned long start,unsigned long end)536 int create_section_mapping(unsigned long start, unsigned long end)
537 {
538 return htab_bolt_mapping(start, end, __pa(start),
539 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
540 mmu_kernel_ssize);
541 }
542
remove_section_mapping(unsigned long start,unsigned long end)543 int remove_section_mapping(unsigned long start, unsigned long end)
544 {
545 return htab_remove_mapping(start, end, mmu_linear_psize,
546 mmu_kernel_ssize);
547 }
548 #endif /* CONFIG_MEMORY_HOTPLUG */
549
550 #define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
551
htab_finish_init(void)552 static void __init htab_finish_init(void)
553 {
554 extern unsigned int *htab_call_hpte_insert1;
555 extern unsigned int *htab_call_hpte_insert2;
556 extern unsigned int *htab_call_hpte_remove;
557 extern unsigned int *htab_call_hpte_updatepp;
558
559 #ifdef CONFIG_PPC_HAS_HASH_64K
560 extern unsigned int *ht64_call_hpte_insert1;
561 extern unsigned int *ht64_call_hpte_insert2;
562 extern unsigned int *ht64_call_hpte_remove;
563 extern unsigned int *ht64_call_hpte_updatepp;
564
565 patch_branch(ht64_call_hpte_insert1,
566 FUNCTION_TEXT(ppc_md.hpte_insert),
567 BRANCH_SET_LINK);
568 patch_branch(ht64_call_hpte_insert2,
569 FUNCTION_TEXT(ppc_md.hpte_insert),
570 BRANCH_SET_LINK);
571 patch_branch(ht64_call_hpte_remove,
572 FUNCTION_TEXT(ppc_md.hpte_remove),
573 BRANCH_SET_LINK);
574 patch_branch(ht64_call_hpte_updatepp,
575 FUNCTION_TEXT(ppc_md.hpte_updatepp),
576 BRANCH_SET_LINK);
577
578 #endif /* CONFIG_PPC_HAS_HASH_64K */
579
580 patch_branch(htab_call_hpte_insert1,
581 FUNCTION_TEXT(ppc_md.hpte_insert),
582 BRANCH_SET_LINK);
583 patch_branch(htab_call_hpte_insert2,
584 FUNCTION_TEXT(ppc_md.hpte_insert),
585 BRANCH_SET_LINK);
586 patch_branch(htab_call_hpte_remove,
587 FUNCTION_TEXT(ppc_md.hpte_remove),
588 BRANCH_SET_LINK);
589 patch_branch(htab_call_hpte_updatepp,
590 FUNCTION_TEXT(ppc_md.hpte_updatepp),
591 BRANCH_SET_LINK);
592 }
593
htab_initialize(void)594 static void __init htab_initialize(void)
595 {
596 unsigned long table;
597 unsigned long pteg_count;
598 unsigned long prot;
599 unsigned long base = 0, size = 0, limit;
600 struct memblock_region *reg;
601
602 DBG(" -> htab_initialize()\n");
603
604 /* Initialize segment sizes */
605 htab_init_seg_sizes();
606
607 /* Initialize page sizes */
608 htab_init_page_sizes();
609
610 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
611 mmu_kernel_ssize = MMU_SEGSIZE_1T;
612 mmu_highuser_ssize = MMU_SEGSIZE_1T;
613 printk(KERN_INFO "Using 1TB segments\n");
614 }
615
616 /*
617 * Calculate the required size of the htab. We want the number of
618 * PTEGs to equal one half the number of real pages.
619 */
620 htab_size_bytes = htab_get_table_size();
621 pteg_count = htab_size_bytes >> 7;
622
623 htab_hash_mask = pteg_count - 1;
624
625 if (firmware_has_feature(FW_FEATURE_LPAR)) {
626 /* Using a hypervisor which owns the htab */
627 htab_address = NULL;
628 _SDR1 = 0;
629 #ifdef CONFIG_FA_DUMP
630 /*
631 * If firmware assisted dump is active firmware preserves
632 * the contents of htab along with entire partition memory.
633 * Clear the htab if firmware assisted dump is active so
634 * that we dont end up using old mappings.
635 */
636 if (is_fadump_active() && ppc_md.hpte_clear_all)
637 ppc_md.hpte_clear_all();
638 #endif
639 } else {
640 /* Find storage for the HPT. Must be contiguous in
641 * the absolute address space. On cell we want it to be
642 * in the first 2 Gig so we can use it for IOMMU hacks.
643 */
644 if (machine_is(cell))
645 limit = 0x80000000;
646 else
647 limit = MEMBLOCK_ALLOC_ANYWHERE;
648
649 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
650
651 DBG("Hash table allocated at %lx, size: %lx\n", table,
652 htab_size_bytes);
653
654 htab_address = abs_to_virt(table);
655
656 /* htab absolute addr + encoded htabsize */
657 _SDR1 = table + __ilog2(pteg_count) - 11;
658
659 /* Initialize the HPT with no entries */
660 memset((void *)table, 0, htab_size_bytes);
661
662 /* Set SDR1 */
663 mtspr(SPRN_SDR1, _SDR1);
664 }
665
666 prot = pgprot_val(PAGE_KERNEL);
667
668 #ifdef CONFIG_DEBUG_PAGEALLOC
669 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
670 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
671 1, ppc64_rma_size));
672 memset(linear_map_hash_slots, 0, linear_map_hash_count);
673 #endif /* CONFIG_DEBUG_PAGEALLOC */
674
675 /* On U3 based machines, we need to reserve the DART area and
676 * _NOT_ map it to avoid cache paradoxes as it's remapped non
677 * cacheable later on
678 */
679
680 /* create bolted the linear mapping in the hash table */
681 for_each_memblock(memory, reg) {
682 base = (unsigned long)__va(reg->base);
683 size = reg->size;
684
685 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
686 base, size, prot);
687
688 #ifdef CONFIG_U3_DART
689 /* Do not map the DART space. Fortunately, it will be aligned
690 * in such a way that it will not cross two memblock regions and
691 * will fit within a single 16Mb page.
692 * The DART space is assumed to be a full 16Mb region even if
693 * we only use 2Mb of that space. We will use more of it later
694 * for AGP GART. We have to use a full 16Mb large page.
695 */
696 DBG("DART base: %lx\n", dart_tablebase);
697
698 if (dart_tablebase != 0 && dart_tablebase >= base
699 && dart_tablebase < (base + size)) {
700 unsigned long dart_table_end = dart_tablebase + 16 * MB;
701 if (base != dart_tablebase)
702 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
703 __pa(base), prot,
704 mmu_linear_psize,
705 mmu_kernel_ssize));
706 if ((base + size) > dart_table_end)
707 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
708 base + size,
709 __pa(dart_table_end),
710 prot,
711 mmu_linear_psize,
712 mmu_kernel_ssize));
713 continue;
714 }
715 #endif /* CONFIG_U3_DART */
716 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
717 prot, mmu_linear_psize, mmu_kernel_ssize));
718 }
719 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
720
721 /*
722 * If we have a memory_limit and we've allocated TCEs then we need to
723 * explicitly map the TCE area at the top of RAM. We also cope with the
724 * case that the TCEs start below memory_limit.
725 * tce_alloc_start/end are 16MB aligned so the mapping should work
726 * for either 4K or 16MB pages.
727 */
728 if (tce_alloc_start) {
729 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
730 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
731
732 if (base + size >= tce_alloc_start)
733 tce_alloc_start = base + size + 1;
734
735 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
736 __pa(tce_alloc_start), prot,
737 mmu_linear_psize, mmu_kernel_ssize));
738 }
739
740 htab_finish_init();
741
742 DBG(" <- htab_initialize()\n");
743 }
744 #undef KB
745 #undef MB
746
early_init_mmu(void)747 void __init early_init_mmu(void)
748 {
749 /* Setup initial STAB address in the PACA */
750 get_paca()->stab_real = __pa((u64)&initial_stab);
751 get_paca()->stab_addr = (u64)&initial_stab;
752
753 /* Initialize the MMU Hash table and create the linear mapping
754 * of memory. Has to be done before stab/slb initialization as
755 * this is currently where the page size encoding is obtained
756 */
757 htab_initialize();
758
759 /* Initialize stab / SLB management */
760 if (mmu_has_feature(MMU_FTR_SLB))
761 slb_initialize();
762 else
763 stab_initialize(get_paca()->stab_real);
764 }
765
766 #ifdef CONFIG_SMP
early_init_mmu_secondary(void)767 void __cpuinit early_init_mmu_secondary(void)
768 {
769 /* Initialize hash table for that CPU */
770 if (!firmware_has_feature(FW_FEATURE_LPAR))
771 mtspr(SPRN_SDR1, _SDR1);
772
773 /* Initialize STAB/SLB. We use a virtual address as it works
774 * in real mode on pSeries.
775 */
776 if (mmu_has_feature(MMU_FTR_SLB))
777 slb_initialize();
778 else
779 stab_initialize(get_paca()->stab_addr);
780 }
781 #endif /* CONFIG_SMP */
782
783 /*
784 * Called by asm hashtable.S for doing lazy icache flush
785 */
hash_page_do_lazy_icache(unsigned int pp,pte_t pte,int trap)786 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
787 {
788 struct page *page;
789
790 if (!pfn_valid(pte_pfn(pte)))
791 return pp;
792
793 page = pte_page(pte);
794
795 /* page is dirty */
796 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
797 if (trap == 0x400) {
798 flush_dcache_icache_page(page);
799 set_bit(PG_arch_1, &page->flags);
800 } else
801 pp |= HPTE_R_N;
802 }
803 return pp;
804 }
805
806 #ifdef CONFIG_PPC_MM_SLICES
get_paca_psize(unsigned long addr)807 unsigned int get_paca_psize(unsigned long addr)
808 {
809 unsigned long index, slices;
810
811 if (addr < SLICE_LOW_TOP) {
812 slices = get_paca()->context.low_slices_psize;
813 index = GET_LOW_SLICE_INDEX(addr);
814 } else {
815 slices = get_paca()->context.high_slices_psize;
816 index = GET_HIGH_SLICE_INDEX(addr);
817 }
818 return (slices >> (index * 4)) & 0xF;
819 }
820
821 #else
get_paca_psize(unsigned long addr)822 unsigned int get_paca_psize(unsigned long addr)
823 {
824 return get_paca()->context.user_psize;
825 }
826 #endif
827
828 /*
829 * Demote a segment to using 4k pages.
830 * For now this makes the whole process use 4k pages.
831 */
832 #ifdef CONFIG_PPC_64K_PAGES
demote_segment_4k(struct mm_struct * mm,unsigned long addr)833 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
834 {
835 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
836 return;
837 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
838 #ifdef CONFIG_SPU_BASE
839 spu_flush_all_slbs(mm);
840 #endif
841 if (get_paca_psize(addr) != MMU_PAGE_4K) {
842 get_paca()->context = mm->context;
843 slb_flush_and_rebolt();
844 }
845 }
846 #endif /* CONFIG_PPC_64K_PAGES */
847
848 #ifdef CONFIG_PPC_SUBPAGE_PROT
849 /*
850 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
851 * Userspace sets the subpage permissions using the subpage_prot system call.
852 *
853 * Result is 0: full permissions, _PAGE_RW: read-only,
854 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
855 */
subpage_protection(struct mm_struct * mm,unsigned long ea)856 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
857 {
858 struct subpage_prot_table *spt = &mm->context.spt;
859 u32 spp = 0;
860 u32 **sbpm, *sbpp;
861
862 if (ea >= spt->maxaddr)
863 return 0;
864 if (ea < 0x100000000) {
865 /* addresses below 4GB use spt->low_prot */
866 sbpm = spt->low_prot;
867 } else {
868 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
869 if (!sbpm)
870 return 0;
871 }
872 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
873 if (!sbpp)
874 return 0;
875 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
876
877 /* extract 2-bit bitfield for this 4k subpage */
878 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
879
880 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
881 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
882 return spp;
883 }
884
885 #else /* CONFIG_PPC_SUBPAGE_PROT */
subpage_protection(struct mm_struct * mm,unsigned long ea)886 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
887 {
888 return 0;
889 }
890 #endif
891
hash_failure_debug(unsigned long ea,unsigned long access,unsigned long vsid,unsigned long trap,int ssize,int psize,unsigned long pte)892 void hash_failure_debug(unsigned long ea, unsigned long access,
893 unsigned long vsid, unsigned long trap,
894 int ssize, int psize, unsigned long pte)
895 {
896 if (!printk_ratelimit())
897 return;
898 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
899 ea, access, current->comm);
900 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
901 trap, vsid, ssize, psize, pte);
902 }
903
904 /* Result code is:
905 * 0 - handled
906 * 1 - normal page fault
907 * -1 - critical hash insertion error
908 * -2 - access not permitted by subpage protection mechanism
909 */
hash_page(unsigned long ea,unsigned long access,unsigned long trap)910 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
911 {
912 pgd_t *pgdir;
913 unsigned long vsid;
914 struct mm_struct *mm;
915 pte_t *ptep;
916 unsigned hugeshift;
917 const struct cpumask *tmp;
918 int rc, user_region = 0, local = 0;
919 int psize, ssize;
920
921 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
922 ea, access, trap);
923
924 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
925 DBG_LOW(" out of pgtable range !\n");
926 return 1;
927 }
928
929 /* Get region & vsid */
930 switch (REGION_ID(ea)) {
931 case USER_REGION_ID:
932 user_region = 1;
933 mm = current->mm;
934 if (! mm) {
935 DBG_LOW(" user region with no mm !\n");
936 return 1;
937 }
938 psize = get_slice_psize(mm, ea);
939 ssize = user_segment_size(ea);
940 vsid = get_vsid(mm->context.id, ea, ssize);
941 break;
942 case VMALLOC_REGION_ID:
943 mm = &init_mm;
944 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
945 if (ea < VMALLOC_END)
946 psize = mmu_vmalloc_psize;
947 else
948 psize = mmu_io_psize;
949 ssize = mmu_kernel_ssize;
950 break;
951 default:
952 /* Not a valid range
953 * Send the problem up to do_page_fault
954 */
955 return 1;
956 }
957 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
958
959 /* Get pgdir */
960 pgdir = mm->pgd;
961 if (pgdir == NULL)
962 return 1;
963
964 /* Check CPU locality */
965 tmp = cpumask_of(smp_processor_id());
966 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
967 local = 1;
968
969 #ifndef CONFIG_PPC_64K_PAGES
970 /* If we use 4K pages and our psize is not 4K, then we might
971 * be hitting a special driver mapping, and need to align the
972 * address before we fetch the PTE.
973 *
974 * It could also be a hugepage mapping, in which case this is
975 * not necessary, but it's not harmful, either.
976 */
977 if (psize != MMU_PAGE_4K)
978 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
979 #endif /* CONFIG_PPC_64K_PAGES */
980
981 /* Get PTE and page size from page tables */
982 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
983 if (ptep == NULL || !pte_present(*ptep)) {
984 DBG_LOW(" no PTE !\n");
985 return 1;
986 }
987
988 /* Add _PAGE_PRESENT to the required access perm */
989 access |= _PAGE_PRESENT;
990
991 /* Pre-check access permissions (will be re-checked atomically
992 * in __hash_page_XX but this pre-check is a fast path
993 */
994 if (access & ~pte_val(*ptep)) {
995 DBG_LOW(" no access !\n");
996 return 1;
997 }
998
999 #ifdef CONFIG_HUGETLB_PAGE
1000 if (hugeshift)
1001 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
1002 ssize, hugeshift, psize);
1003 #endif /* CONFIG_HUGETLB_PAGE */
1004
1005 #ifndef CONFIG_PPC_64K_PAGES
1006 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1007 #else
1008 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1009 pte_val(*(ptep + PTRS_PER_PTE)));
1010 #endif
1011 /* Do actual hashing */
1012 #ifdef CONFIG_PPC_64K_PAGES
1013 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1014 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1015 demote_segment_4k(mm, ea);
1016 psize = MMU_PAGE_4K;
1017 }
1018
1019 /* If this PTE is non-cacheable and we have restrictions on
1020 * using non cacheable large pages, then we switch to 4k
1021 */
1022 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1023 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1024 if (user_region) {
1025 demote_segment_4k(mm, ea);
1026 psize = MMU_PAGE_4K;
1027 } else if (ea < VMALLOC_END) {
1028 /*
1029 * some driver did a non-cacheable mapping
1030 * in vmalloc space, so switch vmalloc
1031 * to 4k pages
1032 */
1033 printk(KERN_ALERT "Reducing vmalloc segment "
1034 "to 4kB pages because of "
1035 "non-cacheable mapping\n");
1036 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1037 #ifdef CONFIG_SPU_BASE
1038 spu_flush_all_slbs(mm);
1039 #endif
1040 }
1041 }
1042 if (user_region) {
1043 if (psize != get_paca_psize(ea)) {
1044 get_paca()->context = mm->context;
1045 slb_flush_and_rebolt();
1046 }
1047 } else if (get_paca()->vmalloc_sllp !=
1048 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1049 get_paca()->vmalloc_sllp =
1050 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1051 slb_vmalloc_update();
1052 }
1053 #endif /* CONFIG_PPC_64K_PAGES */
1054
1055 #ifdef CONFIG_PPC_HAS_HASH_64K
1056 if (psize == MMU_PAGE_64K)
1057 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1058 else
1059 #endif /* CONFIG_PPC_HAS_HASH_64K */
1060 {
1061 int spp = subpage_protection(mm, ea);
1062 if (access & spp)
1063 rc = -2;
1064 else
1065 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1066 local, ssize, spp);
1067 }
1068
1069 /* Dump some info in case of hash insertion failure, they should
1070 * never happen so it is really useful to know if/when they do
1071 */
1072 if (rc == -1)
1073 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1074 pte_val(*ptep));
1075 #ifndef CONFIG_PPC_64K_PAGES
1076 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1077 #else
1078 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1079 pte_val(*(ptep + PTRS_PER_PTE)));
1080 #endif
1081 DBG_LOW(" -> rc=%d\n", rc);
1082 return rc;
1083 }
1084 EXPORT_SYMBOL_GPL(hash_page);
1085
hash_preload(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap)1086 void hash_preload(struct mm_struct *mm, unsigned long ea,
1087 unsigned long access, unsigned long trap)
1088 {
1089 unsigned long vsid;
1090 pgd_t *pgdir;
1091 pte_t *ptep;
1092 unsigned long flags;
1093 int rc, ssize, local = 0;
1094
1095 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1096
1097 #ifdef CONFIG_PPC_MM_SLICES
1098 /* We only prefault standard pages for now */
1099 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1100 return;
1101 #endif
1102
1103 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1104 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1105
1106 /* Get Linux PTE if available */
1107 pgdir = mm->pgd;
1108 if (pgdir == NULL)
1109 return;
1110 ptep = find_linux_pte(pgdir, ea);
1111 if (!ptep)
1112 return;
1113
1114 #ifdef CONFIG_PPC_64K_PAGES
1115 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1116 * a 64K kernel), then we don't preload, hash_page() will take
1117 * care of it once we actually try to access the page.
1118 * That way we don't have to duplicate all of the logic for segment
1119 * page size demotion here
1120 */
1121 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1122 return;
1123 #endif /* CONFIG_PPC_64K_PAGES */
1124
1125 /* Get VSID */
1126 ssize = user_segment_size(ea);
1127 vsid = get_vsid(mm->context.id, ea, ssize);
1128
1129 /* Hash doesn't like irqs */
1130 local_irq_save(flags);
1131
1132 /* Is that local to this CPU ? */
1133 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1134 local = 1;
1135
1136 /* Hash it in */
1137 #ifdef CONFIG_PPC_HAS_HASH_64K
1138 if (mm->context.user_psize == MMU_PAGE_64K)
1139 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1140 else
1141 #endif /* CONFIG_PPC_HAS_HASH_64K */
1142 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1143 subpage_protection(mm, ea));
1144
1145 /* Dump some info in case of hash insertion failure, they should
1146 * never happen so it is really useful to know if/when they do
1147 */
1148 if (rc == -1)
1149 hash_failure_debug(ea, access, vsid, trap, ssize,
1150 mm->context.user_psize, pte_val(*ptep));
1151
1152 local_irq_restore(flags);
1153 }
1154
1155 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1156 * do not forget to update the assembly call site !
1157 */
flush_hash_page(unsigned long va,real_pte_t pte,int psize,int ssize,int local)1158 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1159 int local)
1160 {
1161 unsigned long hash, index, shift, hidx, slot;
1162
1163 DBG_LOW("flush_hash_page(va=%016lx)\n", va);
1164 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1165 hash = hpt_hash(va, shift, ssize);
1166 hidx = __rpte_to_hidx(pte, index);
1167 if (hidx & _PTEIDX_SECONDARY)
1168 hash = ~hash;
1169 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1170 slot += hidx & _PTEIDX_GROUP_IX;
1171 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1172 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1173 } pte_iterate_hashed_end();
1174 }
1175
flush_hash_range(unsigned long number,int local)1176 void flush_hash_range(unsigned long number, int local)
1177 {
1178 if (ppc_md.flush_hash_range)
1179 ppc_md.flush_hash_range(number, local);
1180 else {
1181 int i;
1182 struct ppc64_tlb_batch *batch =
1183 &__get_cpu_var(ppc64_tlb_batch);
1184
1185 for (i = 0; i < number; i++)
1186 flush_hash_page(batch->vaddr[i], batch->pte[i],
1187 batch->psize, batch->ssize, local);
1188 }
1189 }
1190
1191 /*
1192 * low_hash_fault is called when we the low level hash code failed
1193 * to instert a PTE due to an hypervisor error
1194 */
low_hash_fault(struct pt_regs * regs,unsigned long address,int rc)1195 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1196 {
1197 if (user_mode(regs)) {
1198 #ifdef CONFIG_PPC_SUBPAGE_PROT
1199 if (rc == -2)
1200 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1201 else
1202 #endif
1203 _exception(SIGBUS, regs, BUS_ADRERR, address);
1204 } else
1205 bad_page_fault(regs, address, SIGBUS);
1206 }
1207
1208 #ifdef CONFIG_DEBUG_PAGEALLOC
kernel_map_linear_page(unsigned long vaddr,unsigned long lmi)1209 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1210 {
1211 unsigned long hash, hpteg;
1212 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1213 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1214 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1215 int ret;
1216
1217 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1218 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1219
1220 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1221 mode, HPTE_V_BOLTED,
1222 mmu_linear_psize, mmu_kernel_ssize);
1223 BUG_ON (ret < 0);
1224 spin_lock(&linear_map_hash_lock);
1225 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1226 linear_map_hash_slots[lmi] = ret | 0x80;
1227 spin_unlock(&linear_map_hash_lock);
1228 }
1229
kernel_unmap_linear_page(unsigned long vaddr,unsigned long lmi)1230 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1231 {
1232 unsigned long hash, hidx, slot;
1233 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1234 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1235
1236 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1237 spin_lock(&linear_map_hash_lock);
1238 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1239 hidx = linear_map_hash_slots[lmi] & 0x7f;
1240 linear_map_hash_slots[lmi] = 0;
1241 spin_unlock(&linear_map_hash_lock);
1242 if (hidx & _PTEIDX_SECONDARY)
1243 hash = ~hash;
1244 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1245 slot += hidx & _PTEIDX_GROUP_IX;
1246 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1247 }
1248
kernel_map_pages(struct page * page,int numpages,int enable)1249 void kernel_map_pages(struct page *page, int numpages, int enable)
1250 {
1251 unsigned long flags, vaddr, lmi;
1252 int i;
1253
1254 local_irq_save(flags);
1255 for (i = 0; i < numpages; i++, page++) {
1256 vaddr = (unsigned long)page_address(page);
1257 lmi = __pa(vaddr) >> PAGE_SHIFT;
1258 if (lmi >= linear_map_hash_count)
1259 continue;
1260 if (enable)
1261 kernel_map_linear_page(vaddr, lmi);
1262 else
1263 kernel_unmap_linear_page(vaddr, lmi);
1264 }
1265 local_irq_restore(flags);
1266 }
1267 #endif /* CONFIG_DEBUG_PAGEALLOC */
1268
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)1269 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1270 phys_addr_t first_memblock_size)
1271 {
1272 /* We don't currently support the first MEMBLOCK not mapping 0
1273 * physical on those processors
1274 */
1275 BUG_ON(first_memblock_base != 0);
1276
1277 /* On LPAR systems, the first entry is our RMA region,
1278 * non-LPAR 64-bit hash MMU systems don't have a limitation
1279 * on real mode access, but using the first entry works well
1280 * enough. We also clamp it to 1G to avoid some funky things
1281 * such as RTAS bugs etc...
1282 */
1283 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1284
1285 /* Finally limit subsequent allocations */
1286 memblock_set_current_limit(ppc64_rma_size);
1287 }
1288