1 /*
2  * Copyright 2019 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include <core/subdev.h>
23 #include <nvfw/acr.h>
24 
25 void
wpr_header_dump(struct nvkm_subdev * subdev,const struct wpr_header * hdr)26 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr)
27 {
28 	nvkm_debug(subdev, "wprHeader\n");
29 	nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
30 	nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
31 	nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
32 	nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
33 	nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
34 }
35 
36 void
wpr_header_v1_dump(struct nvkm_subdev * subdev,const struct wpr_header_v1 * hdr)37 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr)
38 {
39 	nvkm_debug(subdev, "wprHeader\n");
40 	nvkm_debug(subdev, "\tfalconID      : %d\n", hdr->falcon_id);
41 	nvkm_debug(subdev, "\tlsbOffset     : 0x%x\n", hdr->lsb_offset);
42 	nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
43 	nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
44 	nvkm_debug(subdev, "\tbinVersion    : %d\n", hdr->bin_version);
45 	nvkm_debug(subdev, "\tstatus        : %d\n", hdr->status);
46 }
47 
48 static void
lsb_header_tail_dump(struct nvkm_subdev * subdev,struct lsb_header_tail * hdr)49 lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr)
50 {
51 	nvkm_debug(subdev, "lsbHeader\n");
52 	nvkm_debug(subdev, "\tucodeOff      : 0x%x\n", hdr->ucode_off);
53 	nvkm_debug(subdev, "\tucodeSize     : 0x%x\n", hdr->ucode_size);
54 	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
55 	nvkm_debug(subdev, "\tblCodeSize    : 0x%x\n", hdr->bl_code_size);
56 	nvkm_debug(subdev, "\tblImemOff     : 0x%x\n", hdr->bl_imem_off);
57 	nvkm_debug(subdev, "\tblDataOff     : 0x%x\n", hdr->bl_data_off);
58 	nvkm_debug(subdev, "\tblDataSize    : 0x%x\n", hdr->bl_data_size);
59 	nvkm_debug(subdev, "\tappCodeOff    : 0x%x\n", hdr->app_code_off);
60 	nvkm_debug(subdev, "\tappCodeSize   : 0x%x\n", hdr->app_code_size);
61 	nvkm_debug(subdev, "\tappDataOff    : 0x%x\n", hdr->app_data_off);
62 	nvkm_debug(subdev, "\tappDataSize   : 0x%x\n", hdr->app_data_size);
63 	nvkm_debug(subdev, "\tflags         : 0x%x\n", hdr->flags);
64 }
65 
66 void
lsb_header_dump(struct nvkm_subdev * subdev,struct lsb_header * hdr)67 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr)
68 {
69 	lsb_header_tail_dump(subdev, &hdr->tail);
70 }
71 
72 void
lsb_header_v1_dump(struct nvkm_subdev * subdev,struct lsb_header_v1 * hdr)73 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr)
74 {
75 	lsb_header_tail_dump(subdev, &hdr->tail);
76 }
77 
78 void
flcn_acr_desc_dump(struct nvkm_subdev * subdev,struct flcn_acr_desc * hdr)79 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr)
80 {
81 	int i;
82 
83 	nvkm_debug(subdev, "acrDesc\n");
84 	nvkm_debug(subdev, "\twprRegionId  : %d\n", hdr->wpr_region_id);
85 	nvkm_debug(subdev, "\twprOffset    : 0x%x\n", hdr->wpr_offset);
86 	nvkm_debug(subdev, "\tmmuMemRange  : 0x%x\n",
87 		   hdr->mmu_mem_range);
88 	nvkm_debug(subdev, "\tnoRegions    : %d\n",
89 		   hdr->regions.no_regions);
90 
91 	for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
92 		nvkm_debug(subdev, "\tregion[%d]    :\n", i);
93 		nvkm_debug(subdev, "\t  startAddr  : 0x%x\n",
94 			   hdr->regions.region_props[i].start_addr);
95 		nvkm_debug(subdev, "\t  endAddr    : 0x%x\n",
96 			   hdr->regions.region_props[i].end_addr);
97 		nvkm_debug(subdev, "\t  regionId   : %d\n",
98 			   hdr->regions.region_props[i].region_id);
99 		nvkm_debug(subdev, "\t  readMask   : 0x%x\n",
100 			   hdr->regions.region_props[i].read_mask);
101 		nvkm_debug(subdev, "\t  writeMask  : 0x%x\n",
102 			   hdr->regions.region_props[i].write_mask);
103 		nvkm_debug(subdev, "\t  clientMask : 0x%x\n",
104 			   hdr->regions.region_props[i].client_mask);
105 	}
106 
107 	nvkm_debug(subdev, "\tucodeBlobSize: %d\n",
108 		   hdr->ucode_blob_size);
109 	nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n",
110 		   hdr->ucode_blob_base);
111 	nvkm_debug(subdev, "\tvprEnabled   : %d\n",
112 		   hdr->vpr_desc.vpr_enabled);
113 	nvkm_debug(subdev, "\tvprStart     : 0x%x\n",
114 		   hdr->vpr_desc.vpr_start);
115 	nvkm_debug(subdev, "\tvprEnd       : 0x%x\n",
116 		   hdr->vpr_desc.vpr_end);
117 	nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",
118 		   hdr->vpr_desc.hdcp_policies);
119 }
120 
121 void
flcn_acr_desc_v1_dump(struct nvkm_subdev * subdev,struct flcn_acr_desc_v1 * hdr)122 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr)
123 {
124 	int i;
125 
126 	nvkm_debug(subdev, "acrDesc\n");
127 	nvkm_debug(subdev, "\twprRegionId         : %d\n", hdr->wpr_region_id);
128 	nvkm_debug(subdev, "\twprOffset           : 0x%x\n", hdr->wpr_offset);
129 	nvkm_debug(subdev, "\tmmuMemoryRange      : 0x%x\n",
130 		   hdr->mmu_memory_range);
131 	nvkm_debug(subdev, "\tnoRegions           : %d\n",
132 		   hdr->regions.no_regions);
133 
134 	for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) {
135 		nvkm_debug(subdev, "\tregion[%d]           :\n", i);
136 		nvkm_debug(subdev, "\t  startAddr         : 0x%x\n",
137 			   hdr->regions.region_props[i].start_addr);
138 		nvkm_debug(subdev, "\t  endAddr           : 0x%x\n",
139 			   hdr->regions.region_props[i].end_addr);
140 		nvkm_debug(subdev, "\t  regionId          : %d\n",
141 			   hdr->regions.region_props[i].region_id);
142 		nvkm_debug(subdev, "\t  readMask          : 0x%x\n",
143 			   hdr->regions.region_props[i].read_mask);
144 		nvkm_debug(subdev, "\t  writeMask         : 0x%x\n",
145 			   hdr->regions.region_props[i].write_mask);
146 		nvkm_debug(subdev, "\t  clientMask        : 0x%x\n",
147 			   hdr->regions.region_props[i].client_mask);
148 		nvkm_debug(subdev, "\t  shadowMemStartAddr: 0x%x\n",
149 			   hdr->regions.region_props[i].shadow_mem_start_addr);
150 	}
151 
152 	nvkm_debug(subdev, "\tucodeBlobSize       : %d\n",
153 		   hdr->ucode_blob_size);
154 	nvkm_debug(subdev, "\tucodeBlobBase       : 0x%llx\n",
155 		   hdr->ucode_blob_base);
156 	nvkm_debug(subdev, "\tvprEnabled          : %d\n",
157 		   hdr->vpr_desc.vpr_enabled);
158 	nvkm_debug(subdev, "\tvprStart            : 0x%x\n",
159 		   hdr->vpr_desc.vpr_start);
160 	nvkm_debug(subdev, "\tvprEnd              : 0x%x\n",
161 		   hdr->vpr_desc.vpr_end);
162 	nvkm_debug(subdev, "\thdcpPolicies        : 0x%x\n",
163 		   hdr->vpr_desc.hdcp_policies);
164 }
165