1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28
29 #include "ObjectID.h"
30 #include "atomfirmware.h"
31
32 #include "dc_bios_types.h"
33 #include "include/grph_object_ctrl_defs.h"
34 #include "include/bios_parser_interface.h"
35 #include "include/i2caux_interface.h"
36 #include "include/logger_interface.h"
37
38 #include "command_table2.h"
39
40 #include "bios_parser_helper.h"
41 #include "command_table_helper2.h"
42 #include "bios_parser2.h"
43 #include "bios_parser_types_internal2.h"
44 #include "bios_parser_interface.h"
45
46 #include "bios_parser_common.h"
47
48 #define DC_LOGGER \
49 bp->base.ctx->logger
50
51 #define LAST_RECORD_TYPE 0xff
52 #define SMU9_SYSPLL0_ID 0
53
54 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
55 struct atom_i2c_record *record,
56 struct graphics_object_i2c_info *info);
57
58 static enum bp_result bios_parser_get_firmware_info(
59 struct dc_bios *dcb,
60 struct dc_firmware_info *info);
61
62 static enum bp_result bios_parser_get_encoder_cap_info(
63 struct dc_bios *dcb,
64 struct graphics_object_id object_id,
65 struct bp_encoder_cap_info *info);
66
67 static enum bp_result get_firmware_info_v3_1(
68 struct bios_parser *bp,
69 struct dc_firmware_info *info);
70
71 static enum bp_result get_firmware_info_v3_2(
72 struct bios_parser *bp,
73 struct dc_firmware_info *info);
74
75 static enum bp_result get_firmware_info_v3_4(
76 struct bios_parser *bp,
77 struct dc_firmware_info *info);
78
79 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
80 struct atom_display_object_path_v2 *object);
81
82 static struct atom_encoder_caps_record *get_encoder_cap_record(
83 struct bios_parser *bp,
84 struct atom_display_object_path_v2 *object);
85
86 #define BIOS_IMAGE_SIZE_OFFSET 2
87 #define BIOS_IMAGE_SIZE_UNIT 512
88
89 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
90
bios_parser2_destruct(struct bios_parser * bp)91 static void bios_parser2_destruct(struct bios_parser *bp)
92 {
93 kfree(bp->base.bios_local_image);
94 kfree(bp->base.integrated_info);
95 }
96
firmware_parser_destroy(struct dc_bios ** dcb)97 static void firmware_parser_destroy(struct dc_bios **dcb)
98 {
99 struct bios_parser *bp = BP_FROM_DCB(*dcb);
100
101 if (!bp) {
102 BREAK_TO_DEBUGGER();
103 return;
104 }
105
106 bios_parser2_destruct(bp);
107
108 kfree(bp);
109 *dcb = NULL;
110 }
111
get_atom_data_table_revision(struct atom_common_table_header * atom_data_tbl,struct atom_data_revision * tbl_revision)112 static void get_atom_data_table_revision(
113 struct atom_common_table_header *atom_data_tbl,
114 struct atom_data_revision *tbl_revision)
115 {
116 if (!tbl_revision)
117 return;
118
119 /* initialize the revision to 0 which is invalid revision */
120 tbl_revision->major = 0;
121 tbl_revision->minor = 0;
122
123 if (!atom_data_tbl)
124 return;
125
126 tbl_revision->major =
127 (uint32_t) atom_data_tbl->format_revision & 0x3f;
128 tbl_revision->minor =
129 (uint32_t) atom_data_tbl->content_revision & 0x3f;
130 }
131
132 /* BIOS oject table displaypath is per connector.
133 * There is extra path not for connector. BIOS fill its encoderid as 0
134 */
bios_parser_get_connectors_number(struct dc_bios * dcb)135 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
136 {
137 struct bios_parser *bp = BP_FROM_DCB(dcb);
138 unsigned int count = 0;
139 unsigned int i;
140
141 switch (bp->object_info_tbl.revision.minor) {
142 default:
143 case 4:
144 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
145 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
146 count++;
147
148 break;
149
150 case 5:
151 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
152 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
153 count++;
154
155 break;
156 }
157 return count;
158 }
159
bios_parser_get_connector_id(struct dc_bios * dcb,uint8_t i)160 static struct graphics_object_id bios_parser_get_connector_id(
161 struct dc_bios *dcb,
162 uint8_t i)
163 {
164 struct bios_parser *bp = BP_FROM_DCB(dcb);
165 struct graphics_object_id object_id = dal_graphics_object_id_init(
166 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
167 struct object_info_table *tbl = &bp->object_info_tbl;
168 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
169
170 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
171
172 switch (bp->object_info_tbl.revision.minor) {
173 default:
174 case 4:
175 if (v1_4->number_of_path > i) {
176 /* If display_objid is generic object id, the encoderObj
177 * /extencoderobjId should be 0
178 */
179 if (v1_4->display_path[i].encoderobjid != 0 &&
180 v1_4->display_path[i].display_objid != 0)
181 object_id = object_id_from_bios_object_id(
182 v1_4->display_path[i].display_objid);
183 }
184 break;
185
186 case 5:
187 if (v1_5->number_of_path > i) {
188 /* If display_objid is generic object id, the encoderObjId
189 * should be 0
190 */
191 if (v1_5->display_path[i].encoderobjid != 0 &&
192 v1_5->display_path[i].display_objid != 0)
193 object_id = object_id_from_bios_object_id(
194 v1_5->display_path[i].display_objid);
195 }
196 break;
197 }
198 return object_id;
199 }
200
bios_parser_get_src_obj(struct dc_bios * dcb,struct graphics_object_id object_id,uint32_t index,struct graphics_object_id * src_object_id)201 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
202 struct graphics_object_id object_id, uint32_t index,
203 struct graphics_object_id *src_object_id)
204 {
205 struct bios_parser *bp = BP_FROM_DCB(dcb);
206 unsigned int i;
207 enum bp_result bp_result = BP_RESULT_BADINPUT;
208 struct graphics_object_id obj_id = { 0 };
209 struct object_info_table *tbl = &bp->object_info_tbl;
210
211 if (!src_object_id)
212 return bp_result;
213
214 switch (object_id.type) {
215 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
216 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
217 */
218 case OBJECT_TYPE_ENCODER:
219 /* TODO: since num of src must be less than 2.
220 * If found in for loop, should break.
221 * DAL2 implementation may be changed too
222 */
223 switch (bp->object_info_tbl.revision.minor) {
224 default:
225 case 4:
226 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
227 obj_id = object_id_from_bios_object_id(
228 tbl->v1_4->display_path[i].encoderobjid);
229 if (object_id.type == obj_id.type &&
230 object_id.id == obj_id.id &&
231 object_id.enum_id == obj_id.enum_id) {
232 *src_object_id =
233 object_id_from_bios_object_id(
234 0x1100);
235 /* break; */
236 }
237 }
238 bp_result = BP_RESULT_OK;
239 break;
240
241 case 5:
242 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
243 obj_id = object_id_from_bios_object_id(
244 tbl->v1_5->display_path[i].encoderobjid);
245 if (object_id.type == obj_id.type &&
246 object_id.id == obj_id.id &&
247 object_id.enum_id == obj_id.enum_id) {
248 *src_object_id =
249 object_id_from_bios_object_id(
250 0x1100);
251 /* break; */
252 }
253 }
254 bp_result = BP_RESULT_OK;
255 break;
256 }
257 break;
258 case OBJECT_TYPE_CONNECTOR:
259 switch (bp->object_info_tbl.revision.minor) {
260 default:
261 case 4:
262 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
263 obj_id = object_id_from_bios_object_id(
264 tbl->v1_4->display_path[i]
265 .display_objid);
266
267 if (object_id.type == obj_id.type &&
268 object_id.id == obj_id.id &&
269 object_id.enum_id == obj_id.enum_id) {
270 *src_object_id =
271 object_id_from_bios_object_id(
272 tbl->v1_4
273 ->display_path[i]
274 .encoderobjid);
275 /* break; */
276 }
277 }
278 bp_result = BP_RESULT_OK;
279 break;
280 }
281 bp_result = BP_RESULT_OK;
282 break;
283 case 5:
284 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
285 obj_id = object_id_from_bios_object_id(
286 tbl->v1_5->display_path[i].display_objid);
287
288 if (object_id.type == obj_id.type &&
289 object_id.id == obj_id.id &&
290 object_id.enum_id == obj_id.enum_id) {
291 *src_object_id = object_id_from_bios_object_id(
292 tbl->v1_5->display_path[i].encoderobjid);
293 /* break; */
294 }
295 }
296 bp_result = BP_RESULT_OK;
297 break;
298
299 default:
300 bp_result = BP_RESULT_OK;
301 break;
302 }
303
304 return bp_result;
305 }
306
307 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object(struct bios_parser * bp,struct graphics_object_id id)308 static struct atom_display_object_path_v2 *get_bios_object(
309 struct bios_parser *bp,
310 struct graphics_object_id id)
311 {
312 unsigned int i;
313 struct graphics_object_id obj_id = {0};
314
315 switch (id.type) {
316 case OBJECT_TYPE_ENCODER:
317 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
318 obj_id = object_id_from_bios_object_id(
319 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
320 if (id.type == obj_id.type && id.id == obj_id.id
321 && id.enum_id == obj_id.enum_id)
322 return &bp->object_info_tbl.v1_4->display_path[i];
323 }
324 fallthrough;
325 case OBJECT_TYPE_CONNECTOR:
326 case OBJECT_TYPE_GENERIC:
327 /* Both Generic and Connector Object ID
328 * will be stored on display_objid
329 */
330 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
331 obj_id = object_id_from_bios_object_id(
332 bp->object_info_tbl.v1_4->display_path[i].display_objid);
333 if (id.type == obj_id.type && id.id == obj_id.id
334 && id.enum_id == obj_id.enum_id)
335 return &bp->object_info_tbl.v1_4->display_path[i];
336 }
337 fallthrough;
338 default:
339 return NULL;
340 }
341 }
342
343 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object_from_path_v3(struct bios_parser * bp,struct graphics_object_id id)344 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(
345 struct bios_parser *bp,
346 struct graphics_object_id id)
347 {
348 unsigned int i;
349 struct graphics_object_id obj_id = {0};
350
351 switch (id.type) {
352 case OBJECT_TYPE_ENCODER:
353 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
354 obj_id = object_id_from_bios_object_id(
355 bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
356 if (id.type == obj_id.type && id.id == obj_id.id
357 && id.enum_id == obj_id.enum_id)
358 return &bp->object_info_tbl.v1_5->display_path[i];
359 }
360 break;
361
362 case OBJECT_TYPE_CONNECTOR:
363 case OBJECT_TYPE_GENERIC:
364 /* Both Generic and Connector Object ID
365 * will be stored on display_objid
366 */
367 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
368 obj_id = object_id_from_bios_object_id(
369 bp->object_info_tbl.v1_5->display_path[i].display_objid);
370 if (id.type == obj_id.type && id.id == obj_id.id
371 && id.enum_id == obj_id.enum_id)
372 return &bp->object_info_tbl.v1_5->display_path[i];
373 }
374 break;
375
376 default:
377 return NULL;
378 }
379
380 return NULL;
381 }
382
bios_parser_get_i2c_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_i2c_info * info)383 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
384 struct graphics_object_id id,
385 struct graphics_object_i2c_info *info)
386 {
387 uint32_t offset;
388 struct atom_display_object_path_v2 *object;
389
390 struct atom_display_object_path_v3 *object_path_v3;
391
392 struct atom_common_record_header *header;
393 struct atom_i2c_record *record;
394 struct atom_i2c_record dummy_record = {0};
395 struct bios_parser *bp = BP_FROM_DCB(dcb);
396
397 if (!info)
398 return BP_RESULT_BADINPUT;
399
400 if (id.type == OBJECT_TYPE_GENERIC) {
401 dummy_record.i2c_id = id.id;
402
403 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
404 return BP_RESULT_OK;
405 else
406 return BP_RESULT_NORECORD;
407 }
408
409 switch (bp->object_info_tbl.revision.minor) {
410 case 4:
411 default:
412 object = get_bios_object(bp, id);
413
414 if (!object)
415 return BP_RESULT_BADINPUT;
416
417 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
418 break;
419 case 5:
420 object_path_v3 = get_bios_object_from_path_v3(bp, id);
421
422 if (!object_path_v3)
423 return BP_RESULT_BADINPUT;
424
425 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
426 break;
427 }
428
429 for (;;) {
430 header = GET_IMAGE(struct atom_common_record_header, offset);
431
432 if (!header)
433 return BP_RESULT_BADBIOSTABLE;
434
435 if (header->record_type == LAST_RECORD_TYPE ||
436 !header->record_size)
437 break;
438
439 if (header->record_type == ATOM_I2C_RECORD_TYPE
440 && sizeof(struct atom_i2c_record) <=
441 header->record_size) {
442 /* get the I2C info */
443 record = (struct atom_i2c_record *) header;
444
445 if (get_gpio_i2c_info(bp, record, info) ==
446 BP_RESULT_OK)
447 return BP_RESULT_OK;
448 }
449
450 offset += header->record_size;
451 }
452
453 return BP_RESULT_NORECORD;
454 }
455
get_gpio_i2c_info(struct bios_parser * bp,struct atom_i2c_record * record,struct graphics_object_i2c_info * info)456 static enum bp_result get_gpio_i2c_info(
457 struct bios_parser *bp,
458 struct atom_i2c_record *record,
459 struct graphics_object_i2c_info *info)
460 {
461 struct atom_gpio_pin_lut_v2_1 *header;
462 uint32_t count = 0;
463 unsigned int table_index = 0;
464 bool find_valid = false;
465 struct atom_gpio_pin_assignment *pin;
466
467 if (!info)
468 return BP_RESULT_BADINPUT;
469
470 /* get the GPIO_I2C info */
471 if (!DATA_TABLES(gpio_pin_lut))
472 return BP_RESULT_BADBIOSTABLE;
473
474 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
475 DATA_TABLES(gpio_pin_lut));
476 if (!header)
477 return BP_RESULT_BADBIOSTABLE;
478
479 if (sizeof(struct atom_common_table_header) +
480 sizeof(struct atom_gpio_pin_assignment) >
481 le16_to_cpu(header->table_header.structuresize))
482 return BP_RESULT_BADBIOSTABLE;
483
484 /* TODO: is version change? */
485 if (header->table_header.content_revision != 1)
486 return BP_RESULT_UNSUPPORTED;
487
488 /* get data count */
489 count = (le16_to_cpu(header->table_header.structuresize)
490 - sizeof(struct atom_common_table_header))
491 / sizeof(struct atom_gpio_pin_assignment);
492
493 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin;
494
495 for (table_index = 0; table_index < count; table_index++) {
496 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) &&
497 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) &&
498 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) {
499 /* still valid */
500 find_valid = true;
501 break;
502 }
503 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment));
504 }
505
506 /* If we don't find the entry that we are looking for then
507 * we will return BP_Result_BadBiosTable.
508 */
509 if (find_valid == false)
510 return BP_RESULT_BADBIOSTABLE;
511
512 /* get the GPIO_I2C_INFO */
513 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
514 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
515 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
516 info->i2c_slave_address = record->i2c_slave_addr;
517
518 /* TODO: check how to get register offset for en, Y, etc. */
519 info->gpio_info.clk_a_register_index =
520 le16_to_cpu(
521 header->gpio_pin[table_index].data_a_reg_index);
522 info->gpio_info.clk_a_shift =
523 header->gpio_pin[table_index].gpio_bitshift;
524
525 return BP_RESULT_OK;
526 }
527
get_hpd_record_for_path_v3(struct bios_parser * bp,struct atom_display_object_path_v3 * object)528 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(
529 struct bios_parser *bp,
530 struct atom_display_object_path_v3 *object)
531 {
532 struct atom_common_record_header *header;
533 uint32_t offset;
534
535 if (!object) {
536 BREAK_TO_DEBUGGER(); /* Invalid object */
537 return NULL;
538 }
539
540 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
541
542 for (;;) {
543 header = GET_IMAGE(struct atom_common_record_header, offset);
544
545 if (!header)
546 return NULL;
547
548 if (header->record_type == ATOM_RECORD_END_TYPE ||
549 !header->record_size)
550 break;
551
552 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
553 && sizeof(struct atom_hpd_int_record) <=
554 header->record_size)
555 return (struct atom_hpd_int_record *) header;
556
557 offset += header->record_size;
558 }
559
560 return NULL;
561 }
562
bios_parser_get_hpd_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_hpd_info * info)563 static enum bp_result bios_parser_get_hpd_info(
564 struct dc_bios *dcb,
565 struct graphics_object_id id,
566 struct graphics_object_hpd_info *info)
567 {
568 struct bios_parser *bp = BP_FROM_DCB(dcb);
569 struct atom_display_object_path_v2 *object;
570 struct atom_display_object_path_v3 *object_path_v3;
571 struct atom_hpd_int_record *record = NULL;
572
573 if (!info)
574 return BP_RESULT_BADINPUT;
575
576 switch (bp->object_info_tbl.revision.minor) {
577 case 4:
578 default:
579 object = get_bios_object(bp, id);
580
581 if (!object)
582 return BP_RESULT_BADINPUT;
583
584 record = get_hpd_record(bp, object);
585
586 break;
587 case 5:
588 object_path_v3 = get_bios_object_from_path_v3(bp, id);
589
590 if (!object_path_v3)
591 return BP_RESULT_BADINPUT;
592
593 record = get_hpd_record_for_path_v3(bp, object_path_v3);
594 break;
595 }
596
597 if (record != NULL) {
598 info->hpd_int_gpio_uid = record->pin_id;
599 info->hpd_active = record->plugin_pin_state;
600 return BP_RESULT_OK;
601 }
602
603 return BP_RESULT_NORECORD;
604 }
605
get_hpd_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)606 static struct atom_hpd_int_record *get_hpd_record(
607 struct bios_parser *bp,
608 struct atom_display_object_path_v2 *object)
609 {
610 struct atom_common_record_header *header;
611 uint32_t offset;
612
613 if (!object) {
614 BREAK_TO_DEBUGGER(); /* Invalid object */
615 return NULL;
616 }
617
618 offset = le16_to_cpu(object->disp_recordoffset)
619 + bp->object_info_tbl_offset;
620
621 for (;;) {
622 header = GET_IMAGE(struct atom_common_record_header, offset);
623
624 if (!header)
625 return NULL;
626
627 if (header->record_type == LAST_RECORD_TYPE ||
628 !header->record_size)
629 break;
630
631 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
632 && sizeof(struct atom_hpd_int_record) <=
633 header->record_size)
634 return (struct atom_hpd_int_record *) header;
635
636 offset += header->record_size;
637 }
638
639 return NULL;
640 }
641
642 /**
643 * bios_parser_get_gpio_pin_info
644 * Get GpioPin information of input gpio id
645 *
646 * @dcb: pointer to the DC BIOS
647 * @gpio_id: GPIO ID
648 * @info: GpioPin information structure
649 * return: Bios parser result code
650 * note:
651 * to get the GPIO PIN INFO, we need:
652 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
653 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
654 * to get the registerA offset/mask
655 */
bios_parser_get_gpio_pin_info(struct dc_bios * dcb,uint32_t gpio_id,struct gpio_pin_info * info)656 static enum bp_result bios_parser_get_gpio_pin_info(
657 struct dc_bios *dcb,
658 uint32_t gpio_id,
659 struct gpio_pin_info *info)
660 {
661 struct bios_parser *bp = BP_FROM_DCB(dcb);
662 struct atom_gpio_pin_lut_v2_1 *header;
663 uint32_t count = 0;
664 uint32_t i = 0;
665
666 if (!DATA_TABLES(gpio_pin_lut))
667 return BP_RESULT_BADBIOSTABLE;
668
669 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
670 DATA_TABLES(gpio_pin_lut));
671 if (!header)
672 return BP_RESULT_BADBIOSTABLE;
673
674 if (sizeof(struct atom_common_table_header) +
675 sizeof(struct atom_gpio_pin_assignment)
676 > le16_to_cpu(header->table_header.structuresize))
677 return BP_RESULT_BADBIOSTABLE;
678
679 if (header->table_header.content_revision != 1)
680 return BP_RESULT_UNSUPPORTED;
681
682 /* Temporary hard code gpio pin info */
683 count = (le16_to_cpu(header->table_header.structuresize)
684 - sizeof(struct atom_common_table_header))
685 / sizeof(struct atom_gpio_pin_assignment);
686 for (i = 0; i < count; ++i) {
687 if (header->gpio_pin[i].gpio_id != gpio_id)
688 continue;
689
690 info->offset =
691 (uint32_t) le16_to_cpu(
692 header->gpio_pin[i].data_a_reg_index);
693 info->offset_y = info->offset + 2;
694 info->offset_en = info->offset + 1;
695 info->offset_mask = info->offset - 1;
696
697 info->mask = (uint32_t) (1 <<
698 header->gpio_pin[i].gpio_bitshift);
699 info->mask_y = info->mask + 2;
700 info->mask_en = info->mask + 1;
701 info->mask_mask = info->mask - 1;
702
703 return BP_RESULT_OK;
704 }
705
706 return BP_RESULT_NORECORD;
707 }
708
device_type_from_device_id(uint16_t device_id)709 static struct device_id device_type_from_device_id(uint16_t device_id)
710 {
711
712 struct device_id result_device_id;
713
714 result_device_id.raw_device_tag = device_id;
715
716 switch (device_id) {
717 case ATOM_DISPLAY_LCD1_SUPPORT:
718 result_device_id.device_type = DEVICE_TYPE_LCD;
719 result_device_id.enum_id = 1;
720 break;
721
722 case ATOM_DISPLAY_LCD2_SUPPORT:
723 result_device_id.device_type = DEVICE_TYPE_LCD;
724 result_device_id.enum_id = 2;
725 break;
726
727 case ATOM_DISPLAY_DFP1_SUPPORT:
728 result_device_id.device_type = DEVICE_TYPE_DFP;
729 result_device_id.enum_id = 1;
730 break;
731
732 case ATOM_DISPLAY_DFP2_SUPPORT:
733 result_device_id.device_type = DEVICE_TYPE_DFP;
734 result_device_id.enum_id = 2;
735 break;
736
737 case ATOM_DISPLAY_DFP3_SUPPORT:
738 result_device_id.device_type = DEVICE_TYPE_DFP;
739 result_device_id.enum_id = 3;
740 break;
741
742 case ATOM_DISPLAY_DFP4_SUPPORT:
743 result_device_id.device_type = DEVICE_TYPE_DFP;
744 result_device_id.enum_id = 4;
745 break;
746
747 case ATOM_DISPLAY_DFP5_SUPPORT:
748 result_device_id.device_type = DEVICE_TYPE_DFP;
749 result_device_id.enum_id = 5;
750 break;
751
752 case ATOM_DISPLAY_DFP6_SUPPORT:
753 result_device_id.device_type = DEVICE_TYPE_DFP;
754 result_device_id.enum_id = 6;
755 break;
756
757 default:
758 BREAK_TO_DEBUGGER(); /* Invalid device Id */
759 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
760 result_device_id.enum_id = 0;
761 }
762 return result_device_id;
763 }
764
bios_parser_get_device_tag(struct dc_bios * dcb,struct graphics_object_id connector_object_id,uint32_t device_tag_index,struct connector_device_tag_info * info)765 static enum bp_result bios_parser_get_device_tag(
766 struct dc_bios *dcb,
767 struct graphics_object_id connector_object_id,
768 uint32_t device_tag_index,
769 struct connector_device_tag_info *info)
770 {
771 struct bios_parser *bp = BP_FROM_DCB(dcb);
772 struct atom_display_object_path_v2 *object;
773
774 struct atom_display_object_path_v3 *object_path_v3;
775
776
777 if (!info)
778 return BP_RESULT_BADINPUT;
779
780 switch (bp->object_info_tbl.revision.minor) {
781 case 4:
782 default:
783 /* getBiosObject will return MXM object */
784 object = get_bios_object(bp, connector_object_id);
785
786 if (!object) {
787 BREAK_TO_DEBUGGER(); /* Invalid object id */
788 return BP_RESULT_BADINPUT;
789 }
790
791 info->acpi_device = 0; /* BIOS no longer provides this */
792 info->dev_id = device_type_from_device_id(object->device_tag);
793 break;
794 case 5:
795 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
796
797 if (!object_path_v3) {
798 BREAK_TO_DEBUGGER(); /* Invalid object id */
799 return BP_RESULT_BADINPUT;
800 }
801 info->acpi_device = 0; /* BIOS no longer provides this */
802 info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
803 break;
804 }
805
806 return BP_RESULT_OK;
807 }
808
get_ss_info_v4_1(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)809 static enum bp_result get_ss_info_v4_1(
810 struct bios_parser *bp,
811 uint32_t id,
812 uint32_t index,
813 struct spread_spectrum_info *ss_info)
814 {
815 enum bp_result result = BP_RESULT_OK;
816 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
817 struct atom_smu_info_v3_3 *smu_info = NULL;
818
819 if (!ss_info)
820 return BP_RESULT_BADINPUT;
821
822 if (!DATA_TABLES(dce_info))
823 return BP_RESULT_BADBIOSTABLE;
824
825 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
826 DATA_TABLES(dce_info));
827 if (!disp_cntl_tbl)
828 return BP_RESULT_BADBIOSTABLE;
829
830
831 ss_info->type.STEP_AND_DELAY_INFO = false;
832 ss_info->spread_percentage_divider = 1000;
833 /* BIOS no longer uses target clock. Always enable for now */
834 ss_info->target_clock_range = 0xffffffff;
835
836 switch (id) {
837 case AS_SIGNAL_TYPE_DVI:
838 ss_info->spread_spectrum_percentage =
839 disp_cntl_tbl->dvi_ss_percentage;
840 ss_info->spread_spectrum_range =
841 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
842 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
843 ss_info->type.CENTER_MODE = true;
844
845 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
846 break;
847 case AS_SIGNAL_TYPE_HDMI:
848 ss_info->spread_spectrum_percentage =
849 disp_cntl_tbl->hdmi_ss_percentage;
850 ss_info->spread_spectrum_range =
851 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
852 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
853 ss_info->type.CENTER_MODE = true;
854
855 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
856 break;
857 /* TODO LVDS not support anymore? */
858 case AS_SIGNAL_TYPE_DISPLAY_PORT:
859 ss_info->spread_spectrum_percentage =
860 disp_cntl_tbl->dp_ss_percentage;
861 ss_info->spread_spectrum_range =
862 disp_cntl_tbl->dp_ss_rate_10hz * 10;
863 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
864 ss_info->type.CENTER_MODE = true;
865
866 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
867 break;
868 case AS_SIGNAL_TYPE_GPU_PLL:
869 /* atom_firmware: DAL only get data from dce_info table.
870 * if data within smu_info is needed for DAL, VBIOS should
871 * copy it into dce_info
872 */
873 result = BP_RESULT_UNSUPPORTED;
874 break;
875 case AS_SIGNAL_TYPE_XGMI:
876 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
877 DATA_TABLES(smu_info));
878 if (!smu_info)
879 return BP_RESULT_BADBIOSTABLE;
880 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
881 ss_info->spread_spectrum_percentage =
882 smu_info->waflclk_ss_percentage;
883 ss_info->spread_spectrum_range =
884 smu_info->gpuclk_ss_rate_10hz * 10;
885 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
886 ss_info->type.CENTER_MODE = true;
887
888 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
889 break;
890 default:
891 result = BP_RESULT_UNSUPPORTED;
892 }
893
894 return result;
895 }
896
get_ss_info_v4_2(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)897 static enum bp_result get_ss_info_v4_2(
898 struct bios_parser *bp,
899 uint32_t id,
900 uint32_t index,
901 struct spread_spectrum_info *ss_info)
902 {
903 enum bp_result result = BP_RESULT_OK;
904 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
905 struct atom_smu_info_v3_1 *smu_info = NULL;
906
907 if (!ss_info)
908 return BP_RESULT_BADINPUT;
909
910 if (!DATA_TABLES(dce_info))
911 return BP_RESULT_BADBIOSTABLE;
912
913 if (!DATA_TABLES(smu_info))
914 return BP_RESULT_BADBIOSTABLE;
915
916 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
917 DATA_TABLES(dce_info));
918 if (!disp_cntl_tbl)
919 return BP_RESULT_BADBIOSTABLE;
920
921 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
922 if (!smu_info)
923 return BP_RESULT_BADBIOSTABLE;
924
925 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
926 ss_info->type.STEP_AND_DELAY_INFO = false;
927 ss_info->spread_percentage_divider = 1000;
928 /* BIOS no longer uses target clock. Always enable for now */
929 ss_info->target_clock_range = 0xffffffff;
930
931 switch (id) {
932 case AS_SIGNAL_TYPE_DVI:
933 ss_info->spread_spectrum_percentage =
934 disp_cntl_tbl->dvi_ss_percentage;
935 ss_info->spread_spectrum_range =
936 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
937 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
938 ss_info->type.CENTER_MODE = true;
939
940 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
941 break;
942 case AS_SIGNAL_TYPE_HDMI:
943 ss_info->spread_spectrum_percentage =
944 disp_cntl_tbl->hdmi_ss_percentage;
945 ss_info->spread_spectrum_range =
946 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
947 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
948 ss_info->type.CENTER_MODE = true;
949
950 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
951 break;
952 /* TODO LVDS not support anymore? */
953 case AS_SIGNAL_TYPE_DISPLAY_PORT:
954 ss_info->spread_spectrum_percentage =
955 smu_info->gpuclk_ss_percentage;
956 ss_info->spread_spectrum_range =
957 smu_info->gpuclk_ss_rate_10hz * 10;
958 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
959 ss_info->type.CENTER_MODE = true;
960
961 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
962 break;
963 case AS_SIGNAL_TYPE_GPU_PLL:
964 /* atom_firmware: DAL only get data from dce_info table.
965 * if data within smu_info is needed for DAL, VBIOS should
966 * copy it into dce_info
967 */
968 result = BP_RESULT_UNSUPPORTED;
969 break;
970 default:
971 result = BP_RESULT_UNSUPPORTED;
972 }
973
974 return result;
975 }
976
get_ss_info_v4_5(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)977 static enum bp_result get_ss_info_v4_5(
978 struct bios_parser *bp,
979 uint32_t id,
980 uint32_t index,
981 struct spread_spectrum_info *ss_info)
982 {
983 enum bp_result result = BP_RESULT_OK;
984 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
985
986 if (!ss_info)
987 return BP_RESULT_BADINPUT;
988
989 if (!DATA_TABLES(dce_info))
990 return BP_RESULT_BADBIOSTABLE;
991
992 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
993 DATA_TABLES(dce_info));
994 if (!disp_cntl_tbl)
995 return BP_RESULT_BADBIOSTABLE;
996
997 ss_info->type.STEP_AND_DELAY_INFO = false;
998 ss_info->spread_percentage_divider = 1000;
999 /* BIOS no longer uses target clock. Always enable for now */
1000 ss_info->target_clock_range = 0xffffffff;
1001
1002 switch (id) {
1003 case AS_SIGNAL_TYPE_DVI:
1004 ss_info->spread_spectrum_percentage =
1005 disp_cntl_tbl->dvi_ss_percentage;
1006 ss_info->spread_spectrum_range =
1007 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
1008 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1009 ss_info->type.CENTER_MODE = true;
1010
1011 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1012 break;
1013 case AS_SIGNAL_TYPE_HDMI:
1014 ss_info->spread_spectrum_percentage =
1015 disp_cntl_tbl->hdmi_ss_percentage;
1016 ss_info->spread_spectrum_range =
1017 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
1018 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1019 ss_info->type.CENTER_MODE = true;
1020
1021 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1022 break;
1023 case AS_SIGNAL_TYPE_DISPLAY_PORT:
1024 ss_info->spread_spectrum_percentage =
1025 disp_cntl_tbl->dp_ss_percentage;
1026 ss_info->spread_spectrum_range =
1027 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1028 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1029 ss_info->type.CENTER_MODE = true;
1030
1031 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1032 break;
1033 case AS_SIGNAL_TYPE_GPU_PLL:
1034 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
1035 * SMU Display PLL supposed to be without spread.
1036 * Better place for it would be in atom_display_controller_info_v4_5 table.
1037 */
1038 result = BP_RESULT_UNSUPPORTED;
1039 break;
1040 default:
1041 result = BP_RESULT_UNSUPPORTED;
1042 break;
1043 }
1044
1045 return result;
1046 }
1047
1048 /**
1049 * bios_parser_get_spread_spectrum_info
1050 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
1051 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
1052 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
1053 * ver 3.1,
1054 * there is only one entry for each signal /ss id. However, there is
1055 * no planning of supporting multiple spread Sprectum entry for EverGreen
1056 * @dcb: pointer to the DC BIOS
1057 * @signal: ASSignalType to be converted to info index
1058 * @index: number of entries that match the converted info index
1059 * @ss_info: sprectrum information structure,
1060 * return: Bios parser result code
1061 */
bios_parser_get_spread_spectrum_info(struct dc_bios * dcb,enum as_signal_type signal,uint32_t index,struct spread_spectrum_info * ss_info)1062 static enum bp_result bios_parser_get_spread_spectrum_info(
1063 struct dc_bios *dcb,
1064 enum as_signal_type signal,
1065 uint32_t index,
1066 struct spread_spectrum_info *ss_info)
1067 {
1068 struct bios_parser *bp = BP_FROM_DCB(dcb);
1069 enum bp_result result = BP_RESULT_UNSUPPORTED;
1070 struct atom_common_table_header *header;
1071 struct atom_data_revision tbl_revision;
1072
1073 if (!ss_info) /* check for bad input */
1074 return BP_RESULT_BADINPUT;
1075
1076 if (!DATA_TABLES(dce_info))
1077 return BP_RESULT_UNSUPPORTED;
1078
1079 header = GET_IMAGE(struct atom_common_table_header,
1080 DATA_TABLES(dce_info));
1081 get_atom_data_table_revision(header, &tbl_revision);
1082
1083 switch (tbl_revision.major) {
1084 case 4:
1085 switch (tbl_revision.minor) {
1086 case 1:
1087 return get_ss_info_v4_1(bp, signal, index, ss_info);
1088 case 2:
1089 case 3:
1090 case 4:
1091 return get_ss_info_v4_2(bp, signal, index, ss_info);
1092 case 5:
1093 return get_ss_info_v4_5(bp, signal, index, ss_info);
1094
1095 default:
1096 ASSERT(0);
1097 break;
1098 }
1099 break;
1100 default:
1101 break;
1102 }
1103 /* there can not be more then one entry for SS Info table */
1104 return result;
1105 }
1106
get_soc_bb_info_v4_4(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1107 static enum bp_result get_soc_bb_info_v4_4(
1108 struct bios_parser *bp,
1109 struct bp_soc_bb_info *soc_bb_info)
1110 {
1111 enum bp_result result = BP_RESULT_OK;
1112 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1113
1114 if (!soc_bb_info)
1115 return BP_RESULT_BADINPUT;
1116
1117 if (!DATA_TABLES(dce_info))
1118 return BP_RESULT_BADBIOSTABLE;
1119
1120 if (!DATA_TABLES(smu_info))
1121 return BP_RESULT_BADBIOSTABLE;
1122
1123 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1124 DATA_TABLES(dce_info));
1125 if (!disp_cntl_tbl)
1126 return BP_RESULT_BADBIOSTABLE;
1127
1128 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1129 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1130 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1131
1132 return result;
1133 }
1134
get_soc_bb_info_v4_5(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1135 static enum bp_result get_soc_bb_info_v4_5(
1136 struct bios_parser *bp,
1137 struct bp_soc_bb_info *soc_bb_info)
1138 {
1139 enum bp_result result = BP_RESULT_OK;
1140 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1141
1142 if (!soc_bb_info)
1143 return BP_RESULT_BADINPUT;
1144
1145 if (!DATA_TABLES(dce_info))
1146 return BP_RESULT_BADBIOSTABLE;
1147
1148 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1149 DATA_TABLES(dce_info));
1150 if (!disp_cntl_tbl)
1151 return BP_RESULT_BADBIOSTABLE;
1152
1153 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1154 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1155 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1156
1157 return result;
1158 }
1159
bios_parser_get_soc_bb_info(struct dc_bios * dcb,struct bp_soc_bb_info * soc_bb_info)1160 static enum bp_result bios_parser_get_soc_bb_info(
1161 struct dc_bios *dcb,
1162 struct bp_soc_bb_info *soc_bb_info)
1163 {
1164 struct bios_parser *bp = BP_FROM_DCB(dcb);
1165 enum bp_result result = BP_RESULT_UNSUPPORTED;
1166 struct atom_common_table_header *header;
1167 struct atom_data_revision tbl_revision;
1168
1169 if (!soc_bb_info) /* check for bad input */
1170 return BP_RESULT_BADINPUT;
1171
1172 if (!DATA_TABLES(dce_info))
1173 return BP_RESULT_UNSUPPORTED;
1174
1175 header = GET_IMAGE(struct atom_common_table_header,
1176 DATA_TABLES(dce_info));
1177 get_atom_data_table_revision(header, &tbl_revision);
1178
1179 switch (tbl_revision.major) {
1180 case 4:
1181 switch (tbl_revision.minor) {
1182 case 1:
1183 case 2:
1184 case 3:
1185 break;
1186 case 4:
1187 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
1188 break;
1189 case 5:
1190 result = get_soc_bb_info_v4_5(bp, soc_bb_info);
1191 break;
1192 default:
1193 break;
1194 }
1195 break;
1196 default:
1197 break;
1198 }
1199
1200 return result;
1201 }
1202
get_disp_caps_v4_1(struct bios_parser * bp,uint8_t * dce_caps)1203 static enum bp_result get_disp_caps_v4_1(
1204 struct bios_parser *bp,
1205 uint8_t *dce_caps)
1206 {
1207 enum bp_result result = BP_RESULT_OK;
1208 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
1209
1210 if (!dce_caps)
1211 return BP_RESULT_BADINPUT;
1212
1213 if (!DATA_TABLES(dce_info))
1214 return BP_RESULT_BADBIOSTABLE;
1215
1216 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
1217 DATA_TABLES(dce_info));
1218
1219 if (!disp_cntl_tbl)
1220 return BP_RESULT_BADBIOSTABLE;
1221
1222 *dce_caps = disp_cntl_tbl->display_caps;
1223
1224 return result;
1225 }
1226
get_disp_caps_v4_2(struct bios_parser * bp,uint8_t * dce_caps)1227 static enum bp_result get_disp_caps_v4_2(
1228 struct bios_parser *bp,
1229 uint8_t *dce_caps)
1230 {
1231 enum bp_result result = BP_RESULT_OK;
1232 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
1233
1234 if (!dce_caps)
1235 return BP_RESULT_BADINPUT;
1236
1237 if (!DATA_TABLES(dce_info))
1238 return BP_RESULT_BADBIOSTABLE;
1239
1240 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
1241 DATA_TABLES(dce_info));
1242
1243 if (!disp_cntl_tbl)
1244 return BP_RESULT_BADBIOSTABLE;
1245
1246 *dce_caps = disp_cntl_tbl->display_caps;
1247
1248 return result;
1249 }
1250
get_disp_caps_v4_3(struct bios_parser * bp,uint8_t * dce_caps)1251 static enum bp_result get_disp_caps_v4_3(
1252 struct bios_parser *bp,
1253 uint8_t *dce_caps)
1254 {
1255 enum bp_result result = BP_RESULT_OK;
1256 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
1257
1258 if (!dce_caps)
1259 return BP_RESULT_BADINPUT;
1260
1261 if (!DATA_TABLES(dce_info))
1262 return BP_RESULT_BADBIOSTABLE;
1263
1264 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
1265 DATA_TABLES(dce_info));
1266
1267 if (!disp_cntl_tbl)
1268 return BP_RESULT_BADBIOSTABLE;
1269
1270 *dce_caps = disp_cntl_tbl->display_caps;
1271
1272 return result;
1273 }
1274
get_disp_caps_v4_4(struct bios_parser * bp,uint8_t * dce_caps)1275 static enum bp_result get_disp_caps_v4_4(
1276 struct bios_parser *bp,
1277 uint8_t *dce_caps)
1278 {
1279 enum bp_result result = BP_RESULT_OK;
1280 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1281
1282 if (!dce_caps)
1283 return BP_RESULT_BADINPUT;
1284
1285 if (!DATA_TABLES(dce_info))
1286 return BP_RESULT_BADBIOSTABLE;
1287
1288 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1289 DATA_TABLES(dce_info));
1290
1291 if (!disp_cntl_tbl)
1292 return BP_RESULT_BADBIOSTABLE;
1293
1294 *dce_caps = disp_cntl_tbl->display_caps;
1295
1296 return result;
1297 }
1298
get_disp_caps_v4_5(struct bios_parser * bp,uint8_t * dce_caps)1299 static enum bp_result get_disp_caps_v4_5(
1300 struct bios_parser *bp,
1301 uint8_t *dce_caps)
1302 {
1303 enum bp_result result = BP_RESULT_OK;
1304 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1305
1306 if (!dce_caps)
1307 return BP_RESULT_BADINPUT;
1308
1309 if (!DATA_TABLES(dce_info))
1310 return BP_RESULT_BADBIOSTABLE;
1311
1312 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1313 DATA_TABLES(dce_info));
1314
1315 if (!disp_cntl_tbl)
1316 return BP_RESULT_BADBIOSTABLE;
1317
1318 *dce_caps = disp_cntl_tbl->display_caps;
1319
1320 return result;
1321 }
1322
bios_parser_get_lttpr_interop(struct dc_bios * dcb,uint8_t * dce_caps)1323 static enum bp_result bios_parser_get_lttpr_interop(
1324 struct dc_bios *dcb,
1325 uint8_t *dce_caps)
1326 {
1327 struct bios_parser *bp = BP_FROM_DCB(dcb);
1328 enum bp_result result = BP_RESULT_UNSUPPORTED;
1329 struct atom_common_table_header *header;
1330 struct atom_data_revision tbl_revision;
1331
1332 if (!DATA_TABLES(dce_info))
1333 return BP_RESULT_UNSUPPORTED;
1334
1335 header = GET_IMAGE(struct atom_common_table_header,
1336 DATA_TABLES(dce_info));
1337 get_atom_data_table_revision(header, &tbl_revision);
1338 switch (tbl_revision.major) {
1339 case 4:
1340 switch (tbl_revision.minor) {
1341 case 1:
1342 result = get_disp_caps_v4_1(bp, dce_caps);
1343 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1344 break;
1345 case 2:
1346 result = get_disp_caps_v4_2(bp, dce_caps);
1347 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1348 break;
1349 case 3:
1350 result = get_disp_caps_v4_3(bp, dce_caps);
1351 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1352 break;
1353 case 4:
1354 result = get_disp_caps_v4_4(bp, dce_caps);
1355 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1356 break;
1357 case 5:
1358 result = get_disp_caps_v4_5(bp, dce_caps);
1359 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1360 break;
1361
1362 default:
1363 break;
1364 }
1365 break;
1366 default:
1367 break;
1368 }
1369 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1370 return result;
1371 }
1372
bios_parser_get_lttpr_caps(struct dc_bios * dcb,uint8_t * dce_caps)1373 static enum bp_result bios_parser_get_lttpr_caps(
1374 struct dc_bios *dcb,
1375 uint8_t *dce_caps)
1376 {
1377 struct bios_parser *bp = BP_FROM_DCB(dcb);
1378 enum bp_result result = BP_RESULT_UNSUPPORTED;
1379 struct atom_common_table_header *header;
1380 struct atom_data_revision tbl_revision;
1381
1382 if (!DATA_TABLES(dce_info))
1383 return BP_RESULT_UNSUPPORTED;
1384
1385 *dce_caps = 0;
1386 header = GET_IMAGE(struct atom_common_table_header,
1387 DATA_TABLES(dce_info));
1388 get_atom_data_table_revision(header, &tbl_revision);
1389 switch (tbl_revision.major) {
1390 case 4:
1391 switch (tbl_revision.minor) {
1392 case 1:
1393 result = get_disp_caps_v4_1(bp, dce_caps);
1394 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1395 break;
1396 case 2:
1397 result = get_disp_caps_v4_2(bp, dce_caps);
1398 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1399 break;
1400 case 3:
1401 result = get_disp_caps_v4_3(bp, dce_caps);
1402 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1403 break;
1404 case 4:
1405 result = get_disp_caps_v4_4(bp, dce_caps);
1406 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1407 break;
1408 case 5:
1409 result = get_disp_caps_v4_5(bp, dce_caps);
1410 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1411 break;
1412 default:
1413 break;
1414 }
1415 break;
1416 default:
1417 break;
1418 }
1419 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1420 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {
1421 *dce_caps = 1;
1422 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled");
1423 }
1424 return result;
1425 }
1426
get_embedded_panel_info_v2_1(struct bios_parser * bp,struct embedded_panel_info * info)1427 static enum bp_result get_embedded_panel_info_v2_1(
1428 struct bios_parser *bp,
1429 struct embedded_panel_info *info)
1430 {
1431 struct lcd_info_v2_1 *lvds;
1432
1433 if (!info)
1434 return BP_RESULT_BADINPUT;
1435
1436 if (!DATA_TABLES(lcd_info))
1437 return BP_RESULT_UNSUPPORTED;
1438
1439 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
1440
1441 if (!lvds)
1442 return BP_RESULT_BADBIOSTABLE;
1443
1444 /* TODO: previous vv1_3, should v2_1 */
1445 if (!((lvds->table_header.format_revision == 2)
1446 && (lvds->table_header.content_revision >= 1)))
1447 return BP_RESULT_UNSUPPORTED;
1448
1449 memset(info, 0, sizeof(struct embedded_panel_info));
1450
1451 /* We need to convert from 10KHz units into KHz units */
1452 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1453 /* usHActive does not include borders, according to VBIOS team */
1454 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
1455 /* usHBlanking_Time includes borders, so we should really be
1456 * subtractingborders duing this translation, but LVDS generally
1457 * doesn't have borders, so we should be okay leaving this as is for
1458 * now. May need to revisit if we ever have LVDS with borders
1459 */
1460 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1461 /* usVActive does not include borders, according to VBIOS team*/
1462 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
1463 /* usVBlanking_Time includes borders, so we should really be
1464 * subtracting borders duing this translation, but LVDS generally
1465 * doesn't have borders, so we should be okay leaving this as is for
1466 * now. May need to revisit if we ever have LVDS with borders
1467 */
1468 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1469 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1470 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
1471 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1472 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1473 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1474 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1475
1476 /* not provided by VBIOS */
1477 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1478
1479 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1480 & ATOM_HSYNC_POLARITY);
1481 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1482 & ATOM_VSYNC_POLARITY);
1483
1484 /* not provided by VBIOS */
1485 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1486
1487 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1488 & ATOM_H_REPLICATIONBY2);
1489 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1490 & ATOM_V_REPLICATIONBY2);
1491 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
1492 & ATOM_COMPOSITESYNC);
1493 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
1494
1495 /* not provided by VBIOS*/
1496 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1497 /* not provided by VBIOS*/
1498 info->ss_id = 0;
1499
1500 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
1501
1502 return BP_RESULT_OK;
1503 }
1504
bios_parser_get_embedded_panel_info(struct dc_bios * dcb,struct embedded_panel_info * info)1505 static enum bp_result bios_parser_get_embedded_panel_info(
1506 struct dc_bios *dcb,
1507 struct embedded_panel_info *info)
1508 {
1509 struct bios_parser
1510 *bp = BP_FROM_DCB(dcb);
1511 struct atom_common_table_header *header;
1512 struct atom_data_revision tbl_revision;
1513
1514 if (!DATA_TABLES(lcd_info))
1515 return BP_RESULT_FAILURE;
1516
1517 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1518
1519 if (!header)
1520 return BP_RESULT_BADBIOSTABLE;
1521
1522 get_atom_data_table_revision(header, &tbl_revision);
1523
1524 switch (tbl_revision.major) {
1525 case 2:
1526 switch (tbl_revision.minor) {
1527 case 1:
1528 return get_embedded_panel_info_v2_1(bp, info);
1529 default:
1530 break;
1531 }
1532 break;
1533 default:
1534 break;
1535 }
1536
1537 return BP_RESULT_FAILURE;
1538 }
1539
get_support_mask_for_device_id(struct device_id device_id)1540 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1541 {
1542 enum dal_device_type device_type = device_id.device_type;
1543 uint32_t enum_id = device_id.enum_id;
1544
1545 switch (device_type) {
1546 case DEVICE_TYPE_LCD:
1547 switch (enum_id) {
1548 case 1:
1549 return ATOM_DISPLAY_LCD1_SUPPORT;
1550 default:
1551 break;
1552 }
1553 break;
1554 case DEVICE_TYPE_DFP:
1555 switch (enum_id) {
1556 case 1:
1557 return ATOM_DISPLAY_DFP1_SUPPORT;
1558 case 2:
1559 return ATOM_DISPLAY_DFP2_SUPPORT;
1560 case 3:
1561 return ATOM_DISPLAY_DFP3_SUPPORT;
1562 case 4:
1563 return ATOM_DISPLAY_DFP4_SUPPORT;
1564 case 5:
1565 return ATOM_DISPLAY_DFP5_SUPPORT;
1566 case 6:
1567 return ATOM_DISPLAY_DFP6_SUPPORT;
1568 default:
1569 break;
1570 }
1571 break;
1572 default:
1573 break;
1574 }
1575
1576 /* Unidentified device ID, return empty support mask. */
1577 return 0;
1578 }
1579
bios_parser_is_device_id_supported(struct dc_bios * dcb,struct device_id id)1580 static bool bios_parser_is_device_id_supported(
1581 struct dc_bios *dcb,
1582 struct device_id id)
1583 {
1584 struct bios_parser *bp = BP_FROM_DCB(dcb);
1585
1586 uint32_t mask = get_support_mask_for_device_id(id);
1587
1588 switch (bp->object_info_tbl.revision.minor) {
1589 case 4:
1590 default:
1591 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
1592 break;
1593 case 5:
1594 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
1595 break;
1596 }
1597
1598 return false;
1599 }
1600
bios_parser_get_ss_entry_number(struct dc_bios * dcb,enum as_signal_type signal)1601 static uint32_t bios_parser_get_ss_entry_number(
1602 struct dc_bios *dcb,
1603 enum as_signal_type signal)
1604 {
1605 /* TODO: DAL2 atomfirmware implementation does not need this.
1606 * why DAL3 need this?
1607 */
1608 return 1;
1609 }
1610
bios_parser_transmitter_control(struct dc_bios * dcb,struct bp_transmitter_control * cntl)1611 static enum bp_result bios_parser_transmitter_control(
1612 struct dc_bios *dcb,
1613 struct bp_transmitter_control *cntl)
1614 {
1615 struct bios_parser *bp = BP_FROM_DCB(dcb);
1616
1617 if (!bp->cmd_tbl.transmitter_control)
1618 return BP_RESULT_FAILURE;
1619
1620 return bp->cmd_tbl.transmitter_control(bp, cntl);
1621 }
1622
bios_parser_encoder_control(struct dc_bios * dcb,struct bp_encoder_control * cntl)1623 static enum bp_result bios_parser_encoder_control(
1624 struct dc_bios *dcb,
1625 struct bp_encoder_control *cntl)
1626 {
1627 struct bios_parser *bp = BP_FROM_DCB(dcb);
1628
1629 if (!bp->cmd_tbl.dig_encoder_control)
1630 return BP_RESULT_FAILURE;
1631
1632 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1633 }
1634
bios_parser_set_pixel_clock(struct dc_bios * dcb,struct bp_pixel_clock_parameters * bp_params)1635 static enum bp_result bios_parser_set_pixel_clock(
1636 struct dc_bios *dcb,
1637 struct bp_pixel_clock_parameters *bp_params)
1638 {
1639 struct bios_parser *bp = BP_FROM_DCB(dcb);
1640
1641 if (!bp->cmd_tbl.set_pixel_clock)
1642 return BP_RESULT_FAILURE;
1643
1644 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1645 }
1646
bios_parser_set_dce_clock(struct dc_bios * dcb,struct bp_set_dce_clock_parameters * bp_params)1647 static enum bp_result bios_parser_set_dce_clock(
1648 struct dc_bios *dcb,
1649 struct bp_set_dce_clock_parameters *bp_params)
1650 {
1651 struct bios_parser *bp = BP_FROM_DCB(dcb);
1652
1653 if (!bp->cmd_tbl.set_dce_clock)
1654 return BP_RESULT_FAILURE;
1655
1656 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1657 }
1658
bios_parser_program_crtc_timing(struct dc_bios * dcb,struct bp_hw_crtc_timing_parameters * bp_params)1659 static enum bp_result bios_parser_program_crtc_timing(
1660 struct dc_bios *dcb,
1661 struct bp_hw_crtc_timing_parameters *bp_params)
1662 {
1663 struct bios_parser *bp = BP_FROM_DCB(dcb);
1664
1665 if (!bp->cmd_tbl.set_crtc_timing)
1666 return BP_RESULT_FAILURE;
1667
1668 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1669 }
1670
bios_parser_enable_crtc(struct dc_bios * dcb,enum controller_id id,bool enable)1671 static enum bp_result bios_parser_enable_crtc(
1672 struct dc_bios *dcb,
1673 enum controller_id id,
1674 bool enable)
1675 {
1676 struct bios_parser *bp = BP_FROM_DCB(dcb);
1677
1678 if (!bp->cmd_tbl.enable_crtc)
1679 return BP_RESULT_FAILURE;
1680
1681 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1682 }
1683
bios_parser_enable_disp_power_gating(struct dc_bios * dcb,enum controller_id controller_id,enum bp_pipe_control_action action)1684 static enum bp_result bios_parser_enable_disp_power_gating(
1685 struct dc_bios *dcb,
1686 enum controller_id controller_id,
1687 enum bp_pipe_control_action action)
1688 {
1689 struct bios_parser *bp = BP_FROM_DCB(dcb);
1690
1691 if (!bp->cmd_tbl.enable_disp_power_gating)
1692 return BP_RESULT_FAILURE;
1693
1694 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1695 action);
1696 }
1697
bios_parser_enable_lvtma_control(struct dc_bios * dcb,uint8_t uc_pwr_on,uint8_t panel_instance)1698 static enum bp_result bios_parser_enable_lvtma_control(
1699 struct dc_bios *dcb,
1700 uint8_t uc_pwr_on,
1701 uint8_t panel_instance)
1702 {
1703 struct bios_parser *bp = BP_FROM_DCB(dcb);
1704
1705 if (!bp->cmd_tbl.enable_lvtma_control)
1706 return BP_RESULT_FAILURE;
1707
1708 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance);
1709 }
1710
bios_parser_is_accelerated_mode(struct dc_bios * dcb)1711 static bool bios_parser_is_accelerated_mode(
1712 struct dc_bios *dcb)
1713 {
1714 return bios_is_accelerated_mode(dcb);
1715 }
1716
1717 /**
1718 * bios_parser_set_scratch_critical_state - update critical state bit
1719 * in VBIOS scratch register
1720 *
1721 * @dcb: pointer to the DC BIO
1722 * @state: set or reset state
1723 */
bios_parser_set_scratch_critical_state(struct dc_bios * dcb,bool state)1724 static void bios_parser_set_scratch_critical_state(
1725 struct dc_bios *dcb,
1726 bool state)
1727 {
1728 bios_set_scratch_critical_state(dcb, state);
1729 }
1730
1731 struct atom_dig_transmitter_info_header_v5_3 {
1732 struct atom_common_table_header table_header;
1733 uint16_t dpphy_hdmi_settings_offset;
1734 uint16_t dpphy_dvi_settings_offset;
1735 uint16_t dpphy_dp_setting_table_offset;
1736 uint16_t uniphy_xbar_settings_v2_table_offset;
1737 uint16_t dpphy_internal_reg_overide_offset;
1738 };
1739
bios_parser_get_firmware_info(struct dc_bios * dcb,struct dc_firmware_info * info)1740 static enum bp_result bios_parser_get_firmware_info(
1741 struct dc_bios *dcb,
1742 struct dc_firmware_info *info)
1743 {
1744 struct bios_parser *bp = BP_FROM_DCB(dcb);
1745 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
1746 struct atom_common_table_header *header;
1747
1748 struct atom_data_revision revision;
1749
1750 if (info && DATA_TABLES(firmwareinfo)) {
1751 header = GET_IMAGE(struct atom_common_table_header,
1752 DATA_TABLES(firmwareinfo));
1753 get_atom_data_table_revision(header, &revision);
1754 switch (revision.major) {
1755 case 3:
1756 switch (revision.minor) {
1757 case 1:
1758 result = get_firmware_info_v3_1(bp, info);
1759 break;
1760 case 2:
1761 case 3:
1762 result = get_firmware_info_v3_2(bp, info);
1763 break;
1764 case 4:
1765 result = get_firmware_info_v3_4(bp, info);
1766 break;
1767 default:
1768 break;
1769 }
1770 break;
1771 default:
1772 break;
1773 }
1774 }
1775
1776 return result;
1777 }
1778
get_firmware_info_v3_1(struct bios_parser * bp,struct dc_firmware_info * info)1779 static enum bp_result get_firmware_info_v3_1(
1780 struct bios_parser *bp,
1781 struct dc_firmware_info *info)
1782 {
1783 struct atom_firmware_info_v3_1 *firmware_info;
1784 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1785
1786 if (!info)
1787 return BP_RESULT_BADINPUT;
1788
1789 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1790 DATA_TABLES(firmwareinfo));
1791
1792 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1793 DATA_TABLES(dce_info));
1794
1795 if (!firmware_info || !dce_info)
1796 return BP_RESULT_BADBIOSTABLE;
1797
1798 memset(info, 0, sizeof(*info));
1799
1800 /* Pixel clock pll information. */
1801 /* We need to convert from 10KHz units into KHz units */
1802 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1803 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1804
1805 /* 27MHz for Vega10: */
1806 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1807
1808 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1809 if (info->pll_info.crystal_frequency == 0)
1810 info->pll_info.crystal_frequency = 27000;
1811 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1812 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1813 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1814
1815 /* Get GPU PLL VCO Clock */
1816
1817 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1818 /* VBIOS gives in 10KHz */
1819 info->smu_gpu_pll_output_freq =
1820 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1821 }
1822
1823 info->oem_i2c_present = false;
1824
1825 return BP_RESULT_OK;
1826 }
1827
get_firmware_info_v3_2(struct bios_parser * bp,struct dc_firmware_info * info)1828 static enum bp_result get_firmware_info_v3_2(
1829 struct bios_parser *bp,
1830 struct dc_firmware_info *info)
1831 {
1832 struct atom_firmware_info_v3_2 *firmware_info;
1833 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1834 struct atom_common_table_header *header;
1835 struct atom_data_revision revision;
1836 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1837 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1838
1839 if (!info)
1840 return BP_RESULT_BADINPUT;
1841
1842 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1843 DATA_TABLES(firmwareinfo));
1844
1845 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1846 DATA_TABLES(dce_info));
1847
1848 if (!firmware_info || !dce_info)
1849 return BP_RESULT_BADBIOSTABLE;
1850
1851 memset(info, 0, sizeof(*info));
1852
1853 header = GET_IMAGE(struct atom_common_table_header,
1854 DATA_TABLES(smu_info));
1855 get_atom_data_table_revision(header, &revision);
1856
1857 if (revision.minor == 2) {
1858 /* Vega12 */
1859 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1860 DATA_TABLES(smu_info));
1861 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage);
1862 if (!smu_info_v3_2)
1863 return BP_RESULT_BADBIOSTABLE;
1864
1865 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1866 } else if (revision.minor == 3) {
1867 /* Vega20 */
1868 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1869 DATA_TABLES(smu_info));
1870 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage);
1871 if (!smu_info_v3_3)
1872 return BP_RESULT_BADBIOSTABLE;
1873
1874 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1875 }
1876
1877 // We need to convert from 10KHz units into KHz units.
1878 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1879
1880 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1881 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1882 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1883 if (info->pll_info.crystal_frequency == 0) {
1884 if (revision.minor == 2)
1885 info->pll_info.crystal_frequency = 27000;
1886 else if (revision.minor == 3)
1887 info->pll_info.crystal_frequency = 100000;
1888 }
1889 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1890 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1891 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1892
1893 /* Get GPU PLL VCO Clock */
1894 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1895 if (revision.minor == 2)
1896 info->smu_gpu_pll_output_freq =
1897 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1898 else if (revision.minor == 3)
1899 info->smu_gpu_pll_output_freq =
1900 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1901 }
1902
1903 if (firmware_info->board_i2c_feature_id == 0x2) {
1904 info->oem_i2c_present = true;
1905 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1906 } else {
1907 info->oem_i2c_present = false;
1908 }
1909
1910 return BP_RESULT_OK;
1911 }
1912
get_firmware_info_v3_4(struct bios_parser * bp,struct dc_firmware_info * info)1913 static enum bp_result get_firmware_info_v3_4(
1914 struct bios_parser *bp,
1915 struct dc_firmware_info *info)
1916 {
1917 struct atom_firmware_info_v3_4 *firmware_info;
1918 struct atom_common_table_header *header;
1919 struct atom_data_revision revision;
1920 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
1921 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
1922
1923 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
1924 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
1925 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
1926
1927 if (!info)
1928 return BP_RESULT_BADINPUT;
1929
1930 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
1931 DATA_TABLES(firmwareinfo));
1932
1933 if (!firmware_info)
1934 return BP_RESULT_BADBIOSTABLE;
1935
1936 memset(info, 0, sizeof(*info));
1937
1938 header = GET_IMAGE(struct atom_common_table_header,
1939 DATA_TABLES(dce_info));
1940
1941 get_atom_data_table_revision(header, &revision);
1942
1943 switch (revision.major) {
1944 case 4:
1945 switch (revision.minor) {
1946 case 5:
1947 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
1948 DATA_TABLES(dce_info));
1949
1950 if (!dce_info_v4_5)
1951 return BP_RESULT_BADBIOSTABLE;
1952
1953 /* 100MHz expected */
1954 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
1955 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10;
1956 /* 50MHz expected */
1957 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
1958
1959 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
1960 break;
1961
1962 case 4:
1963 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
1964 DATA_TABLES(dce_info));
1965
1966 if (!dce_info_v4_4)
1967 return BP_RESULT_BADBIOSTABLE;
1968
1969 /* 100MHz expected */
1970 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
1971 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10;
1972 /* 50MHz expected */
1973 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
1974
1975 /* Get SMU Display PLL VCO Frequency in KHz*/
1976 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10;
1977 break;
1978
1979 default:
1980 /* should not come here, keep as backup, as was before */
1981 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
1982 DATA_TABLES(dce_info));
1983
1984 if (!dce_info_v4_1)
1985 return BP_RESULT_BADBIOSTABLE;
1986
1987 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
1988 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10;
1989 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
1990 break;
1991 }
1992 break;
1993
1994 default:
1995 ASSERT(0);
1996 break;
1997 }
1998
1999 header = GET_IMAGE(struct atom_common_table_header,
2000 DATA_TABLES(smu_info));
2001 get_atom_data_table_revision(header, &revision);
2002
2003 switch (revision.major) {
2004 case 3:
2005 switch (revision.minor) {
2006 case 5:
2007 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
2008 DATA_TABLES(smu_info));
2009
2010 if (!smu_info_v3_5)
2011 return BP_RESULT_BADBIOSTABLE;
2012 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage);
2013 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
2014 break;
2015
2016 default:
2017 break;
2018 }
2019 break;
2020
2021 case 4:
2022 switch (revision.minor) {
2023 case 0:
2024 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
2025 DATA_TABLES(smu_info));
2026
2027 if (!smu_info_v4_0)
2028 return BP_RESULT_BADBIOSTABLE;
2029
2030 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
2031 break;
2032
2033 default:
2034 break;
2035 }
2036 break;
2037
2038 default:
2039 break;
2040 }
2041
2042 // We need to convert from 10KHz units into KHz units.
2043 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
2044
2045 if (firmware_info->board_i2c_feature_id == 0x2) {
2046 info->oem_i2c_present = true;
2047 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2048 } else {
2049 info->oem_i2c_present = false;
2050 }
2051
2052 return BP_RESULT_OK;
2053 }
2054
bios_parser_get_encoder_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_encoder_cap_info * info)2055 static enum bp_result bios_parser_get_encoder_cap_info(
2056 struct dc_bios *dcb,
2057 struct graphics_object_id object_id,
2058 struct bp_encoder_cap_info *info)
2059 {
2060 struct bios_parser *bp = BP_FROM_DCB(dcb);
2061 struct atom_display_object_path_v2 *object;
2062 struct atom_encoder_caps_record *record = NULL;
2063
2064 if (!info)
2065 return BP_RESULT_BADINPUT;
2066
2067 #if defined(CONFIG_DRM_AMD_DC_DCN)
2068 /* encoder cap record not available in v1_5 */
2069 if (bp->object_info_tbl.revision.minor == 5)
2070 return BP_RESULT_NORECORD;
2071 #endif
2072
2073 object = get_bios_object(bp, object_id);
2074
2075 if (!object)
2076 return BP_RESULT_BADINPUT;
2077
2078 record = get_encoder_cap_record(bp, object);
2079 if (!record)
2080 return BP_RESULT_NORECORD;
2081 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id);
2082
2083 info->DP_HBR2_CAP = (record->encodercaps &
2084 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
2085 info->DP_HBR2_EN = (record->encodercaps &
2086 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
2087 info->DP_HBR3_EN = (record->encodercaps &
2088 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
2089 info->HDMI_6GB_EN = (record->encodercaps &
2090 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
2091 info->IS_DP2_CAPABLE = (record->encodercaps &
2092 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
2093 info->DP_UHBR10_EN = (record->encodercaps &
2094 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
2095 info->DP_UHBR13_5_EN = (record->encodercaps &
2096 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
2097 info->DP_UHBR20_EN = (record->encodercaps &
2098 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
2099 info->DP_IS_USB_C = (record->encodercaps &
2100 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
2101 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
2102
2103 return BP_RESULT_OK;
2104 }
2105
2106
get_encoder_cap_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2107 static struct atom_encoder_caps_record *get_encoder_cap_record(
2108 struct bios_parser *bp,
2109 struct atom_display_object_path_v2 *object)
2110 {
2111 struct atom_common_record_header *header;
2112 uint32_t offset;
2113
2114 if (!object) {
2115 BREAK_TO_DEBUGGER(); /* Invalid object */
2116 return NULL;
2117 }
2118
2119 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
2120
2121 for (;;) {
2122 header = GET_IMAGE(struct atom_common_record_header, offset);
2123
2124 if (!header)
2125 return NULL;
2126
2127 offset += header->record_size;
2128
2129 if (header->record_type == LAST_RECORD_TYPE ||
2130 !header->record_size)
2131 break;
2132
2133 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
2134 continue;
2135
2136 if (sizeof(struct atom_encoder_caps_record) <=
2137 header->record_size)
2138 return (struct atom_encoder_caps_record *)header;
2139 }
2140
2141 return NULL;
2142 }
2143
get_disp_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2144 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
2145 struct bios_parser *bp,
2146 struct atom_display_object_path_v2 *object)
2147 {
2148 struct atom_common_record_header *header;
2149 uint32_t offset;
2150
2151 if (!object) {
2152 BREAK_TO_DEBUGGER(); /* Invalid object */
2153 return NULL;
2154 }
2155
2156 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2157
2158 for (;;) {
2159 header = GET_IMAGE(struct atom_common_record_header, offset);
2160
2161 if (!header)
2162 return NULL;
2163
2164 offset += header->record_size;
2165
2166 if (header->record_type == LAST_RECORD_TYPE ||
2167 !header->record_size)
2168 break;
2169
2170 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
2171 continue;
2172
2173 if (sizeof(struct atom_disp_connector_caps_record) <=
2174 header->record_size)
2175 return (struct atom_disp_connector_caps_record *)header;
2176 }
2177
2178 return NULL;
2179 }
2180
get_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2181 static struct atom_connector_caps_record *get_connector_caps_record(
2182 struct bios_parser *bp,
2183 struct atom_display_object_path_v3 *object)
2184 {
2185 struct atom_common_record_header *header;
2186 uint32_t offset;
2187
2188 if (!object) {
2189 BREAK_TO_DEBUGGER(); /* Invalid object */
2190 return NULL;
2191 }
2192
2193 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2194
2195 for (;;) {
2196 header = GET_IMAGE(struct atom_common_record_header, offset);
2197
2198 if (!header)
2199 return NULL;
2200
2201 offset += header->record_size;
2202
2203 if (header->record_type == ATOM_RECORD_END_TYPE ||
2204 !header->record_size)
2205 break;
2206
2207 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
2208 continue;
2209
2210 if (sizeof(struct atom_connector_caps_record) <= header->record_size)
2211 return (struct atom_connector_caps_record *)header;
2212 }
2213
2214 return NULL;
2215 }
2216
bios_parser_get_disp_connector_caps_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_disp_connector_caps_info * info)2217 static enum bp_result bios_parser_get_disp_connector_caps_info(
2218 struct dc_bios *dcb,
2219 struct graphics_object_id object_id,
2220 struct bp_disp_connector_caps_info *info)
2221 {
2222 struct bios_parser *bp = BP_FROM_DCB(dcb);
2223 struct atom_display_object_path_v2 *object;
2224
2225 struct atom_display_object_path_v3 *object_path_v3;
2226 struct atom_connector_caps_record *record_path_v3;
2227
2228 struct atom_disp_connector_caps_record *record = NULL;
2229
2230 if (!info)
2231 return BP_RESULT_BADINPUT;
2232
2233 switch (bp->object_info_tbl.revision.minor) {
2234 case 4:
2235 default:
2236 object = get_bios_object(bp, object_id);
2237
2238 if (!object)
2239 return BP_RESULT_BADINPUT;
2240
2241 record = get_disp_connector_caps_record(bp, object);
2242 if (!record)
2243 return BP_RESULT_NORECORD;
2244
2245 info->INTERNAL_DISPLAY =
2246 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
2247 info->INTERNAL_DISPLAY_BL =
2248 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
2249 break;
2250 case 5:
2251 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2252
2253 if (!object_path_v3)
2254 return BP_RESULT_BADINPUT;
2255
2256 record_path_v3 = get_connector_caps_record(bp, object_path_v3);
2257 if (!record_path_v3)
2258 return BP_RESULT_NORECORD;
2259
2260 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
2261 ? 1 : 0;
2262 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
2263 ? 1 : 0;
2264 break;
2265 }
2266
2267 return BP_RESULT_OK;
2268 }
2269
get_connector_speed_cap_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2270 static struct atom_connector_speed_record *get_connector_speed_cap_record(
2271 struct bios_parser *bp,
2272 struct atom_display_object_path_v3 *object)
2273 {
2274 struct atom_common_record_header *header;
2275 uint32_t offset;
2276
2277 if (!object) {
2278 BREAK_TO_DEBUGGER(); /* Invalid object */
2279 return NULL;
2280 }
2281
2282 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2283
2284 for (;;) {
2285 header = GET_IMAGE(struct atom_common_record_header, offset);
2286
2287 if (!header)
2288 return NULL;
2289
2290 offset += header->record_size;
2291
2292 if (header->record_type == ATOM_RECORD_END_TYPE ||
2293 !header->record_size)
2294 break;
2295
2296 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
2297 continue;
2298
2299 if (sizeof(struct atom_connector_speed_record) <= header->record_size)
2300 return (struct atom_connector_speed_record *)header;
2301 }
2302
2303 return NULL;
2304 }
2305
bios_parser_get_connector_speed_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_connector_speed_cap_info * info)2306 static enum bp_result bios_parser_get_connector_speed_cap_info(
2307 struct dc_bios *dcb,
2308 struct graphics_object_id object_id,
2309 struct bp_connector_speed_cap_info *info)
2310 {
2311 struct bios_parser *bp = BP_FROM_DCB(dcb);
2312 struct atom_display_object_path_v3 *object_path_v3;
2313 //struct atom_connector_speed_record *record = NULL;
2314 struct atom_connector_speed_record *record;
2315
2316 if (!info)
2317 return BP_RESULT_BADINPUT;
2318
2319 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2320
2321 if (!object_path_v3)
2322 return BP_RESULT_BADINPUT;
2323
2324 record = get_connector_speed_cap_record(bp, object_path_v3);
2325 if (!record)
2326 return BP_RESULT_NORECORD;
2327
2328 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
2329 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
2330 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
2331 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
2332 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
2333 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
2334 return BP_RESULT_OK;
2335 }
2336
get_vram_info_v23(struct bios_parser * bp,struct dc_vram_info * info)2337 static enum bp_result get_vram_info_v23(
2338 struct bios_parser *bp,
2339 struct dc_vram_info *info)
2340 {
2341 struct atom_vram_info_header_v2_3 *info_v23;
2342 static enum bp_result result = BP_RESULT_OK;
2343
2344 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
2345 DATA_TABLES(vram_info));
2346
2347 if (info_v23 == NULL)
2348 return BP_RESULT_BADBIOSTABLE;
2349
2350 info->num_chans = info_v23->vram_module[0].channel_num;
2351 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2352
2353 return result;
2354 }
2355
get_vram_info_v24(struct bios_parser * bp,struct dc_vram_info * info)2356 static enum bp_result get_vram_info_v24(
2357 struct bios_parser *bp,
2358 struct dc_vram_info *info)
2359 {
2360 struct atom_vram_info_header_v2_4 *info_v24;
2361 static enum bp_result result = BP_RESULT_OK;
2362
2363 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
2364 DATA_TABLES(vram_info));
2365
2366 if (info_v24 == NULL)
2367 return BP_RESULT_BADBIOSTABLE;
2368
2369 info->num_chans = info_v24->vram_module[0].channel_num;
2370 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
2371
2372 return result;
2373 }
2374
get_vram_info_v25(struct bios_parser * bp,struct dc_vram_info * info)2375 static enum bp_result get_vram_info_v25(
2376 struct bios_parser *bp,
2377 struct dc_vram_info *info)
2378 {
2379 struct atom_vram_info_header_v2_5 *info_v25;
2380 static enum bp_result result = BP_RESULT_OK;
2381
2382 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
2383 DATA_TABLES(vram_info));
2384
2385 if (info_v25 == NULL)
2386 return BP_RESULT_BADBIOSTABLE;
2387
2388 info->num_chans = info_v25->vram_module[0].channel_num;
2389 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
2390
2391 return result;
2392 }
2393
get_vram_info_v30(struct bios_parser * bp,struct dc_vram_info * info)2394 static enum bp_result get_vram_info_v30(
2395 struct bios_parser *bp,
2396 struct dc_vram_info *info)
2397 {
2398 struct atom_vram_info_header_v3_0 *info_v30;
2399 enum bp_result result = BP_RESULT_OK;
2400
2401 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2402 DATA_TABLES(vram_info));
2403
2404 if (info_v30 == NULL)
2405 return BP_RESULT_BADBIOSTABLE;
2406
2407 info->num_chans = info_v30->channel_num;
2408 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2409
2410 return result;
2411 }
2412
2413
2414 /*
2415 * get_integrated_info_v11
2416 *
2417 * @brief
2418 * Get V8 integrated BIOS information
2419 *
2420 * @param
2421 * bios_parser *bp - [in]BIOS parser handler to get master data table
2422 * integrated_info *info - [out] store and output integrated info
2423 *
2424 * @return
2425 * static enum bp_result - BP_RESULT_OK if information is available,
2426 * BP_RESULT_BADBIOSTABLE otherwise.
2427 */
get_integrated_info_v11(struct bios_parser * bp,struct integrated_info * info)2428 static enum bp_result get_integrated_info_v11(
2429 struct bios_parser *bp,
2430 struct integrated_info *info)
2431 {
2432 struct atom_integrated_system_info_v1_11 *info_v11;
2433 uint32_t i;
2434
2435 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
2436 DATA_TABLES(integratedsysteminfo));
2437
2438 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage);
2439 if (info_v11 == NULL)
2440 return BP_RESULT_BADBIOSTABLE;
2441
2442 info->gpu_cap_info =
2443 le32_to_cpu(info_v11->gpucapinfo);
2444 /*
2445 * system_config: Bit[0] = 0 : PCIE power gating disabled
2446 * = 1 : PCIE power gating enabled
2447 * Bit[1] = 0 : DDR-PLL shut down disabled
2448 * = 1 : DDR-PLL shut down enabled
2449 * Bit[2] = 0 : DDR-PLL power down disabled
2450 * = 1 : DDR-PLL power down enabled
2451 */
2452 info->system_config = le32_to_cpu(info_v11->system_config);
2453 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
2454 info->memory_type = info_v11->memorytype;
2455 info->ma_channel_number = info_v11->umachannelnumber;
2456 info->lvds_ss_percentage =
2457 le16_to_cpu(info_v11->lvds_ss_percentage);
2458 info->dp_ss_control =
2459 le16_to_cpu(info_v11->reserved1);
2460 info->lvds_sspread_rate_in_10hz =
2461 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
2462 info->hdmi_ss_percentage =
2463 le16_to_cpu(info_v11->hdmi_ss_percentage);
2464 info->hdmi_sspread_rate_in_10hz =
2465 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
2466 info->dvi_ss_percentage =
2467 le16_to_cpu(info_v11->dvi_ss_percentage);
2468 info->dvi_sspread_rate_in_10_hz =
2469 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
2470 info->lvds_misc = info_v11->lvds_misc;
2471 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2472 info->ext_disp_conn_info.gu_id[i] =
2473 info_v11->extdispconninfo.guid[i];
2474 }
2475
2476 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2477 info->ext_disp_conn_info.path[i].device_connector_id =
2478 object_id_from_bios_object_id(
2479 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
2480
2481 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2482 object_id_from_bios_object_id(
2483 le16_to_cpu(
2484 info_v11->extdispconninfo.path[i].ext_encoder_objid));
2485
2486 info->ext_disp_conn_info.path[i].device_tag =
2487 le16_to_cpu(
2488 info_v11->extdispconninfo.path[i].device_tag);
2489 info->ext_disp_conn_info.path[i].device_acpi_enum =
2490 le16_to_cpu(
2491 info_v11->extdispconninfo.path[i].device_acpi_enum);
2492 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2493 info_v11->extdispconninfo.path[i].auxddclut_index;
2494 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2495 info_v11->extdispconninfo.path[i].hpdlut_index;
2496 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2497 info_v11->extdispconninfo.path[i].channelmapping;
2498 info->ext_disp_conn_info.path[i].caps =
2499 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
2500 }
2501 info->ext_disp_conn_info.checksum =
2502 info_v11->extdispconninfo.checksum;
2503
2504 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
2505 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
2506 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2507 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2508 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2509 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2510 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2511 }
2512 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
2513 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2514 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2515 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2516 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2517 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2518 }
2519
2520 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
2521 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
2522 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2523 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2524 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2525 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2526 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2527 }
2528 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
2529 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2530 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2531 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2532 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2533 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2534 }
2535
2536 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
2537 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
2538 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2539 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2540 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2541 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2542 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2543 }
2544 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
2545 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2546 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2547 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2548 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2549 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2550 }
2551
2552 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
2553 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
2554 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2555 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2556 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2557 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2558 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2559 }
2560 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
2561 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2562 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2563 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2564 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2565 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2566 }
2567
2568
2569 /** TODO - review **/
2570 #if 0
2571 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
2572 * 10;
2573 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
2574 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
2575
2576 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2577 /* Convert [10KHz] into [KHz] */
2578 info->disp_clk_voltage[i].max_supported_clk =
2579 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
2580 ulMaximumSupportedCLK) * 10;
2581 info->disp_clk_voltage[i].voltage_index =
2582 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
2583 }
2584
2585 info->boot_up_req_display_vector =
2586 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
2587 info->boot_up_nb_voltage =
2588 le16_to_cpu(info_v11->usBootUpNBVoltage);
2589 info->ext_disp_conn_info_offset =
2590 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
2591 info->gmc_restore_reset_time =
2592 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
2593 info->minimum_n_clk =
2594 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
2595 for (i = 1; i < 4; ++i)
2596 info->minimum_n_clk =
2597 info->minimum_n_clk <
2598 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
2599 info->minimum_n_clk : le32_to_cpu(
2600 info_v11->ulNbpStateNClkFreq[i]);
2601
2602 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
2603 info->ddr_dll_power_up_time =
2604 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
2605 info->ddr_pll_power_up_time =
2606 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
2607 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
2608 info->max_lvds_pclk_freq_in_single_link =
2609 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2610 info->max_lvds_pclk_freq_in_single_link =
2611 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2612 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
2613 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
2614 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
2615 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
2616 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
2617 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
2618 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
2619 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
2620 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
2621 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
2622 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
2623 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
2624 info->lvds_off_to_on_delay_in_4ms =
2625 info_v11->ucLVDSOffToOnDelay_in4Ms;
2626 info->lvds_bit_depth_control_val =
2627 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
2628
2629 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
2630 /* Convert [10KHz] into [KHz] */
2631 info->avail_s_clk[i].supported_s_clk =
2632 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
2633 * 10;
2634 info->avail_s_clk[i].voltage_index =
2635 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
2636 info->avail_s_clk[i].voltage_id =
2637 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
2638 }
2639 #endif /* TODO*/
2640
2641 return BP_RESULT_OK;
2642 }
2643
get_integrated_info_v2_1(struct bios_parser * bp,struct integrated_info * info)2644 static enum bp_result get_integrated_info_v2_1(
2645 struct bios_parser *bp,
2646 struct integrated_info *info)
2647 {
2648 struct atom_integrated_system_info_v2_1 *info_v2_1;
2649 uint32_t i;
2650
2651 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
2652 DATA_TABLES(integratedsysteminfo));
2653 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage);
2654
2655 if (info_v2_1 == NULL)
2656 return BP_RESULT_BADBIOSTABLE;
2657
2658 info->gpu_cap_info =
2659 le32_to_cpu(info_v2_1->gpucapinfo);
2660 /*
2661 * system_config: Bit[0] = 0 : PCIE power gating disabled
2662 * = 1 : PCIE power gating enabled
2663 * Bit[1] = 0 : DDR-PLL shut down disabled
2664 * = 1 : DDR-PLL shut down enabled
2665 * Bit[2] = 0 : DDR-PLL power down disabled
2666 * = 1 : DDR-PLL power down enabled
2667 */
2668 info->system_config = le32_to_cpu(info_v2_1->system_config);
2669 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
2670 info->memory_type = info_v2_1->memorytype;
2671 info->ma_channel_number = info_v2_1->umachannelnumber;
2672 info->dp_ss_control =
2673 le16_to_cpu(info_v2_1->reserved1);
2674
2675 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2676 info->ext_disp_conn_info.gu_id[i] =
2677 info_v2_1->extdispconninfo.guid[i];
2678 }
2679
2680 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2681 info->ext_disp_conn_info.path[i].device_connector_id =
2682 object_id_from_bios_object_id(
2683 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
2684
2685 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2686 object_id_from_bios_object_id(
2687 le16_to_cpu(
2688 info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
2689
2690 info->ext_disp_conn_info.path[i].device_tag =
2691 le16_to_cpu(
2692 info_v2_1->extdispconninfo.path[i].device_tag);
2693 info->ext_disp_conn_info.path[i].device_acpi_enum =
2694 le16_to_cpu(
2695 info_v2_1->extdispconninfo.path[i].device_acpi_enum);
2696 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2697 info_v2_1->extdispconninfo.path[i].auxddclut_index;
2698 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2699 info_v2_1->extdispconninfo.path[i].hpdlut_index;
2700 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2701 info_v2_1->extdispconninfo.path[i].channelmapping;
2702 info->ext_disp_conn_info.path[i].caps =
2703 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
2704 }
2705
2706 info->ext_disp_conn_info.checksum =
2707 info_v2_1->extdispconninfo.checksum;
2708 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
2709 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
2710 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2711 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2712 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2713 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2714 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2715 }
2716 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
2717 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2718 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2719 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2720 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2721 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2722 }
2723 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
2724 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
2725 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2726 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2727 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2728 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2729 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2730 }
2731 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
2732 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2733 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2734 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2735 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2736 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2737 }
2738 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
2739 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
2740 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2741 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2742 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2743 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2744 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2745 }
2746 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
2747 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2748 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2749 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2750 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2751 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2752 }
2753 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
2754 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
2755 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2756 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2757 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2758 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2759 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2760 }
2761 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
2762 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2763 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2764 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2765 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2766 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2767 }
2768
2769 info->edp1_info.edp_backlight_pwm_hz =
2770 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
2771 info->edp1_info.edp_ss_percentage =
2772 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
2773 info->edp1_info.edp_ss_rate_10hz =
2774 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
2775 info->edp1_info.edp_pwr_on_off_delay =
2776 info_v2_1->edp1_info.edp_pwr_on_off_delay;
2777 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2778 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
2779 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2780 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2781 info->edp1_info.edp_panel_bpc =
2782 info_v2_1->edp1_info.edp_panel_bpc;
2783 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
2784
2785 info->edp2_info.edp_backlight_pwm_hz =
2786 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
2787 info->edp2_info.edp_ss_percentage =
2788 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
2789 info->edp2_info.edp_ss_rate_10hz =
2790 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
2791 info->edp2_info.edp_pwr_on_off_delay =
2792 info_v2_1->edp2_info.edp_pwr_on_off_delay;
2793 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2794 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
2795 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2796 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2797 info->edp2_info.edp_panel_bpc =
2798 info_v2_1->edp2_info.edp_panel_bpc;
2799 info->edp2_info.edp_bootup_bl_level =
2800 info_v2_1->edp2_info.edp_bootup_bl_level;
2801
2802 return BP_RESULT_OK;
2803 }
2804
get_integrated_info_v2_2(struct bios_parser * bp,struct integrated_info * info)2805 static enum bp_result get_integrated_info_v2_2(
2806 struct bios_parser *bp,
2807 struct integrated_info *info)
2808 {
2809 struct atom_integrated_system_info_v2_2 *info_v2_2;
2810 uint32_t i;
2811
2812 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
2813 DATA_TABLES(integratedsysteminfo));
2814
2815 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage);
2816
2817 if (info_v2_2 == NULL)
2818 return BP_RESULT_BADBIOSTABLE;
2819
2820 info->gpu_cap_info =
2821 le32_to_cpu(info_v2_2->gpucapinfo);
2822 /*
2823 * system_config: Bit[0] = 0 : PCIE power gating disabled
2824 * = 1 : PCIE power gating enabled
2825 * Bit[1] = 0 : DDR-PLL shut down disabled
2826 * = 1 : DDR-PLL shut down enabled
2827 * Bit[2] = 0 : DDR-PLL power down disabled
2828 * = 1 : DDR-PLL power down enabled
2829 */
2830 info->system_config = le32_to_cpu(info_v2_2->system_config);
2831 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
2832 info->memory_type = info_v2_2->memorytype;
2833 info->ma_channel_number = info_v2_2->umachannelnumber;
2834 info->dp_ss_control =
2835 le16_to_cpu(info_v2_2->reserved1);
2836
2837 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2838 info->ext_disp_conn_info.gu_id[i] =
2839 info_v2_2->extdispconninfo.guid[i];
2840 }
2841
2842 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2843 info->ext_disp_conn_info.path[i].device_connector_id =
2844 object_id_from_bios_object_id(
2845 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
2846
2847 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2848 object_id_from_bios_object_id(
2849 le16_to_cpu(
2850 info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
2851
2852 info->ext_disp_conn_info.path[i].device_tag =
2853 le16_to_cpu(
2854 info_v2_2->extdispconninfo.path[i].device_tag);
2855 info->ext_disp_conn_info.path[i].device_acpi_enum =
2856 le16_to_cpu(
2857 info_v2_2->extdispconninfo.path[i].device_acpi_enum);
2858 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2859 info_v2_2->extdispconninfo.path[i].auxddclut_index;
2860 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2861 info_v2_2->extdispconninfo.path[i].hpdlut_index;
2862 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2863 info_v2_2->extdispconninfo.path[i].channelmapping;
2864 info->ext_disp_conn_info.path[i].caps =
2865 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
2866 }
2867
2868 info->ext_disp_conn_info.checksum =
2869 info_v2_2->extdispconninfo.checksum;
2870 info->ext_disp_conn_info.fixdpvoltageswing =
2871 info_v2_2->extdispconninfo.fixdpvoltageswing;
2872
2873 info->edp1_info.edp_backlight_pwm_hz =
2874 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
2875 info->edp1_info.edp_ss_percentage =
2876 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
2877 info->edp1_info.edp_ss_rate_10hz =
2878 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
2879 info->edp1_info.edp_pwr_on_off_delay =
2880 info_v2_2->edp1_info.edp_pwr_on_off_delay;
2881 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2882 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
2883 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2884 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2885 info->edp1_info.edp_panel_bpc =
2886 info_v2_2->edp1_info.edp_panel_bpc;
2887 info->edp1_info.edp_bootup_bl_level =
2888
2889 info->edp2_info.edp_backlight_pwm_hz =
2890 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
2891 info->edp2_info.edp_ss_percentage =
2892 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
2893 info->edp2_info.edp_ss_rate_10hz =
2894 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
2895 info->edp2_info.edp_pwr_on_off_delay =
2896 info_v2_2->edp2_info.edp_pwr_on_off_delay;
2897 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2898 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
2899 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2900 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2901 info->edp2_info.edp_panel_bpc =
2902 info_v2_2->edp2_info.edp_panel_bpc;
2903 info->edp2_info.edp_bootup_bl_level =
2904 info_v2_2->edp2_info.edp_bootup_bl_level;
2905
2906 return BP_RESULT_OK;
2907 }
2908
2909 /*
2910 * construct_integrated_info
2911 *
2912 * @brief
2913 * Get integrated BIOS information based on table revision
2914 *
2915 * @param
2916 * bios_parser *bp - [in]BIOS parser handler to get master data table
2917 * integrated_info *info - [out] store and output integrated info
2918 *
2919 * @return
2920 * static enum bp_result - BP_RESULT_OK if information is available,
2921 * BP_RESULT_BADBIOSTABLE otherwise.
2922 */
construct_integrated_info(struct bios_parser * bp,struct integrated_info * info)2923 static enum bp_result construct_integrated_info(
2924 struct bios_parser *bp,
2925 struct integrated_info *info)
2926 {
2927 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
2928
2929 struct atom_common_table_header *header;
2930 struct atom_data_revision revision;
2931
2932 struct clock_voltage_caps temp = {0, 0};
2933 uint32_t i;
2934 uint32_t j;
2935
2936 if (info && DATA_TABLES(integratedsysteminfo)) {
2937 header = GET_IMAGE(struct atom_common_table_header,
2938 DATA_TABLES(integratedsysteminfo));
2939
2940 get_atom_data_table_revision(header, &revision);
2941
2942 switch (revision.major) {
2943 case 1:
2944 switch (revision.minor) {
2945 case 11:
2946 case 12:
2947 result = get_integrated_info_v11(bp, info);
2948 break;
2949 default:
2950 return result;
2951 }
2952 break;
2953 case 2:
2954 switch (revision.minor) {
2955 case 1:
2956 result = get_integrated_info_v2_1(bp, info);
2957 break;
2958 case 2:
2959 result = get_integrated_info_v2_2(bp, info);
2960 break;
2961 default:
2962 return result;
2963 }
2964 break;
2965 default:
2966 return result;
2967 }
2968 if (result == BP_RESULT_OK) {
2969
2970 DC_LOG_BIOS("edp1:\n"
2971 "\tedp_pwr_on_off_delay = %d\n"
2972 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2973 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2974 "\tedp_bootup_bl_level = %d\n",
2975 info->edp1_info.edp_pwr_on_off_delay,
2976 info->edp1_info.edp_pwr_on_vary_bl_to_blon,
2977 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff,
2978 info->edp1_info.edp_bootup_bl_level);
2979 DC_LOG_BIOS("edp2:\n"
2980 "\tedp_pwr_on_off_delayv = %d\n"
2981 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2982 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2983 "\tedp_bootup_bl_level = %d\n",
2984 info->edp2_info.edp_pwr_on_off_delay,
2985 info->edp2_info.edp_pwr_on_vary_bl_to_blon,
2986 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff,
2987 info->edp2_info.edp_bootup_bl_level);
2988 }
2989 }
2990
2991 if (result != BP_RESULT_OK)
2992 return result;
2993 else {
2994 // Log each external path
2995 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
2996 if (info->ext_disp_conn_info.path[i].device_tag != 0)
2997 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n"
2998 "DEVICE_TAG: 0x%x\n"
2999 "DEVICE_ACPI_ENUM: 0x%x\n"
3000 "DEVICE_CONNECTOR_ID: 0x%x\n"
3001 "EXT_AUX_DDC_LUT_INDEX: %d\n"
3002 "EXT_HPD_PIN_LUT_INDEX: %d\n"
3003 "EXT_ENCODER_OBJ_ID: 0x%x\n"
3004 "Encoder CAPS: 0x%x\n",
3005 i,
3006 info->ext_disp_conn_info.path[i].device_tag,
3007 info->ext_disp_conn_info.path[i].device_acpi_enum,
3008 info->ext_disp_conn_info.path[i].device_connector_id.id,
3009 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
3010 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
3011 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
3012 info->ext_disp_conn_info.path[i].caps
3013 );
3014 if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3015 DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3016 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
3017 info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3018 DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3019 }
3020 }
3021 // Log the Checksum and Voltage Swing
3022 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
3023 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n",
3024 info->ext_disp_conn_info.checksum,
3025 info->ext_disp_conn_info.fixdpvoltageswing);
3026 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {
3027 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;
3028 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
3029 }
3030 }
3031 /* Sort voltage table from low to high*/
3032 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
3033 for (j = i; j > 0; --j) {
3034 if (info->disp_clk_voltage[j].max_supported_clk <
3035 info->disp_clk_voltage[j-1].max_supported_clk
3036 ) {
3037 /* swap j and j - 1*/
3038 temp = info->disp_clk_voltage[j-1];
3039 info->disp_clk_voltage[j-1] =
3040 info->disp_clk_voltage[j];
3041 info->disp_clk_voltage[j] = temp;
3042 }
3043 }
3044 }
3045
3046 return result;
3047 }
3048
bios_parser_get_vram_info(struct dc_bios * dcb,struct dc_vram_info * info)3049 static enum bp_result bios_parser_get_vram_info(
3050 struct dc_bios *dcb,
3051 struct dc_vram_info *info)
3052 {
3053 struct bios_parser *bp = BP_FROM_DCB(dcb);
3054 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3055 struct atom_common_table_header *header;
3056 struct atom_data_revision revision;
3057
3058 if (info && DATA_TABLES(vram_info)) {
3059 header = GET_IMAGE(struct atom_common_table_header,
3060 DATA_TABLES(vram_info));
3061
3062 get_atom_data_table_revision(header, &revision);
3063
3064 switch (revision.major) {
3065 case 2:
3066 switch (revision.minor) {
3067 case 3:
3068 result = get_vram_info_v23(bp, info);
3069 break;
3070 case 4:
3071 result = get_vram_info_v24(bp, info);
3072 break;
3073 case 5:
3074 result = get_vram_info_v25(bp, info);
3075 break;
3076 default:
3077 break;
3078 }
3079 break;
3080
3081 case 3:
3082 switch (revision.minor) {
3083 case 0:
3084 result = get_vram_info_v30(bp, info);
3085 break;
3086 default:
3087 break;
3088 }
3089 break;
3090
3091 default:
3092 return result;
3093 }
3094
3095 }
3096 return result;
3097 }
3098
bios_parser_create_integrated_info(struct dc_bios * dcb)3099 static struct integrated_info *bios_parser_create_integrated_info(
3100 struct dc_bios *dcb)
3101 {
3102 struct bios_parser *bp = BP_FROM_DCB(dcb);
3103 struct integrated_info *info = NULL;
3104
3105 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
3106
3107 if (info == NULL) {
3108 ASSERT_CRITICAL(0);
3109 return NULL;
3110 }
3111
3112 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
3113 return info;
3114
3115 kfree(info);
3116
3117 return NULL;
3118 }
3119
update_slot_layout_info(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3120 static enum bp_result update_slot_layout_info(
3121 struct dc_bios *dcb,
3122 unsigned int i,
3123 struct slot_layout_info *slot_layout_info)
3124 {
3125 unsigned int record_offset;
3126 unsigned int j;
3127 struct atom_display_object_path_v2 *object;
3128 struct atom_bracket_layout_record *record;
3129 struct atom_common_record_header *record_header;
3130 static enum bp_result result;
3131 struct bios_parser *bp;
3132 struct object_info_table *tbl;
3133 struct display_object_info_table_v1_4 *v1_4;
3134
3135 record = NULL;
3136 record_header = NULL;
3137 result = BP_RESULT_NORECORD;
3138
3139 bp = BP_FROM_DCB(dcb);
3140 tbl = &bp->object_info_tbl;
3141 v1_4 = tbl->v1_4;
3142
3143 object = &v1_4->display_path[i];
3144 record_offset = (unsigned int)
3145 (object->disp_recordoffset) +
3146 (unsigned int)(bp->object_info_tbl_offset);
3147
3148 for (;;) {
3149
3150 record_header = (struct atom_common_record_header *)
3151 GET_IMAGE(struct atom_common_record_header,
3152 record_offset);
3153 if (record_header == NULL) {
3154 result = BP_RESULT_BADBIOSTABLE;
3155 break;
3156 }
3157
3158 /* the end of the list */
3159 if (record_header->record_type == 0xff ||
3160 record_header->record_size == 0) {
3161 break;
3162 }
3163
3164 if (record_header->record_type ==
3165 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
3166 sizeof(struct atom_bracket_layout_record)
3167 <= record_header->record_size) {
3168 record = (struct atom_bracket_layout_record *)
3169 (record_header);
3170 result = BP_RESULT_OK;
3171 break;
3172 }
3173
3174 record_offset += record_header->record_size;
3175 }
3176
3177 /* return if the record not found */
3178 if (result != BP_RESULT_OK)
3179 return result;
3180
3181 /* get slot sizes */
3182 slot_layout_info->length = record->bracketlen;
3183 slot_layout_info->width = record->bracketwidth;
3184
3185 /* get info for each connector in the slot */
3186 slot_layout_info->num_of_connectors = record->conn_num;
3187 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
3188 slot_layout_info->connectors[j].connector_type =
3189 (enum connector_layout_type)
3190 (record->conn_info[j].connector_type);
3191 switch (record->conn_info[j].connector_type) {
3192 case CONNECTOR_TYPE_DVI_D:
3193 slot_layout_info->connectors[j].connector_type =
3194 CONNECTOR_LAYOUT_TYPE_DVI_D;
3195 slot_layout_info->connectors[j].length =
3196 CONNECTOR_SIZE_DVI;
3197 break;
3198
3199 case CONNECTOR_TYPE_HDMI:
3200 slot_layout_info->connectors[j].connector_type =
3201 CONNECTOR_LAYOUT_TYPE_HDMI;
3202 slot_layout_info->connectors[j].length =
3203 CONNECTOR_SIZE_HDMI;
3204 break;
3205
3206 case CONNECTOR_TYPE_DISPLAY_PORT:
3207 slot_layout_info->connectors[j].connector_type =
3208 CONNECTOR_LAYOUT_TYPE_DP;
3209 slot_layout_info->connectors[j].length =
3210 CONNECTOR_SIZE_DP;
3211 break;
3212
3213 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
3214 slot_layout_info->connectors[j].connector_type =
3215 CONNECTOR_LAYOUT_TYPE_MINI_DP;
3216 slot_layout_info->connectors[j].length =
3217 CONNECTOR_SIZE_MINI_DP;
3218 break;
3219
3220 default:
3221 slot_layout_info->connectors[j].connector_type =
3222 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3223 slot_layout_info->connectors[j].length =
3224 CONNECTOR_SIZE_UNKNOWN;
3225 }
3226
3227 slot_layout_info->connectors[j].position =
3228 record->conn_info[j].position;
3229 slot_layout_info->connectors[j].connector_id =
3230 object_id_from_bios_object_id(
3231 record->conn_info[j].connectorobjid);
3232 }
3233 return result;
3234 }
3235
update_slot_layout_info_v2(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3236 static enum bp_result update_slot_layout_info_v2(
3237 struct dc_bios *dcb,
3238 unsigned int i,
3239 struct slot_layout_info *slot_layout_info)
3240 {
3241 unsigned int record_offset;
3242 struct atom_display_object_path_v3 *object;
3243 struct atom_bracket_layout_record_v2 *record;
3244 struct atom_common_record_header *record_header;
3245 static enum bp_result result;
3246 struct bios_parser *bp;
3247 struct object_info_table *tbl;
3248 struct display_object_info_table_v1_5 *v1_5;
3249 struct graphics_object_id connector_id;
3250
3251 record = NULL;
3252 record_header = NULL;
3253 result = BP_RESULT_NORECORD;
3254
3255 bp = BP_FROM_DCB(dcb);
3256 tbl = &bp->object_info_tbl;
3257 v1_5 = tbl->v1_5;
3258
3259 object = &v1_5->display_path[i];
3260 record_offset = (unsigned int)
3261 (object->disp_recordoffset) +
3262 (unsigned int)(bp->object_info_tbl_offset);
3263
3264 for (;;) {
3265
3266 record_header = (struct atom_common_record_header *)
3267 GET_IMAGE(struct atom_common_record_header,
3268 record_offset);
3269 if (record_header == NULL) {
3270 result = BP_RESULT_BADBIOSTABLE;
3271 break;
3272 }
3273
3274 /* the end of the list */
3275 if (record_header->record_type == ATOM_RECORD_END_TYPE ||
3276 record_header->record_size == 0) {
3277 break;
3278 }
3279
3280 if (record_header->record_type ==
3281 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
3282 sizeof(struct atom_bracket_layout_record_v2)
3283 <= record_header->record_size) {
3284 record = (struct atom_bracket_layout_record_v2 *)
3285 (record_header);
3286 result = BP_RESULT_OK;
3287 break;
3288 }
3289
3290 record_offset += record_header->record_size;
3291 }
3292
3293 /* return if the record not found */
3294 if (result != BP_RESULT_OK)
3295 return result;
3296
3297 /* get slot sizes */
3298 connector_id = object_id_from_bios_object_id(object->display_objid);
3299
3300 slot_layout_info->length = record->bracketlen;
3301 slot_layout_info->width = record->bracketwidth;
3302 slot_layout_info->num_of_connectors = v1_5->number_of_path;
3303 slot_layout_info->connectors[i].position = record->conn_num;
3304 slot_layout_info->connectors[i].connector_id = connector_id;
3305
3306 switch (connector_id.id) {
3307 case CONNECTOR_ID_SINGLE_LINK_DVID:
3308 case CONNECTOR_ID_DUAL_LINK_DVID:
3309 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
3310 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
3311 break;
3312
3313 case CONNECTOR_ID_HDMI_TYPE_A:
3314 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
3315 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
3316 break;
3317
3318 case CONNECTOR_ID_DISPLAY_PORT:
3319 case CONNECTOR_ID_USBC:
3320 if (record->mini_type == MINI_TYPE_NORMAL) {
3321 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
3322 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
3323 } else {
3324 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
3325 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
3326 }
3327 break;
3328
3329 default:
3330 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3331 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
3332 }
3333 return result;
3334 }
3335
get_bracket_layout_record(struct dc_bios * dcb,unsigned int bracket_layout_id,struct slot_layout_info * slot_layout_info)3336 static enum bp_result get_bracket_layout_record(
3337 struct dc_bios *dcb,
3338 unsigned int bracket_layout_id,
3339 struct slot_layout_info *slot_layout_info)
3340 {
3341 unsigned int i;
3342 struct bios_parser *bp = BP_FROM_DCB(dcb);
3343 static enum bp_result result;
3344 struct object_info_table *tbl;
3345 struct display_object_info_table_v1_4 *v1_4;
3346 struct display_object_info_table_v1_5 *v1_5;
3347
3348 if (slot_layout_info == NULL) {
3349 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
3350 return BP_RESULT_BADINPUT;
3351 }
3352 tbl = &bp->object_info_tbl;
3353 v1_4 = tbl->v1_4;
3354 v1_5 = tbl->v1_5;
3355
3356 result = BP_RESULT_NORECORD;
3357 switch (bp->object_info_tbl.revision.minor) {
3358 case 4:
3359 default:
3360 for (i = 0; i < v1_4->number_of_path; ++i) {
3361 if (bracket_layout_id ==
3362 v1_4->display_path[i].display_objid) {
3363 result = update_slot_layout_info(dcb, i, slot_layout_info);
3364 break;
3365 }
3366 }
3367 break;
3368 case 5:
3369 for (i = 0; i < v1_5->number_of_path; ++i)
3370 result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
3371 break;
3372 }
3373 return result;
3374 }
3375
bios_get_board_layout_info(struct dc_bios * dcb,struct board_layout_info * board_layout_info)3376 static enum bp_result bios_get_board_layout_info(
3377 struct dc_bios *dcb,
3378 struct board_layout_info *board_layout_info)
3379 {
3380 unsigned int i;
3381
3382 struct bios_parser *bp;
3383
3384 static enum bp_result record_result;
3385 unsigned int max_slots;
3386
3387 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
3388 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
3389 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
3390 0, 0
3391 };
3392
3393
3394 bp = BP_FROM_DCB(dcb);
3395
3396 if (board_layout_info == NULL) {
3397 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
3398 return BP_RESULT_BADINPUT;
3399 }
3400
3401 board_layout_info->num_of_slots = 0;
3402 max_slots = MAX_BOARD_SLOTS;
3403
3404 // Assume single slot on v1_5
3405 if (bp->object_info_tbl.revision.minor == 5) {
3406 max_slots = 1;
3407 }
3408
3409 for (i = 0; i < max_slots; ++i) {
3410 record_result = get_bracket_layout_record(dcb,
3411 slot_index_to_vbios_id[i],
3412 &board_layout_info->slots[i]);
3413
3414 if (record_result == BP_RESULT_NORECORD && i > 0)
3415 break; /* no more slots present in bios */
3416 else if (record_result != BP_RESULT_OK)
3417 return record_result; /* fail */
3418
3419 ++board_layout_info->num_of_slots;
3420 }
3421
3422 /* all data is valid */
3423 board_layout_info->is_number_of_slots_valid = 1;
3424 board_layout_info->is_slots_size_valid = 1;
3425 board_layout_info->is_connector_offsets_valid = 1;
3426 board_layout_info->is_connector_lengths_valid = 1;
3427
3428 return BP_RESULT_OK;
3429 }
3430
3431
bios_parser_pack_data_tables(struct dc_bios * dcb,void * dst)3432 static uint16_t bios_parser_pack_data_tables(
3433 struct dc_bios *dcb,
3434 void *dst)
3435 {
3436 // TODO: There is data bytes alignment issue, disable it for now.
3437 return 0;
3438 }
3439
bios_get_golden_table(struct bios_parser * bp,uint32_t rev_major,uint32_t rev_minor,uint16_t * dc_golden_table_ver)3440 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
3441 struct bios_parser *bp,
3442 uint32_t rev_major,
3443 uint32_t rev_minor,
3444 uint16_t *dc_golden_table_ver)
3445 {
3446 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
3447 uint32_t dc_golden_offset = 0;
3448 *dc_golden_table_ver = 0;
3449
3450 if (!DATA_TABLES(dce_info))
3451 return NULL;
3452
3453 /* ver.4.4 or higher */
3454 switch (rev_major) {
3455 case 4:
3456 switch (rev_minor) {
3457 case 4:
3458 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
3459 DATA_TABLES(dce_info));
3460 if (!disp_cntl_tbl_4_4)
3461 return NULL;
3462 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
3463 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
3464 break;
3465 case 5:
3466 default:
3467 /* For atom_display_controller_info_v4_5 there is no need to get golden table from
3468 * dc_golden_table_offset as all these fields previously in golden table used for AUX
3469 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
3470 */
3471 break;
3472 }
3473 break;
3474 }
3475
3476 if (!dc_golden_offset)
3477 return NULL;
3478
3479 if (*dc_golden_table_ver != 1)
3480 return NULL;
3481
3482 return GET_IMAGE(struct atom_dc_golden_table_v1,
3483 dc_golden_offset);
3484 }
3485
bios_get_atom_dc_golden_table(struct dc_bios * dcb)3486 static enum bp_result bios_get_atom_dc_golden_table(
3487 struct dc_bios *dcb)
3488 {
3489 struct bios_parser *bp = BP_FROM_DCB(dcb);
3490 enum bp_result result = BP_RESULT_OK;
3491 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
3492 struct atom_common_table_header *header;
3493 struct atom_data_revision tbl_revision;
3494 uint16_t dc_golden_table_ver = 0;
3495
3496 header = GET_IMAGE(struct atom_common_table_header,
3497 DATA_TABLES(dce_info));
3498 if (!header)
3499 return BP_RESULT_UNSUPPORTED;
3500
3501 get_atom_data_table_revision(header, &tbl_revision);
3502
3503 atom_dc_golden_table = bios_get_golden_table(bp,
3504 tbl_revision.major,
3505 tbl_revision.minor,
3506 &dc_golden_table_ver);
3507
3508 if (!atom_dc_golden_table)
3509 return BP_RESULT_UNSUPPORTED;
3510
3511 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
3512 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
3513 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
3514 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
3515 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
3516 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
3517 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
3518 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
3519 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
3520 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
3521
3522 return result;
3523 }
3524
3525
3526 static const struct dc_vbios_funcs vbios_funcs = {
3527 .get_connectors_number = bios_parser_get_connectors_number,
3528
3529 .get_connector_id = bios_parser_get_connector_id,
3530
3531 .get_src_obj = bios_parser_get_src_obj,
3532
3533 .get_i2c_info = bios_parser_get_i2c_info,
3534
3535 .get_hpd_info = bios_parser_get_hpd_info,
3536
3537 .get_device_tag = bios_parser_get_device_tag,
3538
3539 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
3540
3541 .get_ss_entry_number = bios_parser_get_ss_entry_number,
3542
3543 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
3544
3545 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
3546
3547 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
3548
3549 .is_device_id_supported = bios_parser_is_device_id_supported,
3550
3551 .is_accelerated_mode = bios_parser_is_accelerated_mode,
3552
3553 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
3554
3555
3556 /* COMMANDS */
3557 .encoder_control = bios_parser_encoder_control,
3558
3559 .transmitter_control = bios_parser_transmitter_control,
3560
3561 .enable_crtc = bios_parser_enable_crtc,
3562
3563 .set_pixel_clock = bios_parser_set_pixel_clock,
3564
3565 .set_dce_clock = bios_parser_set_dce_clock,
3566
3567 .program_crtc_timing = bios_parser_program_crtc_timing,
3568
3569 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
3570
3571 .bios_parser_destroy = firmware_parser_destroy,
3572
3573 .get_board_layout_info = bios_get_board_layout_info,
3574 /* TODO: use this fn in hw init?*/
3575 .pack_data_tables = bios_parser_pack_data_tables,
3576
3577 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
3578
3579 .enable_lvtma_control = bios_parser_enable_lvtma_control,
3580
3581 .get_soc_bb_info = bios_parser_get_soc_bb_info,
3582
3583 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
3584
3585 .get_lttpr_caps = bios_parser_get_lttpr_caps,
3586
3587 .get_lttpr_interop = bios_parser_get_lttpr_interop,
3588
3589 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
3590 };
3591
bios_parser2_construct(struct bios_parser * bp,struct bp_init_data * init,enum dce_version dce_version)3592 static bool bios_parser2_construct(
3593 struct bios_parser *bp,
3594 struct bp_init_data *init,
3595 enum dce_version dce_version)
3596 {
3597 uint16_t *rom_header_offset = NULL;
3598 struct atom_rom_header_v2_2 *rom_header = NULL;
3599 struct display_object_info_table_v1_4 *object_info_tbl;
3600 struct atom_data_revision tbl_rev = {0};
3601
3602 if (!init)
3603 return false;
3604
3605 if (!init->bios)
3606 return false;
3607
3608 bp->base.funcs = &vbios_funcs;
3609 bp->base.bios = init->bios;
3610 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
3611
3612 bp->base.ctx = init->ctx;
3613
3614 bp->base.bios_local_image = NULL;
3615
3616 rom_header_offset =
3617 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
3618
3619 if (!rom_header_offset)
3620 return false;
3621
3622 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
3623
3624 if (!rom_header)
3625 return false;
3626
3627 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
3628 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
3629 return false;
3630
3631 bp->master_data_tbl =
3632 GET_IMAGE(struct atom_master_data_table_v2_1,
3633 rom_header->masterdatatable_offset);
3634
3635 if (!bp->master_data_tbl)
3636 return false;
3637
3638 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
3639
3640 if (!bp->object_info_tbl_offset)
3641 return false;
3642
3643 object_info_tbl =
3644 GET_IMAGE(struct display_object_info_table_v1_4,
3645 bp->object_info_tbl_offset);
3646
3647 if (!object_info_tbl)
3648 return false;
3649
3650 get_atom_data_table_revision(&object_info_tbl->table_header,
3651 &bp->object_info_tbl.revision);
3652
3653 if (bp->object_info_tbl.revision.major == 1
3654 && bp->object_info_tbl.revision.minor == 4) {
3655 struct display_object_info_table_v1_4 *tbl_v1_4;
3656
3657 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
3658 bp->object_info_tbl_offset);
3659 if (!tbl_v1_4)
3660 return false;
3661
3662 bp->object_info_tbl.v1_4 = tbl_v1_4;
3663 } else if (bp->object_info_tbl.revision.major == 1
3664 && bp->object_info_tbl.revision.minor == 5) {
3665 struct display_object_info_table_v1_5 *tbl_v1_5;
3666
3667 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
3668 bp->object_info_tbl_offset);
3669 if (!tbl_v1_5)
3670 return false;
3671
3672 bp->object_info_tbl.v1_5 = tbl_v1_5;
3673 } else {
3674 ASSERT(0);
3675 return false;
3676 }
3677
3678 dal_firmware_parser_init_cmd_tbl(bp);
3679 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
3680
3681 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
3682 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
3683 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
3684
3685 return true;
3686 }
3687
firmware_parser_create(struct bp_init_data * init,enum dce_version dce_version)3688 struct dc_bios *firmware_parser_create(
3689 struct bp_init_data *init,
3690 enum dce_version dce_version)
3691 {
3692 struct bios_parser *bp = NULL;
3693
3694 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
3695 if (!bp)
3696 return NULL;
3697
3698 if (bios_parser2_construct(bp, init, dce_version))
3699 return &bp->base;
3700
3701 kfree(bp);
3702 return NULL;
3703 }
3704
3705
3706