1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
4  *
5  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6  *
7  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
8  *          Younghwan Joo <yhwan.joo@samsung.com>
9  */
10 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
11 
12 #include <linux/device.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/firmware.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
29 #include <linux/videodev2.h>
30 #include <media/videobuf2-dma-contig.h>
31 
32 #include "media-dev.h"
33 #include "fimc-is.h"
34 #include "fimc-is-command.h"
35 #include "fimc-is-errno.h"
36 #include "fimc-is-i2c.h"
37 #include "fimc-is-param.h"
38 #include "fimc-is-regs.h"
39 
40 
41 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
42 	[ISS_CLK_PPMUISPX]		= "ppmuispx",
43 	[ISS_CLK_PPMUISPMX]		= "ppmuispmx",
44 	[ISS_CLK_LITE0]			= "lite0",
45 	[ISS_CLK_LITE1]			= "lite1",
46 	[ISS_CLK_MPLL]			= "mpll",
47 	[ISS_CLK_ISP]			= "isp",
48 	[ISS_CLK_DRC]			= "drc",
49 	[ISS_CLK_FD]			= "fd",
50 	[ISS_CLK_MCUISP]		= "mcuisp",
51 	[ISS_CLK_GICISP]		= "gicisp",
52 	[ISS_CLK_PWM_ISP]		= "pwm_isp",
53 	[ISS_CLK_MCUCTL_ISP]		= "mcuctl_isp",
54 	[ISS_CLK_UART]			= "uart",
55 	[ISS_CLK_ISP_DIV0]		= "ispdiv0",
56 	[ISS_CLK_ISP_DIV1]		= "ispdiv1",
57 	[ISS_CLK_MCUISP_DIV0]		= "mcuispdiv0",
58 	[ISS_CLK_MCUISP_DIV1]		= "mcuispdiv1",
59 	[ISS_CLK_ACLK200]		= "aclk200",
60 	[ISS_CLK_ACLK200_DIV]		= "div_aclk200",
61 	[ISS_CLK_ACLK400MCUISP]		= "aclk400mcuisp",
62 	[ISS_CLK_ACLK400MCUISP_DIV]	= "div_aclk400mcuisp",
63 };
64 
fimc_is_put_clocks(struct fimc_is * is)65 static void fimc_is_put_clocks(struct fimc_is *is)
66 {
67 	int i;
68 
69 	for (i = 0; i < ISS_CLKS_MAX; i++) {
70 		if (IS_ERR(is->clocks[i]))
71 			continue;
72 		clk_put(is->clocks[i]);
73 		is->clocks[i] = ERR_PTR(-EINVAL);
74 	}
75 }
76 
fimc_is_get_clocks(struct fimc_is * is)77 static int fimc_is_get_clocks(struct fimc_is *is)
78 {
79 	int i, ret;
80 
81 	for (i = 0; i < ISS_CLKS_MAX; i++)
82 		is->clocks[i] = ERR_PTR(-EINVAL);
83 
84 	for (i = 0; i < ISS_CLKS_MAX; i++) {
85 		is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
86 		if (IS_ERR(is->clocks[i])) {
87 			ret = PTR_ERR(is->clocks[i]);
88 			goto err;
89 		}
90 	}
91 
92 	return 0;
93 err:
94 	fimc_is_put_clocks(is);
95 	dev_err(&is->pdev->dev, "failed to get clock: %s\n",
96 		fimc_is_clocks[i]);
97 	return ret;
98 }
99 
fimc_is_setup_clocks(struct fimc_is * is)100 static int fimc_is_setup_clocks(struct fimc_is *is)
101 {
102 	int ret;
103 
104 	ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
105 					is->clocks[ISS_CLK_ACLK200_DIV]);
106 	if (ret < 0)
107 		return ret;
108 
109 	ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
110 					is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
111 	if (ret < 0)
112 		return ret;
113 
114 	ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
115 	if (ret < 0)
116 		return ret;
117 
118 	ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
119 	if (ret < 0)
120 		return ret;
121 
122 	ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
123 					ATCLK_MCUISP_FREQUENCY);
124 	if (ret < 0)
125 		return ret;
126 
127 	return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
128 					ATCLK_MCUISP_FREQUENCY);
129 }
130 
fimc_is_enable_clocks(struct fimc_is * is)131 static int fimc_is_enable_clocks(struct fimc_is *is)
132 {
133 	int i, ret;
134 
135 	for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
136 		if (IS_ERR(is->clocks[i]))
137 			continue;
138 		ret = clk_prepare_enable(is->clocks[i]);
139 		if (ret < 0) {
140 			dev_err(&is->pdev->dev, "clock %s enable failed\n",
141 				fimc_is_clocks[i]);
142 			for (--i; i >= 0; i--)
143 				clk_disable_unprepare(is->clocks[i]);
144 			return ret;
145 		}
146 		pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
147 	}
148 	return 0;
149 }
150 
fimc_is_disable_clocks(struct fimc_is * is)151 static void fimc_is_disable_clocks(struct fimc_is *is)
152 {
153 	int i;
154 
155 	for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
156 		if (!IS_ERR(is->clocks[i])) {
157 			clk_disable_unprepare(is->clocks[i]);
158 			pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
159 		}
160 	}
161 }
162 
fimc_is_parse_sensor_config(struct fimc_is * is,unsigned int index,struct device_node * node)163 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
164 						struct device_node *node)
165 {
166 	struct fimc_is_sensor *sensor = &is->sensor[index];
167 	struct device_node *ep, *port;
168 	u32 tmp = 0;
169 	int ret;
170 
171 	sensor->drvdata = fimc_is_sensor_get_drvdata(node);
172 	if (!sensor->drvdata) {
173 		dev_err(&is->pdev->dev, "no driver data found for: %pOF\n",
174 							 node);
175 		return -EINVAL;
176 	}
177 
178 	ep = of_graph_get_next_endpoint(node, NULL);
179 	if (!ep)
180 		return -ENXIO;
181 
182 	port = of_graph_get_remote_port(ep);
183 	of_node_put(ep);
184 	if (!port)
185 		return -ENXIO;
186 
187 	/* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
188 	ret = of_property_read_u32(port, "reg", &tmp);
189 	if (ret < 0) {
190 		dev_err(&is->pdev->dev, "reg property not found at: %pOF\n",
191 							 port);
192 		of_node_put(port);
193 		return ret;
194 	}
195 
196 	of_node_put(port);
197 	sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
198 	return 0;
199 }
200 
fimc_is_register_subdevs(struct fimc_is * is)201 static int fimc_is_register_subdevs(struct fimc_is *is)
202 {
203 	struct device_node *i2c_bus, *child;
204 	int ret, index = 0;
205 
206 	ret = fimc_isp_subdev_create(&is->isp);
207 	if (ret < 0)
208 		return ret;
209 
210 	for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
211 		for_each_available_child_of_node(i2c_bus, child) {
212 			ret = fimc_is_parse_sensor_config(is, index, child);
213 
214 			if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
215 				of_node_put(child);
216 				return ret;
217 			}
218 			index++;
219 		}
220 	}
221 	return 0;
222 }
223 
fimc_is_unregister_subdevs(struct fimc_is * is)224 static int fimc_is_unregister_subdevs(struct fimc_is *is)
225 {
226 	fimc_isp_subdev_destroy(&is->isp);
227 	return 0;
228 }
229 
fimc_is_load_setfile(struct fimc_is * is,char * file_name)230 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
231 {
232 	const struct firmware *fw;
233 	void *buf;
234 	int ret;
235 
236 	ret = request_firmware(&fw, file_name, &is->pdev->dev);
237 	if (ret < 0) {
238 		dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
239 		return ret;
240 	}
241 	buf = is->memory.vaddr + is->setfile.base;
242 	memcpy(buf, fw->data, fw->size);
243 	fimc_is_mem_barrier();
244 	is->setfile.size = fw->size;
245 
246 	pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
247 
248 	memcpy(is->fw.setfile_info,
249 		fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
250 		FIMC_IS_SETFILE_INFO_LEN - 1);
251 
252 	is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
253 	is->setfile.state = 1;
254 
255 	pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
256 		 is->setfile.base, fw->size);
257 
258 	release_firmware(fw);
259 	return ret;
260 }
261 
fimc_is_cpu_set_power(struct fimc_is * is,int on)262 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
263 {
264 	unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
265 
266 	if (on) {
267 		/* Disable watchdog */
268 		mcuctl_write(0, is, REG_WDT_ISP);
269 
270 		/* Cortex-A5 start address setting */
271 		mcuctl_write(is->memory.addr, is, MCUCTL_REG_BBOAR);
272 
273 		/* Enable and start Cortex-A5 */
274 		pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
275 		pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
276 	} else {
277 		/* A5 power off */
278 		pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
279 		pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
280 
281 		while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
282 			if (timeout == 0)
283 				return -ETIME;
284 			timeout--;
285 			udelay(1);
286 		}
287 	}
288 
289 	return 0;
290 }
291 
292 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
fimc_is_wait_event(struct fimc_is * is,unsigned long bit,unsigned int state,unsigned int timeout)293 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
294 		       unsigned int state, unsigned int timeout)
295 {
296 
297 	int ret = wait_event_timeout(is->irq_queue,
298 				     !state ^ test_bit(bit, &is->state),
299 				     timeout);
300 	if (ret == 0) {
301 		dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
302 		return -ETIME;
303 	}
304 	return 0;
305 }
306 
fimc_is_start_firmware(struct fimc_is * is)307 int fimc_is_start_firmware(struct fimc_is *is)
308 {
309 	struct device *dev = &is->pdev->dev;
310 	int ret;
311 
312 	if (is->fw.f_w == NULL) {
313 		dev_err(dev, "firmware is not loaded\n");
314 		return -EINVAL;
315 	}
316 
317 	memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
318 	wmb();
319 
320 	ret = fimc_is_cpu_set_power(is, 1);
321 	if (ret < 0)
322 		return ret;
323 
324 	ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
325 				 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
326 	if (ret < 0)
327 		dev_err(dev, "FIMC-IS CPU power on failed\n");
328 
329 	return ret;
330 }
331 
332 /* Allocate working memory for the FIMC-IS CPU. */
fimc_is_alloc_cpu_memory(struct fimc_is * is)333 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
334 {
335 	struct device *dev = &is->pdev->dev;
336 
337 	is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
338 					      &is->memory.addr, GFP_KERNEL);
339 	if (is->memory.vaddr == NULL)
340 		return -ENOMEM;
341 
342 	is->memory.size = FIMC_IS_CPU_MEM_SIZE;
343 
344 	dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.addr);
345 
346 	if (((u32)is->memory.addr) & FIMC_IS_FW_ADDR_MASK) {
347 		dev_err(dev, "invalid firmware memory alignment: %#x\n",
348 			(u32)is->memory.addr);
349 		dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
350 				  is->memory.addr);
351 		return -EIO;
352 	}
353 
354 	is->is_p_region = (struct is_region *)(is->memory.vaddr +
355 				FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
356 
357 	is->is_dma_p_region = is->memory.addr +
358 				FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
359 
360 	is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
361 				FIMC_IS_SHARED_REGION_OFFSET);
362 	return 0;
363 }
364 
fimc_is_free_cpu_memory(struct fimc_is * is)365 static void fimc_is_free_cpu_memory(struct fimc_is *is)
366 {
367 	struct device *dev = &is->pdev->dev;
368 
369 	if (is->memory.vaddr == NULL)
370 		return;
371 
372 	dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
373 			  is->memory.addr);
374 }
375 
fimc_is_load_firmware(const struct firmware * fw,void * context)376 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
377 {
378 	struct fimc_is *is = context;
379 	struct device *dev = &is->pdev->dev;
380 	void *buf;
381 	int ret;
382 
383 	if (fw == NULL) {
384 		dev_err(dev, "firmware request failed\n");
385 		return;
386 	}
387 	mutex_lock(&is->lock);
388 
389 	if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
390 		dev_err(dev, "wrong firmware size: %zu\n", fw->size);
391 		goto done;
392 	}
393 
394 	is->fw.size = fw->size;
395 
396 	ret = fimc_is_alloc_cpu_memory(is);
397 	if (ret < 0) {
398 		dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
399 		goto done;
400 	}
401 
402 	memcpy(is->memory.vaddr, fw->data, fw->size);
403 	wmb();
404 
405 	/* Read firmware description. */
406 	buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
407 	memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
408 	is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
409 
410 	buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
411 	memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
412 	is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
413 
414 	is->fw.state = 1;
415 
416 	dev_info(dev, "loaded firmware: %s, rev. %s\n",
417 		 is->fw.info, is->fw.version);
418 	dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, &is->memory.addr);
419 
420 	is->is_shared_region->chip_id = 0xe4412;
421 	is->is_shared_region->chip_rev_no = 1;
422 
423 	fimc_is_mem_barrier();
424 
425 	/*
426 	 * FIXME: The firmware is not being released for now, as it is
427 	 * needed around for copying to the IS working memory every
428 	 * time before the Cortex-A5 is restarted.
429 	 */
430 	release_firmware(is->fw.f_w);
431 	is->fw.f_w = fw;
432 done:
433 	mutex_unlock(&is->lock);
434 }
435 
fimc_is_request_firmware(struct fimc_is * is,const char * fw_name)436 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
437 {
438 	return request_firmware_nowait(THIS_MODULE,
439 				FW_ACTION_UEVENT, fw_name, &is->pdev->dev,
440 				GFP_KERNEL, is, fimc_is_load_firmware);
441 }
442 
443 /* General IS interrupt handler */
fimc_is_general_irq_handler(struct fimc_is * is)444 static void fimc_is_general_irq_handler(struct fimc_is *is)
445 {
446 	is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
447 
448 	switch (is->i2h_cmd.cmd) {
449 	case IHC_GET_SENSOR_NUM:
450 		fimc_is_hw_get_params(is, 1);
451 		fimc_is_hw_wait_intmsr0_intmsd0(is);
452 		fimc_is_hw_set_sensor_num(is);
453 		pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
454 		break;
455 	case IHC_SET_FACE_MARK:
456 	case IHC_FRAME_DONE:
457 		fimc_is_hw_get_params(is, 2);
458 		break;
459 	case IHC_SET_SHOT_MARK:
460 	case IHC_AA_DONE:
461 	case IH_REPLY_DONE:
462 		fimc_is_hw_get_params(is, 3);
463 		break;
464 	case IH_REPLY_NOT_DONE:
465 		fimc_is_hw_get_params(is, 4);
466 		break;
467 	case IHC_NOT_READY:
468 		break;
469 	default:
470 		pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
471 	}
472 
473 	fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
474 
475 	switch (is->i2h_cmd.cmd) {
476 	case IHC_GET_SENSOR_NUM:
477 		fimc_is_hw_set_intgr0_gd0(is);
478 		set_bit(IS_ST_A5_PWR_ON, &is->state);
479 		break;
480 
481 	case IHC_SET_SHOT_MARK:
482 		break;
483 
484 	case IHC_SET_FACE_MARK:
485 		is->fd_header.count = is->i2h_cmd.args[0];
486 		is->fd_header.index = is->i2h_cmd.args[1];
487 		is->fd_header.offset = 0;
488 		break;
489 
490 	case IHC_FRAME_DONE:
491 		break;
492 
493 	case IHC_AA_DONE:
494 		pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
495 			 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
496 		break;
497 
498 	case IH_REPLY_DONE:
499 		pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
500 
501 		switch (is->i2h_cmd.args[0]) {
502 		case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
503 			/* Get CAC margin */
504 			set_bit(IS_ST_CHANGE_MODE, &is->state);
505 			is->isp.cac_margin_x = is->i2h_cmd.args[1];
506 			is->isp.cac_margin_y = is->i2h_cmd.args[2];
507 			pr_debug("CAC margin (x,y): (%d,%d)\n",
508 				 is->isp.cac_margin_x, is->isp.cac_margin_y);
509 			break;
510 
511 		case HIC_STREAM_ON:
512 			clear_bit(IS_ST_STREAM_OFF, &is->state);
513 			set_bit(IS_ST_STREAM_ON, &is->state);
514 			break;
515 
516 		case HIC_STREAM_OFF:
517 			clear_bit(IS_ST_STREAM_ON, &is->state);
518 			set_bit(IS_ST_STREAM_OFF, &is->state);
519 			break;
520 
521 		case HIC_SET_PARAMETER:
522 			is->config[is->config_index].p_region_index[0] = 0;
523 			is->config[is->config_index].p_region_index[1] = 0;
524 			set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
525 			pr_debug("HIC_SET_PARAMETER\n");
526 			break;
527 
528 		case HIC_GET_PARAMETER:
529 			break;
530 
531 		case HIC_SET_TUNE:
532 			break;
533 
534 		case HIC_GET_STATUS:
535 			break;
536 
537 		case HIC_OPEN_SENSOR:
538 			set_bit(IS_ST_OPEN_SENSOR, &is->state);
539 			pr_debug("data lanes: %d, settle line: %d\n",
540 				 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
541 			break;
542 
543 		case HIC_CLOSE_SENSOR:
544 			clear_bit(IS_ST_OPEN_SENSOR, &is->state);
545 			is->sensor_index = 0;
546 			break;
547 
548 		case HIC_MSG_TEST:
549 			pr_debug("config MSG level completed\n");
550 			break;
551 
552 		case HIC_POWER_DOWN:
553 			clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
554 			break;
555 
556 		case HIC_GET_SET_FILE_ADDR:
557 			is->setfile.base = is->i2h_cmd.args[1];
558 			set_bit(IS_ST_SETFILE_LOADED, &is->state);
559 			break;
560 
561 		case HIC_LOAD_SET_FILE:
562 			set_bit(IS_ST_SETFILE_LOADED, &is->state);
563 			break;
564 		}
565 		break;
566 
567 	case IH_REPLY_NOT_DONE:
568 		pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
569 		       is->i2h_cmd.args[1],
570 		       fimc_is_strerr(is->i2h_cmd.args[1]));
571 
572 		if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
573 			pr_err("IS_ERROR_TIME_OUT\n");
574 
575 		switch (is->i2h_cmd.args[1]) {
576 		case IS_ERROR_SET_PARAMETER:
577 			fimc_is_mem_barrier();
578 		}
579 
580 		switch (is->i2h_cmd.args[0]) {
581 		case HIC_SET_PARAMETER:
582 			is->config[is->config_index].p_region_index[0] = 0;
583 			is->config[is->config_index].p_region_index[1] = 0;
584 			set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
585 			break;
586 		}
587 		break;
588 
589 	case IHC_NOT_READY:
590 		pr_err("IS control sequence error: Not Ready\n");
591 		break;
592 	}
593 
594 	wake_up(&is->irq_queue);
595 }
596 
fimc_is_irq_handler(int irq,void * priv)597 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
598 {
599 	struct fimc_is *is = priv;
600 	unsigned long flags;
601 	u32 status;
602 
603 	spin_lock_irqsave(&is->slock, flags);
604 	status = mcuctl_read(is, MCUCTL_REG_INTSR1);
605 
606 	if (status & (1UL << FIMC_IS_INT_GENERAL))
607 		fimc_is_general_irq_handler(is);
608 
609 	if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
610 		fimc_isp_irq_handler(is);
611 
612 	spin_unlock_irqrestore(&is->slock, flags);
613 	return IRQ_HANDLED;
614 }
615 
fimc_is_hw_open_sensor(struct fimc_is * is,struct fimc_is_sensor * sensor)616 static int fimc_is_hw_open_sensor(struct fimc_is *is,
617 				  struct fimc_is_sensor *sensor)
618 {
619 	struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
620 
621 	fimc_is_hw_wait_intmsr0_intmsd0(is);
622 
623 	soe->self_calibration_mode = 1;
624 	soe->actuator_type = 0;
625 	soe->mipi_lane_num = 0;
626 	soe->mclk = 0;
627 	soe->mipi_speed	= 0;
628 	soe->fast_open_sensor = 0;
629 	soe->i2c_sclk = 88000000;
630 
631 	fimc_is_mem_barrier();
632 
633 	/*
634 	 * Some user space use cases hang up here without this
635 	 * empirically chosen delay.
636 	 */
637 	udelay(100);
638 
639 	mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
640 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
641 	mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
642 	mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
643 	mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
644 
645 	fimc_is_hw_set_intgr0_gd0(is);
646 
647 	return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
648 				  sensor->drvdata->open_timeout);
649 }
650 
651 
fimc_is_hw_initialize(struct fimc_is * is)652 int fimc_is_hw_initialize(struct fimc_is *is)
653 {
654 	static const int config_ids[] = {
655 		IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
656 		IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
657 	};
658 	struct device *dev = &is->pdev->dev;
659 	u32 prev_id;
660 	int i, ret;
661 
662 	/* Sensor initialization. Only one sensor is currently supported. */
663 	ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
664 	if (ret < 0)
665 		return ret;
666 
667 	/* Get the setfile address. */
668 	fimc_is_hw_get_setfile_addr(is);
669 
670 	ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
671 				 FIMC_IS_CONFIG_TIMEOUT);
672 	if (ret < 0) {
673 		dev_err(dev, "get setfile address timed out\n");
674 		return ret;
675 	}
676 	pr_debug("setfile.base: %#x\n", is->setfile.base);
677 
678 	/* Load the setfile. */
679 	fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
680 	clear_bit(IS_ST_SETFILE_LOADED, &is->state);
681 	fimc_is_hw_load_setfile(is);
682 	ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
683 				 FIMC_IS_CONFIG_TIMEOUT);
684 	if (ret < 0) {
685 		dev_err(dev, "loading setfile timed out\n");
686 		return ret;
687 	}
688 
689 	pr_debug("setfile: base: %#x, size: %d\n",
690 		 is->setfile.base, is->setfile.size);
691 	pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
692 
693 	/* Check magic number. */
694 	if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
695 	    FIMC_IS_MAGIC_NUMBER) {
696 		dev_err(dev, "magic number error!\n");
697 		return -EIO;
698 	}
699 
700 	pr_debug("shared region: %pad, parameter region: %pad\n",
701 		 &is->memory.addr + FIMC_IS_SHARED_REGION_OFFSET,
702 		 &is->is_dma_p_region);
703 
704 	is->setfile.sub_index = 0;
705 
706 	/* Stream off. */
707 	fimc_is_hw_stream_off(is);
708 	ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
709 				 FIMC_IS_CONFIG_TIMEOUT);
710 	if (ret < 0) {
711 		dev_err(dev, "stream off timeout\n");
712 		return ret;
713 	}
714 
715 	/* Preserve previous mode. */
716 	prev_id = is->config_index;
717 
718 	/* Set initial parameter values. */
719 	for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
720 		is->config_index = config_ids[i];
721 		fimc_is_set_initial_params(is);
722 		ret = fimc_is_itf_s_param(is, true);
723 		if (ret < 0) {
724 			is->config_index = prev_id;
725 			return ret;
726 		}
727 	}
728 	is->config_index = prev_id;
729 
730 	set_bit(IS_ST_INIT_DONE, &is->state);
731 	dev_info(dev, "initialization sequence completed (%d)\n",
732 						is->config_index);
733 	return 0;
734 }
735 
fimc_is_show(struct seq_file * s,void * data)736 static int fimc_is_show(struct seq_file *s, void *data)
737 {
738 	struct fimc_is *is = s->private;
739 	const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
740 
741 	if (is->memory.vaddr == NULL) {
742 		dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
743 		return -EIO;
744 	}
745 
746 	seq_printf(s, "%s\n", buf);
747 	return 0;
748 }
749 
750 DEFINE_SHOW_ATTRIBUTE(fimc_is);
751 
fimc_is_debugfs_remove(struct fimc_is * is)752 static void fimc_is_debugfs_remove(struct fimc_is *is)
753 {
754 	debugfs_remove_recursive(is->debugfs_entry);
755 	is->debugfs_entry = NULL;
756 }
757 
fimc_is_debugfs_create(struct fimc_is * is)758 static void fimc_is_debugfs_create(struct fimc_is *is)
759 {
760 	is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
761 
762 	debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry, is,
763 			    &fimc_is_fops);
764 }
765 
766 static int fimc_is_runtime_resume(struct device *dev);
767 static int fimc_is_runtime_suspend(struct device *dev);
768 
fimc_is_probe(struct platform_device * pdev)769 static int fimc_is_probe(struct platform_device *pdev)
770 {
771 	struct device *dev = &pdev->dev;
772 	struct fimc_is *is;
773 	struct resource res;
774 	struct device_node *node;
775 	int ret;
776 
777 	is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
778 	if (!is)
779 		return -ENOMEM;
780 
781 	is->pdev = pdev;
782 	is->isp.pdev = pdev;
783 
784 	init_waitqueue_head(&is->irq_queue);
785 	spin_lock_init(&is->slock);
786 	mutex_init(&is->lock);
787 
788 	ret = of_address_to_resource(dev->of_node, 0, &res);
789 	if (ret < 0)
790 		return ret;
791 
792 	is->regs = devm_ioremap_resource(dev, &res);
793 	if (IS_ERR(is->regs))
794 		return PTR_ERR(is->regs);
795 
796 	node = of_get_child_by_name(dev->of_node, "pmu");
797 	if (!node)
798 		return -ENODEV;
799 
800 	is->pmu_regs = of_iomap(node, 0);
801 	of_node_put(node);
802 	if (!is->pmu_regs)
803 		return -ENOMEM;
804 
805 	is->irq = irq_of_parse_and_map(dev->of_node, 0);
806 	if (!is->irq) {
807 		dev_err(dev, "no irq found\n");
808 		ret = -EINVAL;
809 		goto err_iounmap;
810 	}
811 
812 	ret = fimc_is_get_clocks(is);
813 	if (ret < 0)
814 		goto err_iounmap;
815 
816 	platform_set_drvdata(pdev, is);
817 
818 	ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
819 	if (ret < 0) {
820 		dev_err(dev, "irq request failed\n");
821 		goto err_clk;
822 	}
823 	pm_runtime_enable(dev);
824 
825 	if (!pm_runtime_enabled(dev)) {
826 		ret = fimc_is_runtime_resume(dev);
827 		if (ret < 0)
828 			goto err_irq;
829 	}
830 
831 	ret = pm_runtime_resume_and_get(dev);
832 	if (ret < 0)
833 		goto err_pm_disable;
834 
835 	vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
836 
837 	ret = devm_of_platform_populate(dev);
838 	if (ret < 0)
839 		goto err_pm;
840 
841 	/*
842 	 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
843 	 * will be created within the subdev's registered() callback.
844 	 */
845 	ret = fimc_is_register_subdevs(is);
846 	if (ret < 0)
847 		goto err_pm;
848 
849 	fimc_is_debugfs_create(is);
850 
851 	ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
852 	if (ret < 0)
853 		goto err_dfs;
854 
855 	pm_runtime_put_sync(dev);
856 
857 	dev_dbg(dev, "FIMC-IS registered successfully\n");
858 	return 0;
859 
860 err_dfs:
861 	fimc_is_debugfs_remove(is);
862 	fimc_is_unregister_subdevs(is);
863 err_pm:
864 	pm_runtime_put_noidle(dev);
865 	if (!pm_runtime_enabled(dev))
866 		fimc_is_runtime_suspend(dev);
867 err_pm_disable:
868 	pm_runtime_disable(dev);
869 err_irq:
870 	free_irq(is->irq, is);
871 err_clk:
872 	fimc_is_put_clocks(is);
873 err_iounmap:
874 	iounmap(is->pmu_regs);
875 	return ret;
876 }
877 
fimc_is_runtime_resume(struct device * dev)878 static int fimc_is_runtime_resume(struct device *dev)
879 {
880 	struct fimc_is *is = dev_get_drvdata(dev);
881 	int ret;
882 
883 	ret = fimc_is_setup_clocks(is);
884 	if (ret)
885 		return ret;
886 
887 	return fimc_is_enable_clocks(is);
888 }
889 
fimc_is_runtime_suspend(struct device * dev)890 static int fimc_is_runtime_suspend(struct device *dev)
891 {
892 	struct fimc_is *is = dev_get_drvdata(dev);
893 
894 	fimc_is_disable_clocks(is);
895 	return 0;
896 }
897 
898 #ifdef CONFIG_PM_SLEEP
fimc_is_resume(struct device * dev)899 static int fimc_is_resume(struct device *dev)
900 {
901 	/* TODO: */
902 	return 0;
903 }
904 
fimc_is_suspend(struct device * dev)905 static int fimc_is_suspend(struct device *dev)
906 {
907 	struct fimc_is *is = dev_get_drvdata(dev);
908 
909 	/* TODO: */
910 	if (test_bit(IS_ST_A5_PWR_ON, &is->state))
911 		return -EBUSY;
912 
913 	return 0;
914 }
915 #endif /* CONFIG_PM_SLEEP */
916 
fimc_is_remove(struct platform_device * pdev)917 static int fimc_is_remove(struct platform_device *pdev)
918 {
919 	struct device *dev = &pdev->dev;
920 	struct fimc_is *is = dev_get_drvdata(dev);
921 
922 	pm_runtime_disable(dev);
923 	pm_runtime_set_suspended(dev);
924 	if (!pm_runtime_status_suspended(dev))
925 		fimc_is_runtime_suspend(dev);
926 	free_irq(is->irq, is);
927 	fimc_is_unregister_subdevs(is);
928 	vb2_dma_contig_clear_max_seg_size(dev);
929 	fimc_is_put_clocks(is);
930 	iounmap(is->pmu_regs);
931 	fimc_is_debugfs_remove(is);
932 	release_firmware(is->fw.f_w);
933 	fimc_is_free_cpu_memory(is);
934 
935 	return 0;
936 }
937 
938 static const struct of_device_id fimc_is_of_match[] = {
939 	{ .compatible = "samsung,exynos4212-fimc-is" },
940 	{ /* sentinel */ },
941 };
942 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
943 
944 static const struct dev_pm_ops fimc_is_pm_ops = {
945 	SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
946 	SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
947 			   NULL)
948 };
949 
950 static struct platform_driver fimc_is_driver = {
951 	.probe		= fimc_is_probe,
952 	.remove		= fimc_is_remove,
953 	.driver = {
954 		.of_match_table	= fimc_is_of_match,
955 		.name		= FIMC_IS_DRV_NAME,
956 		.pm		= &fimc_is_pm_ops,
957 	}
958 };
959 
fimc_is_module_init(void)960 static int fimc_is_module_init(void)
961 {
962 	int ret;
963 
964 	ret = fimc_is_register_i2c_driver();
965 	if (ret < 0)
966 		return ret;
967 
968 	ret = platform_driver_register(&fimc_is_driver);
969 
970 	if (ret < 0)
971 		fimc_is_unregister_i2c_driver();
972 
973 	return ret;
974 }
975 
fimc_is_module_exit(void)976 static void fimc_is_module_exit(void)
977 {
978 	fimc_is_unregister_i2c_driver();
979 	platform_driver_unregister(&fimc_is_driver);
980 }
981 
982 module_init(fimc_is_module_init);
983 module_exit(fimc_is_module_exit);
984 
985 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
986 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
987 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
988 MODULE_LICENSE("GPL v2");
989