1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
4  *
5  * Copyright (C) 2008 Marvell Semiconductor
6  *
7  * References:
8  * - Unified Layer 2 Cache for Feroceon CPU Cores,
9  *   Document ID MV-S104858-00, Rev. A, October 23 2007.
10  */
11 
12 #include <linux/init.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/highmem.h>
16 #include <linux/io.h>
17 #include <asm/cacheflush.h>
18 #include <asm/cp15.h>
19 #include <asm/hardware/cache-feroceon-l2.h>
20 
21 #define L2_WRITETHROUGH_KIRKWOOD	BIT(4)
22 
23 /*
24  * Low-level cache maintenance operations.
25  *
26  * As well as the regular 'clean/invalidate/flush L2 cache line by
27  * MVA' instructions, the Feroceon L2 cache controller also features
28  * 'clean/invalidate L2 range by MVA' operations.
29  *
30  * Cache range operations are initiated by writing the start and
31  * end addresses to successive cp15 registers, and process every
32  * cache line whose first byte address lies in the inclusive range
33  * [start:end].
34  *
35  * The cache range operations stall the CPU pipeline until completion.
36  *
37  * The range operations require two successive cp15 writes, in
38  * between which we don't want to be preempted.
39  */
40 
l2_get_va(unsigned long paddr)41 static inline unsigned long l2_get_va(unsigned long paddr)
42 {
43 #ifdef CONFIG_HIGHMEM
44 	/*
45 	 * Because range ops can't be done on physical addresses,
46 	 * we simply install a virtual mapping for it only for the
47 	 * TLB lookup to occur, hence no need to flush the untouched
48 	 * memory mapping afterwards (note: a cache flush may happen
49 	 * in some circumstances depending on the path taken in kunmap_atomic).
50 	 */
51 	void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);
52 	return (unsigned long)vaddr + (paddr & ~PAGE_MASK);
53 #else
54 	return __phys_to_virt(paddr);
55 #endif
56 }
57 
l2_put_va(unsigned long vaddr)58 static inline void l2_put_va(unsigned long vaddr)
59 {
60 #ifdef CONFIG_HIGHMEM
61 	kunmap_atomic((void *)vaddr);
62 #endif
63 }
64 
l2_clean_pa(unsigned long addr)65 static inline void l2_clean_pa(unsigned long addr)
66 {
67 	__asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
68 }
69 
l2_clean_pa_range(unsigned long start,unsigned long end)70 static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
71 {
72 	unsigned long va_start, va_end, flags;
73 
74 	/*
75 	 * Make sure 'start' and 'end' reference the same page, as
76 	 * L2 is PIPT and range operations only do a TLB lookup on
77 	 * the start address.
78 	 */
79 	BUG_ON((start ^ end) >> PAGE_SHIFT);
80 
81 	va_start = l2_get_va(start);
82 	va_end = va_start + (end - start);
83 	raw_local_irq_save(flags);
84 	__asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
85 		"mcr p15, 1, %1, c15, c9, 5"
86 		: : "r" (va_start), "r" (va_end));
87 	raw_local_irq_restore(flags);
88 	l2_put_va(va_start);
89 }
90 
l2_clean_inv_pa(unsigned long addr)91 static inline void l2_clean_inv_pa(unsigned long addr)
92 {
93 	__asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
94 }
95 
l2_inv_pa(unsigned long addr)96 static inline void l2_inv_pa(unsigned long addr)
97 {
98 	__asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
99 }
100 
l2_inv_pa_range(unsigned long start,unsigned long end)101 static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
102 {
103 	unsigned long va_start, va_end, flags;
104 
105 	/*
106 	 * Make sure 'start' and 'end' reference the same page, as
107 	 * L2 is PIPT and range operations only do a TLB lookup on
108 	 * the start address.
109 	 */
110 	BUG_ON((start ^ end) >> PAGE_SHIFT);
111 
112 	va_start = l2_get_va(start);
113 	va_end = va_start + (end - start);
114 	raw_local_irq_save(flags);
115 	__asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
116 		"mcr p15, 1, %1, c15, c11, 5"
117 		: : "r" (va_start), "r" (va_end));
118 	raw_local_irq_restore(flags);
119 	l2_put_va(va_start);
120 }
121 
l2_inv_all(void)122 static inline void l2_inv_all(void)
123 {
124 	__asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0));
125 }
126 
127 /*
128  * Linux primitives.
129  *
130  * Note that the end addresses passed to Linux primitives are
131  * noninclusive, while the hardware cache range operations use
132  * inclusive start and end addresses.
133  */
134 #define CACHE_LINE_SIZE		32
135 #define MAX_RANGE_SIZE		1024
136 
137 static int l2_wt_override;
138 
calc_range_end(unsigned long start,unsigned long end)139 static unsigned long calc_range_end(unsigned long start, unsigned long end)
140 {
141 	unsigned long range_end;
142 
143 	BUG_ON(start & (CACHE_LINE_SIZE - 1));
144 	BUG_ON(end & (CACHE_LINE_SIZE - 1));
145 
146 	/*
147 	 * Try to process all cache lines between 'start' and 'end'.
148 	 */
149 	range_end = end;
150 
151 	/*
152 	 * Limit the number of cache lines processed at once,
153 	 * since cache range operations stall the CPU pipeline
154 	 * until completion.
155 	 */
156 	if (range_end > start + MAX_RANGE_SIZE)
157 		range_end = start + MAX_RANGE_SIZE;
158 
159 	/*
160 	 * Cache range operations can't straddle a page boundary.
161 	 */
162 	if (range_end > (start | (PAGE_SIZE - 1)) + 1)
163 		range_end = (start | (PAGE_SIZE - 1)) + 1;
164 
165 	return range_end;
166 }
167 
feroceon_l2_inv_range(unsigned long start,unsigned long end)168 static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
169 {
170 	/*
171 	 * Clean and invalidate partial first cache line.
172 	 */
173 	if (start & (CACHE_LINE_SIZE - 1)) {
174 		l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
175 		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
176 	}
177 
178 	/*
179 	 * Clean and invalidate partial last cache line.
180 	 */
181 	if (start < end && end & (CACHE_LINE_SIZE - 1)) {
182 		l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
183 		end &= ~(CACHE_LINE_SIZE - 1);
184 	}
185 
186 	/*
187 	 * Invalidate all full cache lines between 'start' and 'end'.
188 	 */
189 	while (start < end) {
190 		unsigned long range_end = calc_range_end(start, end);
191 		l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
192 		start = range_end;
193 	}
194 
195 	dsb();
196 }
197 
feroceon_l2_clean_range(unsigned long start,unsigned long end)198 static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
199 {
200 	/*
201 	 * If L2 is forced to WT, the L2 will always be clean and we
202 	 * don't need to do anything here.
203 	 */
204 	if (!l2_wt_override) {
205 		start &= ~(CACHE_LINE_SIZE - 1);
206 		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
207 		while (start != end) {
208 			unsigned long range_end = calc_range_end(start, end);
209 			l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
210 			start = range_end;
211 		}
212 	}
213 
214 	dsb();
215 }
216 
feroceon_l2_flush_range(unsigned long start,unsigned long end)217 static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
218 {
219 	start &= ~(CACHE_LINE_SIZE - 1);
220 	end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
221 	while (start != end) {
222 		unsigned long range_end = calc_range_end(start, end);
223 		if (!l2_wt_override)
224 			l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
225 		l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
226 		start = range_end;
227 	}
228 
229 	dsb();
230 }
231 
232 
233 /*
234  * Routines to disable and re-enable the D-cache and I-cache at run
235  * time.  These are necessary because the L2 cache can only be enabled
236  * or disabled while the L1 Dcache and Icache are both disabled.
237  */
flush_and_disable_dcache(void)238 static int __init flush_and_disable_dcache(void)
239 {
240 	u32 cr;
241 
242 	cr = get_cr();
243 	if (cr & CR_C) {
244 		unsigned long flags;
245 
246 		raw_local_irq_save(flags);
247 		flush_cache_all();
248 		set_cr(cr & ~CR_C);
249 		raw_local_irq_restore(flags);
250 		return 1;
251 	}
252 	return 0;
253 }
254 
enable_dcache(void)255 static void __init enable_dcache(void)
256 {
257 	u32 cr;
258 
259 	cr = get_cr();
260 	set_cr(cr | CR_C);
261 }
262 
__invalidate_icache(void)263 static void __init __invalidate_icache(void)
264 {
265 	__asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
266 }
267 
invalidate_and_disable_icache(void)268 static int __init invalidate_and_disable_icache(void)
269 {
270 	u32 cr;
271 
272 	cr = get_cr();
273 	if (cr & CR_I) {
274 		set_cr(cr & ~CR_I);
275 		__invalidate_icache();
276 		return 1;
277 	}
278 	return 0;
279 }
280 
enable_icache(void)281 static void __init enable_icache(void)
282 {
283 	u32 cr;
284 
285 	cr = get_cr();
286 	set_cr(cr | CR_I);
287 }
288 
read_extra_features(void)289 static inline u32 read_extra_features(void)
290 {
291 	u32 u;
292 
293 	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
294 
295 	return u;
296 }
297 
write_extra_features(u32 u)298 static inline void write_extra_features(u32 u)
299 {
300 	__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
301 }
302 
disable_l2_prefetch(void)303 static void __init disable_l2_prefetch(void)
304 {
305 	u32 u;
306 
307 	/*
308 	 * Read the CPU Extra Features register and verify that the
309 	 * Disable L2 Prefetch bit is set.
310 	 */
311 	u = read_extra_features();
312 	if (!(u & 0x01000000)) {
313 		pr_info("Feroceon L2: Disabling L2 prefetch.\n");
314 		write_extra_features(u | 0x01000000);
315 	}
316 }
317 
enable_l2(void)318 static void __init enable_l2(void)
319 {
320 	u32 u;
321 
322 	u = read_extra_features();
323 	if (!(u & 0x00400000)) {
324 		int i, d;
325 
326 		pr_info("Feroceon L2: Enabling L2\n");
327 
328 		d = flush_and_disable_dcache();
329 		i = invalidate_and_disable_icache();
330 		l2_inv_all();
331 		write_extra_features(u | 0x00400000);
332 		if (i)
333 			enable_icache();
334 		if (d)
335 			enable_dcache();
336 	} else
337 		pr_err(FW_BUG
338 		       "Feroceon L2: bootloader left the L2 cache on!\n");
339 }
340 
feroceon_l2_init(int __l2_wt_override)341 void __init feroceon_l2_init(int __l2_wt_override)
342 {
343 	l2_wt_override = __l2_wt_override;
344 
345 	disable_l2_prefetch();
346 
347 	outer_cache.inv_range = feroceon_l2_inv_range;
348 	outer_cache.clean_range = feroceon_l2_clean_range;
349 	outer_cache.flush_range = feroceon_l2_flush_range;
350 
351 	enable_l2();
352 
353 	pr_info("Feroceon L2: Cache support initialised%s.\n",
354 			 l2_wt_override ? ", in WT override mode" : "");
355 }
356 #ifdef CONFIG_OF
357 static const struct of_device_id feroceon_ids[] __initconst = {
358 	{ .compatible = "marvell,kirkwood-cache"},
359 	{ .compatible = "marvell,feroceon-cache"},
360 	{}
361 };
362 
feroceon_of_init(void)363 int __init feroceon_of_init(void)
364 {
365 	struct device_node *node;
366 	void __iomem *base;
367 	bool l2_wt_override = false;
368 
369 #if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
370 	l2_wt_override = true;
371 #endif
372 
373 	node = of_find_matching_node(NULL, feroceon_ids);
374 	if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
375 		base = of_iomap(node, 0);
376 		if (!base)
377 			return -ENOMEM;
378 
379 		if (l2_wt_override)
380 			writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
381 		else
382 			writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
383 	}
384 
385 	feroceon_l2_init(l2_wt_override);
386 
387 	return 0;
388 }
389 #endif
390