1 /* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
2 *
3 * Samsung SoC MIPI-DSI common driver.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd
6 *
7 * InKi Dae, <inki.dae@samsung.com>
8 * Donghwa Lee, <dh09.lee@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/mutex.h>
19 #include <linux/wait.h>
20 #include <linux/fs.h>
21 #include <linux/mm.h>
22 #include <linux/fb.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/memory.h>
27 #include <linux/delay.h>
28 #include <linux/kthread.h>
29
30 #include <video/mipi_display.h>
31 #include <video/exynos_mipi_dsim.h>
32
33 #include <mach/map.h>
34
35 #include "exynos_mipi_dsi_regs.h"
36 #include "exynos_mipi_dsi_lowlevel.h"
37 #include "exynos_mipi_dsi_common.h"
38
39 #define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
40 #define MIPI_RX_FIFO_READ_DONE 0x30800002
41 #define MIPI_MAX_RX_FIFO 20
42 #define MHZ (1000 * 1000)
43 #define FIN_HZ (24 * MHZ)
44
45 #define DFIN_PLL_MIN_HZ (6 * MHZ)
46 #define DFIN_PLL_MAX_HZ (12 * MHZ)
47
48 #define DFVCO_MIN_HZ (500 * MHZ)
49 #define DFVCO_MAX_HZ (1000 * MHZ)
50
51 #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
52 #define TRY_FIFO_CLEAR (10)
53
54 /* MIPI-DSIM status types. */
55 enum {
56 DSIM_STATE_INIT, /* should be initialized. */
57 DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
58 DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
59 DSIM_STATE_ULPS
60 };
61
62 /* define DSI lane types. */
63 enum {
64 DSIM_LANE_CLOCK = (1 << 0),
65 DSIM_LANE_DATA0 = (1 << 1),
66 DSIM_LANE_DATA1 = (1 << 2),
67 DSIM_LANE_DATA2 = (1 << 3),
68 DSIM_LANE_DATA3 = (1 << 4)
69 };
70
71 static unsigned int dpll_table[15] = {
72 100, 120, 170, 220, 270,
73 320, 390, 450, 510, 560,
74 640, 690, 770, 870, 950
75 };
76
exynos_mipi_dsi_interrupt_handler(int irq,void * dev_id)77 irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
78 {
79 unsigned int intsrc = 0;
80 unsigned int intmsk = 0;
81 struct mipi_dsim_device *dsim = NULL;
82
83 dsim = dev_id;
84 if (!dsim) {
85 dev_dbg(dsim->dev, KERN_ERR "%s:error: wrong parameter\n",
86 __func__);
87 return IRQ_HANDLED;
88 }
89
90 intsrc = exynos_mipi_dsi_read_interrupt(dsim);
91 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
92
93 intmsk = ~(intmsk) & intsrc;
94
95 switch (intmsk) {
96 case INTMSK_RX_DONE:
97 complete(&dsim_rd_comp);
98 dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
99 break;
100 case INTMSK_FIFO_EMPTY:
101 complete(&dsim_wr_comp);
102 dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
103 break;
104 default:
105 break;
106 }
107
108 exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
109
110 return IRQ_HANDLED;
111 }
112
113 /*
114 * write long packet to mipi dsi slave
115 * @dsim: mipi dsim device structure.
116 * @data0: packet data to send.
117 * @data1: size of packet data
118 */
exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device * dsim,const unsigned char * data0,unsigned int data_size)119 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
120 const unsigned char *data0, unsigned int data_size)
121 {
122 unsigned int data_cnt = 0, payload = 0;
123
124 /* in case that data count is more then 4 */
125 for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
126 /*
127 * after sending 4bytes per one time,
128 * send remainder data less then 4.
129 */
130 if ((data_size - data_cnt) < 4) {
131 if ((data_size - data_cnt) == 3) {
132 payload = data0[data_cnt] |
133 data0[data_cnt + 1] << 8 |
134 data0[data_cnt + 2] << 16;
135 dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
136 payload, data0[data_cnt],
137 data0[data_cnt + 1],
138 data0[data_cnt + 2]);
139 } else if ((data_size - data_cnt) == 2) {
140 payload = data0[data_cnt] |
141 data0[data_cnt + 1] << 8;
142 dev_dbg(dsim->dev,
143 "count = 2 payload = %x, %x %x\n", payload,
144 data0[data_cnt],
145 data0[data_cnt + 1]);
146 } else if ((data_size - data_cnt) == 1) {
147 payload = data0[data_cnt];
148 }
149
150 exynos_mipi_dsi_wr_tx_data(dsim, payload);
151 /* send 4bytes per one time. */
152 } else {
153 payload = data0[data_cnt] |
154 data0[data_cnt + 1] << 8 |
155 data0[data_cnt + 2] << 16 |
156 data0[data_cnt + 3] << 24;
157
158 dev_dbg(dsim->dev,
159 "count = 4 payload = %x, %x %x %x %x\n",
160 payload, *(u8 *)(data0 + data_cnt),
161 data0[data_cnt + 1],
162 data0[data_cnt + 2],
163 data0[data_cnt + 3]);
164
165 exynos_mipi_dsi_wr_tx_data(dsim, payload);
166 }
167 }
168 }
169
exynos_mipi_dsi_wr_data(struct mipi_dsim_device * dsim,unsigned int data_id,const unsigned char * data0,unsigned int data_size)170 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
171 const unsigned char *data0, unsigned int data_size)
172 {
173 unsigned int check_rx_ack = 0;
174
175 if (dsim->state == DSIM_STATE_ULPS) {
176 dev_err(dsim->dev, "state is ULPS.\n");
177
178 return -EINVAL;
179 }
180
181 /* FIXME!!! why does it need this delay? */
182 msleep(20);
183
184 mutex_lock(&dsim->lock);
185
186 switch (data_id) {
187 /* short packet types of packet types for command. */
188 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
189 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
190 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
191 case MIPI_DSI_DCS_SHORT_WRITE:
192 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
193 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
194 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
195 if (check_rx_ack) {
196 /* process response func should be implemented */
197 mutex_unlock(&dsim->lock);
198 return 0;
199 } else {
200 mutex_unlock(&dsim->lock);
201 return -EINVAL;
202 }
203
204 /* general command */
205 case MIPI_DSI_COLOR_MODE_OFF:
206 case MIPI_DSI_COLOR_MODE_ON:
207 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
208 case MIPI_DSI_TURN_ON_PERIPHERAL:
209 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
210 if (check_rx_ack) {
211 /* process response func should be implemented. */
212 mutex_unlock(&dsim->lock);
213 return 0;
214 } else {
215 mutex_unlock(&dsim->lock);
216 return -EINVAL;
217 }
218
219 /* packet types for video data */
220 case MIPI_DSI_V_SYNC_START:
221 case MIPI_DSI_V_SYNC_END:
222 case MIPI_DSI_H_SYNC_START:
223 case MIPI_DSI_H_SYNC_END:
224 case MIPI_DSI_END_OF_TRANSMISSION:
225 mutex_unlock(&dsim->lock);
226 return 0;
227
228 /* long packet type and null packet */
229 case MIPI_DSI_NULL_PACKET:
230 case MIPI_DSI_BLANKING_PACKET:
231 mutex_unlock(&dsim->lock);
232 return 0;
233 case MIPI_DSI_GENERIC_LONG_WRITE:
234 case MIPI_DSI_DCS_LONG_WRITE:
235 {
236 unsigned int size, payload = 0;
237 INIT_COMPLETION(dsim_wr_comp);
238
239 size = data_size * 4;
240
241 /* if data count is less then 4, then send 3bytes data. */
242 if (data_size < 4) {
243 payload = data0[0] |
244 data0[1] << 8 |
245 data0[2] << 16;
246
247 exynos_mipi_dsi_wr_tx_data(dsim, payload);
248
249 dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
250 data_size, payload, data0[0],
251 data0[1], data0[2]);
252
253 /* in case that data count is more then 4 */
254 } else
255 exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
256
257 /* put data into header fifo */
258 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
259 (data_size & 0xff00) >> 8);
260
261 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
262 MIPI_FIFO_TIMEOUT)) {
263 dev_warn(dsim->dev, "command write timeout.\n");
264 mutex_unlock(&dsim->lock);
265 return -EAGAIN;
266 }
267
268 if (check_rx_ack) {
269 /* process response func should be implemented. */
270 mutex_unlock(&dsim->lock);
271 return 0;
272 } else {
273 mutex_unlock(&dsim->lock);
274 return -EINVAL;
275 }
276 }
277
278 /* packet typo for video data */
279 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
280 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
281 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
282 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
283 if (check_rx_ack) {
284 /* process response func should be implemented. */
285 mutex_unlock(&dsim->lock);
286 return 0;
287 } else {
288 mutex_unlock(&dsim->lock);
289 return -EINVAL;
290 }
291 default:
292 dev_warn(dsim->dev,
293 "data id %x is not supported current DSI spec.\n",
294 data_id);
295
296 mutex_unlock(&dsim->lock);
297 return -EINVAL;
298 }
299
300 mutex_unlock(&dsim->lock);
301 return 0;
302 }
303
exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device * dsim,unsigned int req_size,unsigned int rx_data,u8 * rx_buf)304 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
305 unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
306 {
307 unsigned int rcv_pkt, i, j;
308 u16 rxsize;
309
310 /* for long packet */
311 rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
312 dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
313 if (rxsize != req_size) {
314 dev_dbg(dsim->dev,
315 "received size mismatch received: %d, requested: %d\n",
316 rxsize, req_size);
317 goto err;
318 }
319
320 for (i = 0; i < (rxsize >> 2); i++) {
321 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
322 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
323 for (j = 0; j < 4; j++) {
324 rx_buf[(i * 4) + j] =
325 (u8)(rcv_pkt >> (j * 8)) & 0xff;
326 dev_dbg(dsim->dev, "received value : %02x\n",
327 (rcv_pkt >> (j * 8)) & 0xff);
328 }
329 }
330 if (rxsize % 4) {
331 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
332 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
333 for (j = 0; j < (rxsize % 4); j++) {
334 rx_buf[(i * 4) + j] =
335 (u8)(rcv_pkt >> (j * 8)) & 0xff;
336 dev_dbg(dsim->dev, "received value : %02x\n",
337 (rcv_pkt >> (j * 8)) & 0xff);
338 }
339 }
340
341 return rxsize;
342
343 err:
344 return -EINVAL;
345 }
346
exynos_mipi_dsi_response_size(unsigned int req_size)347 static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
348 {
349 switch (req_size) {
350 case 1:
351 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
352 case 2:
353 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
354 default:
355 return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
356 }
357 }
358
exynos_mipi_dsi_rd_data(struct mipi_dsim_device * dsim,unsigned int data_id,unsigned int data0,unsigned int req_size,u8 * rx_buf)359 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
360 unsigned int data0, unsigned int req_size, u8 *rx_buf)
361 {
362 unsigned int rx_data, rcv_pkt, i;
363 u8 response = 0;
364 u16 rxsize;
365
366 if (dsim->state == DSIM_STATE_ULPS) {
367 dev_err(dsim->dev, "state is ULPS.\n");
368
369 return -EINVAL;
370 }
371
372 /* FIXME!!! */
373 msleep(20);
374
375 mutex_lock(&dsim->lock);
376 INIT_COMPLETION(dsim_rd_comp);
377 exynos_mipi_dsi_rd_tx_header(dsim,
378 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
379
380 response = exynos_mipi_dsi_response_size(req_size);
381
382 switch (data_id) {
383 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
384 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
385 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
386 case MIPI_DSI_DCS_READ:
387 exynos_mipi_dsi_rd_tx_header(dsim,
388 data_id, data0);
389 /* process response func should be implemented. */
390 break;
391 default:
392 dev_warn(dsim->dev,
393 "data id %x is not supported current DSI spec.\n",
394 data_id);
395
396 return -EINVAL;
397 }
398
399 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
400 MIPI_FIFO_TIMEOUT)) {
401 pr_err("RX done interrupt timeout\n");
402 mutex_unlock(&dsim->lock);
403 return 0;
404 }
405
406 msleep(20);
407
408 rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
409
410 if ((u8)(rx_data & 0xff) != response) {
411 printk(KERN_ERR
412 "mipi dsi wrong response rx_data : %x, response:%x\n",
413 rx_data, response);
414 goto clear_rx_fifo;
415 }
416
417 if (req_size <= 2) {
418 /* for short packet */
419 for (i = 0; i < req_size; i++)
420 rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
421 rxsize = req_size;
422 } else {
423 /* for long packet */
424 rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
425 rx_buf);
426 if (rxsize != req_size)
427 goto clear_rx_fifo;
428 }
429
430 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
431
432 msleep(20);
433
434 if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
435 dev_info(dsim->dev,
436 "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
437 goto clear_rx_fifo;
438 }
439
440 mutex_unlock(&dsim->lock);
441
442 return rxsize;
443
444 clear_rx_fifo:
445 i = 0;
446 while (1) {
447 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
448 if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
449 || (i > MIPI_MAX_RX_FIFO))
450 break;
451 dev_dbg(dsim->dev,
452 "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
453 i++;
454 }
455 dev_info(dsim->dev,
456 "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
457
458 mutex_unlock(&dsim->lock);
459
460 return 0;
461 }
462
exynos_mipi_dsi_pll_on(struct mipi_dsim_device * dsim,unsigned int enable)463 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
464 unsigned int enable)
465 {
466 int sw_timeout;
467
468 if (enable) {
469 sw_timeout = 1000;
470
471 exynos_mipi_dsi_enable_pll(dsim, 1);
472 while (1) {
473 sw_timeout--;
474 if (exynos_mipi_dsi_is_pll_stable(dsim))
475 return 0;
476 if (sw_timeout == 0)
477 return -EINVAL;
478 }
479 } else
480 exynos_mipi_dsi_enable_pll(dsim, 0);
481
482 return 0;
483 }
484
exynos_mipi_dsi_change_pll(struct mipi_dsim_device * dsim,unsigned int pre_divider,unsigned int main_divider,unsigned int scaler)485 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
486 unsigned int pre_divider, unsigned int main_divider,
487 unsigned int scaler)
488 {
489 unsigned long dfin_pll, dfvco, dpll_out;
490 unsigned int i, freq_band = 0xf;
491
492 dfin_pll = (FIN_HZ / pre_divider);
493
494 /******************************************************
495 * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
496 ******************************************************
497 * ~ 99.99 MHz 0000
498 * 100 ~ 119.99 MHz 0001
499 * 120 ~ 159.99 MHz 0010
500 * 160 ~ 199.99 MHz 0011
501 * 200 ~ 239.99 MHz 0100
502 * 140 ~ 319.99 MHz 0101
503 * 320 ~ 389.99 MHz 0110
504 * 390 ~ 449.99 MHz 0111
505 * 450 ~ 509.99 MHz 1000
506 * 510 ~ 559.99 MHz 1001
507 * 560 ~ 639.99 MHz 1010
508 * 640 ~ 689.99 MHz 1011
509 * 690 ~ 769.99 MHz 1100
510 * 770 ~ 869.99 MHz 1101
511 * 870 ~ 949.99 MHz 1110
512 * 950 ~ 1000 MHz 1111
513 ******************************************************/
514 if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
515 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
516 exynos_mipi_dsi_enable_afc(dsim, 0, 0);
517 } else {
518 if (dfin_pll < 7 * MHZ)
519 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
520 else if (dfin_pll < 8 * MHZ)
521 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
522 else if (dfin_pll < 9 * MHZ)
523 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
524 else if (dfin_pll < 10 * MHZ)
525 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
526 else if (dfin_pll < 11 * MHZ)
527 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
528 else
529 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
530 }
531
532 dfvco = dfin_pll * main_divider;
533 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
534 dfvco, dfin_pll, main_divider);
535 if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
536 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
537
538 dpll_out = dfvco / (1 << scaler);
539 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
540 dpll_out, dfvco, scaler);
541
542 for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
543 if (dpll_out < dpll_table[i] * MHZ) {
544 freq_band = i;
545 break;
546 }
547 }
548
549 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
550
551 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
552
553 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
554 exynos_mipi_dsi_prep_ctrl(dsim, 0);
555
556 /* Freq Band */
557 exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
558
559 /* Stable time */
560 exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
561
562 /* Enable PLL */
563 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
564 (dpll_out / MHZ));
565
566 return dpll_out;
567 }
568
exynos_mipi_dsi_set_clock(struct mipi_dsim_device * dsim,unsigned int byte_clk_sel,unsigned int enable)569 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
570 unsigned int byte_clk_sel, unsigned int enable)
571 {
572 unsigned int esc_div;
573 unsigned long esc_clk_error_rate;
574 unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
575
576 if (enable) {
577 dsim->e_clk_src = byte_clk_sel;
578
579 /* Escape mode clock and byte clock source */
580 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
581
582 /* DPHY, DSIM Link : D-PHY clock out */
583 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
584 hs_clk = exynos_mipi_dsi_change_pll(dsim,
585 dsim->dsim_config->p, dsim->dsim_config->m,
586 dsim->dsim_config->s);
587 if (hs_clk == 0) {
588 dev_err(dsim->dev,
589 "failed to get hs clock.\n");
590 return -EINVAL;
591 }
592
593 byte_clk = hs_clk / 8;
594 exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
595 exynos_mipi_dsi_pll_on(dsim, 1);
596 /* DPHY : D-PHY clock out, DSIM link : external clock out */
597 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
598 dev_warn(dsim->dev, "this project is not support\n");
599 dev_warn(dsim->dev,
600 "external clock source for MIPI DSIM.\n");
601 } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
602 dev_warn(dsim->dev, "this project is not support\n");
603 dev_warn(dsim->dev,
604 "external clock source for MIPI DSIM\n");
605 }
606
607 /* escape clock divider */
608 esc_div = byte_clk / (dsim->dsim_config->esc_clk);
609 dev_dbg(dsim->dev,
610 "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
611 esc_div, byte_clk, dsim->dsim_config->esc_clk);
612 if ((byte_clk / esc_div) >= (20 * MHZ) ||
613 (byte_clk / esc_div) >
614 dsim->dsim_config->esc_clk)
615 esc_div += 1;
616
617 escape_clk = byte_clk / esc_div;
618 dev_dbg(dsim->dev,
619 "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
620 escape_clk, byte_clk, esc_div);
621
622 /* enable escape clock. */
623 exynos_mipi_dsi_enable_byte_clock(dsim, 1);
624
625 /* enable byte clk and escape clock */
626 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
627 /* escape clock on lane */
628 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
629 (DSIM_LANE_CLOCK | dsim->data_lane), 1);
630
631 dev_dbg(dsim->dev, "byte clock is %luMHz\n",
632 (byte_clk / MHZ));
633 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
634 (dsim->dsim_config->esc_clk / MHZ));
635 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
636 dev_dbg(dsim->dev, "escape clock is %luMHz\n",
637 ((byte_clk / esc_div) / MHZ));
638
639 if ((byte_clk / esc_div) > escape_clk) {
640 esc_clk_error_rate = escape_clk /
641 (byte_clk / esc_div);
642 dev_warn(dsim->dev, "error rate is %lu over.\n",
643 (esc_clk_error_rate / 100));
644 } else if ((byte_clk / esc_div) < (escape_clk)) {
645 esc_clk_error_rate = (byte_clk / esc_div) /
646 escape_clk;
647 dev_warn(dsim->dev, "error rate is %lu under.\n",
648 (esc_clk_error_rate / 100));
649 }
650 } else {
651 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
652 (DSIM_LANE_CLOCK | dsim->data_lane), 0);
653 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
654
655 /* disable escape clock. */
656 exynos_mipi_dsi_enable_byte_clock(dsim, 0);
657
658 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
659 exynos_mipi_dsi_pll_on(dsim, 0);
660 }
661
662 return 0;
663 }
664
exynos_mipi_dsi_init_dsim(struct mipi_dsim_device * dsim)665 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
666 {
667 dsim->state = DSIM_STATE_INIT;
668
669 switch (dsim->dsim_config->e_no_data_lane) {
670 case DSIM_DATA_LANE_1:
671 dsim->data_lane = DSIM_LANE_DATA0;
672 break;
673 case DSIM_DATA_LANE_2:
674 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
675 break;
676 case DSIM_DATA_LANE_3:
677 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
678 DSIM_LANE_DATA2;
679 break;
680 case DSIM_DATA_LANE_4:
681 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
682 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
683 break;
684 default:
685 dev_info(dsim->dev, "data lane is invalid.\n");
686 return -EINVAL;
687 };
688
689 exynos_mipi_dsi_sw_reset(dsim);
690 exynos_mipi_dsi_func_reset(dsim);
691
692 exynos_mipi_dsi_dp_dn_swap(dsim, 0);
693
694 return 0;
695 }
696
exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device * dsim)697 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
698 {
699 unsigned int src = 0;
700
701 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
702 exynos_mipi_dsi_set_interrupt(dsim, src, 1);
703
704 src = 0;
705 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
706 exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
707 }
708
exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device * dsim,unsigned int enable)709 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
710 unsigned int enable)
711 {
712 /* enable only frame done interrupt */
713 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
714
715 return 0;
716 }
717
exynos_mipi_dsi_stand_by(struct mipi_dsim_device * dsim,unsigned int enable)718 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
719 unsigned int enable)
720 {
721
722 /* consider Main display and Sub display. */
723
724 exynos_mipi_dsi_set_main_stand_by(dsim, enable);
725 }
726
exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device * dsim,struct mipi_dsim_config * dsim_config)727 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
728 struct mipi_dsim_config *dsim_config)
729 {
730 struct mipi_dsim_platform_data *dsim_pd;
731 struct fb_videomode *timing;
732
733 dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
734 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
735
736 /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
737 if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
738 if (dsim_config->auto_vertical_cnt == 0) {
739 exynos_mipi_dsi_set_main_disp_vporch(dsim,
740 dsim_config->cmd_allow,
741 timing->upper_margin,
742 timing->lower_margin);
743 exynos_mipi_dsi_set_main_disp_hporch(dsim,
744 timing->left_margin,
745 timing->right_margin);
746 exynos_mipi_dsi_set_main_disp_sync_area(dsim,
747 timing->vsync_len,
748 timing->hsync_len);
749 }
750 }
751
752 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
753 timing->yres);
754
755 exynos_mipi_dsi_display_config(dsim, dsim_config);
756
757 dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
758 timing->xres, timing->yres);
759
760 return 0;
761 }
762
exynos_mipi_dsi_init_link(struct mipi_dsim_device * dsim)763 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
764 {
765 unsigned int time_out = 100;
766
767 switch (dsim->state) {
768 case DSIM_STATE_INIT:
769 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
770
771 /* dsi configuration */
772 exynos_mipi_dsi_init_config(dsim);
773 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
774 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
775
776 /* set clock configuration */
777 exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
778
779 /* check clock and data lane state are stop state */
780 while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
781 time_out--;
782 if (time_out == 0) {
783 dev_err(dsim->dev,
784 "DSI Master is not stop state.\n");
785 dev_err(dsim->dev,
786 "Check initialization process\n");
787
788 return -EINVAL;
789 }
790 }
791 if (time_out != 0) {
792 dev_info(dsim->dev,
793 "DSI Master driver has been completed.\n");
794 dev_info(dsim->dev, "DSI Master state is stop state\n");
795 }
796
797 dsim->state = DSIM_STATE_STOP;
798
799 /* BTA sequence counters */
800 exynos_mipi_dsi_set_stop_state_counter(dsim,
801 dsim->dsim_config->stop_holding_cnt);
802 exynos_mipi_dsi_set_bta_timeout(dsim,
803 dsim->dsim_config->bta_timeout);
804 exynos_mipi_dsi_set_lpdr_timeout(dsim,
805 dsim->dsim_config->rx_timeout);
806
807 return 0;
808 default:
809 dev_info(dsim->dev, "DSI Master is already init.\n");
810 return 0;
811 }
812
813 return 0;
814 }
815
exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device * dsim)816 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
817 {
818 if (dsim->state != DSIM_STATE_STOP) {
819 dev_warn(dsim->dev, "DSIM is not in stop state.\n");
820 return 0;
821 }
822
823 if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
824 dev_warn(dsim->dev, "clock source is external bypass.\n");
825 return 0;
826 }
827
828 dsim->state = DSIM_STATE_HSCLKEN;
829
830 /* set LCDC and CPU transfer mode to HS. */
831 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
832 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
833 exynos_mipi_dsi_enable_hs_clock(dsim, 1);
834
835 return 0;
836 }
837
exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device * dsim,unsigned int mode)838 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
839 unsigned int mode)
840 {
841 if (mode) {
842 if (dsim->state != DSIM_STATE_HSCLKEN) {
843 dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
844 return -EINVAL;
845 }
846
847 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
848 } else {
849 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
850 DSIM_STATE_ULPS) {
851 dev_err(dsim->dev,
852 "DSI Master is not STOP or HSDT state.\n");
853 return -EINVAL;
854 }
855
856 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
857 }
858
859 return 0;
860 }
861
exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device * dsim)862 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
863 {
864 return _exynos_mipi_dsi_get_frame_done_status(dsim);
865 }
866
exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device * dsim)867 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
868 {
869 _exynos_mipi_dsi_clear_frame_done(dsim);
870
871 return 0;
872 }
873
exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device * dsim,unsigned int val)874 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
875 unsigned int val)
876 {
877 int try = TRY_FIFO_CLEAR;
878
879 exynos_mipi_dsi_sw_reset_release(dsim);
880 exynos_mipi_dsi_func_reset(dsim);
881
882 do {
883 if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
884 exynos_mipi_dsi_init_interrupt(dsim);
885 dev_dbg(dsim->dev, "reset release done.\n");
886 return 0;
887 }
888 } while (--try);
889
890 dev_err(dsim->dev, "failed to clear dsim fifo.\n");
891 return -EAGAIN;
892 }
893
894 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
895 MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
896 MODULE_LICENSE("GPL");
897