1 /*
2  *  Copyright (C) 1991, 1992  Linus Torvalds
3  *  Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4  *
5  *  Pentium III FXSR, SSE support
6  *	Gareth Hughes <gareth@valinux.com>, May 2000
7  */
8 
9 /*
10  * Handle hardware traps and faults.
11  */
12 
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 
15 #include <linux/context_tracking.h>
16 #include <linux/interrupt.h>
17 #include <linux/kallsyms.h>
18 #include <linux/kmsan.h>
19 #include <linux/spinlock.h>
20 #include <linux/kprobes.h>
21 #include <linux/uaccess.h>
22 #include <linux/kdebug.h>
23 #include <linux/kgdb.h>
24 #include <linux/kernel.h>
25 #include <linux/export.h>
26 #include <linux/ptrace.h>
27 #include <linux/uprobes.h>
28 #include <linux/string.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/kexec.h>
32 #include <linux/sched.h>
33 #include <linux/sched/task_stack.h>
34 #include <linux/timer.h>
35 #include <linux/init.h>
36 #include <linux/bug.h>
37 #include <linux/nmi.h>
38 #include <linux/mm.h>
39 #include <linux/smp.h>
40 #include <linux/io.h>
41 #include <linux/hardirq.h>
42 #include <linux/atomic.h>
43 #include <linux/ioasid.h>
44 
45 #include <asm/stacktrace.h>
46 #include <asm/processor.h>
47 #include <asm/debugreg.h>
48 #include <asm/realmode.h>
49 #include <asm/text-patching.h>
50 #include <asm/ftrace.h>
51 #include <asm/traps.h>
52 #include <asm/desc.h>
53 #include <asm/fpu/api.h>
54 #include <asm/cpu.h>
55 #include <asm/cpu_entry_area.h>
56 #include <asm/mce.h>
57 #include <asm/fixmap.h>
58 #include <asm/mach_traps.h>
59 #include <asm/alternative.h>
60 #include <asm/fpu/xstate.h>
61 #include <asm/vm86.h>
62 #include <asm/umip.h>
63 #include <asm/insn.h>
64 #include <asm/insn-eval.h>
65 #include <asm/vdso.h>
66 #include <asm/tdx.h>
67 #include <asm/cfi.h>
68 
69 #ifdef CONFIG_X86_64
70 #include <asm/x86_init.h>
71 #include <asm/proto.h>
72 #else
73 #include <asm/processor-flags.h>
74 #include <asm/setup.h>
75 #include <asm/proto.h>
76 #endif
77 
78 DECLARE_BITMAP(system_vectors, NR_VECTORS);
79 
cond_local_irq_enable(struct pt_regs * regs)80 static inline void cond_local_irq_enable(struct pt_regs *regs)
81 {
82 	if (regs->flags & X86_EFLAGS_IF)
83 		local_irq_enable();
84 }
85 
cond_local_irq_disable(struct pt_regs * regs)86 static inline void cond_local_irq_disable(struct pt_regs *regs)
87 {
88 	if (regs->flags & X86_EFLAGS_IF)
89 		local_irq_disable();
90 }
91 
is_valid_bugaddr(unsigned long addr)92 __always_inline int is_valid_bugaddr(unsigned long addr)
93 {
94 	if (addr < TASK_SIZE_MAX)
95 		return 0;
96 
97 	/*
98 	 * We got #UD, if the text isn't readable we'd have gotten
99 	 * a different exception.
100 	 */
101 	return *(unsigned short *)addr == INSN_UD2;
102 }
103 
104 static nokprobe_inline int
do_trap_no_signal(struct task_struct * tsk,int trapnr,const char * str,struct pt_regs * regs,long error_code)105 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
106 		  struct pt_regs *regs,	long error_code)
107 {
108 	if (v8086_mode(regs)) {
109 		/*
110 		 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
111 		 * On nmi (interrupt 2), do_trap should not be called.
112 		 */
113 		if (trapnr < X86_TRAP_UD) {
114 			if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
115 						error_code, trapnr))
116 				return 0;
117 		}
118 	} else if (!user_mode(regs)) {
119 		if (fixup_exception(regs, trapnr, error_code, 0))
120 			return 0;
121 
122 		tsk->thread.error_code = error_code;
123 		tsk->thread.trap_nr = trapnr;
124 		die(str, regs, error_code);
125 	} else {
126 		if (fixup_vdso_exception(regs, trapnr, error_code, 0))
127 			return 0;
128 	}
129 
130 	/*
131 	 * We want error_code and trap_nr set for userspace faults and
132 	 * kernelspace faults which result in die(), but not
133 	 * kernelspace faults which are fixed up.  die() gives the
134 	 * process no chance to handle the signal and notice the
135 	 * kernel fault information, so that won't result in polluting
136 	 * the information about previously queued, but not yet
137 	 * delivered, faults.  See also exc_general_protection below.
138 	 */
139 	tsk->thread.error_code = error_code;
140 	tsk->thread.trap_nr = trapnr;
141 
142 	return -1;
143 }
144 
show_signal(struct task_struct * tsk,int signr,const char * type,const char * desc,struct pt_regs * regs,long error_code)145 static void show_signal(struct task_struct *tsk, int signr,
146 			const char *type, const char *desc,
147 			struct pt_regs *regs, long error_code)
148 {
149 	if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
150 	    printk_ratelimit()) {
151 		pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
152 			tsk->comm, task_pid_nr(tsk), type, desc,
153 			regs->ip, regs->sp, error_code);
154 		print_vma_addr(KERN_CONT " in ", regs->ip);
155 		pr_cont("\n");
156 	}
157 }
158 
159 static void
do_trap(int trapnr,int signr,char * str,struct pt_regs * regs,long error_code,int sicode,void __user * addr)160 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
161 	long error_code, int sicode, void __user *addr)
162 {
163 	struct task_struct *tsk = current;
164 
165 	if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
166 		return;
167 
168 	show_signal(tsk, signr, "trap ", str, regs, error_code);
169 
170 	if (!sicode)
171 		force_sig(signr);
172 	else
173 		force_sig_fault(signr, sicode, addr);
174 }
175 NOKPROBE_SYMBOL(do_trap);
176 
do_error_trap(struct pt_regs * regs,long error_code,char * str,unsigned long trapnr,int signr,int sicode,void __user * addr)177 static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
178 	unsigned long trapnr, int signr, int sicode, void __user *addr)
179 {
180 	RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
181 
182 	if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
183 			NOTIFY_STOP) {
184 		cond_local_irq_enable(regs);
185 		do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
186 		cond_local_irq_disable(regs);
187 	}
188 }
189 
190 /*
191  * Posix requires to provide the address of the faulting instruction for
192  * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
193  *
194  * This address is usually regs->ip, but when an uprobe moved the code out
195  * of line then regs->ip points to the XOL code which would confuse
196  * anything which analyzes the fault address vs. the unmodified binary. If
197  * a trap happened in XOL code then uprobe maps regs->ip back to the
198  * original instruction address.
199  */
error_get_trap_addr(struct pt_regs * regs)200 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
201 {
202 	return (void __user *)uprobe_get_trap_addr(regs);
203 }
204 
DEFINE_IDTENTRY(exc_divide_error)205 DEFINE_IDTENTRY(exc_divide_error)
206 {
207 	do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE,
208 		      FPE_INTDIV, error_get_trap_addr(regs));
209 }
210 
DEFINE_IDTENTRY(exc_overflow)211 DEFINE_IDTENTRY(exc_overflow)
212 {
213 	do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
214 }
215 
216 #ifdef CONFIG_X86_KERNEL_IBT
217 
218 static __ro_after_init bool ibt_fatal = true;
219 
220 extern void ibt_selftest_ip(void); /* code label defined in asm below */
221 
222 enum cp_error_code {
223 	CP_EC        = (1 << 15) - 1,
224 
225 	CP_RET       = 1,
226 	CP_IRET      = 2,
227 	CP_ENDBR     = 3,
228 	CP_RSTRORSSP = 4,
229 	CP_SETSSBSY  = 5,
230 
231 	CP_ENCL	     = 1 << 15,
232 };
233 
DEFINE_IDTENTRY_ERRORCODE(exc_control_protection)234 DEFINE_IDTENTRY_ERRORCODE(exc_control_protection)
235 {
236 	if (!cpu_feature_enabled(X86_FEATURE_IBT)) {
237 		pr_err("Unexpected #CP\n");
238 		BUG();
239 	}
240 
241 	if (WARN_ON_ONCE(user_mode(regs) || (error_code & CP_EC) != CP_ENDBR))
242 		return;
243 
244 	if (unlikely(regs->ip == (unsigned long)&ibt_selftest_ip)) {
245 		regs->ax = 0;
246 		return;
247 	}
248 
249 	pr_err("Missing ENDBR: %pS\n", (void *)instruction_pointer(regs));
250 	if (!ibt_fatal) {
251 		printk(KERN_DEFAULT CUT_HERE);
252 		__warn(__FILE__, __LINE__, (void *)regs->ip, TAINT_WARN, regs, NULL);
253 		return;
254 	}
255 	BUG();
256 }
257 
258 /* Must be noinline to ensure uniqueness of ibt_selftest_ip. */
ibt_selftest(void)259 noinline bool ibt_selftest(void)
260 {
261 	unsigned long ret;
262 
263 	asm ("	lea ibt_selftest_ip(%%rip), %%rax\n\t"
264 	     ANNOTATE_RETPOLINE_SAFE
265 	     "	jmp *%%rax\n\t"
266 	     "ibt_selftest_ip:\n\t"
267 	     UNWIND_HINT_FUNC
268 	     ANNOTATE_NOENDBR
269 	     "	nop\n\t"
270 
271 	     : "=a" (ret) : : "memory");
272 
273 	return !ret;
274 }
275 
ibt_setup(char * str)276 static int __init ibt_setup(char *str)
277 {
278 	if (!strcmp(str, "off"))
279 		setup_clear_cpu_cap(X86_FEATURE_IBT);
280 
281 	if (!strcmp(str, "warn"))
282 		ibt_fatal = false;
283 
284 	return 1;
285 }
286 
287 __setup("ibt=", ibt_setup);
288 
289 #endif /* CONFIG_X86_KERNEL_IBT */
290 
291 #ifdef CONFIG_X86_F00F_BUG
handle_invalid_op(struct pt_regs * regs)292 void handle_invalid_op(struct pt_regs *regs)
293 #else
294 static inline void handle_invalid_op(struct pt_regs *regs)
295 #endif
296 {
297 	do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
298 		      ILL_ILLOPN, error_get_trap_addr(regs));
299 }
300 
handle_bug(struct pt_regs * regs)301 static noinstr bool handle_bug(struct pt_regs *regs)
302 {
303 	bool handled = false;
304 
305 	/*
306 	 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug()
307 	 * is a rare case that uses @regs without passing them to
308 	 * irqentry_enter().
309 	 */
310 	kmsan_unpoison_entry_regs(regs);
311 	if (!is_valid_bugaddr(regs->ip))
312 		return handled;
313 
314 	/*
315 	 * All lies, just get the WARN/BUG out.
316 	 */
317 	instrumentation_begin();
318 	/*
319 	 * Since we're emulating a CALL with exceptions, restore the interrupt
320 	 * state to what it was at the exception site.
321 	 */
322 	if (regs->flags & X86_EFLAGS_IF)
323 		raw_local_irq_enable();
324 	if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN ||
325 	    handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) {
326 		regs->ip += LEN_UD2;
327 		handled = true;
328 	}
329 	if (regs->flags & X86_EFLAGS_IF)
330 		raw_local_irq_disable();
331 	instrumentation_end();
332 
333 	return handled;
334 }
335 
DEFINE_IDTENTRY_RAW(exc_invalid_op)336 DEFINE_IDTENTRY_RAW(exc_invalid_op)
337 {
338 	irqentry_state_t state;
339 
340 	/*
341 	 * We use UD2 as a short encoding for 'CALL __WARN', as such
342 	 * handle it before exception entry to avoid recursive WARN
343 	 * in case exception entry is the one triggering WARNs.
344 	 */
345 	if (!user_mode(regs) && handle_bug(regs))
346 		return;
347 
348 	state = irqentry_enter(regs);
349 	instrumentation_begin();
350 	handle_invalid_op(regs);
351 	instrumentation_end();
352 	irqentry_exit(regs, state);
353 }
354 
DEFINE_IDTENTRY(exc_coproc_segment_overrun)355 DEFINE_IDTENTRY(exc_coproc_segment_overrun)
356 {
357 	do_error_trap(regs, 0, "coprocessor segment overrun",
358 		      X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
359 }
360 
DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)361 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
362 {
363 	do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
364 		      0, NULL);
365 }
366 
DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)367 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
368 {
369 	do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
370 		      SIGBUS, 0, NULL);
371 }
372 
DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)373 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
374 {
375 	do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
376 		      0, NULL);
377 }
378 
DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)379 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
380 {
381 	char *str = "alignment check";
382 
383 	if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
384 		return;
385 
386 	if (!user_mode(regs))
387 		die("Split lock detected\n", regs, error_code);
388 
389 	local_irq_enable();
390 
391 	if (handle_user_split_lock(regs, error_code))
392 		goto out;
393 
394 	do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
395 		error_code, BUS_ADRALN, NULL);
396 
397 out:
398 	local_irq_disable();
399 }
400 
401 #ifdef CONFIG_VMAP_STACK
handle_stack_overflow(struct pt_regs * regs,unsigned long fault_address,struct stack_info * info)402 __visible void __noreturn handle_stack_overflow(struct pt_regs *regs,
403 						unsigned long fault_address,
404 						struct stack_info *info)
405 {
406 	const char *name = stack_type_name(info->type);
407 
408 	printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n",
409 	       name, (void *)fault_address, info->begin, info->end);
410 
411 	die("stack guard page", regs, 0);
412 
413 	/* Be absolutely certain we don't return. */
414 	panic("%s stack guard hit", name);
415 }
416 #endif
417 
418 /*
419  * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
420  *
421  * On x86_64, this is more or less a normal kernel entry.  Notwithstanding the
422  * SDM's warnings about double faults being unrecoverable, returning works as
423  * expected.  Presumably what the SDM actually means is that the CPU may get
424  * the register state wrong on entry, so returning could be a bad idea.
425  *
426  * Various CPU engineers have promised that double faults due to an IRET fault
427  * while the stack is read-only are, in fact, recoverable.
428  *
429  * On x86_32, this is entered through a task gate, and regs are synthesized
430  * from the TSS.  Returning is, in principle, okay, but changes to regs will
431  * be lost.  If, for some reason, we need to return to a context with modified
432  * regs, the shim code could be adjusted to synchronize the registers.
433  *
434  * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
435  * to be read before doing anything else.
436  */
DEFINE_IDTENTRY_DF(exc_double_fault)437 DEFINE_IDTENTRY_DF(exc_double_fault)
438 {
439 	static const char str[] = "double fault";
440 	struct task_struct *tsk = current;
441 
442 #ifdef CONFIG_VMAP_STACK
443 	unsigned long address = read_cr2();
444 	struct stack_info info;
445 #endif
446 
447 #ifdef CONFIG_X86_ESPFIX64
448 	extern unsigned char native_irq_return_iret[];
449 
450 	/*
451 	 * If IRET takes a non-IST fault on the espfix64 stack, then we
452 	 * end up promoting it to a doublefault.  In that case, take
453 	 * advantage of the fact that we're not using the normal (TSS.sp0)
454 	 * stack right now.  We can write a fake #GP(0) frame at TSS.sp0
455 	 * and then modify our own IRET frame so that, when we return,
456 	 * we land directly at the #GP(0) vector with the stack already
457 	 * set up according to its expectations.
458 	 *
459 	 * The net result is that our #GP handler will think that we
460 	 * entered from usermode with the bad user context.
461 	 *
462 	 * No need for nmi_enter() here because we don't use RCU.
463 	 */
464 	if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
465 		regs->cs == __KERNEL_CS &&
466 		regs->ip == (unsigned long)native_irq_return_iret)
467 	{
468 		struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
469 		unsigned long *p = (unsigned long *)regs->sp;
470 
471 		/*
472 		 * regs->sp points to the failing IRET frame on the
473 		 * ESPFIX64 stack.  Copy it to the entry stack.  This fills
474 		 * in gpregs->ss through gpregs->ip.
475 		 *
476 		 */
477 		gpregs->ip	= p[0];
478 		gpregs->cs	= p[1];
479 		gpregs->flags	= p[2];
480 		gpregs->sp	= p[3];
481 		gpregs->ss	= p[4];
482 		gpregs->orig_ax = 0;  /* Missing (lost) #GP error code */
483 
484 		/*
485 		 * Adjust our frame so that we return straight to the #GP
486 		 * vector with the expected RSP value.  This is safe because
487 		 * we won't enable interrupts or schedule before we invoke
488 		 * general_protection, so nothing will clobber the stack
489 		 * frame we just set up.
490 		 *
491 		 * We will enter general_protection with kernel GSBASE,
492 		 * which is what the stub expects, given that the faulting
493 		 * RIP will be the IRET instruction.
494 		 */
495 		regs->ip = (unsigned long)asm_exc_general_protection;
496 		regs->sp = (unsigned long)&gpregs->orig_ax;
497 
498 		return;
499 	}
500 #endif
501 
502 	irqentry_nmi_enter(regs);
503 	instrumentation_begin();
504 	notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
505 
506 	tsk->thread.error_code = error_code;
507 	tsk->thread.trap_nr = X86_TRAP_DF;
508 
509 #ifdef CONFIG_VMAP_STACK
510 	/*
511 	 * If we overflow the stack into a guard page, the CPU will fail
512 	 * to deliver #PF and will send #DF instead.  Similarly, if we
513 	 * take any non-IST exception while too close to the bottom of
514 	 * the stack, the processor will get a page fault while
515 	 * delivering the exception and will generate a double fault.
516 	 *
517 	 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
518 	 * Page-Fault Exception (#PF):
519 	 *
520 	 *   Processors update CR2 whenever a page fault is detected. If a
521 	 *   second page fault occurs while an earlier page fault is being
522 	 *   delivered, the faulting linear address of the second fault will
523 	 *   overwrite the contents of CR2 (replacing the previous
524 	 *   address). These updates to CR2 occur even if the page fault
525 	 *   results in a double fault or occurs during the delivery of a
526 	 *   double fault.
527 	 *
528 	 * The logic below has a small possibility of incorrectly diagnosing
529 	 * some errors as stack overflows.  For example, if the IDT or GDT
530 	 * gets corrupted such that #GP delivery fails due to a bad descriptor
531 	 * causing #GP and we hit this condition while CR2 coincidentally
532 	 * points to the stack guard page, we'll think we overflowed the
533 	 * stack.  Given that we're going to panic one way or another
534 	 * if this happens, this isn't necessarily worth fixing.
535 	 *
536 	 * If necessary, we could improve the test by only diagnosing
537 	 * a stack overflow if the saved RSP points within 47 bytes of
538 	 * the bottom of the stack: if RSP == tsk_stack + 48 and we
539 	 * take an exception, the stack is already aligned and there
540 	 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
541 	 * possible error code, so a stack overflow would *not* double
542 	 * fault.  With any less space left, exception delivery could
543 	 * fail, and, as a practical matter, we've overflowed the
544 	 * stack even if the actual trigger for the double fault was
545 	 * something else.
546 	 */
547 	if (get_stack_guard_info((void *)address, &info))
548 		handle_stack_overflow(regs, address, &info);
549 #endif
550 
551 	pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
552 	die("double fault", regs, error_code);
553 	panic("Machine halted.");
554 	instrumentation_end();
555 }
556 
DEFINE_IDTENTRY(exc_bounds)557 DEFINE_IDTENTRY(exc_bounds)
558 {
559 	if (notify_die(DIE_TRAP, "bounds", regs, 0,
560 			X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
561 		return;
562 	cond_local_irq_enable(regs);
563 
564 	if (!user_mode(regs))
565 		die("bounds", regs, 0);
566 
567 	do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
568 
569 	cond_local_irq_disable(regs);
570 }
571 
572 enum kernel_gp_hint {
573 	GP_NO_HINT,
574 	GP_NON_CANONICAL,
575 	GP_CANONICAL
576 };
577 
578 /*
579  * When an uncaught #GP occurs, try to determine the memory address accessed by
580  * the instruction and return that address to the caller. Also, try to figure
581  * out whether any part of the access to that address was non-canonical.
582  */
get_kernel_gp_address(struct pt_regs * regs,unsigned long * addr)583 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
584 						 unsigned long *addr)
585 {
586 	u8 insn_buf[MAX_INSN_SIZE];
587 	struct insn insn;
588 	int ret;
589 
590 	if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
591 			MAX_INSN_SIZE))
592 		return GP_NO_HINT;
593 
594 	ret = insn_decode_kernel(&insn, insn_buf);
595 	if (ret < 0)
596 		return GP_NO_HINT;
597 
598 	*addr = (unsigned long)insn_get_addr_ref(&insn, regs);
599 	if (*addr == -1UL)
600 		return GP_NO_HINT;
601 
602 #ifdef CONFIG_X86_64
603 	/*
604 	 * Check that:
605 	 *  - the operand is not in the kernel half
606 	 *  - the last byte of the operand is not in the user canonical half
607 	 */
608 	if (*addr < ~__VIRTUAL_MASK &&
609 	    *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
610 		return GP_NON_CANONICAL;
611 #endif
612 
613 	return GP_CANONICAL;
614 }
615 
616 #define GPFSTR "general protection fault"
617 
fixup_iopl_exception(struct pt_regs * regs)618 static bool fixup_iopl_exception(struct pt_regs *regs)
619 {
620 	struct thread_struct *t = &current->thread;
621 	unsigned char byte;
622 	unsigned long ip;
623 
624 	if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3)
625 		return false;
626 
627 	if (insn_get_effective_ip(regs, &ip))
628 		return false;
629 
630 	if (get_user(byte, (const char __user *)ip))
631 		return false;
632 
633 	if (byte != 0xfa && byte != 0xfb)
634 		return false;
635 
636 	if (!t->iopl_warn && printk_ratelimit()) {
637 		pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx",
638 		       current->comm, task_pid_nr(current), ip);
639 		print_vma_addr(KERN_CONT " in ", ip);
640 		pr_cont("\n");
641 		t->iopl_warn = 1;
642 	}
643 
644 	regs->ip += 1;
645 	return true;
646 }
647 
648 /*
649  * The unprivileged ENQCMD instruction generates #GPs if the
650  * IA32_PASID MSR has not been populated.  If possible, populate
651  * the MSR from a PASID previously allocated to the mm.
652  */
try_fixup_enqcmd_gp(void)653 static bool try_fixup_enqcmd_gp(void)
654 {
655 #ifdef CONFIG_IOMMU_SVA
656 	u32 pasid;
657 
658 	/*
659 	 * MSR_IA32_PASID is managed using XSAVE.  Directly
660 	 * writing to the MSR is only possible when fpregs
661 	 * are valid and the fpstate is not.  This is
662 	 * guaranteed when handling a userspace exception
663 	 * in *before* interrupts are re-enabled.
664 	 */
665 	lockdep_assert_irqs_disabled();
666 
667 	/*
668 	 * Hardware without ENQCMD will not generate
669 	 * #GPs that can be fixed up here.
670 	 */
671 	if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
672 		return false;
673 
674 	pasid = current->mm->pasid;
675 
676 	/*
677 	 * If the mm has not been allocated a
678 	 * PASID, the #GP can not be fixed up.
679 	 */
680 	if (!pasid_valid(pasid))
681 		return false;
682 
683 	/*
684 	 * Did this thread already have its PASID activated?
685 	 * If so, the #GP must be from something else.
686 	 */
687 	if (current->pasid_activated)
688 		return false;
689 
690 	wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID);
691 	current->pasid_activated = 1;
692 
693 	return true;
694 #else
695 	return false;
696 #endif
697 }
698 
gp_try_fixup_and_notify(struct pt_regs * regs,int trapnr,unsigned long error_code,const char * str)699 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr,
700 				    unsigned long error_code, const char *str)
701 {
702 	if (fixup_exception(regs, trapnr, error_code, 0))
703 		return true;
704 
705 	current->thread.error_code = error_code;
706 	current->thread.trap_nr = trapnr;
707 
708 	/*
709 	 * To be potentially processing a kprobe fault and to trust the result
710 	 * from kprobe_running(), we have to be non-preemptible.
711 	 */
712 	if (!preemptible() && kprobe_running() &&
713 	    kprobe_fault_handler(regs, trapnr))
714 		return true;
715 
716 	return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP;
717 }
718 
gp_user_force_sig_segv(struct pt_regs * regs,int trapnr,unsigned long error_code,const char * str)719 static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr,
720 				   unsigned long error_code, const char *str)
721 {
722 	current->thread.error_code = error_code;
723 	current->thread.trap_nr = trapnr;
724 	show_signal(current, SIGSEGV, "", str, regs, error_code);
725 	force_sig(SIGSEGV);
726 }
727 
DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)728 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
729 {
730 	char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
731 	enum kernel_gp_hint hint = GP_NO_HINT;
732 	unsigned long gp_addr;
733 
734 	if (user_mode(regs) && try_fixup_enqcmd_gp())
735 		return;
736 
737 	cond_local_irq_enable(regs);
738 
739 	if (static_cpu_has(X86_FEATURE_UMIP)) {
740 		if (user_mode(regs) && fixup_umip_exception(regs))
741 			goto exit;
742 	}
743 
744 	if (v8086_mode(regs)) {
745 		local_irq_enable();
746 		handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
747 		local_irq_disable();
748 		return;
749 	}
750 
751 	if (user_mode(regs)) {
752 		if (fixup_iopl_exception(regs))
753 			goto exit;
754 
755 		if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0))
756 			goto exit;
757 
758 		gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc);
759 		goto exit;
760 	}
761 
762 	if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc))
763 		goto exit;
764 
765 	if (error_code)
766 		snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
767 	else
768 		hint = get_kernel_gp_address(regs, &gp_addr);
769 
770 	if (hint != GP_NO_HINT)
771 		snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
772 			 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
773 						    : "maybe for address",
774 			 gp_addr);
775 
776 	/*
777 	 * KASAN is interested only in the non-canonical case, clear it
778 	 * otherwise.
779 	 */
780 	if (hint != GP_NON_CANONICAL)
781 		gp_addr = 0;
782 
783 	die_addr(desc, regs, error_code, gp_addr);
784 
785 exit:
786 	cond_local_irq_disable(regs);
787 }
788 
do_int3(struct pt_regs * regs)789 static bool do_int3(struct pt_regs *regs)
790 {
791 	int res;
792 
793 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
794 	if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
795 			 SIGTRAP) == NOTIFY_STOP)
796 		return true;
797 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
798 
799 #ifdef CONFIG_KPROBES
800 	if (kprobe_int3_handler(regs))
801 		return true;
802 #endif
803 	res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
804 
805 	return res == NOTIFY_STOP;
806 }
807 NOKPROBE_SYMBOL(do_int3);
808 
do_int3_user(struct pt_regs * regs)809 static void do_int3_user(struct pt_regs *regs)
810 {
811 	if (do_int3(regs))
812 		return;
813 
814 	cond_local_irq_enable(regs);
815 	do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
816 	cond_local_irq_disable(regs);
817 }
818 
DEFINE_IDTENTRY_RAW(exc_int3)819 DEFINE_IDTENTRY_RAW(exc_int3)
820 {
821 	/*
822 	 * poke_int3_handler() is completely self contained code; it does (and
823 	 * must) *NOT* call out to anything, lest it hits upon yet another
824 	 * INT3.
825 	 */
826 	if (poke_int3_handler(regs))
827 		return;
828 
829 	/*
830 	 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
831 	 * and therefore can trigger INT3, hence poke_int3_handler() must
832 	 * be done before. If the entry came from kernel mode, then use
833 	 * nmi_enter() because the INT3 could have been hit in any context
834 	 * including NMI.
835 	 */
836 	if (user_mode(regs)) {
837 		irqentry_enter_from_user_mode(regs);
838 		instrumentation_begin();
839 		do_int3_user(regs);
840 		instrumentation_end();
841 		irqentry_exit_to_user_mode(regs);
842 	} else {
843 		irqentry_state_t irq_state = irqentry_nmi_enter(regs);
844 
845 		instrumentation_begin();
846 		if (!do_int3(regs))
847 			die("int3", regs, 0);
848 		instrumentation_end();
849 		irqentry_nmi_exit(regs, irq_state);
850 	}
851 }
852 
853 #ifdef CONFIG_X86_64
854 /*
855  * Help handler running on a per-cpu (IST or entry trampoline) stack
856  * to switch to the normal thread stack if the interrupted code was in
857  * user mode. The actual stack switch is done in entry_64.S
858  */
sync_regs(struct pt_regs * eregs)859 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
860 {
861 	struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
862 	if (regs != eregs)
863 		*regs = *eregs;
864 	return regs;
865 }
866 
867 #ifdef CONFIG_AMD_MEM_ENCRYPT
vc_switch_off_ist(struct pt_regs * regs)868 asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs)
869 {
870 	unsigned long sp, *stack;
871 	struct stack_info info;
872 	struct pt_regs *regs_ret;
873 
874 	/*
875 	 * In the SYSCALL entry path the RSP value comes from user-space - don't
876 	 * trust it and switch to the current kernel stack
877 	 */
878 	if (ip_within_syscall_gap(regs)) {
879 		sp = this_cpu_read(cpu_current_top_of_stack);
880 		goto sync;
881 	}
882 
883 	/*
884 	 * From here on the RSP value is trusted. Now check whether entry
885 	 * happened from a safe stack. Not safe are the entry or unknown stacks,
886 	 * use the fall-back stack instead in this case.
887 	 */
888 	sp    = regs->sp;
889 	stack = (unsigned long *)sp;
890 
891 	if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY ||
892 	    info.type > STACK_TYPE_EXCEPTION_LAST)
893 		sp = __this_cpu_ist_top_va(VC2);
894 
895 sync:
896 	/*
897 	 * Found a safe stack - switch to it as if the entry didn't happen via
898 	 * IST stack. The code below only copies pt_regs, the real switch happens
899 	 * in assembly code.
900 	 */
901 	sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret);
902 
903 	regs_ret = (struct pt_regs *)sp;
904 	*regs_ret = *regs;
905 
906 	return regs_ret;
907 }
908 #endif
909 
fixup_bad_iret(struct pt_regs * bad_regs)910 asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs)
911 {
912 	struct pt_regs tmp, *new_stack;
913 
914 	/*
915 	 * This is called from entry_64.S early in handling a fault
916 	 * caused by a bad iret to user mode.  To handle the fault
917 	 * correctly, we want to move our stack frame to where it would
918 	 * be had we entered directly on the entry stack (rather than
919 	 * just below the IRET frame) and we want to pretend that the
920 	 * exception came from the IRET target.
921 	 */
922 	new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
923 
924 	/* Copy the IRET target to the temporary storage. */
925 	__memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8);
926 
927 	/* Copy the remainder of the stack from the current stack. */
928 	__memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip));
929 
930 	/* Update the entry stack */
931 	__memcpy(new_stack, &tmp, sizeof(tmp));
932 
933 	BUG_ON(!user_mode(new_stack));
934 	return new_stack;
935 }
936 #endif
937 
is_sysenter_singlestep(struct pt_regs * regs)938 static bool is_sysenter_singlestep(struct pt_regs *regs)
939 {
940 	/*
941 	 * We don't try for precision here.  If we're anywhere in the region of
942 	 * code that can be single-stepped in the SYSENTER entry path, then
943 	 * assume that this is a useless single-step trap due to SYSENTER
944 	 * being invoked with TF set.  (We don't know in advance exactly
945 	 * which instructions will be hit because BTF could plausibly
946 	 * be set.)
947 	 */
948 #ifdef CONFIG_X86_32
949 	return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
950 		(unsigned long)__end_SYSENTER_singlestep_region -
951 		(unsigned long)__begin_SYSENTER_singlestep_region;
952 #elif defined(CONFIG_IA32_EMULATION)
953 	return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
954 		(unsigned long)__end_entry_SYSENTER_compat -
955 		(unsigned long)entry_SYSENTER_compat;
956 #else
957 	return false;
958 #endif
959 }
960 
debug_read_clear_dr6(void)961 static __always_inline unsigned long debug_read_clear_dr6(void)
962 {
963 	unsigned long dr6;
964 
965 	/*
966 	 * The Intel SDM says:
967 	 *
968 	 *   Certain debug exceptions may clear bits 0-3. The remaining
969 	 *   contents of the DR6 register are never cleared by the
970 	 *   processor. To avoid confusion in identifying debug
971 	 *   exceptions, debug handlers should clear the register before
972 	 *   returning to the interrupted task.
973 	 *
974 	 * Keep it simple: clear DR6 immediately.
975 	 */
976 	get_debugreg(dr6, 6);
977 	set_debugreg(DR6_RESERVED, 6);
978 	dr6 ^= DR6_RESERVED; /* Flip to positive polarity */
979 
980 	return dr6;
981 }
982 
983 /*
984  * Our handling of the processor debug registers is non-trivial.
985  * We do not clear them on entry and exit from the kernel. Therefore
986  * it is possible to get a watchpoint trap here from inside the kernel.
987  * However, the code in ./ptrace.c has ensured that the user can
988  * only set watchpoints on userspace addresses. Therefore the in-kernel
989  * watchpoint trap can only occur in code which is reading/writing
990  * from user space. Such code must not hold kernel locks (since it
991  * can equally take a page fault), therefore it is safe to call
992  * force_sig_info even though that claims and releases locks.
993  *
994  * Code in ./signal.c ensures that the debug control register
995  * is restored before we deliver any signal, and therefore that
996  * user code runs with the correct debug control register even though
997  * we clear it here.
998  *
999  * Being careful here means that we don't have to be as careful in a
1000  * lot of more complicated places (task switching can be a bit lazy
1001  * about restoring all the debug state, and ptrace doesn't have to
1002  * find every occurrence of the TF bit that could be saved away even
1003  * by user code)
1004  *
1005  * May run on IST stack.
1006  */
1007 
notify_debug(struct pt_regs * regs,unsigned long * dr6)1008 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6)
1009 {
1010 	/*
1011 	 * Notifiers will clear bits in @dr6 to indicate the event has been
1012 	 * consumed - hw_breakpoint_handler(), single_stop_cont().
1013 	 *
1014 	 * Notifiers will set bits in @virtual_dr6 to indicate the desire
1015 	 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler().
1016 	 */
1017 	if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP)
1018 		return true;
1019 
1020 	return false;
1021 }
1022 
exc_debug_kernel(struct pt_regs * regs,unsigned long dr6)1023 static __always_inline void exc_debug_kernel(struct pt_regs *regs,
1024 					     unsigned long dr6)
1025 {
1026 	/*
1027 	 * Disable breakpoints during exception handling; recursive exceptions
1028 	 * are exceedingly 'fun'.
1029 	 *
1030 	 * Since this function is NOKPROBE, and that also applies to
1031 	 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
1032 	 * HW_BREAKPOINT_W on our stack)
1033 	 *
1034 	 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
1035 	 * includes the entry stack is excluded for everything.
1036 	 */
1037 	unsigned long dr7 = local_db_save();
1038 	irqentry_state_t irq_state = irqentry_nmi_enter(regs);
1039 	instrumentation_begin();
1040 
1041 	/*
1042 	 * If something gets miswired and we end up here for a user mode
1043 	 * #DB, we will malfunction.
1044 	 */
1045 	WARN_ON_ONCE(user_mode(regs));
1046 
1047 	if (test_thread_flag(TIF_BLOCKSTEP)) {
1048 		/*
1049 		 * The SDM says "The processor clears the BTF flag when it
1050 		 * generates a debug exception." but PTRACE_BLOCKSTEP requested
1051 		 * it for userspace, but we just took a kernel #DB, so re-set
1052 		 * BTF.
1053 		 */
1054 		unsigned long debugctl;
1055 
1056 		rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1057 		debugctl |= DEBUGCTLMSR_BTF;
1058 		wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1059 	}
1060 
1061 	/*
1062 	 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
1063 	 * watchpoint at the same time then that will still be handled.
1064 	 */
1065 	if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs))
1066 		dr6 &= ~DR_STEP;
1067 
1068 	/*
1069 	 * The kernel doesn't use INT1
1070 	 */
1071 	if (!dr6)
1072 		goto out;
1073 
1074 	if (notify_debug(regs, &dr6))
1075 		goto out;
1076 
1077 	/*
1078 	 * The kernel doesn't use TF single-step outside of:
1079 	 *
1080 	 *  - Kprobes, consumed through kprobe_debug_handler()
1081 	 *  - KGDB, consumed through notify_debug()
1082 	 *
1083 	 * So if we get here with DR_STEP set, something is wonky.
1084 	 *
1085 	 * A known way to trigger this is through QEMU's GDB stub,
1086 	 * which leaks #DB into the guest and causes IST recursion.
1087 	 */
1088 	if (WARN_ON_ONCE(dr6 & DR_STEP))
1089 		regs->flags &= ~X86_EFLAGS_TF;
1090 out:
1091 	instrumentation_end();
1092 	irqentry_nmi_exit(regs, irq_state);
1093 
1094 	local_db_restore(dr7);
1095 }
1096 
exc_debug_user(struct pt_regs * regs,unsigned long dr6)1097 static __always_inline void exc_debug_user(struct pt_regs *regs,
1098 					   unsigned long dr6)
1099 {
1100 	bool icebp;
1101 
1102 	/*
1103 	 * If something gets miswired and we end up here for a kernel mode
1104 	 * #DB, we will malfunction.
1105 	 */
1106 	WARN_ON_ONCE(!user_mode(regs));
1107 
1108 	/*
1109 	 * NB: We can't easily clear DR7 here because
1110 	 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access
1111 	 * user memory, etc.  This means that a recursive #DB is possible.  If
1112 	 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
1113 	 * Since we're not on the IST stack right now, everything will be
1114 	 * fine.
1115 	 */
1116 
1117 	irqentry_enter_from_user_mode(regs);
1118 	instrumentation_begin();
1119 
1120 	/*
1121 	 * Start the virtual/ptrace DR6 value with just the DR_STEP mask
1122 	 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits.
1123 	 *
1124 	 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6)
1125 	 * even if it is not the result of PTRACE_SINGLESTEP.
1126 	 */
1127 	current->thread.virtual_dr6 = (dr6 & DR_STEP);
1128 
1129 	/*
1130 	 * The SDM says "The processor clears the BTF flag when it
1131 	 * generates a debug exception."  Clear TIF_BLOCKSTEP to keep
1132 	 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
1133 	 */
1134 	clear_thread_flag(TIF_BLOCKSTEP);
1135 
1136 	/*
1137 	 * If dr6 has no reason to give us about the origin of this trap,
1138 	 * then it's very likely the result of an icebp/int01 trap.
1139 	 * User wants a sigtrap for that.
1140 	 */
1141 	icebp = !dr6;
1142 
1143 	if (notify_debug(regs, &dr6))
1144 		goto out;
1145 
1146 	/* It's safe to allow irq's after DR6 has been saved */
1147 	local_irq_enable();
1148 
1149 	if (v8086_mode(regs)) {
1150 		handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB);
1151 		goto out_irq;
1152 	}
1153 
1154 	/* #DB for bus lock can only be triggered from userspace. */
1155 	if (dr6 & DR_BUS_LOCK)
1156 		handle_bus_lock(regs);
1157 
1158 	/* Add the virtual_dr6 bits for signals. */
1159 	dr6 |= current->thread.virtual_dr6;
1160 	if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp)
1161 		send_sigtrap(regs, 0, get_si_code(dr6));
1162 
1163 out_irq:
1164 	local_irq_disable();
1165 out:
1166 	instrumentation_end();
1167 	irqentry_exit_to_user_mode(regs);
1168 }
1169 
1170 #ifdef CONFIG_X86_64
1171 /* IST stack entry */
DEFINE_IDTENTRY_DEBUG(exc_debug)1172 DEFINE_IDTENTRY_DEBUG(exc_debug)
1173 {
1174 	exc_debug_kernel(regs, debug_read_clear_dr6());
1175 }
1176 
1177 /* User entry, runs on regular task stack */
DEFINE_IDTENTRY_DEBUG_USER(exc_debug)1178 DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
1179 {
1180 	exc_debug_user(regs, debug_read_clear_dr6());
1181 }
1182 #else
1183 /* 32 bit does not have separate entry points. */
DEFINE_IDTENTRY_RAW(exc_debug)1184 DEFINE_IDTENTRY_RAW(exc_debug)
1185 {
1186 	unsigned long dr6 = debug_read_clear_dr6();
1187 
1188 	if (user_mode(regs))
1189 		exc_debug_user(regs, dr6);
1190 	else
1191 		exc_debug_kernel(regs, dr6);
1192 }
1193 #endif
1194 
1195 /*
1196  * Note that we play around with the 'TS' bit in an attempt to get
1197  * the correct behaviour even in the presence of the asynchronous
1198  * IRQ13 behaviour
1199  */
math_error(struct pt_regs * regs,int trapnr)1200 static void math_error(struct pt_regs *regs, int trapnr)
1201 {
1202 	struct task_struct *task = current;
1203 	struct fpu *fpu = &task->thread.fpu;
1204 	int si_code;
1205 	char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
1206 						"simd exception";
1207 
1208 	cond_local_irq_enable(regs);
1209 
1210 	if (!user_mode(regs)) {
1211 		if (fixup_exception(regs, trapnr, 0, 0))
1212 			goto exit;
1213 
1214 		task->thread.error_code = 0;
1215 		task->thread.trap_nr = trapnr;
1216 
1217 		if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
1218 			       SIGFPE) != NOTIFY_STOP)
1219 			die(str, regs, 0);
1220 		goto exit;
1221 	}
1222 
1223 	/*
1224 	 * Synchronize the FPU register state to the memory register state
1225 	 * if necessary. This allows the exception handler to inspect it.
1226 	 */
1227 	fpu_sync_fpstate(fpu);
1228 
1229 	task->thread.trap_nr	= trapnr;
1230 	task->thread.error_code = 0;
1231 
1232 	si_code = fpu__exception_code(fpu, trapnr);
1233 	/* Retry when we get spurious exceptions: */
1234 	if (!si_code)
1235 		goto exit;
1236 
1237 	if (fixup_vdso_exception(regs, trapnr, 0, 0))
1238 		goto exit;
1239 
1240 	force_sig_fault(SIGFPE, si_code,
1241 			(void __user *)uprobe_get_trap_addr(regs));
1242 exit:
1243 	cond_local_irq_disable(regs);
1244 }
1245 
DEFINE_IDTENTRY(exc_coprocessor_error)1246 DEFINE_IDTENTRY(exc_coprocessor_error)
1247 {
1248 	math_error(regs, X86_TRAP_MF);
1249 }
1250 
DEFINE_IDTENTRY(exc_simd_coprocessor_error)1251 DEFINE_IDTENTRY(exc_simd_coprocessor_error)
1252 {
1253 	if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
1254 		/* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
1255 		if (!static_cpu_has(X86_FEATURE_XMM)) {
1256 			__exc_general_protection(regs, 0);
1257 			return;
1258 		}
1259 	}
1260 	math_error(regs, X86_TRAP_XF);
1261 }
1262 
DEFINE_IDTENTRY(exc_spurious_interrupt_bug)1263 DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1264 {
1265 	/*
1266 	 * This addresses a Pentium Pro Erratum:
1267 	 *
1268 	 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1269 	 * Virtual Wire mode implemented through the local APIC, an
1270 	 * interrupt vector of 0Fh (Intel reserved encoding) may be
1271 	 * generated by the local APIC (Int 15).  This vector may be
1272 	 * generated upon receipt of a spurious interrupt (an interrupt
1273 	 * which is removed before the system receives the INTA sequence)
1274 	 * instead of the programmed 8259 spurious interrupt vector.
1275 	 *
1276 	 * IMPLICATION: The spurious interrupt vector programmed in the
1277 	 * 8259 is normally handled by an operating system's spurious
1278 	 * interrupt handler. However, a vector of 0Fh is unknown to some
1279 	 * operating systems, which would crash if this erratum occurred.
1280 	 *
1281 	 * In theory this could be limited to 32bit, but the handler is not
1282 	 * hurting and who knows which other CPUs suffer from this.
1283 	 */
1284 }
1285 
handle_xfd_event(struct pt_regs * regs)1286 static bool handle_xfd_event(struct pt_regs *regs)
1287 {
1288 	u64 xfd_err;
1289 	int err;
1290 
1291 	if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD))
1292 		return false;
1293 
1294 	rdmsrl(MSR_IA32_XFD_ERR, xfd_err);
1295 	if (!xfd_err)
1296 		return false;
1297 
1298 	wrmsrl(MSR_IA32_XFD_ERR, 0);
1299 
1300 	/* Die if that happens in kernel space */
1301 	if (WARN_ON(!user_mode(regs)))
1302 		return false;
1303 
1304 	local_irq_enable();
1305 
1306 	err = xfd_enable_feature(xfd_err);
1307 
1308 	switch (err) {
1309 	case -EPERM:
1310 		force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs));
1311 		break;
1312 	case -EFAULT:
1313 		force_sig(SIGSEGV);
1314 		break;
1315 	}
1316 
1317 	local_irq_disable();
1318 	return true;
1319 }
1320 
DEFINE_IDTENTRY(exc_device_not_available)1321 DEFINE_IDTENTRY(exc_device_not_available)
1322 {
1323 	unsigned long cr0 = read_cr0();
1324 
1325 	if (handle_xfd_event(regs))
1326 		return;
1327 
1328 #ifdef CONFIG_MATH_EMULATION
1329 	if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1330 		struct math_emu_info info = { };
1331 
1332 		cond_local_irq_enable(regs);
1333 
1334 		info.regs = regs;
1335 		math_emulate(&info);
1336 
1337 		cond_local_irq_disable(regs);
1338 		return;
1339 	}
1340 #endif
1341 
1342 	/* This should not happen. */
1343 	if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1344 		/* Try to fix it up and carry on. */
1345 		write_cr0(cr0 & ~X86_CR0_TS);
1346 	} else {
1347 		/*
1348 		 * Something terrible happened, and we're better off trying
1349 		 * to kill the task than getting stuck in a never-ending
1350 		 * loop of #NM faults.
1351 		 */
1352 		die("unexpected #NM exception", regs, 0);
1353 	}
1354 }
1355 
1356 #ifdef CONFIG_INTEL_TDX_GUEST
1357 
1358 #define VE_FAULT_STR "VE fault"
1359 
ve_raise_fault(struct pt_regs * regs,long error_code)1360 static void ve_raise_fault(struct pt_regs *regs, long error_code)
1361 {
1362 	if (user_mode(regs)) {
1363 		gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR);
1364 		return;
1365 	}
1366 
1367 	if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, VE_FAULT_STR))
1368 		return;
1369 
1370 	die_addr(VE_FAULT_STR, regs, error_code, 0);
1371 }
1372 
1373 /*
1374  * Virtualization Exceptions (#VE) are delivered to TDX guests due to
1375  * specific guest actions which may happen in either user space or the
1376  * kernel:
1377  *
1378  *  * Specific instructions (WBINVD, for example)
1379  *  * Specific MSR accesses
1380  *  * Specific CPUID leaf accesses
1381  *  * Access to specific guest physical addresses
1382  *
1383  * In the settings that Linux will run in, virtualization exceptions are
1384  * never generated on accesses to normal, TD-private memory that has been
1385  * accepted (by BIOS or with tdx_enc_status_changed()).
1386  *
1387  * Syscall entry code has a critical window where the kernel stack is not
1388  * yet set up. Any exception in this window leads to hard to debug issues
1389  * and can be exploited for privilege escalation. Exceptions in the NMI
1390  * entry code also cause issues. Returning from the exception handler with
1391  * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack.
1392  *
1393  * For these reasons, the kernel avoids #VEs during the syscall gap and
1394  * the NMI entry code. Entry code paths do not access TD-shared memory,
1395  * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves
1396  * that might generate #VE. VMM can remove memory from TD at any point,
1397  * but access to unaccepted (or missing) private memory leads to VM
1398  * termination, not to #VE.
1399  *
1400  * Similarly to page faults and breakpoints, #VEs are allowed in NMI
1401  * handlers once the kernel is ready to deal with nested NMIs.
1402  *
1403  * During #VE delivery, all interrupts, including NMIs, are blocked until
1404  * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads
1405  * the VE info.
1406  *
1407  * If a guest kernel action which would normally cause a #VE occurs in
1408  * the interrupt-disabled region before TDGETVEINFO, a #DF (fault
1409  * exception) is delivered to the guest which will result in an oops.
1410  *
1411  * The entry code has been audited carefully for following these expectations.
1412  * Changes in the entry code have to be audited for correctness vs. this
1413  * aspect. Similarly to #PF, #VE in these places will expose kernel to
1414  * privilege escalation or may lead to random crashes.
1415  */
DEFINE_IDTENTRY(exc_virtualization_exception)1416 DEFINE_IDTENTRY(exc_virtualization_exception)
1417 {
1418 	struct ve_info ve;
1419 
1420 	/*
1421 	 * NMIs/Machine-checks/Interrupts will be in a disabled state
1422 	 * till TDGETVEINFO TDCALL is executed. This ensures that VE
1423 	 * info cannot be overwritten by a nested #VE.
1424 	 */
1425 	tdx_get_ve_info(&ve);
1426 
1427 	cond_local_irq_enable(regs);
1428 
1429 	/*
1430 	 * If tdx_handle_virt_exception() could not process
1431 	 * it successfully, treat it as #GP(0) and handle it.
1432 	 */
1433 	if (!tdx_handle_virt_exception(regs, &ve))
1434 		ve_raise_fault(regs, 0);
1435 
1436 	cond_local_irq_disable(regs);
1437 }
1438 
1439 #endif
1440 
1441 #ifdef CONFIG_X86_32
DEFINE_IDTENTRY_SW(iret_error)1442 DEFINE_IDTENTRY_SW(iret_error)
1443 {
1444 	local_irq_enable();
1445 	if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1446 			X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1447 		do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1448 			ILL_BADSTK, (void __user *)NULL);
1449 	}
1450 	local_irq_disable();
1451 }
1452 #endif
1453 
trap_init(void)1454 void __init trap_init(void)
1455 {
1456 	/* Init cpu_entry_area before IST entries are set up */
1457 	setup_cpu_entry_areas();
1458 
1459 	/* Init GHCB memory pages when running as an SEV-ES guest */
1460 	sev_es_init_vc_handling();
1461 
1462 	/* Initialize TSS before setting up traps so ISTs work */
1463 	cpu_init_exception_handling();
1464 	/* Setup traps as cpu_init() might #GP */
1465 	idt_setup_traps();
1466 	cpu_init();
1467 }
1468