1 /*
2 * BK Id: %F% %I% %G% %U% %#%
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * <mlocke@mvista.com>
6 *
7 * Not much needed for the Embedded Planet 405gp board
8 *
9 * History: 11/09/2001 - armin
10 * added board_init to add in additional instuctions needed during platfrom_init
11 * cleaned up map_irq.
12 *
13 * 1/22/2002 - Armin
14 * converted pci to ocp
15 *
16 * Please read the COPYING file for all license details.
17 */
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <asm/system.h>
22 #include <asm/pci-bridge.h>
23 #include <asm/machdep.h>
24 #include <asm/todc.h>
25 #include <platforms/ibm_ocp.h>
26
27 #undef DEBUG
28 #ifdef DEBUG
29 #define DBG(x...) printk(x)
30 #else
31 #define DBG(x...)
32 #endif
33
34 u8 *ep405_bcsr;
35 u8 *ep405_nvram;
36
37 static struct {
38 u8 cpld_xirq_select;
39 int pci_idsel;
40 int irq;
41 } ep405_devtable[] = {
42 #ifdef CONFIG_EP405PC
43 {0x07, 0x0E, 25}, /* EP405PC: USB */
44 #endif
45 };
46 #define EP405_DEVTABLE_SIZE (sizeof(ep405_devtable)/sizeof(ep405_devtable[0]))
47
48 int __init
ppc405_map_irq(struct pci_dev * dev,unsigned char idsel,unsigned char pin)49 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
50 {
51 int i;
52
53 /* AFAICT this is only called a few times during PCI setup, so
54 performance is not critical */
55 for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
56 if (idsel == ep405_devtable[i].pci_idsel)
57 return ep405_devtable[i].irq;
58 }
59 return -1;
60 };
61
62 void __init
board_setup_arch(void)63 board_setup_arch(void)
64 {
65 bd_t *bip = (bd_t *) __res;
66
67 if (bip->bi_nvramsize == 512*1024) {
68 /* FIXME: we should properly handle NVRTCs of different sizes */
69 TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
70 }
71 }
72
73 #ifdef CONFIG_PCI
74 void __init
bios_fixup(struct pci_controller * hose,struct pcil0_regs * pcip)75 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
76 {
77 unsigned int bar_response, bar;
78 /*
79 * Expected PCI mapping:
80 *
81 * PLB addr PCI memory addr
82 * --------------------- ---------------------
83 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
84 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
85 *
86 * PLB addr PCI io addr
87 * --------------------- ---------------------
88 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
89 *
90 */
91
92 /* Disable region zero first */
93 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
94 /* PLB starting addr, PCI: 0x80000000 */
95 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
96 /* PCI start addr, 0x80000000 */
97 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
98 /* 512MB range of PLB to PCI */
99 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
100 /* Enable no pre-fetch, enable region */
101 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
102 (PPC405_PCI_UPPER_MEM -
103 PPC405_PCI_MEM_BASE)) | 0x01));
104
105 /* Disable region one */
106 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
107 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
108 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
109 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
110 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
111 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
112
113 /* Disable region two */
114 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
115 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
116 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
117 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
118 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
119 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
120
121 /* Configure PTM (PCI->PLB) region 1 */
122 out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
123 /* Disable PTM region 2 */
124 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
125
126 /* Zero config bars */
127 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
128 early_write_config_dword(hose, hose->first_busno,
129 PCI_FUNC(hose->first_busno), bar,
130 0x00000000);
131 early_read_config_dword(hose, hose->first_busno,
132 PCI_FUNC(hose->first_busno), bar,
133 &bar_response);
134 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
135 hose->first_busno, PCI_SLOT(hose->first_busno),
136 PCI_FUNC(hose->first_busno), bar, bar_response);
137 }
138 /* end work arround */
139 }
140 #endif
141
142 void __init
board_io_mapping(void)143 board_io_mapping(void)
144 {
145 bd_t *bip = (bd_t *) __res;
146
147 ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
148
149 if (bip->bi_nvramsize > 0) {
150 ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
151 }
152 }
153
154 void __init
board_setup_irq(void)155 board_setup_irq(void)
156 {
157 int i;
158
159 /* Workaround for a bug in the firmware it incorrectly sets
160 the IRQ polarities for XIRQ0 and XIRQ1 */
161 mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
162 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
163
164 /* Activate the XIRQs from the CPLD */
165 writeb(0xf0, ep405_bcsr+10);
166
167 /* Set up IRQ routing */
168 for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
169 if ( (ep405_devtable[i].irq >= 25)
170 && (ep405_devtable[i].irq) <= 31) {
171 writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
172 writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
173 }
174 }
175 }
176
177 void __init
board_init(void)178 board_init(void)
179 {
180 bd_t *bip = (bd_t *) __res;
181
182 #ifdef CONFIG_PPC_RTC
183 /* FIXME: we should be able to access the NVRAM even if PPC_RTC is not configured */
184 ppc_md.nvram_read_val = todc_direct_read_val;
185 ppc_md.nvram_write_val = todc_direct_write_val;
186
187 if (bip->bi_nvramsize == 512*1024) {
188 ppc_md.time_init = todc_time_init;
189 ppc_md.set_rtc_time = todc_set_rtc_time;
190 ppc_md.get_rtc_time = todc_get_rtc_time;
191 } else {
192 printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");
193 }
194
195 #endif
196 }
197