1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9
10 #include "capabilities.h"
11 #include "../kvm_cache_regs.h"
12 #include "posted_intr.h"
13 #include "vmcs.h"
14 #include "vmx_ops.h"
15 #include "../cpuid.h"
16 #include "run_flags.h"
17
18 #define MSR_TYPE_R 1
19 #define MSR_TYPE_W 2
20 #define MSR_TYPE_RW 3
21
22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
23
24 #ifdef CONFIG_X86_64
25 #define MAX_NR_USER_RETURN_MSRS 7
26 #else
27 #define MAX_NR_USER_RETURN_MSRS 4
28 #endif
29
30 #define MAX_NR_LOADSTORE_MSRS 8
31
32 struct vmx_msrs {
33 unsigned int nr;
34 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
35 };
36
37 struct vmx_uret_msr {
38 bool load_into_hardware;
39 u64 data;
40 u64 mask;
41 };
42
43 enum segment_cache_field {
44 SEG_FIELD_SEL = 0,
45 SEG_FIELD_BASE = 1,
46 SEG_FIELD_LIMIT = 2,
47 SEG_FIELD_AR = 3,
48
49 SEG_FIELD_NR = 4
50 };
51
52 #define RTIT_ADDR_RANGE 4
53
54 struct pt_ctx {
55 u64 ctl;
56 u64 status;
57 u64 output_base;
58 u64 output_mask;
59 u64 cr3_match;
60 u64 addr_a[RTIT_ADDR_RANGE];
61 u64 addr_b[RTIT_ADDR_RANGE];
62 };
63
64 struct pt_desc {
65 u64 ctl_bitmask;
66 u32 num_address_ranges;
67 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
68 struct pt_ctx host;
69 struct pt_ctx guest;
70 };
71
72 union vmx_exit_reason {
73 struct {
74 u32 basic : 16;
75 u32 reserved16 : 1;
76 u32 reserved17 : 1;
77 u32 reserved18 : 1;
78 u32 reserved19 : 1;
79 u32 reserved20 : 1;
80 u32 reserved21 : 1;
81 u32 reserved22 : 1;
82 u32 reserved23 : 1;
83 u32 reserved24 : 1;
84 u32 reserved25 : 1;
85 u32 bus_lock_detected : 1;
86 u32 enclave_mode : 1;
87 u32 smi_pending_mtf : 1;
88 u32 smi_from_vmx_root : 1;
89 u32 reserved30 : 1;
90 u32 failed_vmentry : 1;
91 };
92 u32 full;
93 };
94
intel_pmu_has_perf_global_ctrl(struct kvm_pmu * pmu)95 static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
96 {
97 /*
98 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
99 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
100 * greater than zero. However, KVM only exposes and emulates the MSR
101 * to/for the guest if the guest PMU supports at least "Architectural
102 * Performance Monitoring Version 2".
103 */
104 return pmu->version > 1;
105 }
106
107 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
108 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
109
110 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
111 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
112
113 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
114 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
115
116 struct lbr_desc {
117 /* Basic info about guest LBR records. */
118 struct x86_pmu_lbr records;
119
120 /*
121 * Emulate LBR feature via passthrough LBR registers when the
122 * per-vcpu guest LBR event is scheduled on the current pcpu.
123 *
124 * The records may be inaccurate if the host reclaims the LBR.
125 */
126 struct perf_event *event;
127
128 /* True if LBRs are marked as not intercepted in the MSR bitmap */
129 bool msr_passthrough;
130 };
131
132 /*
133 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
134 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
135 */
136 struct nested_vmx {
137 /* Has the level1 guest done vmxon? */
138 bool vmxon;
139 gpa_t vmxon_ptr;
140 bool pml_full;
141
142 /* The guest-physical address of the current VMCS L1 keeps for L2 */
143 gpa_t current_vmptr;
144 /*
145 * Cache of the guest's VMCS, existing outside of guest memory.
146 * Loaded from guest memory during VMPTRLD. Flushed to guest
147 * memory during VMCLEAR and VMPTRLD.
148 */
149 struct vmcs12 *cached_vmcs12;
150 /*
151 * Cache of the guest's shadow VMCS, existing outside of guest
152 * memory. Loaded from guest memory during VM entry. Flushed
153 * to guest memory during VM exit.
154 */
155 struct vmcs12 *cached_shadow_vmcs12;
156
157 /*
158 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
159 */
160 struct gfn_to_hva_cache shadow_vmcs12_cache;
161
162 /*
163 * GPA to HVA cache for VMCS12
164 */
165 struct gfn_to_hva_cache vmcs12_cache;
166
167 /*
168 * Indicates if the shadow vmcs or enlightened vmcs must be updated
169 * with the data held by struct vmcs12.
170 */
171 bool need_vmcs12_to_shadow_sync;
172 bool dirty_vmcs12;
173
174 /*
175 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
176 * changes in MSR bitmap for L1 or switching to a different L2. Note,
177 * this flag can only be used reliably in conjunction with a paravirt L1
178 * which informs L0 whether any changes to MSR bitmap for L2 were done
179 * on its side.
180 */
181 bool force_msr_bitmap_recalc;
182
183 /*
184 * Indicates lazily loaded guest state has not yet been decached from
185 * vmcs02.
186 */
187 bool need_sync_vmcs02_to_vmcs12_rare;
188
189 /*
190 * vmcs02 has been initialized, i.e. state that is constant for
191 * vmcs02 has been written to the backing VMCS. Initialization
192 * is delayed until L1 actually attempts to run a nested VM.
193 */
194 bool vmcs02_initialized;
195
196 bool change_vmcs01_virtual_apic_mode;
197 bool reload_vmcs01_apic_access_page;
198 bool update_vmcs01_cpu_dirty_logging;
199 bool update_vmcs01_apicv_status;
200
201 /*
202 * Enlightened VMCS has been enabled. It does not mean that L1 has to
203 * use it. However, VMX features available to L1 will be limited based
204 * on what the enlightened VMCS supports.
205 */
206 bool enlightened_vmcs_enabled;
207
208 /* L2 must run next, and mustn't decide to exit to L1. */
209 bool nested_run_pending;
210
211 /* Pending MTF VM-exit into L1. */
212 bool mtf_pending;
213
214 struct loaded_vmcs vmcs02;
215
216 /*
217 * Guest pages referred to in the vmcs02 with host-physical
218 * pointers, so we must keep them pinned while L2 runs.
219 */
220 struct page *apic_access_page;
221 struct kvm_host_map virtual_apic_map;
222 struct kvm_host_map pi_desc_map;
223
224 struct kvm_host_map msr_bitmap_map;
225
226 struct pi_desc *pi_desc;
227 bool pi_pending;
228 u16 posted_intr_nv;
229
230 struct hrtimer preemption_timer;
231 u64 preemption_timer_deadline;
232 bool has_preemption_timer_deadline;
233 bool preemption_timer_expired;
234
235 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
236 u64 vmcs01_debugctl;
237 u64 vmcs01_guest_bndcfgs;
238
239 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
240 int l1_tpr_threshold;
241
242 u16 vpid02;
243 u16 last_vpid;
244
245 struct nested_vmx_msrs msrs;
246
247 /* SMM related state */
248 struct {
249 /* in VMX operation on SMM entry? */
250 bool vmxon;
251 /* in guest mode on SMM entry? */
252 bool guest_mode;
253 } smm;
254
255 gpa_t hv_evmcs_vmptr;
256 struct kvm_host_map hv_evmcs_map;
257 struct hv_enlightened_vmcs *hv_evmcs;
258 };
259
260 struct vcpu_vmx {
261 struct kvm_vcpu vcpu;
262 u8 fail;
263 u8 x2apic_msr_bitmap_mode;
264
265 /*
266 * If true, host state has been stored in vmx->loaded_vmcs for
267 * the CPU registers that only need to be switched when transitioning
268 * to/from the kernel, and the registers have been loaded with guest
269 * values. If false, host state is loaded in the CPU registers
270 * and vmx->loaded_vmcs->host_state is invalid.
271 */
272 bool guest_state_loaded;
273
274 unsigned long exit_qualification;
275 u32 exit_intr_info;
276 u32 idt_vectoring_info;
277 ulong rflags;
278
279 /*
280 * User return MSRs are always emulated when enabled in the guest, but
281 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
282 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
283 * be loaded into hardware if those conditions aren't met.
284 */
285 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
286 bool guest_uret_msrs_loaded;
287 #ifdef CONFIG_X86_64
288 u64 msr_host_kernel_gs_base;
289 u64 msr_guest_kernel_gs_base;
290 #endif
291
292 u64 spec_ctrl;
293 u32 msr_ia32_umwait_control;
294
295 /*
296 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
297 * non-nested (L1) guest, it always points to vmcs01. For a nested
298 * guest (L2), it points to a different VMCS.
299 */
300 struct loaded_vmcs vmcs01;
301 struct loaded_vmcs *loaded_vmcs;
302
303 struct msr_autoload {
304 struct vmx_msrs guest;
305 struct vmx_msrs host;
306 } msr_autoload;
307
308 struct msr_autostore {
309 struct vmx_msrs guest;
310 } msr_autostore;
311
312 struct {
313 int vm86_active;
314 ulong save_rflags;
315 struct kvm_segment segs[8];
316 } rmode;
317 struct {
318 u32 bitmask; /* 4 bits per segment (1 bit per field) */
319 struct kvm_save_segment {
320 u16 selector;
321 unsigned long base;
322 u32 limit;
323 u32 ar;
324 } seg[8];
325 } segment_cache;
326 int vpid;
327 bool emulation_required;
328
329 union vmx_exit_reason exit_reason;
330
331 /* Posted interrupt descriptor */
332 struct pi_desc pi_desc;
333
334 /* Used if this vCPU is waiting for PI notification wakeup. */
335 struct list_head pi_wakeup_list;
336
337 /* Support for a guest hypervisor (nested VMX) */
338 struct nested_vmx nested;
339
340 /* Dynamic PLE window. */
341 unsigned int ple_window;
342 bool ple_window_dirty;
343
344 bool req_immediate_exit;
345
346 /* Support for PML */
347 #define PML_ENTITY_NUM 512
348 struct page *pml_pg;
349
350 /* apic deadline value in host tsc */
351 u64 hv_deadline_tsc;
352
353 unsigned long host_debugctlmsr;
354
355 /*
356 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
357 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
358 * in msr_ia32_feature_control_valid_bits.
359 */
360 u64 msr_ia32_feature_control;
361 u64 msr_ia32_feature_control_valid_bits;
362 /* SGX Launch Control public key hash */
363 u64 msr_ia32_sgxlepubkeyhash[4];
364 u64 msr_ia32_mcu_opt_ctrl;
365 bool disable_fb_clear;
366
367 struct pt_desc pt_desc;
368 struct lbr_desc lbr_desc;
369
370 /* Save desired MSR intercept (read: pass-through) state */
371 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 15
372 struct {
373 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
374 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
375 } shadow_msr_intercept;
376 };
377
378 struct kvm_vmx {
379 struct kvm kvm;
380
381 unsigned int tss_addr;
382 bool ept_identity_pagetable_done;
383 gpa_t ept_identity_map_addr;
384 };
385
386 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
387 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
388 struct loaded_vmcs *buddy);
389 int allocate_vpid(void);
390 void free_vpid(int vpid);
391 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
392 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
393 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
394 unsigned long fs_base, unsigned long gs_base);
395 int vmx_get_cpl(struct kvm_vcpu *vcpu);
396 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
397 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
398 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
399 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
400 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
401 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
402 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
403 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
404 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
405 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
406 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
407 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
408 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
409
410 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
411 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
412 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
413 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
414 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
415 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
416 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
417 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
418 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
419 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
420 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
421 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
422 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
423 unsigned int flags);
424 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
425 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
426
427 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
428 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
429
430 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
431 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
432
vmx_set_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type,bool value)433 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
434 int type, bool value)
435 {
436 if (value)
437 vmx_enable_intercept_for_msr(vcpu, msr, type);
438 else
439 vmx_disable_intercept_for_msr(vcpu, msr, type);
440 }
441
442 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
443
444 /*
445 * Note, early Intel manuals have the write-low and read-high bitmap offsets
446 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
447 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
448 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
449 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
450 * VM-Exit.
451 */
452 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
453 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
454 u32 msr) \
455 { \
456 int f = sizeof(unsigned long); \
457 \
458 if (msr <= 0x1fff) \
459 return bitop##_bit(msr, bitmap + base / f); \
460 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
461 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
462 return (rtype)true; \
463 }
464 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
465 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
466 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
467
BUILD_VMX_MSR_BITMAP_HELPERS(bool,test,test)468 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
469 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
470 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
471
472 static inline u8 vmx_get_rvi(void)
473 {
474 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
475 }
476
477 #define BUILD_CONTROLS_SHADOW(lname, uname) \
478 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
479 { \
480 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
481 vmcs_write32(uname, val); \
482 vmx->loaded_vmcs->controls_shadow.lname = val; \
483 } \
484 } \
485 static inline u32 __##lname##_controls_get(struct loaded_vmcs *vmcs) \
486 { \
487 return vmcs->controls_shadow.lname; \
488 } \
489 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
490 { \
491 return __##lname##_controls_get(vmx->loaded_vmcs); \
492 } \
493 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
494 { \
495 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
496 } \
497 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
498 { \
499 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
500 }
BUILD_CONTROLS_SHADOW(vm_entry,VM_ENTRY_CONTROLS)501 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
502 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
503 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
504 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
505 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
506
507 /*
508 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
509 * cache on demand. Other registers not listed here are synced to
510 * the cache immediately after VM-Exit.
511 */
512 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \
513 (1 << VCPU_REGS_RSP) | \
514 (1 << VCPU_EXREG_RFLAGS) | \
515 (1 << VCPU_EXREG_PDPTR) | \
516 (1 << VCPU_EXREG_SEGMENTS) | \
517 (1 << VCPU_EXREG_CR0) | \
518 (1 << VCPU_EXREG_CR3) | \
519 (1 << VCPU_EXREG_CR4) | \
520 (1 << VCPU_EXREG_EXIT_INFO_1) | \
521 (1 << VCPU_EXREG_EXIT_INFO_2))
522
523 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
524 {
525 return container_of(kvm, struct kvm_vmx, kvm);
526 }
527
to_vmx(struct kvm_vcpu * vcpu)528 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
529 {
530 return container_of(vcpu, struct vcpu_vmx, vcpu);
531 }
532
vmx_get_exit_qual(struct kvm_vcpu * vcpu)533 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
534 {
535 struct vcpu_vmx *vmx = to_vmx(vcpu);
536
537 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
538 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
539 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
540 }
541 return vmx->exit_qualification;
542 }
543
vmx_get_intr_info(struct kvm_vcpu * vcpu)544 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
545 {
546 struct vcpu_vmx *vmx = to_vmx(vcpu);
547
548 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
549 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
550 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
551 }
552 return vmx->exit_intr_info;
553 }
554
555 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
556 void free_vmcs(struct vmcs *vmcs);
557 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
558 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
559 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
560
alloc_vmcs(bool shadow)561 static inline struct vmcs *alloc_vmcs(bool shadow)
562 {
563 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
564 GFP_KERNEL_ACCOUNT);
565 }
566
vmx_has_waitpkg(struct vcpu_vmx * vmx)567 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
568 {
569 return secondary_exec_controls_get(vmx) &
570 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
571 }
572
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)573 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
574 {
575 if (!enable_ept)
576 return true;
577
578 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
579 }
580
is_unrestricted_guest(struct kvm_vcpu * vcpu)581 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
582 {
583 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
584 (secondary_exec_controls_get(to_vmx(vcpu)) &
585 SECONDARY_EXEC_UNRESTRICTED_GUEST));
586 }
587
588 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)589 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
590 {
591 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
592 }
593
594 void dump_vmcs(struct kvm_vcpu *vcpu);
595
vmx_get_instr_info_reg2(u32 vmx_instr_info)596 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
597 {
598 return (vmx_instr_info >> 28) & 0xf;
599 }
600
601 #endif /* __KVM_X86_VMX_H */
602