1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_gpio.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/console.h>
20 #include <linux/clk.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/delay.h>
25
26 #include <asm/mach-pic32/pic32.h>
27
28 /* UART name and device definitions */
29 #define PIC32_DEV_NAME "pic32-uart"
30 #define PIC32_MAX_UARTS 6
31 #define PIC32_SDEV_NAME "ttyPIC"
32
33 #define PIC32_UART_DFLT_BRATE 9600
34 #define PIC32_UART_TX_FIFO_DEPTH 8
35 #define PIC32_UART_RX_FIFO_DEPTH 8
36
37 #define PIC32_UART_MODE 0x00
38 #define PIC32_UART_STA 0x10
39 #define PIC32_UART_TX 0x20
40 #define PIC32_UART_RX 0x30
41 #define PIC32_UART_BRG 0x40
42
43 /* struct pic32_sport - pic32 serial port descriptor
44 * @port: uart port descriptor
45 * @idx: port index
46 * @irq_fault: virtual fault interrupt number
47 * @irq_fault_name: irq fault name
48 * @irq_rx: virtual rx interrupt number
49 * @irq_rx_name: irq rx name
50 * @irq_tx: virtual tx interrupt number
51 * @irq_tx_name: irq tx name
52 * @cts_gpiod: clear to send GPIO
53 * @dev: device descriptor
54 **/
55 struct pic32_sport {
56 struct uart_port port;
57 int idx;
58
59 int irq_fault;
60 const char *irq_fault_name;
61 int irq_rx;
62 const char *irq_rx_name;
63 int irq_tx;
64 const char *irq_tx_name;
65 bool enable_tx_irq;
66
67 struct gpio_desc *cts_gpiod;
68
69 struct clk *clk;
70
71 struct device *dev;
72 };
73
to_pic32_sport(struct uart_port * port)74 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
75 {
76 return container_of(port, struct pic32_sport, port);
77 }
78
pic32_uart_writel(struct pic32_sport * sport,u32 reg,u32 val)79 static inline void pic32_uart_writel(struct pic32_sport *sport,
80 u32 reg, u32 val)
81 {
82 __raw_writel(val, sport->port.membase + reg);
83 }
84
pic32_uart_readl(struct pic32_sport * sport,u32 reg)85 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
86 {
87 return __raw_readl(sport->port.membase + reg);
88 }
89
90 /* pic32 uart mode register bits */
91 #define PIC32_UART_MODE_ON BIT(15)
92 #define PIC32_UART_MODE_FRZ BIT(14)
93 #define PIC32_UART_MODE_SIDL BIT(13)
94 #define PIC32_UART_MODE_IREN BIT(12)
95 #define PIC32_UART_MODE_RTSMD BIT(11)
96 #define PIC32_UART_MODE_RESV1 BIT(10)
97 #define PIC32_UART_MODE_UEN1 BIT(9)
98 #define PIC32_UART_MODE_UEN0 BIT(8)
99 #define PIC32_UART_MODE_WAKE BIT(7)
100 #define PIC32_UART_MODE_LPBK BIT(6)
101 #define PIC32_UART_MODE_ABAUD BIT(5)
102 #define PIC32_UART_MODE_RXINV BIT(4)
103 #define PIC32_UART_MODE_BRGH BIT(3)
104 #define PIC32_UART_MODE_PDSEL1 BIT(2)
105 #define PIC32_UART_MODE_PDSEL0 BIT(1)
106 #define PIC32_UART_MODE_STSEL BIT(0)
107
108 /* pic32 uart status register bits */
109 #define PIC32_UART_STA_UTXISEL1 BIT(15)
110 #define PIC32_UART_STA_UTXISEL0 BIT(14)
111 #define PIC32_UART_STA_UTXINV BIT(13)
112 #define PIC32_UART_STA_URXEN BIT(12)
113 #define PIC32_UART_STA_UTXBRK BIT(11)
114 #define PIC32_UART_STA_UTXEN BIT(10)
115 #define PIC32_UART_STA_UTXBF BIT(9)
116 #define PIC32_UART_STA_TRMT BIT(8)
117 #define PIC32_UART_STA_URXISEL1 BIT(7)
118 #define PIC32_UART_STA_URXISEL0 BIT(6)
119 #define PIC32_UART_STA_ADDEN BIT(5)
120 #define PIC32_UART_STA_RIDLE BIT(4)
121 #define PIC32_UART_STA_PERR BIT(3)
122 #define PIC32_UART_STA_FERR BIT(2)
123 #define PIC32_UART_STA_OERR BIT(1)
124 #define PIC32_UART_STA_URXDA BIT(0)
125
126 /* pic32_sport pointer for console use */
127 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
128
pic32_wait_deplete_txbuf(struct pic32_sport * sport)129 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
130 {
131 /* wait for tx empty, otherwise chars will be lost or corrupted */
132 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
133 udelay(1);
134 }
135
136 /* serial core request to check if uart tx buffer is empty */
pic32_uart_tx_empty(struct uart_port * port)137 static unsigned int pic32_uart_tx_empty(struct uart_port *port)
138 {
139 struct pic32_sport *sport = to_pic32_sport(port);
140 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
141
142 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
143 }
144
145 /* serial core request to set UART outputs */
pic32_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)146 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
147 {
148 struct pic32_sport *sport = to_pic32_sport(port);
149
150 /* set loopback mode */
151 if (mctrl & TIOCM_LOOP)
152 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
153 PIC32_UART_MODE_LPBK);
154 else
155 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
156 PIC32_UART_MODE_LPBK);
157 }
158
159 /* serial core request to return the state of misc UART input pins */
pic32_uart_get_mctrl(struct uart_port * port)160 static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
161 {
162 struct pic32_sport *sport = to_pic32_sport(port);
163 unsigned int mctrl = 0;
164
165 /* get the state of CTS input pin for this port */
166 if (!sport->cts_gpiod)
167 mctrl |= TIOCM_CTS;
168 else if (gpiod_get_value(sport->cts_gpiod))
169 mctrl |= TIOCM_CTS;
170
171 /* DSR and CD are not supported in PIC32, so return 1
172 * RI is not supported in PIC32, so return 0
173 */
174 mctrl |= TIOCM_CD;
175 mctrl |= TIOCM_DSR;
176
177 return mctrl;
178 }
179
180 /* stop tx and start tx are not called in pairs, therefore a flag indicates
181 * the status of irq to control the irq-depth.
182 */
pic32_uart_irqtxen(struct pic32_sport * sport,u8 en)183 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
184 {
185 if (en && !sport->enable_tx_irq) {
186 enable_irq(sport->irq_tx);
187 sport->enable_tx_irq = true;
188 } else if (!en && sport->enable_tx_irq) {
189 /* use disable_irq_nosync() and not disable_irq() to avoid self
190 * imposed deadlock by not waiting for irq handler to end,
191 * since this callback is called from interrupt context.
192 */
193 disable_irq_nosync(sport->irq_tx);
194 sport->enable_tx_irq = false;
195 }
196 }
197
198 /* serial core request to disable tx ASAP (used for flow control) */
pic32_uart_stop_tx(struct uart_port * port)199 static void pic32_uart_stop_tx(struct uart_port *port)
200 {
201 struct pic32_sport *sport = to_pic32_sport(port);
202
203 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
204 return;
205
206 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
207 return;
208
209 /* wait for tx empty */
210 pic32_wait_deplete_txbuf(sport);
211
212 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
213 PIC32_UART_STA_UTXEN);
214 pic32_uart_irqtxen(sport, 0);
215 }
216
217 /* serial core request to (re)enable tx */
pic32_uart_start_tx(struct uart_port * port)218 static void pic32_uart_start_tx(struct uart_port *port)
219 {
220 struct pic32_sport *sport = to_pic32_sport(port);
221
222 pic32_uart_irqtxen(sport, 1);
223 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
224 PIC32_UART_STA_UTXEN);
225 }
226
227 /* serial core request to stop rx, called before port shutdown */
pic32_uart_stop_rx(struct uart_port * port)228 static void pic32_uart_stop_rx(struct uart_port *port)
229 {
230 struct pic32_sport *sport = to_pic32_sport(port);
231
232 /* disable rx interrupts */
233 disable_irq(sport->irq_rx);
234
235 /* receiver Enable bit OFF */
236 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
237 PIC32_UART_STA_URXEN);
238 }
239
240 /* serial core request to start/stop emitting break char */
pic32_uart_break_ctl(struct uart_port * port,int ctl)241 static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
242 {
243 struct pic32_sport *sport = to_pic32_sport(port);
244 unsigned long flags;
245
246 spin_lock_irqsave(&port->lock, flags);
247
248 if (ctl)
249 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
250 PIC32_UART_STA_UTXBRK);
251 else
252 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
253 PIC32_UART_STA_UTXBRK);
254
255 spin_unlock_irqrestore(&port->lock, flags);
256 }
257
258 /* get port type in string format */
pic32_uart_type(struct uart_port * port)259 static const char *pic32_uart_type(struct uart_port *port)
260 {
261 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
262 }
263
264 /* read all chars in rx fifo and send them to core */
pic32_uart_do_rx(struct uart_port * port)265 static void pic32_uart_do_rx(struct uart_port *port)
266 {
267 struct pic32_sport *sport = to_pic32_sport(port);
268 struct tty_port *tty;
269 unsigned int max_count;
270
271 /* limit number of char read in interrupt, should not be
272 * higher than fifo size anyway since we're much faster than
273 * serial port
274 */
275 max_count = PIC32_UART_RX_FIFO_DEPTH;
276
277 spin_lock(&port->lock);
278
279 tty = &port->state->port;
280
281 do {
282 u32 sta_reg, c;
283 char flag;
284
285 /* get overrun/fifo empty information from status register */
286 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
287 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
288
289 /* fifo reset is required to clear interrupt */
290 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
291 PIC32_UART_STA_OERR);
292
293 port->icount.overrun++;
294 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
295 }
296
297 /* Can at least one more character can be read? */
298 if (!(sta_reg & PIC32_UART_STA_URXDA))
299 break;
300
301 /* read the character and increment the rx counter */
302 c = pic32_uart_readl(sport, PIC32_UART_RX);
303
304 port->icount.rx++;
305 flag = TTY_NORMAL;
306 c &= 0xff;
307
308 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
309 (sta_reg & PIC32_UART_STA_FERR))) {
310
311 /* do stats first */
312 if (sta_reg & PIC32_UART_STA_PERR)
313 port->icount.parity++;
314 if (sta_reg & PIC32_UART_STA_FERR)
315 port->icount.frame++;
316
317 /* update flag wrt read_status_mask */
318 sta_reg &= port->read_status_mask;
319
320 if (sta_reg & PIC32_UART_STA_FERR)
321 flag = TTY_FRAME;
322 if (sta_reg & PIC32_UART_STA_PERR)
323 flag = TTY_PARITY;
324 }
325
326 if (uart_handle_sysrq_char(port, c))
327 continue;
328
329 if ((sta_reg & port->ignore_status_mask) == 0)
330 tty_insert_flip_char(tty, c, flag);
331
332 } while (--max_count);
333
334 spin_unlock(&port->lock);
335
336 tty_flip_buffer_push(tty);
337 }
338
339 /* fill tx fifo with chars to send, stop when fifo is about to be full
340 * or when all chars have been sent.
341 */
pic32_uart_do_tx(struct uart_port * port)342 static void pic32_uart_do_tx(struct uart_port *port)
343 {
344 struct pic32_sport *sport = to_pic32_sport(port);
345 struct circ_buf *xmit = &port->state->xmit;
346 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
347
348 if (port->x_char) {
349 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
350 port->icount.tx++;
351 port->x_char = 0;
352 return;
353 }
354
355 if (uart_tx_stopped(port)) {
356 pic32_uart_stop_tx(port);
357 return;
358 }
359
360 if (uart_circ_empty(xmit))
361 goto txq_empty;
362
363 /* keep stuffing chars into uart tx buffer
364 * 1) until uart fifo is full
365 * or
366 * 2) until the circ buffer is empty
367 * (all chars have been sent)
368 * or
369 * 3) until the max count is reached
370 * (prevents lingering here for too long in certain cases)
371 */
372 while (!(PIC32_UART_STA_UTXBF &
373 pic32_uart_readl(sport, PIC32_UART_STA))) {
374 unsigned int c = xmit->buf[xmit->tail];
375
376 pic32_uart_writel(sport, PIC32_UART_TX, c);
377
378 uart_xmit_advance(port, 1);
379 if (uart_circ_empty(xmit))
380 break;
381 if (--max_count == 0)
382 break;
383 }
384
385 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
386 uart_write_wakeup(port);
387
388 if (uart_circ_empty(xmit))
389 goto txq_empty;
390
391 return;
392
393 txq_empty:
394 pic32_uart_irqtxen(sport, 0);
395 }
396
397 /* RX interrupt handler */
pic32_uart_rx_interrupt(int irq,void * dev_id)398 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
399 {
400 struct uart_port *port = dev_id;
401
402 pic32_uart_do_rx(port);
403
404 return IRQ_HANDLED;
405 }
406
407 /* TX interrupt handler */
pic32_uart_tx_interrupt(int irq,void * dev_id)408 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
409 {
410 struct uart_port *port = dev_id;
411 unsigned long flags;
412
413 spin_lock_irqsave(&port->lock, flags);
414 pic32_uart_do_tx(port);
415 spin_unlock_irqrestore(&port->lock, flags);
416
417 return IRQ_HANDLED;
418 }
419
420 /* FAULT interrupt handler */
pic32_uart_fault_interrupt(int irq,void * dev_id)421 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
422 {
423 /* do nothing: pic32_uart_do_rx() handles faults. */
424 return IRQ_HANDLED;
425 }
426
427 /* enable rx & tx operation on uart */
pic32_uart_en_and_unmask(struct uart_port * port)428 static void pic32_uart_en_and_unmask(struct uart_port *port)
429 {
430 struct pic32_sport *sport = to_pic32_sport(port);
431
432 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
433 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
434 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
435 PIC32_UART_MODE_ON);
436 }
437
438 /* disable rx & tx operation on uart */
pic32_uart_dsbl_and_mask(struct uart_port * port)439 static void pic32_uart_dsbl_and_mask(struct uart_port *port)
440 {
441 struct pic32_sport *sport = to_pic32_sport(port);
442
443 /* wait for tx empty, otherwise chars will be lost or corrupted */
444 pic32_wait_deplete_txbuf(sport);
445
446 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
447 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
448 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
449 PIC32_UART_MODE_ON);
450 }
451
452 /* serial core request to initialize uart and start rx operation */
pic32_uart_startup(struct uart_port * port)453 static int pic32_uart_startup(struct uart_port *port)
454 {
455 struct pic32_sport *sport = to_pic32_sport(port);
456 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
457 unsigned long flags;
458 int ret;
459
460 local_irq_save(flags);
461
462 ret = clk_prepare_enable(sport->clk);
463 if (ret) {
464 local_irq_restore(flags);
465 goto out_done;
466 }
467
468 /* clear status and mode registers */
469 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
470 pic32_uart_writel(sport, PIC32_UART_STA, 0);
471
472 /* disable uart and mask all interrupts */
473 pic32_uart_dsbl_and_mask(port);
474
475 /* set default baud */
476 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
477
478 local_irq_restore(flags);
479
480 /* Each UART of a PIC32 has three interrupts therefore,
481 * we setup driver to register the 3 irqs for the device.
482 *
483 * For each irq request_irq() is called with interrupt disabled.
484 * And the irq is enabled as soon as we are ready to handle them.
485 */
486 sport->enable_tx_irq = false;
487
488 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
489 pic32_uart_type(port),
490 sport->idx);
491 if (!sport->irq_fault_name) {
492 dev_err(port->dev, "%s: kasprintf err!", __func__);
493 ret = -ENOMEM;
494 goto out_disable_clk;
495 }
496 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
497 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
498 IRQF_NO_THREAD, sport->irq_fault_name, port);
499 if (ret) {
500 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
501 __func__, sport->irq_fault, ret,
502 pic32_uart_type(port));
503 goto out_f;
504 }
505
506 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
507 pic32_uart_type(port),
508 sport->idx);
509 if (!sport->irq_rx_name) {
510 dev_err(port->dev, "%s: kasprintf err!", __func__);
511 ret = -ENOMEM;
512 goto out_f;
513 }
514 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
515 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
516 IRQF_NO_THREAD, sport->irq_rx_name, port);
517 if (ret) {
518 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
519 __func__, sport->irq_rx, ret,
520 pic32_uart_type(port));
521 goto out_r;
522 }
523
524 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
525 pic32_uart_type(port),
526 sport->idx);
527 if (!sport->irq_tx_name) {
528 dev_err(port->dev, "%s: kasprintf err!", __func__);
529 ret = -ENOMEM;
530 goto out_r;
531 }
532 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
533 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
534 IRQF_NO_THREAD, sport->irq_tx_name, port);
535 if (ret) {
536 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
537 __func__, sport->irq_tx, ret,
538 pic32_uart_type(port));
539 goto out_t;
540 }
541
542 local_irq_save(flags);
543
544 /* set rx interrupt on first receive */
545 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
546 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
547
548 /* set interrupt on empty */
549 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
550 PIC32_UART_STA_UTXISEL1);
551
552 /* enable all interrupts and eanable uart */
553 pic32_uart_en_and_unmask(port);
554
555 local_irq_restore(flags);
556
557 enable_irq(sport->irq_rx);
558
559 return 0;
560
561 out_t:
562 free_irq(sport->irq_tx, port);
563 kfree(sport->irq_tx_name);
564 out_r:
565 free_irq(sport->irq_rx, port);
566 kfree(sport->irq_rx_name);
567 out_f:
568 free_irq(sport->irq_fault, port);
569 kfree(sport->irq_fault_name);
570 out_disable_clk:
571 clk_disable_unprepare(sport->clk);
572 out_done:
573 return ret;
574 }
575
576 /* serial core request to flush & disable uart */
pic32_uart_shutdown(struct uart_port * port)577 static void pic32_uart_shutdown(struct uart_port *port)
578 {
579 struct pic32_sport *sport = to_pic32_sport(port);
580 unsigned long flags;
581
582 /* disable uart */
583 spin_lock_irqsave(&port->lock, flags);
584 pic32_uart_dsbl_and_mask(port);
585 spin_unlock_irqrestore(&port->lock, flags);
586 clk_disable_unprepare(sport->clk);
587
588 /* free all 3 interrupts for this UART */
589 free_irq(sport->irq_fault, port);
590 kfree(sport->irq_fault_name);
591 free_irq(sport->irq_tx, port);
592 kfree(sport->irq_tx_name);
593 free_irq(sport->irq_rx, port);
594 kfree(sport->irq_rx_name);
595 }
596
597 /* serial core request to change current uart setting */
pic32_uart_set_termios(struct uart_port * port,struct ktermios * new,const struct ktermios * old)598 static void pic32_uart_set_termios(struct uart_port *port,
599 struct ktermios *new,
600 const struct ktermios *old)
601 {
602 struct pic32_sport *sport = to_pic32_sport(port);
603 unsigned int baud;
604 unsigned int quot;
605 unsigned long flags;
606
607 spin_lock_irqsave(&port->lock, flags);
608
609 /* disable uart and mask all interrupts while changing speed */
610 pic32_uart_dsbl_and_mask(port);
611
612 /* stop bit options */
613 if (new->c_cflag & CSTOPB)
614 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
615 PIC32_UART_MODE_STSEL);
616 else
617 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
618 PIC32_UART_MODE_STSEL);
619
620 /* parity options */
621 if (new->c_cflag & PARENB) {
622 if (new->c_cflag & PARODD) {
623 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
624 PIC32_UART_MODE_PDSEL1);
625 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
626 PIC32_UART_MODE_PDSEL0);
627 } else {
628 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
629 PIC32_UART_MODE_PDSEL0);
630 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
631 PIC32_UART_MODE_PDSEL1);
632 }
633 } else {
634 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
635 PIC32_UART_MODE_PDSEL1 |
636 PIC32_UART_MODE_PDSEL0);
637 }
638 /* if hw flow ctrl, then the pins must be specified in device tree */
639 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
640 /* enable hardware flow control */
641 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
642 PIC32_UART_MODE_UEN1);
643 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
644 PIC32_UART_MODE_UEN0);
645 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
646 PIC32_UART_MODE_RTSMD);
647 } else {
648 /* disable hardware flow control */
649 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
650 PIC32_UART_MODE_UEN1);
651 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
652 PIC32_UART_MODE_UEN0);
653 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
654 PIC32_UART_MODE_RTSMD);
655 }
656
657 /* Always 8-bit */
658 new->c_cflag |= CS8;
659
660 /* Mark/Space parity is not supported */
661 new->c_cflag &= ~CMSPAR;
662
663 /* update baud */
664 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
665 quot = uart_get_divisor(port, baud) - 1;
666 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
667 uart_update_timeout(port, new->c_cflag, baud);
668
669 if (tty_termios_baud_rate(new))
670 tty_termios_encode_baud_rate(new, baud, baud);
671
672 /* enable uart */
673 pic32_uart_en_and_unmask(port);
674
675 spin_unlock_irqrestore(&port->lock, flags);
676 }
677
678 /* serial core request to claim uart iomem */
pic32_uart_request_port(struct uart_port * port)679 static int pic32_uart_request_port(struct uart_port *port)
680 {
681 struct platform_device *pdev = to_platform_device(port->dev);
682 struct resource *res_mem;
683
684 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685 if (unlikely(!res_mem))
686 return -EINVAL;
687
688 if (!request_mem_region(port->mapbase, resource_size(res_mem),
689 "pic32_uart_mem"))
690 return -EBUSY;
691
692 port->membase = devm_ioremap(port->dev, port->mapbase,
693 resource_size(res_mem));
694 if (!port->membase) {
695 dev_err(port->dev, "Unable to map registers\n");
696 release_mem_region(port->mapbase, resource_size(res_mem));
697 return -ENOMEM;
698 }
699
700 return 0;
701 }
702
703 /* serial core request to release uart iomem */
pic32_uart_release_port(struct uart_port * port)704 static void pic32_uart_release_port(struct uart_port *port)
705 {
706 struct platform_device *pdev = to_platform_device(port->dev);
707 struct resource *res_mem;
708 unsigned int res_size;
709
710 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 if (unlikely(!res_mem))
712 return;
713 res_size = resource_size(res_mem);
714
715 release_mem_region(port->mapbase, res_size);
716 }
717
718 /* serial core request to do any port required auto-configuration */
pic32_uart_config_port(struct uart_port * port,int flags)719 static void pic32_uart_config_port(struct uart_port *port, int flags)
720 {
721 if (flags & UART_CONFIG_TYPE) {
722 if (pic32_uart_request_port(port))
723 return;
724 port->type = PORT_PIC32;
725 }
726 }
727
728 /* serial core request to check that port information in serinfo are suitable */
pic32_uart_verify_port(struct uart_port * port,struct serial_struct * serinfo)729 static int pic32_uart_verify_port(struct uart_port *port,
730 struct serial_struct *serinfo)
731 {
732 if (port->type != PORT_PIC32)
733 return -EINVAL;
734 if (port->irq != serinfo->irq)
735 return -EINVAL;
736 if (port->iotype != serinfo->io_type)
737 return -EINVAL;
738 if (port->mapbase != (unsigned long)serinfo->iomem_base)
739 return -EINVAL;
740
741 return 0;
742 }
743
744 /* serial core callbacks */
745 static const struct uart_ops pic32_uart_ops = {
746 .tx_empty = pic32_uart_tx_empty,
747 .get_mctrl = pic32_uart_get_mctrl,
748 .set_mctrl = pic32_uart_set_mctrl,
749 .start_tx = pic32_uart_start_tx,
750 .stop_tx = pic32_uart_stop_tx,
751 .stop_rx = pic32_uart_stop_rx,
752 .break_ctl = pic32_uart_break_ctl,
753 .startup = pic32_uart_startup,
754 .shutdown = pic32_uart_shutdown,
755 .set_termios = pic32_uart_set_termios,
756 .type = pic32_uart_type,
757 .release_port = pic32_uart_release_port,
758 .request_port = pic32_uart_request_port,
759 .config_port = pic32_uart_config_port,
760 .verify_port = pic32_uart_verify_port,
761 };
762
763 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
764 /* output given char */
pic32_console_putchar(struct uart_port * port,unsigned char ch)765 static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
766 {
767 struct pic32_sport *sport = to_pic32_sport(port);
768
769 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
770 return;
771
772 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
773 return;
774
775 /* wait for tx empty */
776 pic32_wait_deplete_txbuf(sport);
777
778 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
779 }
780
781 /* console core request to output given string */
pic32_console_write(struct console * co,const char * s,unsigned int count)782 static void pic32_console_write(struct console *co, const char *s,
783 unsigned int count)
784 {
785 struct pic32_sport *sport = pic32_sports[co->index];
786
787 /* call uart helper to deal with \r\n */
788 uart_console_write(&sport->port, s, count, pic32_console_putchar);
789 }
790
791 /* console core request to setup given console, find matching uart
792 * port and setup it.
793 */
pic32_console_setup(struct console * co,char * options)794 static int pic32_console_setup(struct console *co, char *options)
795 {
796 struct pic32_sport *sport;
797 int baud = 115200;
798 int bits = 8;
799 int parity = 'n';
800 int flow = 'n';
801 int ret = 0;
802
803 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
804 return -ENODEV;
805
806 sport = pic32_sports[co->index];
807 if (!sport)
808 return -ENODEV;
809
810 ret = clk_prepare_enable(sport->clk);
811 if (ret)
812 return ret;
813
814 if (options)
815 uart_parse_options(options, &baud, &parity, &bits, &flow);
816
817 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
818 }
819
820 static struct uart_driver pic32_uart_driver;
821 static struct console pic32_console = {
822 .name = PIC32_SDEV_NAME,
823 .write = pic32_console_write,
824 .device = uart_console_device,
825 .setup = pic32_console_setup,
826 .flags = CON_PRINTBUFFER,
827 .index = -1,
828 .data = &pic32_uart_driver,
829 };
830 #define PIC32_SCONSOLE (&pic32_console)
831
pic32_console_init(void)832 static int __init pic32_console_init(void)
833 {
834 register_console(&pic32_console);
835 return 0;
836 }
837 console_initcall(pic32_console_init);
838
839 /*
840 * Late console initialization.
841 */
pic32_late_console_init(void)842 static int __init pic32_late_console_init(void)
843 {
844 if (!console_is_registered(&pic32_console))
845 register_console(&pic32_console);
846
847 return 0;
848 }
849
850 core_initcall(pic32_late_console_init);
851
852 #else
853 #define PIC32_SCONSOLE NULL
854 #endif
855
856 static struct uart_driver pic32_uart_driver = {
857 .owner = THIS_MODULE,
858 .driver_name = PIC32_DEV_NAME,
859 .dev_name = PIC32_SDEV_NAME,
860 .nr = PIC32_MAX_UARTS,
861 .cons = PIC32_SCONSOLE,
862 };
863
pic32_uart_probe(struct platform_device * pdev)864 static int pic32_uart_probe(struct platform_device *pdev)
865 {
866 struct device *dev = &pdev->dev;
867 struct device_node *np = dev->of_node;
868 struct pic32_sport *sport;
869 int uart_idx = 0;
870 struct resource *res_mem;
871 struct uart_port *port;
872 int ret;
873
874 uart_idx = of_alias_get_id(np, "serial");
875 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
876 return -EINVAL;
877
878 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879 if (!res_mem)
880 return -EINVAL;
881
882 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
883 if (!sport)
884 return -ENOMEM;
885
886 sport->idx = uart_idx;
887 sport->irq_fault = irq_of_parse_and_map(np, 0);
888 sport->irq_rx = irq_of_parse_and_map(np, 1);
889 sport->irq_tx = irq_of_parse_and_map(np, 2);
890 sport->clk = devm_clk_get(&pdev->dev, NULL);
891 if (IS_ERR(sport->clk))
892 return PTR_ERR(sport->clk);
893 sport->dev = &pdev->dev;
894
895 /* Hardware flow control: gpios
896 * !Note: Basically, CTS is needed for reading the status.
897 */
898 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
899 if (IS_ERR(sport->cts_gpiod))
900 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
901 gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
902
903 pic32_sports[uart_idx] = sport;
904 port = &sport->port;
905 port->iotype = UPIO_MEM;
906 port->mapbase = res_mem->start;
907 port->ops = &pic32_uart_ops;
908 port->flags = UPF_BOOT_AUTOCONF;
909 port->dev = &pdev->dev;
910 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
911 port->uartclk = clk_get_rate(sport->clk);
912 port->line = uart_idx;
913
914 ret = uart_add_one_port(&pic32_uart_driver, port);
915 if (ret) {
916 port->membase = NULL;
917 dev_err(port->dev, "%s: uart add port error!\n", __func__);
918 goto err;
919 }
920
921 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
922 if (uart_console_registered(port)) {
923 /* The peripheral clock has been enabled by console_setup,
924 * so disable it till the port is used.
925 */
926 clk_disable_unprepare(sport->clk);
927 }
928 #endif
929
930 platform_set_drvdata(pdev, port);
931
932 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
933 __func__, uart_idx);
934
935 return 0;
936 err:
937 /* automatic unroll of sport and gpios */
938 return ret;
939 }
940
pic32_uart_remove(struct platform_device * pdev)941 static int pic32_uart_remove(struct platform_device *pdev)
942 {
943 struct uart_port *port = platform_get_drvdata(pdev);
944 struct pic32_sport *sport = to_pic32_sport(port);
945
946 uart_remove_one_port(&pic32_uart_driver, port);
947 clk_disable_unprepare(sport->clk);
948 platform_set_drvdata(pdev, NULL);
949 pic32_sports[sport->idx] = NULL;
950
951 /* automatic unroll of sport and gpios */
952 return 0;
953 }
954
955 static const struct of_device_id pic32_serial_dt_ids[] = {
956 { .compatible = "microchip,pic32mzda-uart" },
957 { /* sentinel */ }
958 };
959 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
960
961 static struct platform_driver pic32_uart_platform_driver = {
962 .probe = pic32_uart_probe,
963 .remove = pic32_uart_remove,
964 .driver = {
965 .name = PIC32_DEV_NAME,
966 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
967 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
968 },
969 };
970
pic32_uart_init(void)971 static int __init pic32_uart_init(void)
972 {
973 int ret;
974
975 ret = uart_register_driver(&pic32_uart_driver);
976 if (ret) {
977 pr_err("failed to register %s:%d\n",
978 pic32_uart_driver.driver_name, ret);
979 return ret;
980 }
981
982 ret = platform_driver_register(&pic32_uart_platform_driver);
983 if (ret) {
984 pr_err("fail to register pic32 uart\n");
985 uart_unregister_driver(&pic32_uart_driver);
986 }
987
988 return ret;
989 }
990 arch_initcall(pic32_uart_init);
991
pic32_uart_exit(void)992 static void __exit pic32_uart_exit(void)
993 {
994 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
995 unregister_console(&pic32_console);
996 #endif
997 platform_driver_unregister(&pic32_uart_platform_driver);
998 uart_unregister_driver(&pic32_uart_driver);
999 }
1000 module_exit(pic32_uart_exit);
1001
1002 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1003 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1004 MODULE_LICENSE("GPL v2");
1005