1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 *
5 * Copyright (C) 1992 Linus Torvalds
6 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
7 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
8 * Copyright (C) 1999-2000 Grant Grundler
9 * Copyright (c) 2005 Matthew Wilcox
10 */
11 #include <linux/bitops.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/types.h>
18 #include <linux/sched/task_stack.h>
19 #include <asm/io.h>
20
21 #include <asm/softirq_stack.h>
22 #include <asm/smp.h>
23 #include <asm/ldcw.h>
24
25 #undef PARISC_IRQ_CR16_COUNTS
26
27 extern irqreturn_t timer_interrupt(int, void *);
28 extern irqreturn_t ipi_interrupt(int, void *);
29
30 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
31
32 /* Bits in EIEM correlate with cpu_irq_action[].
33 ** Numbered *Big Endian*! (ie bit 0 is MSB)
34 */
35 static volatile unsigned long cpu_eiem = 0;
36
37 /*
38 ** local ACK bitmap ... habitually set to 1, but reset to zero
39 ** between ->ack() and ->end() of the interrupt to prevent
40 ** re-interruption of a processing interrupt.
41 */
42 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
43
cpu_mask_irq(struct irq_data * d)44 static void cpu_mask_irq(struct irq_data *d)
45 {
46 unsigned long eirr_bit = EIEM_MASK(d->irq);
47
48 cpu_eiem &= ~eirr_bit;
49 /* Do nothing on the other CPUs. If they get this interrupt,
50 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
51 * handle it, and the set_eiem() at the bottom will ensure it
52 * then gets disabled */
53 }
54
__cpu_unmask_irq(unsigned int irq)55 static void __cpu_unmask_irq(unsigned int irq)
56 {
57 unsigned long eirr_bit = EIEM_MASK(irq);
58
59 cpu_eiem |= eirr_bit;
60
61 /* This is just a simple NOP IPI. But what it does is cause
62 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
63 * of the interrupt handler */
64 smp_send_all_nop();
65 }
66
cpu_unmask_irq(struct irq_data * d)67 static void cpu_unmask_irq(struct irq_data *d)
68 {
69 __cpu_unmask_irq(d->irq);
70 }
71
cpu_ack_irq(struct irq_data * d)72 void cpu_ack_irq(struct irq_data *d)
73 {
74 unsigned long mask = EIEM_MASK(d->irq);
75 int cpu = smp_processor_id();
76
77 /* Clear in EIEM so we can no longer process */
78 per_cpu(local_ack_eiem, cpu) &= ~mask;
79
80 /* disable the interrupt */
81 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
82
83 /* and now ack it */
84 mtctl(mask, 23);
85 }
86
cpu_eoi_irq(struct irq_data * d)87 void cpu_eoi_irq(struct irq_data *d)
88 {
89 unsigned long mask = EIEM_MASK(d->irq);
90 int cpu = smp_processor_id();
91
92 /* set it in the eiems---it's no longer in process */
93 per_cpu(local_ack_eiem, cpu) |= mask;
94
95 /* enable the interrupt */
96 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
97 }
98
99 #ifdef CONFIG_SMP
cpu_check_affinity(struct irq_data * d,const struct cpumask * dest)100 int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
101 {
102 int cpu_dest;
103
104 /* timer and ipi have to always be received on all CPUs */
105 if (irqd_is_per_cpu(d))
106 return -EINVAL;
107
108 cpu_dest = cpumask_first_and(dest, cpu_online_mask);
109 if (cpu_dest >= nr_cpu_ids)
110 cpu_dest = cpumask_first(cpu_online_mask);
111
112 return cpu_dest;
113 }
114 #endif
115
116 static struct irq_chip cpu_interrupt_type = {
117 .name = "CPU",
118 .irq_mask = cpu_mask_irq,
119 .irq_unmask = cpu_unmask_irq,
120 .irq_ack = cpu_ack_irq,
121 .irq_eoi = cpu_eoi_irq,
122 /* XXX: Needs to be written. We managed without it so far, but
123 * we really ought to write it.
124 */
125 .irq_retrigger = NULL,
126 };
127
128 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
129 #define irq_stats(x) (&per_cpu(irq_stat, x))
130
131 /*
132 * /proc/interrupts printing for arch specific interrupts
133 */
arch_show_interrupts(struct seq_file * p,int prec)134 int arch_show_interrupts(struct seq_file *p, int prec)
135 {
136 int j;
137
138 #ifdef CONFIG_DEBUG_STACKOVERFLOW
139 seq_printf(p, "%*s: ", prec, "STK");
140 for_each_online_cpu(j)
141 seq_printf(p, "%10u ", irq_stats(j)->kernel_stack_usage);
142 seq_puts(p, " Kernel stack usage\n");
143 # ifdef CONFIG_IRQSTACKS
144 seq_printf(p, "%*s: ", prec, "IST");
145 for_each_online_cpu(j)
146 seq_printf(p, "%10u ", irq_stats(j)->irq_stack_usage);
147 seq_puts(p, " Interrupt stack usage\n");
148 # endif
149 #endif
150 #ifdef CONFIG_SMP
151 if (num_online_cpus() > 1) {
152 seq_printf(p, "%*s: ", prec, "RES");
153 for_each_online_cpu(j)
154 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
155 seq_puts(p, " Rescheduling interrupts\n");
156 seq_printf(p, "%*s: ", prec, "CAL");
157 for_each_online_cpu(j)
158 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
159 seq_puts(p, " Function call interrupts\n");
160 }
161 #endif
162 seq_printf(p, "%*s: ", prec, "UAH");
163 for_each_online_cpu(j)
164 seq_printf(p, "%10u ", irq_stats(j)->irq_unaligned_count);
165 seq_puts(p, " Unaligned access handler traps\n");
166 seq_printf(p, "%*s: ", prec, "FPA");
167 for_each_online_cpu(j)
168 seq_printf(p, "%10u ", irq_stats(j)->irq_fpassist_count);
169 seq_puts(p, " Floating point assist traps\n");
170 seq_printf(p, "%*s: ", prec, "TLB");
171 for_each_online_cpu(j)
172 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
173 seq_puts(p, " TLB shootdowns\n");
174 return 0;
175 }
176
show_interrupts(struct seq_file * p,void * v)177 int show_interrupts(struct seq_file *p, void *v)
178 {
179 int i = *(loff_t *) v, j;
180 unsigned long flags;
181
182 if (i == 0) {
183 seq_puts(p, " ");
184 for_each_online_cpu(j)
185 seq_printf(p, " CPU%d", j);
186
187 #ifdef PARISC_IRQ_CR16_COUNTS
188 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
189 #endif
190 seq_putc(p, '\n');
191 }
192
193 if (i < NR_IRQS) {
194 struct irq_desc *desc = irq_to_desc(i);
195 struct irqaction *action;
196
197 raw_spin_lock_irqsave(&desc->lock, flags);
198 action = desc->action;
199 if (!action)
200 goto skip;
201 seq_printf(p, "%3d: ", i);
202
203 for_each_online_cpu(j)
204 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, j));
205
206 seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
207 #ifndef PARISC_IRQ_CR16_COUNTS
208 seq_printf(p, " %s", action->name);
209
210 while ((action = action->next))
211 seq_printf(p, ", %s", action->name);
212 #else
213 for ( ;action; action = action->next) {
214 unsigned int k, avg, min, max;
215
216 min = max = action->cr16_hist[0];
217
218 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
219 int hist = action->cr16_hist[k];
220
221 if (hist) {
222 avg += hist;
223 } else
224 break;
225
226 if (hist > max) max = hist;
227 if (hist < min) min = hist;
228 }
229
230 avg /= k;
231 seq_printf(p, " %s[%d/%d/%d]", action->name,
232 min,avg,max);
233 }
234 #endif
235
236 seq_putc(p, '\n');
237 skip:
238 raw_spin_unlock_irqrestore(&desc->lock, flags);
239 }
240
241 if (i == NR_IRQS)
242 arch_show_interrupts(p, 3);
243
244 return 0;
245 }
246
247
248
249 /*
250 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
251 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
252 **
253 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
254 ** Then use that to get the Transaction address and data.
255 */
256
cpu_claim_irq(unsigned int irq,struct irq_chip * type,void * data)257 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
258 {
259 if (irq_has_action(irq))
260 return -EBUSY;
261 if (irq_get_chip(irq) != &cpu_interrupt_type)
262 return -EBUSY;
263
264 /* for iosapic interrupts */
265 if (type) {
266 irq_set_chip_and_handler(irq, type, handle_percpu_irq);
267 irq_set_chip_data(irq, data);
268 __cpu_unmask_irq(irq);
269 }
270 return 0;
271 }
272
txn_claim_irq(int irq)273 int txn_claim_irq(int irq)
274 {
275 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
276 }
277
278 /*
279 * The bits_wide parameter accommodates the limitations of the HW/SW which
280 * use these bits:
281 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
282 * V-class (EPIC): 6 bits
283 * N/L/A-class (iosapic): 8 bits
284 * PCI 2.2 MSI: 16 bits
285 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
286 *
287 * On the service provider side:
288 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
289 * o PA 2.0 wide mode 6-bits (per processor)
290 * o IA64 8-bits (0-256 total)
291 *
292 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
293 * by the processor...and the N/L-class I/O subsystem supports more bits than
294 * PA2.0 has. The first case is the problem.
295 */
txn_alloc_irq(unsigned int bits_wide)296 int txn_alloc_irq(unsigned int bits_wide)
297 {
298 int irq;
299
300 /* never return irq 0 cause that's the interval timer */
301 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
302 if (cpu_claim_irq(irq, NULL, NULL) < 0)
303 continue;
304 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
305 continue;
306 return irq;
307 }
308
309 /* unlikely, but be prepared */
310 return -1;
311 }
312
313
txn_affinity_addr(unsigned int irq,int cpu)314 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
315 {
316 #ifdef CONFIG_SMP
317 struct irq_data *d = irq_get_irq_data(irq);
318 irq_data_update_affinity(d, cpumask_of(cpu));
319 #endif
320
321 return per_cpu(cpu_data, cpu).txn_addr;
322 }
323
324
txn_alloc_addr(unsigned int virt_irq)325 unsigned long txn_alloc_addr(unsigned int virt_irq)
326 {
327 static int next_cpu = -1;
328
329 next_cpu++; /* assign to "next" CPU we want this bugger on */
330
331 /* validate entry */
332 while ((next_cpu < nr_cpu_ids) &&
333 (!per_cpu(cpu_data, next_cpu).txn_addr ||
334 !cpu_online(next_cpu)))
335 next_cpu++;
336
337 if (next_cpu >= nr_cpu_ids)
338 next_cpu = 0; /* nothing else, assign monarch */
339
340 return txn_affinity_addr(virt_irq, next_cpu);
341 }
342
343
txn_alloc_data(unsigned int virt_irq)344 unsigned int txn_alloc_data(unsigned int virt_irq)
345 {
346 return virt_irq - CPU_IRQ_BASE;
347 }
348
eirr_to_irq(unsigned long eirr)349 static inline int eirr_to_irq(unsigned long eirr)
350 {
351 int bit = fls_long(eirr);
352 return (BITS_PER_LONG - bit) + TIMER_IRQ;
353 }
354
355 #ifdef CONFIG_IRQSTACKS
356 /*
357 * IRQ STACK - used for irq handler
358 */
359 #ifdef CONFIG_64BIT
360 #define IRQ_STACK_SIZE (4096 << 4) /* 64k irq stack size */
361 #else
362 #define IRQ_STACK_SIZE (4096 << 3) /* 32k irq stack size */
363 #endif
364
365 union irq_stack_union {
366 unsigned long stack[IRQ_STACK_SIZE/sizeof(unsigned long)];
367 volatile unsigned int slock[4];
368 volatile unsigned int lock[1];
369 };
370
371 DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = {
372 .slock = { 1,1,1,1 },
373 };
374 #endif
375
376
377 int sysctl_panic_on_stackoverflow = 1;
378
stack_overflow_check(struct pt_regs * regs)379 static inline void stack_overflow_check(struct pt_regs *regs)
380 {
381 #ifdef CONFIG_DEBUG_STACKOVERFLOW
382 #define STACK_MARGIN (256*6)
383
384 unsigned long stack_start = (unsigned long) task_stack_page(current);
385 unsigned long sp = regs->gr[30];
386 unsigned long stack_usage;
387 unsigned int *last_usage;
388 int cpu = smp_processor_id();
389
390 /* if sr7 != 0, we interrupted a userspace process which we do not want
391 * to check for stack overflow. We will only check the kernel stack. */
392 if (regs->sr[7])
393 return;
394
395 /* exit if already in panic */
396 if (sysctl_panic_on_stackoverflow < 0)
397 return;
398
399 /* calculate kernel stack usage */
400 stack_usage = sp - stack_start;
401 #ifdef CONFIG_IRQSTACKS
402 if (likely(stack_usage <= THREAD_SIZE))
403 goto check_kernel_stack; /* found kernel stack */
404
405 /* check irq stack usage */
406 stack_start = (unsigned long) &per_cpu(irq_stack_union, cpu).stack;
407 stack_usage = sp - stack_start;
408
409 last_usage = &per_cpu(irq_stat.irq_stack_usage, cpu);
410 if (unlikely(stack_usage > *last_usage))
411 *last_usage = stack_usage;
412
413 if (likely(stack_usage < (IRQ_STACK_SIZE - STACK_MARGIN)))
414 return;
415
416 pr_emerg("stackcheck: %s will most likely overflow irq stack "
417 "(sp:%lx, stk bottom-top:%lx-%lx)\n",
418 current->comm, sp, stack_start, stack_start + IRQ_STACK_SIZE);
419 goto panic_check;
420
421 check_kernel_stack:
422 #endif
423
424 /* check kernel stack usage */
425 last_usage = &per_cpu(irq_stat.kernel_stack_usage, cpu);
426
427 if (unlikely(stack_usage > *last_usage))
428 *last_usage = stack_usage;
429
430 if (likely(stack_usage < (THREAD_SIZE - STACK_MARGIN)))
431 return;
432
433 pr_emerg("stackcheck: %s will most likely overflow kernel stack "
434 "(sp:%lx, stk bottom-top:%lx-%lx)\n",
435 current->comm, sp, stack_start, stack_start + THREAD_SIZE);
436
437 #ifdef CONFIG_IRQSTACKS
438 panic_check:
439 #endif
440 if (sysctl_panic_on_stackoverflow) {
441 sysctl_panic_on_stackoverflow = -1; /* disable further checks */
442 panic("low stack detected by irq handler - check messages\n");
443 }
444 #endif
445 }
446
447 #ifdef CONFIG_IRQSTACKS
448 /* in entry.S: */
449 void call_on_stack(unsigned long p1, void *func, unsigned long new_stack);
450
execute_on_irq_stack(void * func,unsigned long param1)451 static void execute_on_irq_stack(void *func, unsigned long param1)
452 {
453 union irq_stack_union *union_ptr;
454 unsigned long irq_stack;
455 volatile unsigned int *irq_stack_in_use;
456
457 union_ptr = &per_cpu(irq_stack_union, smp_processor_id());
458 irq_stack = (unsigned long) &union_ptr->stack;
459 irq_stack = ALIGN(irq_stack + sizeof(irq_stack_union.slock),
460 FRAME_ALIGN); /* align for stack frame usage */
461
462 /* We may be called recursive. If we are already using the irq stack,
463 * just continue to use it. Use spinlocks to serialize
464 * the irq stack usage.
465 */
466 irq_stack_in_use = (volatile unsigned int *)__ldcw_align(union_ptr);
467 if (!__ldcw(irq_stack_in_use)) {
468 void (*direct_call)(unsigned long p1) = func;
469
470 /* We are using the IRQ stack already.
471 * Do direct call on current stack. */
472 direct_call(param1);
473 return;
474 }
475
476 /* This is where we switch to the IRQ stack. */
477 call_on_stack(param1, func, irq_stack);
478
479 /* free up irq stack usage. */
480 *irq_stack_in_use = 1;
481 }
482
483 #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
do_softirq_own_stack(void)484 void do_softirq_own_stack(void)
485 {
486 execute_on_irq_stack(__do_softirq, 0);
487 }
488 #endif
489 #endif /* CONFIG_IRQSTACKS */
490
491 /* ONLY called from entry.S:intr_extint() */
do_cpu_irq_mask(struct pt_regs * regs)492 void do_cpu_irq_mask(struct pt_regs *regs)
493 {
494 struct pt_regs *old_regs;
495 unsigned long eirr_val;
496 int irq, cpu = smp_processor_id();
497 struct irq_data *irq_data;
498 #ifdef CONFIG_SMP
499 cpumask_t dest;
500 #endif
501
502 old_regs = set_irq_regs(regs);
503 local_irq_disable();
504 irq_enter();
505
506 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
507 if (!eirr_val)
508 goto set_out;
509 irq = eirr_to_irq(eirr_val);
510
511 irq_data = irq_get_irq_data(irq);
512
513 /* Filter out spurious interrupts, mostly from serial port at bootup */
514 if (unlikely(!irq_desc_has_action(irq_data_to_desc(irq_data))))
515 goto set_out;
516
517 #ifdef CONFIG_SMP
518 cpumask_copy(&dest, irq_data_get_affinity_mask(irq_data));
519 if (irqd_is_per_cpu(irq_data) &&
520 !cpumask_test_cpu(smp_processor_id(), &dest)) {
521 int cpu = cpumask_first(&dest);
522
523 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
524 irq, smp_processor_id(), cpu);
525 gsc_writel(irq + CPU_IRQ_BASE,
526 per_cpu(cpu_data, cpu).hpa);
527 goto set_out;
528 }
529 #endif
530 stack_overflow_check(regs);
531
532 #ifdef CONFIG_IRQSTACKS
533 execute_on_irq_stack(&generic_handle_irq, irq);
534 #else
535 generic_handle_irq(irq);
536 #endif /* CONFIG_IRQSTACKS */
537
538 out:
539 irq_exit();
540 set_irq_regs(old_regs);
541 return;
542
543 set_out:
544 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
545 goto out;
546 }
547
claim_cpu_irqs(void)548 static void claim_cpu_irqs(void)
549 {
550 unsigned long flags = IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL;
551 int i;
552
553 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
554 irq_set_chip_and_handler(i, &cpu_interrupt_type,
555 handle_percpu_irq);
556 }
557
558 irq_set_handler(TIMER_IRQ, handle_percpu_irq);
559 if (request_irq(TIMER_IRQ, timer_interrupt, flags, "timer", NULL))
560 pr_err("Failed to register timer interrupt\n");
561 #ifdef CONFIG_SMP
562 irq_set_handler(IPI_IRQ, handle_percpu_irq);
563 if (request_irq(IPI_IRQ, ipi_interrupt, IRQF_PERCPU, "IPI", NULL))
564 pr_err("Failed to register IPI interrupt\n");
565 #endif
566 }
567
init_IRQ(void)568 void init_IRQ(void)
569 {
570 local_irq_disable(); /* PARANOID - should already be disabled */
571 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
572 #ifdef CONFIG_SMP
573 if (!cpu_eiem) {
574 claim_cpu_irqs();
575 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
576 }
577 #else
578 claim_cpu_irqs();
579 cpu_eiem = EIEM_MASK(TIMER_IRQ);
580 #endif
581 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
582 }
583