1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2001-2002 by David Brownell
4  */
5 
6 #ifndef __LINUX_EHCI_HCD_H
7 #define __LINUX_EHCI_HCD_H
8 
9 /* definitions used for the EHCI driver */
10 
11 /*
12  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
13  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
14  * the host controller implementation.
15  *
16  * To facilitate the strongest possible byte-order checking from "sparse"
17  * and so on, we use __leXX unless that's not practical.
18  */
19 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
20 typedef __u32 __bitwise __hc32;
21 typedef __u16 __bitwise __hc16;
22 #else
23 #define __hc32	__le32
24 #define __hc16	__le16
25 #endif
26 
27 /* statistics can be kept for tuning/monitoring */
28 #ifdef CONFIG_DYNAMIC_DEBUG
29 #define EHCI_STATS
30 #endif
31 
32 struct ehci_stats {
33 	/* irq usage */
34 	unsigned long		normal;
35 	unsigned long		error;
36 	unsigned long		iaa;
37 	unsigned long		lost_iaa;
38 
39 	/* termination of urbs from core */
40 	unsigned long		complete;
41 	unsigned long		unlink;
42 };
43 
44 /*
45  * Scheduling and budgeting information for periodic transfers, for both
46  * high-speed devices and full/low-speed devices lying behind a TT.
47  */
48 struct ehci_per_sched {
49 	struct usb_device	*udev;		/* access to the TT */
50 	struct usb_host_endpoint *ep;
51 	struct list_head	ps_list;	/* node on ehci_tt's ps_list */
52 	u16			tt_usecs;	/* time on the FS/LS bus */
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
54 	u16			period;		/* actual period in frames */
55 	u16			phase;		/* actual phase, frame part */
56 	u8			bw_phase;	/* same, for bandwidth
57 						   reservation */
58 	u8			phase_uf;	/* uframe part of the phase */
59 	u8			usecs, c_usecs;	/* times on the HS bus */
60 	u8			bw_uperiod;	/* period in microframes, for
61 						   bandwidth reservation */
62 	u8			bw_period;	/* same, in frames */
63 };
64 #define NO_FRAME	29999			/* frame not assigned yet */
65 
66 /* ehci_hcd->lock guards shared data against other CPUs:
67  *   ehci_hcd:	async, unlink, periodic (and shadow), ...
68  *   usb_host_endpoint: hcpriv
69  *   ehci_qh:	qh_next, qtd_list
70  *   ehci_qtd:	qtd_list
71  *
72  * Also, hold this lock when talking to HC registers or
73  * when updating hw_* fields in shared qh/qtd/... structures.
74  */
75 
76 #define	EHCI_MAX_ROOT_PORTS	15		/* see HCS_N_PORTS */
77 
78 /*
79  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
80  * controller may be doing DMA.  Lower values mean there's no DMA.
81  */
82 enum ehci_rh_state {
83 	EHCI_RH_HALTED,
84 	EHCI_RH_SUSPENDED,
85 	EHCI_RH_RUNNING,
86 	EHCI_RH_STOPPING
87 };
88 
89 /*
90  * Timer events, ordered by increasing delay length.
91  * Always update event_delays_ns[] and event_handlers[] (defined in
92  * ehci-timer.c) in parallel with this list.
93  */
94 enum ehci_hrtimer_event {
95 	EHCI_HRTIMER_POLL_ASS,		/* Poll for async schedule off */
96 	EHCI_HRTIMER_POLL_PSS,		/* Poll for periodic schedule off */
97 	EHCI_HRTIMER_POLL_DEAD,		/* Wait for dead controller to stop */
98 	EHCI_HRTIMER_UNLINK_INTR,	/* Wait for interrupt QH unlink */
99 	EHCI_HRTIMER_FREE_ITDS,		/* Wait for unused iTDs and siTDs */
100 	EHCI_HRTIMER_ACTIVE_UNLINK,	/* Wait while unlinking an active QH */
101 	EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
102 	EHCI_HRTIMER_ASYNC_UNLINKS,	/* Unlink empty async QHs */
103 	EHCI_HRTIMER_IAA_WATCHDOG,	/* Handle lost IAA interrupts */
104 	EHCI_HRTIMER_DISABLE_PERIODIC,	/* Wait to disable periodic sched */
105 	EHCI_HRTIMER_DISABLE_ASYNC,	/* Wait to disable async sched */
106 	EHCI_HRTIMER_IO_WATCHDOG,	/* Check for missing IRQs */
107 	EHCI_HRTIMER_NUM_EVENTS		/* Must come last */
108 };
109 #define EHCI_HRTIMER_NO_EVENT	99
110 
111 struct ehci_hcd {			/* one per controller */
112 	/* timing support */
113 	enum ehci_hrtimer_event	next_hrtimer_event;
114 	unsigned		enabled_hrtimer_events;
115 	ktime_t			hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
116 	struct hrtimer		hrtimer;
117 
118 	int			PSS_poll_count;
119 	int			ASS_poll_count;
120 	int			died_poll_count;
121 
122 	/* glue to PCI and HCD framework */
123 	struct ehci_caps __iomem *caps;
124 	struct ehci_regs __iomem *regs;
125 	struct ehci_dbg_port __iomem *debug;
126 
127 	__u32			hcs_params;	/* cached register copy */
128 	spinlock_t		lock;
129 	enum ehci_rh_state	rh_state;
130 
131 	/* general schedule support */
132 	bool			scanning:1;
133 	bool			need_rescan:1;
134 	bool			intr_unlinking:1;
135 	bool			iaa_in_progress:1;
136 	bool			async_unlinking:1;
137 	bool			shutdown:1;
138 	struct ehci_qh		*qh_scan_next;
139 
140 	/* async schedule support */
141 	struct ehci_qh		*async;
142 	struct ehci_qh		*dummy;		/* For AMD quirk use */
143 	struct list_head	async_unlink;
144 	struct list_head	async_idle;
145 	unsigned		async_unlink_cycle;
146 	unsigned		async_count;	/* async activity count */
147 	__hc32			old_current;	/* Test for QH becoming */
148 	__hc32			old_token;	/*  inactive during unlink */
149 
150 	/* periodic schedule support */
151 #define	DEFAULT_I_TDPS		1024		/* some HCs can do less */
152 	unsigned		periodic_size;
153 	__hc32			*periodic;	/* hw periodic table */
154 	dma_addr_t		periodic_dma;
155 	struct list_head	intr_qh_list;
156 	unsigned		i_thresh;	/* uframes HC might cache */
157 
158 	union ehci_shadow	*pshadow;	/* mirror hw periodic table */
159 	struct list_head	intr_unlink_wait;
160 	struct list_head	intr_unlink;
161 	unsigned		intr_unlink_wait_cycle;
162 	unsigned		intr_unlink_cycle;
163 	unsigned		now_frame;	/* frame from HC hardware */
164 	unsigned		last_iso_frame;	/* last frame scanned for iso */
165 	unsigned		intr_count;	/* intr activity count */
166 	unsigned		isoc_count;	/* isoc activity count */
167 	unsigned		periodic_count;	/* periodic activity count */
168 	unsigned		uframe_periodic_max; /* max periodic time per uframe */
169 
170 
171 	/* list of itds & sitds completed while now_frame was still active */
172 	struct list_head	cached_itd_list;
173 	struct ehci_itd		*last_itd_to_free;
174 	struct list_head	cached_sitd_list;
175 	struct ehci_sitd	*last_sitd_to_free;
176 
177 	/* per root hub port */
178 	unsigned long		reset_done[EHCI_MAX_ROOT_PORTS];
179 
180 	/* bit vectors (one bit per port) */
181 	unsigned long		bus_suspended;		/* which ports were
182 			already suspended at the start of a bus suspend */
183 	unsigned long		companion_ports;	/* which ports are
184 			dedicated to the companion controller */
185 	unsigned long		owned_ports;		/* which ports are
186 			owned by the companion during a bus suspend */
187 	unsigned long		port_c_suspend;		/* which ports have
188 			the change-suspend feature turned on */
189 	unsigned long		suspended_ports;	/* which ports are
190 			suspended */
191 	unsigned long		resuming_ports;		/* which ports have
192 			started to resume */
193 
194 	/* per-HC memory pools (could be per-bus, but ...) */
195 	struct dma_pool		*qh_pool;	/* qh per active urb */
196 	struct dma_pool		*qtd_pool;	/* one or more per qh */
197 	struct dma_pool		*itd_pool;	/* itd per iso urb */
198 	struct dma_pool		*sitd_pool;	/* sitd per split iso urb */
199 
200 	unsigned		random_frame;
201 	unsigned long		next_statechange;
202 	ktime_t			last_periodic_enable;
203 	u32			command;
204 
205 	/* SILICON QUIRKS */
206 	unsigned		no_selective_suspend:1;
207 	unsigned		has_fsl_port_bug:1; /* FreeScale */
208 	unsigned		has_fsl_hs_errata:1;	/* Freescale HS quirk */
209 	unsigned		has_fsl_susp_errata:1;	/* NXP SUSP quirk */
210 	unsigned		big_endian_mmio:1;
211 	unsigned		big_endian_desc:1;
212 	unsigned		big_endian_capbase:1;
213 	unsigned		has_amcc_usb23:1;
214 	unsigned		need_io_watchdog:1;
215 	unsigned		amd_pll_fix:1;
216 	unsigned		use_dummy_qh:1;	/* AMD Frame List table quirk*/
217 	unsigned		has_synopsys_hc_bug:1; /* Synopsys HC */
218 	unsigned		frame_index_bug:1; /* MosChip (AKA NetMos) */
219 	unsigned		need_oc_pp_cycle:1; /* MPC834X port power */
220 	unsigned		imx28_write_fix:1; /* For Freescale i.MX28 */
221 	unsigned		spurious_oc:1;
222 	unsigned		is_aspeed:1;
223 	unsigned		zx_wakeup_clear_needed:1;
224 
225 	/* required for usb32 quirk */
226 	#define OHCI_CTRL_HCFS          (3 << 6)
227 	#define OHCI_USB_OPER           (2 << 6)
228 	#define OHCI_USB_SUSPEND        (3 << 6)
229 
230 	#define OHCI_HCCTRL_OFFSET      0x4
231 	#define OHCI_HCCTRL_LEN         0x4
232 	__hc32			*ohci_hcctrl_reg;
233 	unsigned		has_hostpc:1;
234 	unsigned		has_tdi_phy_lpm:1;
235 	unsigned		has_ppcd:1; /* support per-port change bits */
236 	u8			sbrn;		/* packed release number */
237 
238 	/* irq statistics */
239 #ifdef EHCI_STATS
240 	struct ehci_stats	stats;
241 #	define INCR(x) ((x)++)
242 #else
243 #	define INCR(x) do {} while (0)
244 #endif
245 
246 	/* debug files */
247 #ifdef CONFIG_DYNAMIC_DEBUG
248 	struct dentry		*debug_dir;
249 #endif
250 
251 	/* bandwidth usage */
252 #define EHCI_BANDWIDTH_SIZE	64
253 #define EHCI_BANDWIDTH_FRAMES	(EHCI_BANDWIDTH_SIZE >> 3)
254 	u8			bandwidth[EHCI_BANDWIDTH_SIZE];
255 						/* us allocated per uframe */
256 	u8			tt_budget[EHCI_BANDWIDTH_SIZE];
257 						/* us budgeted per uframe */
258 	struct list_head	tt_list;
259 
260 	/* platform-specific data -- must come last */
261 	unsigned long		priv[] __aligned(sizeof(s64));
262 };
263 
264 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_ehci(struct usb_hcd * hcd)265 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
266 {
267 	return (struct ehci_hcd *) (hcd->hcd_priv);
268 }
ehci_to_hcd(struct ehci_hcd * ehci)269 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
270 {
271 	return container_of((void *) ehci, struct usb_hcd, hcd_priv);
272 }
273 
274 /*-------------------------------------------------------------------------*/
275 
276 #include <linux/usb/ehci_def.h>
277 
278 /*-------------------------------------------------------------------------*/
279 
280 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)
281 
282 /*
283  * EHCI Specification 0.95 Section 3.5
284  * QTD: describe data transfer components (buffer, direction, ...)
285  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
286  *
287  * These are associated only with "QH" (Queue Head) structures,
288  * used with control, bulk, and interrupt transfers.
289  */
290 struct ehci_qtd {
291 	/* first part defined by EHCI spec */
292 	__hc32			hw_next;	/* see EHCI 3.5.1 */
293 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
294 	__hc32			hw_token;       /* see EHCI 3.5.3 */
295 #define	QTD_TOGGLE	(1 << 31)	/* data toggle */
296 #define	QTD_LENGTH(tok)	(((tok)>>16) & 0x7fff)
297 #define	QTD_IOC		(1 << 15)	/* interrupt on complete */
298 #define	QTD_CERR(tok)	(((tok)>>10) & 0x3)
299 #define	QTD_PID(tok)	(((tok)>>8) & 0x3)
300 #define	QTD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
301 #define	QTD_STS_HALT	(1 << 6)	/* halted on error */
302 #define	QTD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
303 #define	QTD_STS_BABBLE	(1 << 4)	/* device was babbling (qtd halted) */
304 #define	QTD_STS_XACT	(1 << 3)	/* device gave illegal response */
305 #define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
306 #define	QTD_STS_STS	(1 << 1)	/* split transaction state */
307 #define	QTD_STS_PING	(1 << 0)	/* issue PING? */
308 
309 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)
310 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)
311 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)
312 
313 	__hc32			hw_buf[5];        /* see EHCI 3.5.4 */
314 	__hc32			hw_buf_hi[5];        /* Appendix B */
315 
316 	/* the rest is HCD-private */
317 	dma_addr_t		qtd_dma;		/* qtd address */
318 	struct list_head	qtd_list;		/* sw qtd list */
319 	struct urb		*urb;			/* qtd's urb */
320 	size_t			length;			/* length of buffer */
321 } __aligned(32);
322 
323 /* mask NakCnt+T in qh->hw_alt_next */
324 #define QTD_MASK(ehci)	cpu_to_hc32(ehci, ~0x1f)
325 
326 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
327 
328 /*-------------------------------------------------------------------------*/
329 
330 /* type tag from {qh,itd,sitd,fstn}->hw_next */
331 #define Q_NEXT_TYPE(ehci, dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))
332 
333 /*
334  * Now the following defines are not converted using the
335  * cpu_to_le32() macro anymore, since we have to support
336  * "dynamic" switching between be and le support, so that the driver
337  * can be used on one system with SoC EHCI controller using big-endian
338  * descriptors as well as a normal little-endian PCI EHCI controller.
339  */
340 /* values for that type tag */
341 #define Q_TYPE_ITD	(0 << 1)
342 #define Q_TYPE_QH	(1 << 1)
343 #define Q_TYPE_SITD	(2 << 1)
344 #define Q_TYPE_FSTN	(3 << 1)
345 
346 /* next async queue entry, or pointer to interrupt/periodic QH */
347 #define QH_NEXT(ehci, dma) \
348 		(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
349 
350 /* for periodic/async schedules and qtd lists, mark end of list */
351 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
352 
353 /*
354  * Entries in periodic shadow table are pointers to one of four kinds
355  * of data structure.  That's dictated by the hardware; a type tag is
356  * encoded in the low bits of the hardware's periodic schedule.  Use
357  * Q_NEXT_TYPE to get the tag.
358  *
359  * For entries in the async schedule, the type tag always says "qh".
360  */
361 union ehci_shadow {
362 	struct ehci_qh		*qh;		/* Q_TYPE_QH */
363 	struct ehci_itd		*itd;		/* Q_TYPE_ITD */
364 	struct ehci_sitd	*sitd;		/* Q_TYPE_SITD */
365 	struct ehci_fstn	*fstn;		/* Q_TYPE_FSTN */
366 	__hc32			*hw_next;	/* (all types) */
367 	void			*ptr;
368 };
369 
370 /*-------------------------------------------------------------------------*/
371 
372 /*
373  * EHCI Specification 0.95 Section 3.6
374  * QH: describes control/bulk/interrupt endpoints
375  * See Fig 3-7 "Queue Head Structure Layout".
376  *
377  * These appear in both the async and (for interrupt) periodic schedules.
378  */
379 
380 /* first part defined by EHCI spec */
381 struct ehci_qh_hw {
382 	__hc32			hw_next;	/* see EHCI 3.6.1 */
383 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
384 #define	QH_CONTROL_EP	(1 << 27)	/* FS/LS control endpoint */
385 #define	QH_HEAD		(1 << 15)	/* Head of async reclamation list */
386 #define	QH_TOGGLE_CTL	(1 << 14)	/* Data toggle control */
387 #define	QH_HIGH_SPEED	(2 << 12)	/* Endpoint speed */
388 #define	QH_LOW_SPEED	(1 << 12)
389 #define	QH_FULL_SPEED	(0 << 12)
390 #define	QH_INACTIVATE	(1 << 7)	/* Inactivate on next transaction */
391 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
392 #define	QH_SMASK	0x000000ff
393 #define	QH_CMASK	0x0000ff00
394 #define	QH_HUBADDR	0x007f0000
395 #define	QH_HUBPORT	0x3f800000
396 #define	QH_MULT		0xc0000000
397 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
398 
399 	/* qtd overlay (hardware parts of a struct ehci_qtd) */
400 	__hc32			hw_qtd_next;
401 	__hc32			hw_alt_next;
402 	__hc32			hw_token;
403 	__hc32			hw_buf[5];
404 	__hc32			hw_buf_hi[5];
405 } __aligned(32);
406 
407 struct ehci_qh {
408 	struct ehci_qh_hw	*hw;		/* Must come first */
409 	/* the rest is HCD-private */
410 	dma_addr_t		qh_dma;		/* address of qh */
411 	union ehci_shadow	qh_next;	/* ptr to qh; or periodic */
412 	struct list_head	qtd_list;	/* sw qtd list */
413 	struct list_head	intr_node;	/* list of intr QHs */
414 	struct ehci_qtd		*dummy;
415 	struct list_head	unlink_node;
416 	struct ehci_per_sched	ps;		/* scheduling info */
417 
418 	unsigned		unlink_cycle;
419 
420 	u8			qh_state;
421 #define	QH_STATE_LINKED		1		/* HC sees this */
422 #define	QH_STATE_UNLINK		2		/* HC may still see this */
423 #define	QH_STATE_IDLE		3		/* HC doesn't see this */
424 #define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on unlink q */
425 #define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */
426 
427 	u8			xacterrs;	/* XactErr retry counter */
428 #define	QH_XACTERR_MAX		32		/* XactErr retry limit */
429 
430 	u8			unlink_reason;
431 #define QH_UNLINK_HALTED	0x01		/* Halt flag is set */
432 #define QH_UNLINK_SHORT_READ	0x02		/* Recover from a short read */
433 #define QH_UNLINK_DUMMY_OVERLAY	0x04		/* QH overlayed the dummy TD */
434 #define QH_UNLINK_SHUTDOWN	0x08		/* The HC isn't running */
435 #define QH_UNLINK_QUEUE_EMPTY	0x10		/* Reached end of the queue */
436 #define QH_UNLINK_REQUESTED	0x20		/* Disable, reset, or dequeue */
437 
438 	u8			gap_uf;		/* uframes split/csplit gap */
439 
440 	unsigned		is_out:1;	/* bulk or intr OUT */
441 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
442 	unsigned		dequeue_during_giveback:1;
443 	unsigned		should_be_inactive:1;
444 };
445 
446 /*-------------------------------------------------------------------------*/
447 
448 /* description of one iso transaction (up to 3 KB data if highspeed) */
449 struct ehci_iso_packet {
450 	/* These will be copied to iTD when scheduling */
451 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
452 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
453 	u8			cross;		/* buf crosses pages */
454 	/* for full speed OUT splits */
455 	u32			buf1;
456 };
457 
458 /* temporary schedule data for packets from iso urbs (both speeds)
459  * each packet is one logical usb transaction to the device (not TT),
460  * beginning at stream->next_uframe
461  */
462 struct ehci_iso_sched {
463 	struct list_head	td_list;
464 	unsigned		span;
465 	unsigned		first_packet;
466 	struct ehci_iso_packet	packet[];
467 };
468 
469 /*
470  * ehci_iso_stream - groups all (s)itds for this endpoint.
471  * acts like a qh would, if EHCI had them for ISO.
472  */
473 struct ehci_iso_stream {
474 	/* first field matches ehci_hq, but is NULL */
475 	struct ehci_qh_hw	*hw;
476 
477 	u8			bEndpointAddress;
478 	u8			highspeed;
479 	struct list_head	td_list;	/* queued itds/sitds */
480 	struct list_head	free_list;	/* list of unused itds/sitds */
481 
482 	/* output of (re)scheduling */
483 	struct ehci_per_sched	ps;		/* scheduling info */
484 	unsigned		next_uframe;
485 	__hc32			splits;
486 
487 	/* the rest is derived from the endpoint descriptor,
488 	 * including the extra info for hw_bufp[0..2]
489 	 */
490 	u16			uperiod;	/* period in uframes */
491 	u16			maxp;
492 	unsigned		bandwidth;
493 
494 	/* This is used to initialize iTD's hw_bufp fields */
495 	__hc32			buf0;
496 	__hc32			buf1;
497 	__hc32			buf2;
498 
499 	/* this is used to initialize sITD's tt info */
500 	__hc32			address;
501 };
502 
503 /*-------------------------------------------------------------------------*/
504 
505 /*
506  * EHCI Specification 0.95 Section 3.3
507  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
508  *
509  * Schedule records for high speed iso xfers
510  */
511 struct ehci_itd {
512 	/* first part defined by EHCI spec */
513 	__hc32			hw_next;           /* see EHCI 3.3.1 */
514 	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
515 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
516 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
517 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
518 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
519 #define	EHCI_ITD_LENGTH(tok)	(((tok)>>16) & 0x0fff)
520 #define	EHCI_ITD_IOC		(1 << 15)	/* interrupt on complete */
521 
522 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
523 
524 	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
525 	__hc32			hw_bufp_hi[7];	/* Appendix B */
526 
527 	/* the rest is HCD-private */
528 	dma_addr_t		itd_dma;	/* for this itd */
529 	union ehci_shadow	itd_next;	/* ptr to periodic q entry */
530 
531 	struct urb		*urb;
532 	struct ehci_iso_stream	*stream;	/* endpoint's queue */
533 	struct list_head	itd_list;	/* list of stream's itds */
534 
535 	/* any/all hw_transactions here may be used by that urb */
536 	unsigned		frame;		/* where scheduled */
537 	unsigned		pg;
538 	unsigned		index[8];	/* in urb->iso_frame_desc */
539 } __aligned(32);
540 
541 /*-------------------------------------------------------------------------*/
542 
543 /*
544  * EHCI Specification 0.95 Section 3.4
545  * siTD, aka split-transaction isochronous Transfer Descriptor
546  *       ... describe full speed iso xfers through TT in hubs
547  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
548  */
549 struct ehci_sitd {
550 	/* first part defined by EHCI spec */
551 	__hc32			hw_next;
552 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
553 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
554 	__hc32			hw_uframe;		/* EHCI table 3-10 */
555 	__hc32			hw_results;		/* EHCI table 3-11 */
556 #define	SITD_IOC	(1 << 31)	/* interrupt on completion */
557 #define	SITD_PAGE	(1 << 30)	/* buffer 0/1 */
558 #define	SITD_LENGTH(x)	(((x) >> 16) & 0x3ff)
559 #define	SITD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
560 #define	SITD_STS_ERR	(1 << 6)	/* error from TT */
561 #define	SITD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
562 #define	SITD_STS_BABBLE	(1 << 4)	/* device was babbling */
563 #define	SITD_STS_XACT	(1 << 3)	/* illegal IN response */
564 #define	SITD_STS_MMF	(1 << 2)	/* incomplete split transaction */
565 #define	SITD_STS_STS	(1 << 1)	/* split transaction state */
566 
567 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)
568 
569 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
570 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
571 	__hc32			hw_buf_hi[2];		/* Appendix B */
572 
573 	/* the rest is HCD-private */
574 	dma_addr_t		sitd_dma;
575 	union ehci_shadow	sitd_next;	/* ptr to periodic q entry */
576 
577 	struct urb		*urb;
578 	struct ehci_iso_stream	*stream;	/* endpoint's queue */
579 	struct list_head	sitd_list;	/* list of stream's sitds */
580 	unsigned		frame;
581 	unsigned		index;
582 } __aligned(32);
583 
584 /*-------------------------------------------------------------------------*/
585 
586 /*
587  * EHCI Specification 0.96 Section 3.7
588  * Periodic Frame Span Traversal Node (FSTN)
589  *
590  * Manages split interrupt transactions (using TT) that span frame boundaries
591  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
592  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
593  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
594  */
595 struct ehci_fstn {
596 	__hc32			hw_next;	/* any periodic q entry */
597 	__hc32			hw_prev;	/* qh or EHCI_LIST_END */
598 
599 	/* the rest is HCD-private */
600 	dma_addr_t		fstn_dma;
601 	union ehci_shadow	fstn_next;	/* ptr to periodic q entry */
602 } __aligned(32);
603 
604 /*-------------------------------------------------------------------------*/
605 
606 /*
607  * USB-2.0 Specification Sections 11.14 and 11.18
608  * Scheduling and budgeting split transactions using TTs
609  *
610  * A hub can have a single TT for all its ports, or multiple TTs (one for each
611  * port).  The bandwidth and budgeting information for the full/low-speed bus
612  * below each TT is self-contained and independent of the other TTs or the
613  * high-speed bus.
614  *
615  * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
616  * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
617  * the best-case estimate of the number of full-speed bytes allocated to an
618  * endpoint for each microframe within an allocated frame.
619  *
620  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
621  * keep an up-to-date record, we recompute the budget when it is needed.
622  */
623 
624 struct ehci_tt {
625 	u16			bandwidth[EHCI_BANDWIDTH_FRAMES];
626 
627 	struct list_head	tt_list;	/* List of all ehci_tt's */
628 	struct list_head	ps_list;	/* Items using this TT */
629 	struct usb_tt		*usb_tt;
630 	int			tt_port;	/* TT port number */
631 };
632 
633 /*-------------------------------------------------------------------------*/
634 
635 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
636 
637 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)	\
638 		ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
639 
640 #define ehci_prepare_ports_for_controller_resume(ehci)			\
641 		ehci_adjust_port_wakeup_flags(ehci, false, false)
642 
643 /*-------------------------------------------------------------------------*/
644 
645 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
646 
647 /*
648  * Some EHCI controllers have a Transaction Translator built into the
649  * root hub. This is a non-standard feature.  Each controller will need
650  * to add code to the following inline functions, and call them as
651  * needed (mostly in root hub code).
652  */
653 
654 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
655 
656 /* Returns the speed of a device attached to a port on the root hub. */
657 static inline unsigned int
ehci_port_speed(struct ehci_hcd * ehci,unsigned int portsc)658 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
659 {
660 	if (ehci_is_TDI(ehci)) {
661 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
662 		case 0:
663 			return 0;
664 		case 1:
665 			return USB_PORT_STAT_LOW_SPEED;
666 		case 2:
667 		default:
668 			return USB_PORT_STAT_HIGH_SPEED;
669 		}
670 	}
671 	return USB_PORT_STAT_HIGH_SPEED;
672 }
673 
674 #else
675 
676 #define	ehci_is_TDI(e)			(0)
677 
678 #define	ehci_port_speed(ehci, portsc)	USB_PORT_STAT_HIGH_SPEED
679 #endif
680 
681 /*-------------------------------------------------------------------------*/
682 
683 #ifdef CONFIG_PPC_83xx
684 /* Some Freescale processors have an erratum in which the TT
685  * port number in the queue head was 0..N-1 instead of 1..N.
686  */
687 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
688 #else
689 #define	ehci_has_fsl_portno_bug(e)		(0)
690 #endif
691 
692 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
693 
694 #if defined(CONFIG_PPC_85xx)
695 /* Some Freescale processors have an erratum (USB A-005275) in which
696  * incoming packets get corrupted in HS mode
697  */
698 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
699 #else
700 #define ehci_has_fsl_hs_errata(e)	(0)
701 #endif
702 
703 /*
704  * Some Freescale/NXP processors have an erratum (USB A-005697)
705  * in which we need to wait for 10ms for bus to enter suspend mode
706  * after setting SUSP bit.
707  */
708 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
709 
710 /*
711  * While most USB host controllers implement their registers in
712  * little-endian format, a minority (celleb companion chip) implement
713  * them in big endian format.
714  *
715  * This attempts to support either format at compile time without a
716  * runtime penalty, or both formats with the additional overhead
717  * of checking a flag bit.
718  *
719  * ehci_big_endian_capbase is a special quirk for controllers that
720  * implement the HC capability registers as separate registers and not
721  * as fields of a 32-bit register.
722  */
723 
724 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
725 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
726 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
727 #else
728 #define ehci_big_endian_mmio(e)		0
729 #define ehci_big_endian_capbase(e)	0
730 #endif
731 
732 /*
733  * Big-endian read/write functions are arch-specific.
734  * Other arches can be added if/when they're needed.
735  */
736 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
737 #define readl_be(addr)		__raw_readl((__force unsigned *)addr)
738 #define writel_be(val, addr)	__raw_writel(val, (__force unsigned *)addr)
739 #endif
740 
ehci_readl(const struct ehci_hcd * ehci,__u32 __iomem * regs)741 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
742 		__u32 __iomem *regs)
743 {
744 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
745 	return ehci_big_endian_mmio(ehci) ?
746 		readl_be(regs) :
747 		readl(regs);
748 #else
749 	return readl(regs);
750 #endif
751 }
752 
753 #ifdef CONFIG_SOC_IMX28
imx28_ehci_writel(const unsigned int val,volatile __u32 __iomem * addr)754 static inline void imx28_ehci_writel(const unsigned int val,
755 		volatile __u32 __iomem *addr)
756 {
757 	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
758 }
759 #else
imx28_ehci_writel(const unsigned int val,volatile __u32 __iomem * addr)760 static inline void imx28_ehci_writel(const unsigned int val,
761 		volatile __u32 __iomem *addr)
762 {
763 }
764 #endif
ehci_writel(const struct ehci_hcd * ehci,const unsigned int val,__u32 __iomem * regs)765 static inline void ehci_writel(const struct ehci_hcd *ehci,
766 		const unsigned int val, __u32 __iomem *regs)
767 {
768 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
769 	ehci_big_endian_mmio(ehci) ?
770 		writel_be(val, regs) :
771 		writel(val, regs);
772 #else
773 	if (ehci->imx28_write_fix)
774 		imx28_ehci_writel(val, regs);
775 	else
776 		writel(val, regs);
777 #endif
778 }
779 
780 /*
781  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
782  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
783  * Other common bits are dependent on has_amcc_usb23 quirk flag.
784  */
785 #ifdef CONFIG_44x
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)786 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
787 {
788 	u32 hc_control;
789 
790 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
791 	if (operational)
792 		hc_control |= OHCI_USB_OPER;
793 	else
794 		hc_control |= OHCI_USB_SUSPEND;
795 
796 	writel_be(hc_control, ehci->ohci_hcctrl_reg);
797 	(void) readl_be(ehci->ohci_hcctrl_reg);
798 }
799 #else
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)800 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
801 { }
802 #endif
803 
804 /*-------------------------------------------------------------------------*/
805 
806 /*
807  * The AMCC 440EPx not only implements its EHCI registers in big-endian
808  * format, but also its DMA data structures (descriptors).
809  *
810  * EHCI controllers accessed through PCI work normally (little-endian
811  * everywhere), so we won't bother supporting a BE-only mode for now.
812  */
813 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
814 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
815 
816 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)817 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
818 {
819 	return ehci_big_endian_desc(ehci)
820 		? (__force __hc32)cpu_to_be32(x)
821 		: (__force __hc32)cpu_to_le32(x);
822 }
823 
824 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)825 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
826 {
827 	return ehci_big_endian_desc(ehci)
828 		? be32_to_cpu((__force __be32)x)
829 		: le32_to_cpu((__force __le32)x);
830 }
831 
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)832 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
833 {
834 	return ehci_big_endian_desc(ehci)
835 		? be32_to_cpup((__force __be32 *)x)
836 		: le32_to_cpup((__force __le32 *)x);
837 }
838 
839 #else
840 
841 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)842 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
843 {
844 	return cpu_to_le32(x);
845 }
846 
847 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)848 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
849 {
850 	return le32_to_cpu(x);
851 }
852 
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)853 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
854 {
855 	return le32_to_cpup(x);
856 }
857 
858 #endif
859 
860 /*-------------------------------------------------------------------------*/
861 
862 #define ehci_dbg(ehci, fmt, args...) \
863 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
864 #define ehci_err(ehci, fmt, args...) \
865 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
866 #define ehci_info(ehci, fmt, args...) \
867 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868 #define ehci_warn(ehci, fmt, args...) \
869 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
870 
871 /*-------------------------------------------------------------------------*/
872 
873 /* Declarations of things exported for use by ehci platform drivers */
874 
875 struct ehci_driver_overrides {
876 	size_t		extra_priv_size;
877 	int		(*reset)(struct usb_hcd *hcd);
878 	int		(*port_power)(struct usb_hcd *hcd,
879 				int portnum, bool enable);
880 };
881 
882 extern void	ehci_init_driver(struct hc_driver *drv,
883 				const struct ehci_driver_overrides *over);
884 extern int	ehci_setup(struct usb_hcd *hcd);
885 extern int	ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
886 				u32 mask, u32 done, int usec);
887 extern int	ehci_reset(struct ehci_hcd *ehci);
888 
889 extern int	ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
890 extern int	ehci_resume(struct usb_hcd *hcd, bool force_reset);
891 extern void	ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
892 			bool suspending, bool do_wakeup);
893 
894 extern int	ehci_hub_control(struct usb_hcd	*hcd, u16 typeReq, u16 wValue,
895 				 u16 wIndex, char *buf, u16 wLength);
896 
897 #endif /* __LINUX_EHCI_HCD_H */
898