1 /*
2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
3 *
4 * Copyright (c) 2000-2004 by David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #ifndef CONFIG_PCI
22 #error "This file is PCI bus glue. CONFIG_PCI must be defined."
23 #endif
24
25 /* defined here to avoid adding to pci_ids.h for single instance use */
26 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
27
28 /*-------------------------------------------------------------------------*/
29
30 /* called after powerup, by probe or system-pm "wakeup" */
ehci_pci_reinit(struct ehci_hcd * ehci,struct pci_dev * pdev)31 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
32 {
33 int retval;
34
35 /* we expect static quirk code to handle the "extended capabilities"
36 * (currently just BIOS handoff) allowed starting with EHCI 0.96
37 */
38
39 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
40 retval = pci_set_mwi(pdev);
41 if (!retval)
42 ehci_dbg(ehci, "MWI active\n");
43
44 return 0;
45 }
46
47 /* called during probe() after chip reset completes */
ehci_pci_setup(struct usb_hcd * hcd)48 static int ehci_pci_setup(struct usb_hcd *hcd)
49 {
50 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
51 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
52 struct pci_dev *p_smbus;
53 u8 rev;
54 u32 temp;
55 int retval;
56
57 switch (pdev->vendor) {
58 case PCI_VENDOR_ID_TOSHIBA_2:
59 /* celleb's companion chip */
60 if (pdev->device == 0x01b5) {
61 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
62 ehci->big_endian_mmio = 1;
63 #else
64 ehci_warn(ehci,
65 "unsupported big endian Toshiba quirk\n");
66 #endif
67 }
68 break;
69 }
70
71 ehci->caps = hcd->regs;
72 ehci->regs = hcd->regs +
73 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
74
75 dbg_hcs_params(ehci, "reset");
76 dbg_hcc_params(ehci, "reset");
77
78 /* ehci_init() causes memory for DMA transfers to be
79 * allocated. Thus, any vendor-specific workarounds based on
80 * limiting the type of memory used for DMA transfers must
81 * happen before ehci_init() is called. */
82 switch (pdev->vendor) {
83 case PCI_VENDOR_ID_NVIDIA:
84 /* NVidia reports that certain chips don't handle
85 * QH, ITD, or SITD addresses above 2GB. (But TD,
86 * data buffer, and periodic schedule are normal.)
87 */
88 switch (pdev->device) {
89 case 0x003c: /* MCP04 */
90 case 0x005b: /* CK804 */
91 case 0x00d8: /* CK8 */
92 case 0x00e8: /* CK8S */
93 if (pci_set_consistent_dma_mask(pdev,
94 DMA_BIT_MASK(31)) < 0)
95 ehci_warn(ehci, "can't enable NVidia "
96 "workaround for >2GB RAM\n");
97 break;
98 }
99 break;
100 }
101
102 /* cache this readonly data; minimize chip reads */
103 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
104
105 retval = ehci_halt(ehci);
106 if (retval)
107 return retval;
108
109 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
110 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
111 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
112 * read/write memory space which does not belong to it when
113 * there is NULL pointer with T-bit set to 1 in the frame list
114 * table. To avoid the issue, the frame list link pointer
115 * should always contain a valid pointer to a inactive qh.
116 */
117 ehci->use_dummy_qh = 1;
118 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
119 "dummy qh workaround\n");
120 }
121
122 /* data structure init */
123 retval = ehci_init(hcd);
124 if (retval)
125 return retval;
126
127 switch (pdev->vendor) {
128 case PCI_VENDOR_ID_NEC:
129 ehci->need_io_watchdog = 0;
130 break;
131 case PCI_VENDOR_ID_INTEL:
132 ehci->need_io_watchdog = 0;
133 ehci->fs_i_thresh = 1;
134 if (pdev->device == 0x27cc) {
135 ehci->broken_periodic = 1;
136 ehci_info(ehci, "using broken periodic workaround\n");
137 }
138 if (pdev->device == 0x0806 || pdev->device == 0x0811
139 || pdev->device == 0x0829) {
140 ehci_info(ehci, "disable lpm for langwell/penwell\n");
141 ehci->has_lpm = 0;
142 }
143 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
144 hcd->has_tt = 1;
145 tdi_reset(ehci);
146 }
147 break;
148 case PCI_VENDOR_ID_TDI:
149 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
150 hcd->has_tt = 1;
151 tdi_reset(ehci);
152 }
153 break;
154 case PCI_VENDOR_ID_AMD:
155 /* AMD PLL quirk */
156 if (usb_amd_find_chipset_info())
157 ehci->amd_pll_fix = 1;
158 /* AMD8111 EHCI doesn't work, according to AMD errata */
159 if (pdev->device == 0x7463) {
160 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
161 retval = -EIO;
162 goto done;
163 }
164 break;
165 case PCI_VENDOR_ID_NVIDIA:
166 switch (pdev->device) {
167 /* Some NForce2 chips have problems with selective suspend;
168 * fixed in newer silicon.
169 */
170 case 0x0068:
171 if (pdev->revision < 0xa4)
172 ehci->no_selective_suspend = 1;
173 break;
174
175 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
176 * fetching device descriptors unless LPM is disabled.
177 * There are also intermittent problems enumerating
178 * devices with PPCD enabled.
179 */
180 case 0x0d9d:
181 ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
182 ehci->has_lpm = 0;
183 ehci->has_ppcd = 0;
184 ehci->command &= ~CMD_PPCEE;
185 break;
186 }
187 break;
188 case PCI_VENDOR_ID_VIA:
189 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
190 u8 tmp;
191
192 /* The VT6212 defaults to a 1 usec EHCI sleep time which
193 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
194 * that sleep time use the conventional 10 usec.
195 */
196 pci_read_config_byte(pdev, 0x4b, &tmp);
197 if (tmp & 0x20)
198 break;
199 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
200 }
201 break;
202 case PCI_VENDOR_ID_ATI:
203 /* AMD PLL quirk */
204 if (usb_amd_find_chipset_info())
205 ehci->amd_pll_fix = 1;
206 /* SB600 and old version of SB700 have a bug in EHCI controller,
207 * which causes usb devices lose response in some cases.
208 */
209 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
210 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
211 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
212 NULL);
213 if (!p_smbus)
214 break;
215 rev = p_smbus->revision;
216 if ((pdev->device == 0x4386) || (rev == 0x3a)
217 || (rev == 0x3b)) {
218 u8 tmp;
219 ehci_info(ehci, "applying AMD SB600/SB700 USB "
220 "freeze workaround\n");
221 pci_read_config_byte(pdev, 0x53, &tmp);
222 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
223 }
224 pci_dev_put(p_smbus);
225 }
226 break;
227 case PCI_VENDOR_ID_NETMOS:
228 /* MosChip frame-index-register bug */
229 ehci_info(ehci, "applying MosChip frame-index workaround\n");
230 ehci->frame_index_bug = 1;
231 break;
232 }
233
234 /* optional debug port, normally in the first BAR */
235 temp = pci_find_capability(pdev, 0x0a);
236 if (temp) {
237 pci_read_config_dword(pdev, temp, &temp);
238 temp >>= 16;
239 if ((temp & (3 << 13)) == (1 << 13)) {
240 temp &= 0x1fff;
241 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
242 temp = ehci_readl(ehci, &ehci->debug->control);
243 ehci_info(ehci, "debug port %d%s\n",
244 HCS_DEBUG_PORT(ehci->hcs_params),
245 (temp & DBGP_ENABLED)
246 ? " IN USE"
247 : "");
248 if (!(temp & DBGP_ENABLED))
249 ehci->debug = NULL;
250 }
251 }
252
253 ehci_reset(ehci);
254
255 /* at least the Genesys GL880S needs fixup here */
256 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
257 temp &= 0x0f;
258 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
259 ehci_dbg(ehci, "bogus port configuration: "
260 "cc=%d x pcc=%d < ports=%d\n",
261 HCS_N_CC(ehci->hcs_params),
262 HCS_N_PCC(ehci->hcs_params),
263 HCS_N_PORTS(ehci->hcs_params));
264
265 switch (pdev->vendor) {
266 case 0x17a0: /* GENESYS */
267 /* GL880S: should be PORTS=2 */
268 temp |= (ehci->hcs_params & ~0xf);
269 ehci->hcs_params = temp;
270 break;
271 case PCI_VENDOR_ID_NVIDIA:
272 /* NF4: should be PCC=10 */
273 break;
274 }
275 }
276
277 /* Serial Bus Release Number is at PCI 0x60 offset */
278 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
279 if (pdev->vendor == PCI_VENDOR_ID_STMICRO
280 && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
281 ehci->sbrn = 0x20; /* ConneXT has no sbrn register */
282
283 /* Keep this around for a while just in case some EHCI
284 * implementation uses legacy PCI PM support. This test
285 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
286 * been triggered by then.
287 */
288 if (!device_can_wakeup(&pdev->dev)) {
289 u16 port_wake;
290
291 pci_read_config_word(pdev, 0x62, &port_wake);
292 if (port_wake & 0x0001) {
293 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
294 device_set_wakeup_capable(&pdev->dev, 1);
295 }
296 }
297
298 #ifdef CONFIG_USB_SUSPEND
299 /* REVISIT: the controller works fine for wakeup iff the root hub
300 * itself is "globally" suspended, but usbcore currently doesn't
301 * understand such things.
302 *
303 * System suspend currently expects to be able to suspend the entire
304 * device tree, device-at-a-time. If we failed selective suspend
305 * reports, system suspend would fail; so the root hub code must claim
306 * success. That's lying to usbcore, and it matters for runtime
307 * PM scenarios with selective suspend and remote wakeup...
308 */
309 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
310 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
311 #endif
312
313 ehci_port_power(ehci, 1);
314 retval = ehci_pci_reinit(ehci, pdev);
315 done:
316 return retval;
317 }
318
319 /*-------------------------------------------------------------------------*/
320
321 #ifdef CONFIG_PM
322
323 /* suspend/resume, section 4.3 */
324
325 /* These routines rely on the PCI bus glue
326 * to handle powerdown and wakeup, and currently also on
327 * transceivers that don't need any software attention to set up
328 * the right sort of wakeup.
329 * Also they depend on separate root hub suspend/resume.
330 */
331
ehci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)332 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
333 {
334 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
335 unsigned long flags;
336 int rc = 0;
337
338 if (time_before(jiffies, ehci->next_statechange))
339 msleep(10);
340
341 /* Root hub was already suspended. Disable irq emission and
342 * mark HW unaccessible. The PM and USB cores make sure that
343 * the root hub is either suspended or stopped.
344 */
345 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
346 spin_lock_irqsave (&ehci->lock, flags);
347 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
348 (void)ehci_readl(ehci, &ehci->regs->intr_enable);
349
350 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
351 spin_unlock_irqrestore (&ehci->lock, flags);
352
353 // could save FLADJ in case of Vaux power loss
354 // ... we'd only use it to handle clock skew
355
356 return rc;
357 }
358
usb_is_intel_switchable_ehci(struct pci_dev * pdev)359 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
360 {
361 return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
362 pdev->vendor == PCI_VENDOR_ID_INTEL &&
363 (pdev->device == 0x1E26 ||
364 pdev->device == 0x8C2D ||
365 pdev->device == 0x8C26 ||
366 pdev->device == 0x9C26);
367 }
368
ehci_enable_xhci_companion(void)369 static void ehci_enable_xhci_companion(void)
370 {
371 struct pci_dev *companion = NULL;
372
373 /* The xHCI and EHCI controllers are not on the same PCI slot */
374 for_each_pci_dev(companion) {
375 if (!usb_is_intel_switchable_xhci(companion))
376 continue;
377 usb_enable_xhci_ports(companion);
378 return;
379 }
380 }
381
ehci_pci_resume(struct usb_hcd * hcd,bool hibernated)382 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
383 {
384 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
385 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
386
387 /* The BIOS on systems with the Intel Panther Point chipset may or may
388 * not support xHCI natively. That means that during system resume, it
389 * may switch the ports back to EHCI so that users can use their
390 * keyboard to select a kernel from GRUB after resume from hibernate.
391 *
392 * The BIOS is supposed to remember whether the OS had xHCI ports
393 * enabled before resume, and switch the ports back to xHCI when the
394 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
395 * writers.
396 *
397 * Unconditionally switch the ports back to xHCI after a system resume.
398 * We can't tell whether the EHCI or xHCI controller will be resumed
399 * first, so we have to do the port switchover in both drivers. Writing
400 * a '1' to the port switchover registers should have no effect if the
401 * port was already switched over.
402 */
403 if (usb_is_intel_switchable_ehci(pdev))
404 ehci_enable_xhci_companion();
405
406 // maybe restore FLADJ
407
408 if (time_before(jiffies, ehci->next_statechange))
409 msleep(100);
410
411 /* Mark hardware accessible again as we are out of D3 state by now */
412 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
413
414 /* If CF is still set and we aren't resuming from hibernation
415 * then we maintained PCI Vaux power.
416 * Just undo the effect of ehci_pci_suspend().
417 */
418 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
419 !hibernated) {
420 int mask = INTR_MASK;
421
422 ehci_prepare_ports_for_controller_resume(ehci);
423 if (!hcd->self.root_hub->do_remote_wakeup)
424 mask &= ~STS_PCD;
425 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
426 ehci_readl(ehci, &ehci->regs->intr_enable);
427 return 0;
428 }
429
430 usb_root_hub_lost_power(hcd->self.root_hub);
431
432 /* Else reset, to cope with power loss or flush-to-storage
433 * style "resume" having let BIOS kick in during reboot.
434 */
435 (void) ehci_halt(ehci);
436 (void) ehci_reset(ehci);
437 (void) ehci_pci_reinit(ehci, pdev);
438
439 /* emptying the schedule aborts any urbs */
440 spin_lock_irq(&ehci->lock);
441 if (ehci->reclaim)
442 end_unlink_async(ehci);
443 ehci_work(ehci);
444 spin_unlock_irq(&ehci->lock);
445
446 ehci_writel(ehci, ehci->command, &ehci->regs->command);
447 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
448 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
449
450 /* here we "know" root ports should always stay powered */
451 ehci_port_power(ehci, 1);
452
453 ehci->rh_state = EHCI_RH_SUSPENDED;
454 return 0;
455 }
456 #endif
457
ehci_update_device(struct usb_hcd * hcd,struct usb_device * udev)458 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
459 {
460 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
461 int rc = 0;
462
463 if (!udev->parent) /* udev is root hub itself, impossible */
464 rc = -1;
465 /* we only support lpm device connected to root hub yet */
466 if (ehci->has_lpm && !udev->parent->parent) {
467 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
468 if (!rc)
469 rc = ehci_lpm_check(ehci, udev->portnum);
470 }
471 return rc;
472 }
473
474 static const struct hc_driver ehci_pci_hc_driver = {
475 .description = hcd_name,
476 .product_desc = "EHCI Host Controller",
477 .hcd_priv_size = sizeof(struct ehci_hcd),
478
479 /*
480 * generic hardware linkage
481 */
482 .irq = ehci_irq,
483 .flags = HCD_MEMORY | HCD_USB2,
484
485 /*
486 * basic lifecycle operations
487 */
488 .reset = ehci_pci_setup,
489 .start = ehci_run,
490 #ifdef CONFIG_PM
491 .pci_suspend = ehci_pci_suspend,
492 .pci_resume = ehci_pci_resume,
493 #endif
494 .stop = ehci_stop,
495 .shutdown = ehci_shutdown,
496
497 /*
498 * managing i/o requests and associated device resources
499 */
500 .urb_enqueue = ehci_urb_enqueue,
501 .urb_dequeue = ehci_urb_dequeue,
502 .endpoint_disable = ehci_endpoint_disable,
503 .endpoint_reset = ehci_endpoint_reset,
504
505 /*
506 * scheduling support
507 */
508 .get_frame_number = ehci_get_frame,
509
510 /*
511 * root hub support
512 */
513 .hub_status_data = ehci_hub_status_data,
514 .hub_control = ehci_hub_control,
515 .bus_suspend = ehci_bus_suspend,
516 .bus_resume = ehci_bus_resume,
517 .relinquish_port = ehci_relinquish_port,
518 .port_handed_over = ehci_port_handed_over,
519
520 /*
521 * call back when device connected and addressed
522 */
523 .update_device = ehci_update_device,
524
525 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
526 };
527
528 /*-------------------------------------------------------------------------*/
529
530 /* PCI driver selection metadata; PCI hotplugging uses this */
531 static const struct pci_device_id pci_ids [] = { {
532 /* handle any USB 2.0 EHCI controller */
533 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
534 .driver_data = (unsigned long) &ehci_pci_hc_driver,
535 }, {
536 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
537 .driver_data = (unsigned long) &ehci_pci_hc_driver,
538 },
539 { /* end: all zeroes */ }
540 };
541 MODULE_DEVICE_TABLE(pci, pci_ids);
542
543 /* pci driver glue; this is a "new style" PCI driver module */
544 static struct pci_driver ehci_pci_driver = {
545 .name = (char *) hcd_name,
546 .id_table = pci_ids,
547
548 .probe = usb_hcd_pci_probe,
549 .remove = usb_hcd_pci_remove,
550 .shutdown = usb_hcd_pci_shutdown,
551
552 #ifdef CONFIG_PM
553 .driver = {
554 .pm = &usb_hcd_pci_pm_ops
555 },
556 #endif
557 };
558