1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2011 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/seq_file.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "regs.h"
22 #include "io.h"
23 #include "workarounds.h"
24
25 /**************************************************************************
26 *
27 * Configurable values
28 *
29 **************************************************************************
30 */
31
32 /* This is set to 16 for a good reason. In summary, if larger than
33 * 16, the descriptor cache holds more than a default socket
34 * buffer's worth of packets (for UDP we can only have at most one
35 * socket buffer's worth outstanding). This combined with the fact
36 * that we only get 1 TX event per descriptor cache means the NIC
37 * goes idle.
38 */
39 #define TX_DC_ENTRIES 16
40 #define TX_DC_ENTRIES_ORDER 1
41
42 #define RX_DC_ENTRIES 64
43 #define RX_DC_ENTRIES_ORDER 3
44
45 /* If EFX_MAX_INT_ERRORS internal errors occur within
46 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
47 * disable it.
48 */
49 #define EFX_INT_ERROR_EXPIRE 3600
50 #define EFX_MAX_INT_ERRORS 5
51
52 /* Depth of RX flush request fifo */
53 #define EFX_RX_FLUSH_COUNT 4
54
55 /* Driver generated events */
56 #define _EFX_CHANNEL_MAGIC_TEST 0x000101
57 #define _EFX_CHANNEL_MAGIC_FILL 0x000102
58 #define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103
59 #define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104
60
61 #define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data))
62 #define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8)
63
64 #define EFX_CHANNEL_MAGIC_TEST(_channel) \
65 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
66 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \
67 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \
68 efx_rx_queue_index(_rx_queue))
69 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \
70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \
71 efx_rx_queue_index(_rx_queue))
72 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \
73 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \
74 (_tx_queue)->queue)
75
76 static void efx_magic_event(struct efx_channel *channel, u32 magic);
77
78 /**************************************************************************
79 *
80 * Solarstorm hardware access
81 *
82 **************************************************************************/
83
efx_write_buf_tbl(struct efx_nic * efx,efx_qword_t * value,unsigned int index)84 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
85 unsigned int index)
86 {
87 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
88 value, index);
89 }
90
91 /* Read the current event from the event queue */
efx_event(struct efx_channel * channel,unsigned int index)92 static inline efx_qword_t *efx_event(struct efx_channel *channel,
93 unsigned int index)
94 {
95 return ((efx_qword_t *) (channel->eventq.addr)) +
96 (index & channel->eventq_mask);
97 }
98
99 /* See if an event is present
100 *
101 * We check both the high and low dword of the event for all ones. We
102 * wrote all ones when we cleared the event, and no valid event can
103 * have all ones in either its high or low dwords. This approach is
104 * robust against reordering.
105 *
106 * Note that using a single 64-bit comparison is incorrect; even
107 * though the CPU read will be atomic, the DMA write may not be.
108 */
efx_event_present(efx_qword_t * event)109 static inline int efx_event_present(efx_qword_t *event)
110 {
111 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
112 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
113 }
114
efx_masked_compare_oword(const efx_oword_t * a,const efx_oword_t * b,const efx_oword_t * mask)115 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
116 const efx_oword_t *mask)
117 {
118 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
119 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
120 }
121
efx_nic_test_registers(struct efx_nic * efx,const struct efx_nic_register_test * regs,size_t n_regs)122 int efx_nic_test_registers(struct efx_nic *efx,
123 const struct efx_nic_register_test *regs,
124 size_t n_regs)
125 {
126 unsigned address = 0, i, j;
127 efx_oword_t mask, imask, original, reg, buf;
128
129 for (i = 0; i < n_regs; ++i) {
130 address = regs[i].address;
131 mask = imask = regs[i].mask;
132 EFX_INVERT_OWORD(imask);
133
134 efx_reado(efx, &original, address);
135
136 /* bit sweep on and off */
137 for (j = 0; j < 128; j++) {
138 if (!EFX_EXTRACT_OWORD32(mask, j, j))
139 continue;
140
141 /* Test this testable bit can be set in isolation */
142 EFX_AND_OWORD(reg, original, mask);
143 EFX_SET_OWORD32(reg, j, j, 1);
144
145 efx_writeo(efx, ®, address);
146 efx_reado(efx, &buf, address);
147
148 if (efx_masked_compare_oword(®, &buf, &mask))
149 goto fail;
150
151 /* Test this testable bit can be cleared in isolation */
152 EFX_OR_OWORD(reg, original, mask);
153 EFX_SET_OWORD32(reg, j, j, 0);
154
155 efx_writeo(efx, ®, address);
156 efx_reado(efx, &buf, address);
157
158 if (efx_masked_compare_oword(®, &buf, &mask))
159 goto fail;
160 }
161
162 efx_writeo(efx, &original, address);
163 }
164
165 return 0;
166
167 fail:
168 netif_err(efx, hw, efx->net_dev,
169 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
170 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
171 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
172 return -EIO;
173 }
174
175 /**************************************************************************
176 *
177 * Special buffer handling
178 * Special buffers are used for event queues and the TX and RX
179 * descriptor rings.
180 *
181 *************************************************************************/
182
183 /*
184 * Initialise a special buffer
185 *
186 * This will define a buffer (previously allocated via
187 * efx_alloc_special_buffer()) in the buffer table, allowing
188 * it to be used for event queues, descriptor rings etc.
189 */
190 static void
efx_init_special_buffer(struct efx_nic * efx,struct efx_special_buffer * buffer)191 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
192 {
193 efx_qword_t buf_desc;
194 unsigned int index;
195 dma_addr_t dma_addr;
196 int i;
197
198 EFX_BUG_ON_PARANOID(!buffer->addr);
199
200 /* Write buffer descriptors to NIC */
201 for (i = 0; i < buffer->entries; i++) {
202 index = buffer->index + i;
203 dma_addr = buffer->dma_addr + (i * EFX_BUF_SIZE);
204 netif_dbg(efx, probe, efx->net_dev,
205 "mapping special buffer %d at %llx\n",
206 index, (unsigned long long)dma_addr);
207 EFX_POPULATE_QWORD_3(buf_desc,
208 FRF_AZ_BUF_ADR_REGION, 0,
209 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
210 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
211 efx_write_buf_tbl(efx, &buf_desc, index);
212 }
213 }
214
215 /* Unmaps a buffer and clears the buffer table entries */
216 static void
efx_fini_special_buffer(struct efx_nic * efx,struct efx_special_buffer * buffer)217 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
218 {
219 efx_oword_t buf_tbl_upd;
220 unsigned int start = buffer->index;
221 unsigned int end = (buffer->index + buffer->entries - 1);
222
223 if (!buffer->entries)
224 return;
225
226 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
227 buffer->index, buffer->index + buffer->entries - 1);
228
229 EFX_POPULATE_OWORD_4(buf_tbl_upd,
230 FRF_AZ_BUF_UPD_CMD, 0,
231 FRF_AZ_BUF_CLR_CMD, 1,
232 FRF_AZ_BUF_CLR_END_ID, end,
233 FRF_AZ_BUF_CLR_START_ID, start);
234 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
235 }
236
237 /*
238 * Allocate a new special buffer
239 *
240 * This allocates memory for a new buffer, clears it and allocates a
241 * new buffer ID range. It does not write into the buffer table.
242 *
243 * This call will allocate 4KB buffers, since 8KB buffers can't be
244 * used for event queues and descriptor rings.
245 */
efx_alloc_special_buffer(struct efx_nic * efx,struct efx_special_buffer * buffer,unsigned int len)246 static int efx_alloc_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer,
248 unsigned int len)
249 {
250 len = ALIGN(len, EFX_BUF_SIZE);
251
252 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
253 &buffer->dma_addr, GFP_KERNEL);
254 if (!buffer->addr)
255 return -ENOMEM;
256 buffer->len = len;
257 buffer->entries = len / EFX_BUF_SIZE;
258 BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
259
260 /* All zeros is a potentially valid event so memset to 0xff */
261 memset(buffer->addr, 0xff, len);
262
263 /* Select new buffer ID */
264 buffer->index = efx->next_buffer_table;
265 efx->next_buffer_table += buffer->entries;
266 #ifdef CONFIG_SFC_SRIOV
267 BUG_ON(efx_sriov_enabled(efx) &&
268 efx->vf_buftbl_base < efx->next_buffer_table);
269 #endif
270
271 netif_dbg(efx, probe, efx->net_dev,
272 "allocating special buffers %d-%d at %llx+%x "
273 "(virt %p phys %llx)\n", buffer->index,
274 buffer->index + buffer->entries - 1,
275 (u64)buffer->dma_addr, len,
276 buffer->addr, (u64)virt_to_phys(buffer->addr));
277
278 return 0;
279 }
280
281 static void
efx_free_special_buffer(struct efx_nic * efx,struct efx_special_buffer * buffer)282 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
283 {
284 if (!buffer->addr)
285 return;
286
287 netif_dbg(efx, hw, efx->net_dev,
288 "deallocating special buffers %d-%d at %llx+%x "
289 "(virt %p phys %llx)\n", buffer->index,
290 buffer->index + buffer->entries - 1,
291 (u64)buffer->dma_addr, buffer->len,
292 buffer->addr, (u64)virt_to_phys(buffer->addr));
293
294 dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr,
295 buffer->dma_addr);
296 buffer->addr = NULL;
297 buffer->entries = 0;
298 }
299
300 /**************************************************************************
301 *
302 * Generic buffer handling
303 * These buffers are used for interrupt status and MAC stats
304 *
305 **************************************************************************/
306
efx_nic_alloc_buffer(struct efx_nic * efx,struct efx_buffer * buffer,unsigned int len)307 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
308 unsigned int len)
309 {
310 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
311 &buffer->dma_addr);
312 if (!buffer->addr)
313 return -ENOMEM;
314 buffer->len = len;
315 memset(buffer->addr, 0, len);
316 return 0;
317 }
318
efx_nic_free_buffer(struct efx_nic * efx,struct efx_buffer * buffer)319 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
320 {
321 if (buffer->addr) {
322 pci_free_consistent(efx->pci_dev, buffer->len,
323 buffer->addr, buffer->dma_addr);
324 buffer->addr = NULL;
325 }
326 }
327
328 /**************************************************************************
329 *
330 * TX path
331 *
332 **************************************************************************/
333
334 /* Returns a pointer to the specified transmit descriptor in the TX
335 * descriptor queue belonging to the specified channel.
336 */
337 static inline efx_qword_t *
efx_tx_desc(struct efx_tx_queue * tx_queue,unsigned int index)338 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
339 {
340 return ((efx_qword_t *) (tx_queue->txd.addr)) + index;
341 }
342
343 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
efx_notify_tx_desc(struct efx_tx_queue * tx_queue)344 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
345 {
346 unsigned write_ptr;
347 efx_dword_t reg;
348
349 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
350 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
351 efx_writed_page(tx_queue->efx, ®,
352 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
353 }
354
355 /* Write pointer and first descriptor for TX descriptor ring */
efx_push_tx_desc(struct efx_tx_queue * tx_queue,const efx_qword_t * txd)356 static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue,
357 const efx_qword_t *txd)
358 {
359 unsigned write_ptr;
360 efx_oword_t reg;
361
362 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
363 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
364
365 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
366 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
367 FRF_AZ_TX_DESC_WPTR, write_ptr);
368 reg.qword[0] = *txd;
369 efx_writeo_page(tx_queue->efx, ®,
370 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
371 }
372
373 static inline bool
efx_may_push_tx_desc(struct efx_tx_queue * tx_queue,unsigned int write_count)374 efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count)
375 {
376 unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
377
378 if (empty_read_count == 0)
379 return false;
380
381 tx_queue->empty_read_count = 0;
382 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0
383 && tx_queue->write_count - write_count == 1;
384 }
385
386 /* For each entry inserted into the software descriptor ring, create a
387 * descriptor in the hardware TX descriptor ring (in host memory), and
388 * write a doorbell.
389 */
efx_nic_push_buffers(struct efx_tx_queue * tx_queue)390 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
391 {
392
393 struct efx_tx_buffer *buffer;
394 efx_qword_t *txd;
395 unsigned write_ptr;
396 unsigned old_write_count = tx_queue->write_count;
397
398 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
399
400 do {
401 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
402 buffer = &tx_queue->buffer[write_ptr];
403 txd = efx_tx_desc(tx_queue, write_ptr);
404 ++tx_queue->write_count;
405
406 /* Create TX descriptor ring entry */
407 EFX_POPULATE_QWORD_4(*txd,
408 FSF_AZ_TX_KER_CONT, buffer->continuation,
409 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
410 FSF_AZ_TX_KER_BUF_REGION, 0,
411 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
412 } while (tx_queue->write_count != tx_queue->insert_count);
413
414 wmb(); /* Ensure descriptors are written before they are fetched */
415
416 if (efx_may_push_tx_desc(tx_queue, old_write_count)) {
417 txd = efx_tx_desc(tx_queue,
418 old_write_count & tx_queue->ptr_mask);
419 efx_push_tx_desc(tx_queue, txd);
420 ++tx_queue->pushes;
421 } else {
422 efx_notify_tx_desc(tx_queue);
423 }
424 }
425
426 /* Allocate hardware resources for a TX queue */
efx_nic_probe_tx(struct efx_tx_queue * tx_queue)427 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
428 {
429 struct efx_nic *efx = tx_queue->efx;
430 unsigned entries;
431
432 entries = tx_queue->ptr_mask + 1;
433 return efx_alloc_special_buffer(efx, &tx_queue->txd,
434 entries * sizeof(efx_qword_t));
435 }
436
efx_nic_init_tx(struct efx_tx_queue * tx_queue)437 void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
438 {
439 struct efx_nic *efx = tx_queue->efx;
440 efx_oword_t reg;
441
442 /* Pin TX descriptor ring */
443 efx_init_special_buffer(efx, &tx_queue->txd);
444
445 /* Push TX descriptor ring to card */
446 EFX_POPULATE_OWORD_10(reg,
447 FRF_AZ_TX_DESCQ_EN, 1,
448 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
449 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
450 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
451 FRF_AZ_TX_DESCQ_EVQ_ID,
452 tx_queue->channel->channel,
453 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
454 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
455 FRF_AZ_TX_DESCQ_SIZE,
456 __ffs(tx_queue->txd.entries),
457 FRF_AZ_TX_DESCQ_TYPE, 0,
458 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
459
460 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
461 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
462 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
463 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
464 !csum);
465 }
466
467 efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base,
468 tx_queue->queue);
469
470 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
471 /* Only 128 bits in this register */
472 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
473
474 efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG);
475 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
476 clear_bit_le(tx_queue->queue, (void *)®);
477 else
478 set_bit_le(tx_queue->queue, (void *)®);
479 efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG);
480 }
481
482 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
483 EFX_POPULATE_OWORD_1(reg,
484 FRF_BZ_TX_PACE,
485 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
486 FFE_BZ_TX_PACE_OFF :
487 FFE_BZ_TX_PACE_RESERVED);
488 efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL,
489 tx_queue->queue);
490 }
491 }
492
efx_flush_tx_queue(struct efx_tx_queue * tx_queue)493 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
494 {
495 struct efx_nic *efx = tx_queue->efx;
496 efx_oword_t tx_flush_descq;
497
498 WARN_ON(atomic_read(&tx_queue->flush_outstanding));
499 atomic_set(&tx_queue->flush_outstanding, 1);
500
501 EFX_POPULATE_OWORD_2(tx_flush_descq,
502 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
503 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
504 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
505 }
506
efx_nic_fini_tx(struct efx_tx_queue * tx_queue)507 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
508 {
509 struct efx_nic *efx = tx_queue->efx;
510 efx_oword_t tx_desc_ptr;
511
512 /* Remove TX descriptor ring from card */
513 EFX_ZERO_OWORD(tx_desc_ptr);
514 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
515 tx_queue->queue);
516
517 /* Unpin TX descriptor ring */
518 efx_fini_special_buffer(efx, &tx_queue->txd);
519 }
520
521 /* Free buffers backing TX queue */
efx_nic_remove_tx(struct efx_tx_queue * tx_queue)522 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
523 {
524 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
525 }
526
527 /**************************************************************************
528 *
529 * RX path
530 *
531 **************************************************************************/
532
533 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
534 static inline efx_qword_t *
efx_rx_desc(struct efx_rx_queue * rx_queue,unsigned int index)535 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
536 {
537 return ((efx_qword_t *) (rx_queue->rxd.addr)) + index;
538 }
539
540 /* This creates an entry in the RX descriptor queue */
541 static inline void
efx_build_rx_desc(struct efx_rx_queue * rx_queue,unsigned index)542 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
543 {
544 struct efx_rx_buffer *rx_buf;
545 efx_qword_t *rxd;
546
547 rxd = efx_rx_desc(rx_queue, index);
548 rx_buf = efx_rx_buffer(rx_queue, index);
549 EFX_POPULATE_QWORD_3(*rxd,
550 FSF_AZ_RX_KER_BUF_SIZE,
551 rx_buf->len -
552 rx_queue->efx->type->rx_buffer_padding,
553 FSF_AZ_RX_KER_BUF_REGION, 0,
554 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
555 }
556
557 /* This writes to the RX_DESC_WPTR register for the specified receive
558 * descriptor ring.
559 */
efx_nic_notify_rx_desc(struct efx_rx_queue * rx_queue)560 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
561 {
562 struct efx_nic *efx = rx_queue->efx;
563 efx_dword_t reg;
564 unsigned write_ptr;
565
566 while (rx_queue->notified_count != rx_queue->added_count) {
567 efx_build_rx_desc(
568 rx_queue,
569 rx_queue->notified_count & rx_queue->ptr_mask);
570 ++rx_queue->notified_count;
571 }
572
573 wmb();
574 write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
575 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
576 efx_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0,
577 efx_rx_queue_index(rx_queue));
578 }
579
efx_nic_probe_rx(struct efx_rx_queue * rx_queue)580 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
581 {
582 struct efx_nic *efx = rx_queue->efx;
583 unsigned entries;
584
585 entries = rx_queue->ptr_mask + 1;
586 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
587 entries * sizeof(efx_qword_t));
588 }
589
efx_nic_init_rx(struct efx_rx_queue * rx_queue)590 void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
591 {
592 efx_oword_t rx_desc_ptr;
593 struct efx_nic *efx = rx_queue->efx;
594 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
595 bool iscsi_digest_en = is_b0;
596
597 netif_dbg(efx, hw, efx->net_dev,
598 "RX queue %d ring in special buffers %d-%d\n",
599 efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
600 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
601
602 /* Pin RX descriptor ring */
603 efx_init_special_buffer(efx, &rx_queue->rxd);
604
605 /* Push RX descriptor ring to card */
606 EFX_POPULATE_OWORD_10(rx_desc_ptr,
607 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
608 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
609 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
610 FRF_AZ_RX_DESCQ_EVQ_ID,
611 efx_rx_queue_channel(rx_queue)->channel,
612 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
613 FRF_AZ_RX_DESCQ_LABEL,
614 efx_rx_queue_index(rx_queue),
615 FRF_AZ_RX_DESCQ_SIZE,
616 __ffs(rx_queue->rxd.entries),
617 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
618 /* For >=B0 this is scatter so disable */
619 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
620 FRF_AZ_RX_DESCQ_EN, 1);
621 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
622 efx_rx_queue_index(rx_queue));
623 }
624
efx_flush_rx_queue(struct efx_rx_queue * rx_queue)625 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
626 {
627 struct efx_nic *efx = rx_queue->efx;
628 efx_oword_t rx_flush_descq;
629
630 EFX_POPULATE_OWORD_2(rx_flush_descq,
631 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
632 FRF_AZ_RX_FLUSH_DESCQ,
633 efx_rx_queue_index(rx_queue));
634 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
635 }
636
efx_nic_fini_rx(struct efx_rx_queue * rx_queue)637 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
638 {
639 efx_oword_t rx_desc_ptr;
640 struct efx_nic *efx = rx_queue->efx;
641
642 /* Remove RX descriptor ring from card */
643 EFX_ZERO_OWORD(rx_desc_ptr);
644 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
645 efx_rx_queue_index(rx_queue));
646
647 /* Unpin RX descriptor ring */
648 efx_fini_special_buffer(efx, &rx_queue->rxd);
649 }
650
651 /* Free buffers backing RX queue */
efx_nic_remove_rx(struct efx_rx_queue * rx_queue)652 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
653 {
654 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
655 }
656
657 /**************************************************************************
658 *
659 * Flush handling
660 *
661 **************************************************************************/
662
663 /* efx_nic_flush_queues() must be woken up when all flushes are completed,
664 * or more RX flushes can be kicked off.
665 */
efx_flush_wake(struct efx_nic * efx)666 static bool efx_flush_wake(struct efx_nic *efx)
667 {
668 /* Ensure that all updates are visible to efx_nic_flush_queues() */
669 smp_mb();
670
671 return (atomic_read(&efx->drain_pending) == 0 ||
672 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
673 && atomic_read(&efx->rxq_flush_pending) > 0));
674 }
675
efx_check_tx_flush_complete(struct efx_nic * efx)676 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
677 {
678 bool i = true;
679 efx_oword_t txd_ptr_tbl;
680 struct efx_channel *channel;
681 struct efx_tx_queue *tx_queue;
682
683 efx_for_each_channel(channel, efx) {
684 efx_for_each_channel_tx_queue(tx_queue, channel) {
685 efx_reado_table(efx, &txd_ptr_tbl,
686 FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
687 if (EFX_OWORD_FIELD(txd_ptr_tbl,
688 FRF_AZ_TX_DESCQ_FLUSH) ||
689 EFX_OWORD_FIELD(txd_ptr_tbl,
690 FRF_AZ_TX_DESCQ_EN)) {
691 netif_dbg(efx, hw, efx->net_dev,
692 "flush did not complete on TXQ %d\n",
693 tx_queue->queue);
694 i = false;
695 } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
696 1, 0)) {
697 /* The flush is complete, but we didn't
698 * receive a flush completion event
699 */
700 netif_dbg(efx, hw, efx->net_dev,
701 "flush complete on TXQ %d, so drain "
702 "the queue\n", tx_queue->queue);
703 /* Don't need to increment drain_pending as it
704 * has already been incremented for the queues
705 * which did not drain
706 */
707 efx_magic_event(channel,
708 EFX_CHANNEL_MAGIC_TX_DRAIN(
709 tx_queue));
710 }
711 }
712 }
713
714 return i;
715 }
716
717 /* Flush all the transmit queues, and continue flushing receive queues until
718 * they're all flushed. Wait for the DRAIN events to be recieved so that there
719 * are no more RX and TX events left on any channel. */
efx_nic_flush_queues(struct efx_nic * efx)720 int efx_nic_flush_queues(struct efx_nic *efx)
721 {
722 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
723 struct efx_channel *channel;
724 struct efx_rx_queue *rx_queue;
725 struct efx_tx_queue *tx_queue;
726 int rc = 0;
727
728 efx->type->prepare_flush(efx);
729
730 efx_for_each_channel(channel, efx) {
731 efx_for_each_channel_tx_queue(tx_queue, channel) {
732 atomic_inc(&efx->drain_pending);
733 efx_flush_tx_queue(tx_queue);
734 }
735 efx_for_each_channel_rx_queue(rx_queue, channel) {
736 atomic_inc(&efx->drain_pending);
737 rx_queue->flush_pending = true;
738 atomic_inc(&efx->rxq_flush_pending);
739 }
740 }
741
742 while (timeout && atomic_read(&efx->drain_pending) > 0) {
743 /* If SRIOV is enabled, then offload receive queue flushing to
744 * the firmware (though we will still have to poll for
745 * completion). If that fails, fall back to the old scheme.
746 */
747 if (efx_sriov_enabled(efx)) {
748 rc = efx_mcdi_flush_rxqs(efx);
749 if (!rc)
750 goto wait;
751 }
752
753 /* The hardware supports four concurrent rx flushes, each of
754 * which may need to be retried if there is an outstanding
755 * descriptor fetch
756 */
757 efx_for_each_channel(channel, efx) {
758 efx_for_each_channel_rx_queue(rx_queue, channel) {
759 if (atomic_read(&efx->rxq_flush_outstanding) >=
760 EFX_RX_FLUSH_COUNT)
761 break;
762
763 if (rx_queue->flush_pending) {
764 rx_queue->flush_pending = false;
765 atomic_dec(&efx->rxq_flush_pending);
766 atomic_inc(&efx->rxq_flush_outstanding);
767 efx_flush_rx_queue(rx_queue);
768 }
769 }
770 }
771
772 wait:
773 timeout = wait_event_timeout(efx->flush_wq, efx_flush_wake(efx),
774 timeout);
775 }
776
777 if (atomic_read(&efx->drain_pending) &&
778 !efx_check_tx_flush_complete(efx)) {
779 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
780 "(rx %d+%d)\n", atomic_read(&efx->drain_pending),
781 atomic_read(&efx->rxq_flush_outstanding),
782 atomic_read(&efx->rxq_flush_pending));
783 rc = -ETIMEDOUT;
784
785 atomic_set(&efx->drain_pending, 0);
786 atomic_set(&efx->rxq_flush_pending, 0);
787 atomic_set(&efx->rxq_flush_outstanding, 0);
788 }
789
790 efx->type->finish_flush(efx);
791
792 return rc;
793 }
794
795 /**************************************************************************
796 *
797 * Event queue processing
798 * Event queues are processed by per-channel tasklets.
799 *
800 **************************************************************************/
801
802 /* Update a channel's event queue's read pointer (RPTR) register
803 *
804 * This writes the EVQ_RPTR_REG register for the specified channel's
805 * event queue.
806 */
efx_nic_eventq_read_ack(struct efx_channel * channel)807 void efx_nic_eventq_read_ack(struct efx_channel *channel)
808 {
809 efx_dword_t reg;
810 struct efx_nic *efx = channel->efx;
811
812 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
813 channel->eventq_read_ptr & channel->eventq_mask);
814 efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base,
815 channel->channel);
816 }
817
818 /* Use HW to insert a SW defined event */
efx_generate_event(struct efx_nic * efx,unsigned int evq,efx_qword_t * event)819 void efx_generate_event(struct efx_nic *efx, unsigned int evq,
820 efx_qword_t *event)
821 {
822 efx_oword_t drv_ev_reg;
823
824 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
825 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
826 drv_ev_reg.u32[0] = event->u32[0];
827 drv_ev_reg.u32[1] = event->u32[1];
828 drv_ev_reg.u32[2] = 0;
829 drv_ev_reg.u32[3] = 0;
830 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
831 efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
832 }
833
efx_magic_event(struct efx_channel * channel,u32 magic)834 static void efx_magic_event(struct efx_channel *channel, u32 magic)
835 {
836 efx_qword_t event;
837
838 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
839 FSE_AZ_EV_CODE_DRV_GEN_EV,
840 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
841 efx_generate_event(channel->efx, channel->channel, &event);
842 }
843
844 /* Handle a transmit completion event
845 *
846 * The NIC batches TX completion events; the message we receive is of
847 * the form "complete all TX events up to this index".
848 */
849 static int
efx_handle_tx_event(struct efx_channel * channel,efx_qword_t * event)850 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
851 {
852 unsigned int tx_ev_desc_ptr;
853 unsigned int tx_ev_q_label;
854 struct efx_tx_queue *tx_queue;
855 struct efx_nic *efx = channel->efx;
856 int tx_packets = 0;
857
858 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
859 return 0;
860
861 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
862 /* Transmit completion */
863 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
864 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
865 tx_queue = efx_channel_get_tx_queue(
866 channel, tx_ev_q_label % EFX_TXQ_TYPES);
867 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
868 tx_queue->ptr_mask);
869 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
870 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
871 /* Rewrite the FIFO write pointer */
872 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
873 tx_queue = efx_channel_get_tx_queue(
874 channel, tx_ev_q_label % EFX_TXQ_TYPES);
875
876 netif_tx_lock(efx->net_dev);
877 efx_notify_tx_desc(tx_queue);
878 netif_tx_unlock(efx->net_dev);
879 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
880 EFX_WORKAROUND_10727(efx)) {
881 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
882 } else {
883 netif_err(efx, tx_err, efx->net_dev,
884 "channel %d unexpected TX event "
885 EFX_QWORD_FMT"\n", channel->channel,
886 EFX_QWORD_VAL(*event));
887 }
888
889 return tx_packets;
890 }
891
892 /* Detect errors included in the rx_evt_pkt_ok bit. */
efx_handle_rx_not_ok(struct efx_rx_queue * rx_queue,const efx_qword_t * event)893 static u16 efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
894 const efx_qword_t *event)
895 {
896 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
897 struct efx_nic *efx = rx_queue->efx;
898 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
899 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
900 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
901 bool rx_ev_other_err, rx_ev_pause_frm;
902 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
903 unsigned rx_ev_pkt_type;
904
905 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
906 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
907 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
908 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
909 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
910 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
911 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
912 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
913 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
914 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
915 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
916 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
917 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
918 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
919 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
920
921 /* Every error apart from tobe_disc and pause_frm */
922 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
923 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
924 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
925
926 /* Count errors that are not in MAC stats. Ignore expected
927 * checksum errors during self-test. */
928 if (rx_ev_frm_trunc)
929 ++channel->n_rx_frm_trunc;
930 else if (rx_ev_tobe_disc)
931 ++channel->n_rx_tobe_disc;
932 else if (!efx->loopback_selftest) {
933 if (rx_ev_ip_hdr_chksum_err)
934 ++channel->n_rx_ip_hdr_chksum_err;
935 else if (rx_ev_tcp_udp_chksum_err)
936 ++channel->n_rx_tcp_udp_chksum_err;
937 }
938
939 /* TOBE_DISC is expected on unicast mismatches; don't print out an
940 * error message. FRM_TRUNC indicates RXDP dropped the packet due
941 * to a FIFO overflow.
942 */
943 #ifdef DEBUG
944 if (rx_ev_other_err && net_ratelimit()) {
945 netif_dbg(efx, rx_err, efx->net_dev,
946 " RX queue %d unexpected RX event "
947 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
948 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
949 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
950 rx_ev_ip_hdr_chksum_err ?
951 " [IP_HDR_CHKSUM_ERR]" : "",
952 rx_ev_tcp_udp_chksum_err ?
953 " [TCP_UDP_CHKSUM_ERR]" : "",
954 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
955 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
956 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
957 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
958 rx_ev_pause_frm ? " [PAUSE]" : "");
959 }
960 #endif
961
962 /* The frame must be discarded if any of these are true. */
963 return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
964 rx_ev_tobe_disc | rx_ev_pause_frm) ?
965 EFX_RX_PKT_DISCARD : 0;
966 }
967
968 /* Handle receive events that are not in-order. */
969 static void
efx_handle_rx_bad_index(struct efx_rx_queue * rx_queue,unsigned index)970 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
971 {
972 struct efx_nic *efx = rx_queue->efx;
973 unsigned expected, dropped;
974
975 expected = rx_queue->removed_count & rx_queue->ptr_mask;
976 dropped = (index - expected) & rx_queue->ptr_mask;
977 netif_info(efx, rx_err, efx->net_dev,
978 "dropped %d events (index=%d expected=%d)\n",
979 dropped, index, expected);
980
981 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
982 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
983 }
984
985 /* Handle a packet received event
986 *
987 * The NIC gives a "discard" flag if it's a unicast packet with the
988 * wrong destination address
989 * Also "is multicast" and "matches multicast filter" flags can be used to
990 * discard non-matching multicast packets.
991 */
992 static void
efx_handle_rx_event(struct efx_channel * channel,const efx_qword_t * event)993 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
994 {
995 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
996 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
997 unsigned expected_ptr;
998 bool rx_ev_pkt_ok;
999 u16 flags;
1000 struct efx_rx_queue *rx_queue;
1001 struct efx_nic *efx = channel->efx;
1002
1003 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1004 return;
1005
1006 /* Basic packet information */
1007 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1008 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1009 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1010 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
1011 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
1012 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
1013 channel->channel);
1014
1015 rx_queue = efx_channel_get_rx_queue(channel);
1016
1017 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
1018 expected_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1019 if (unlikely(rx_ev_desc_ptr != expected_ptr))
1020 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
1021
1022 if (likely(rx_ev_pkt_ok)) {
1023 /* If packet is marked as OK and packet type is TCP/IP or
1024 * UDP/IP, then we can rely on the hardware checksum.
1025 */
1026 flags = (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
1027 rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP) ?
1028 EFX_RX_PKT_CSUMMED : 0;
1029 } else {
1030 flags = efx_handle_rx_not_ok(rx_queue, event);
1031 }
1032
1033 /* Detect multicast packets that didn't match the filter */
1034 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1035 if (rx_ev_mcast_pkt) {
1036 unsigned int rx_ev_mcast_hash_match =
1037 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1038
1039 if (unlikely(!rx_ev_mcast_hash_match)) {
1040 ++channel->n_rx_mcast_mismatch;
1041 flags |= EFX_RX_PKT_DISCARD;
1042 }
1043 }
1044
1045 channel->irq_mod_score += 2;
1046
1047 /* Handle received packet */
1048 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, flags);
1049 }
1050
1051 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1052 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1053 * of all transmit completions.
1054 */
1055 static void
efx_handle_tx_flush_done(struct efx_nic * efx,efx_qword_t * event)1056 efx_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1057 {
1058 struct efx_tx_queue *tx_queue;
1059 int qid;
1060
1061 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1062 if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1063 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1064 qid % EFX_TXQ_TYPES);
1065 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1066 efx_magic_event(tx_queue->channel,
1067 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1068 }
1069 }
1070 }
1071
1072 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1073 * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1074 * the RX queue back to the mask of RX queues in need of flushing.
1075 */
1076 static void
efx_handle_rx_flush_done(struct efx_nic * efx,efx_qword_t * event)1077 efx_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1078 {
1079 struct efx_channel *channel;
1080 struct efx_rx_queue *rx_queue;
1081 int qid;
1082 bool failed;
1083
1084 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1085 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1086 if (qid >= efx->n_channels)
1087 return;
1088 channel = efx_get_channel(efx, qid);
1089 if (!efx_channel_has_rx_queue(channel))
1090 return;
1091 rx_queue = efx_channel_get_rx_queue(channel);
1092
1093 if (failed) {
1094 netif_info(efx, hw, efx->net_dev,
1095 "RXQ %d flush retry\n", qid);
1096 rx_queue->flush_pending = true;
1097 atomic_inc(&efx->rxq_flush_pending);
1098 } else {
1099 efx_magic_event(efx_rx_queue_channel(rx_queue),
1100 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1101 }
1102 atomic_dec(&efx->rxq_flush_outstanding);
1103 if (efx_flush_wake(efx))
1104 wake_up(&efx->flush_wq);
1105 }
1106
1107 static void
efx_handle_drain_event(struct efx_channel * channel)1108 efx_handle_drain_event(struct efx_channel *channel)
1109 {
1110 struct efx_nic *efx = channel->efx;
1111
1112 WARN_ON(atomic_read(&efx->drain_pending) == 0);
1113 atomic_dec(&efx->drain_pending);
1114 if (efx_flush_wake(efx))
1115 wake_up(&efx->flush_wq);
1116 }
1117
1118 static void
efx_handle_generated_event(struct efx_channel * channel,efx_qword_t * event)1119 efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
1120 {
1121 struct efx_nic *efx = channel->efx;
1122 struct efx_rx_queue *rx_queue =
1123 efx_channel_has_rx_queue(channel) ?
1124 efx_channel_get_rx_queue(channel) : NULL;
1125 unsigned magic, code;
1126
1127 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1128 code = _EFX_CHANNEL_MAGIC_CODE(magic);
1129
1130 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1131 channel->event_test_cpu = raw_smp_processor_id();
1132 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1133 /* The queue must be empty, so we won't receive any rx
1134 * events, so efx_process_channel() won't refill the
1135 * queue. Refill it here */
1136 efx_fast_push_rx_descriptors(rx_queue);
1137 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1138 rx_queue->enabled = false;
1139 efx_handle_drain_event(channel);
1140 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1141 efx_handle_drain_event(channel);
1142 } else {
1143 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1144 "generated event "EFX_QWORD_FMT"\n",
1145 channel->channel, EFX_QWORD_VAL(*event));
1146 }
1147 }
1148
1149 static void
efx_handle_driver_event(struct efx_channel * channel,efx_qword_t * event)1150 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1151 {
1152 struct efx_nic *efx = channel->efx;
1153 unsigned int ev_sub_code;
1154 unsigned int ev_sub_data;
1155
1156 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1157 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1158
1159 switch (ev_sub_code) {
1160 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1161 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1162 channel->channel, ev_sub_data);
1163 efx_handle_tx_flush_done(efx, event);
1164 efx_sriov_tx_flush_done(efx, event);
1165 break;
1166 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1167 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1168 channel->channel, ev_sub_data);
1169 efx_handle_rx_flush_done(efx, event);
1170 efx_sriov_rx_flush_done(efx, event);
1171 break;
1172 case FSE_AZ_EVQ_INIT_DONE_EV:
1173 netif_dbg(efx, hw, efx->net_dev,
1174 "channel %d EVQ %d initialised\n",
1175 channel->channel, ev_sub_data);
1176 break;
1177 case FSE_AZ_SRM_UPD_DONE_EV:
1178 netif_vdbg(efx, hw, efx->net_dev,
1179 "channel %d SRAM update done\n", channel->channel);
1180 break;
1181 case FSE_AZ_WAKE_UP_EV:
1182 netif_vdbg(efx, hw, efx->net_dev,
1183 "channel %d RXQ %d wakeup event\n",
1184 channel->channel, ev_sub_data);
1185 break;
1186 case FSE_AZ_TIMER_EV:
1187 netif_vdbg(efx, hw, efx->net_dev,
1188 "channel %d RX queue %d timer expired\n",
1189 channel->channel, ev_sub_data);
1190 break;
1191 case FSE_AA_RX_RECOVER_EV:
1192 netif_err(efx, rx_err, efx->net_dev,
1193 "channel %d seen DRIVER RX_RESET event. "
1194 "Resetting.\n", channel->channel);
1195 atomic_inc(&efx->rx_reset);
1196 efx_schedule_reset(efx,
1197 EFX_WORKAROUND_6555(efx) ?
1198 RESET_TYPE_RX_RECOVERY :
1199 RESET_TYPE_DISABLE);
1200 break;
1201 case FSE_BZ_RX_DSC_ERROR_EV:
1202 if (ev_sub_data < EFX_VI_BASE) {
1203 netif_err(efx, rx_err, efx->net_dev,
1204 "RX DMA Q %d reports descriptor fetch error."
1205 " RX Q %d is disabled.\n", ev_sub_data,
1206 ev_sub_data);
1207 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1208 } else
1209 efx_sriov_desc_fetch_err(efx, ev_sub_data);
1210 break;
1211 case FSE_BZ_TX_DSC_ERROR_EV:
1212 if (ev_sub_data < EFX_VI_BASE) {
1213 netif_err(efx, tx_err, efx->net_dev,
1214 "TX DMA Q %d reports descriptor fetch error."
1215 " TX Q %d is disabled.\n", ev_sub_data,
1216 ev_sub_data);
1217 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1218 } else
1219 efx_sriov_desc_fetch_err(efx, ev_sub_data);
1220 break;
1221 default:
1222 netif_vdbg(efx, hw, efx->net_dev,
1223 "channel %d unknown driver event code %d "
1224 "data %04x\n", channel->channel, ev_sub_code,
1225 ev_sub_data);
1226 break;
1227 }
1228 }
1229
efx_nic_process_eventq(struct efx_channel * channel,int budget)1230 int efx_nic_process_eventq(struct efx_channel *channel, int budget)
1231 {
1232 struct efx_nic *efx = channel->efx;
1233 unsigned int read_ptr;
1234 efx_qword_t event, *p_event;
1235 int ev_code;
1236 int tx_packets = 0;
1237 int spent = 0;
1238
1239 read_ptr = channel->eventq_read_ptr;
1240
1241 for (;;) {
1242 p_event = efx_event(channel, read_ptr);
1243 event = *p_event;
1244
1245 if (!efx_event_present(&event))
1246 /* End of events */
1247 break;
1248
1249 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1250 "channel %d event is "EFX_QWORD_FMT"\n",
1251 channel->channel, EFX_QWORD_VAL(event));
1252
1253 /* Clear this event by marking it all ones */
1254 EFX_SET_QWORD(*p_event);
1255
1256 ++read_ptr;
1257
1258 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1259
1260 switch (ev_code) {
1261 case FSE_AZ_EV_CODE_RX_EV:
1262 efx_handle_rx_event(channel, &event);
1263 if (++spent == budget)
1264 goto out;
1265 break;
1266 case FSE_AZ_EV_CODE_TX_EV:
1267 tx_packets += efx_handle_tx_event(channel, &event);
1268 if (tx_packets > efx->txq_entries) {
1269 spent = budget;
1270 goto out;
1271 }
1272 break;
1273 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1274 efx_handle_generated_event(channel, &event);
1275 break;
1276 case FSE_AZ_EV_CODE_DRIVER_EV:
1277 efx_handle_driver_event(channel, &event);
1278 break;
1279 case FSE_CZ_EV_CODE_USER_EV:
1280 efx_sriov_event(channel, &event);
1281 break;
1282 case FSE_CZ_EV_CODE_MCDI_EV:
1283 efx_mcdi_process_event(channel, &event);
1284 break;
1285 case FSE_AZ_EV_CODE_GLOBAL_EV:
1286 if (efx->type->handle_global_event &&
1287 efx->type->handle_global_event(channel, &event))
1288 break;
1289 /* else fall through */
1290 default:
1291 netif_err(channel->efx, hw, channel->efx->net_dev,
1292 "channel %d unknown event type %d (data "
1293 EFX_QWORD_FMT ")\n", channel->channel,
1294 ev_code, EFX_QWORD_VAL(event));
1295 }
1296 }
1297
1298 out:
1299 channel->eventq_read_ptr = read_ptr;
1300 return spent;
1301 }
1302
1303 /* Check whether an event is present in the eventq at the current
1304 * read pointer. Only useful for self-test.
1305 */
efx_nic_event_present(struct efx_channel * channel)1306 bool efx_nic_event_present(struct efx_channel *channel)
1307 {
1308 return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
1309 }
1310
1311 /* Allocate buffer table entries for event queue */
efx_nic_probe_eventq(struct efx_channel * channel)1312 int efx_nic_probe_eventq(struct efx_channel *channel)
1313 {
1314 struct efx_nic *efx = channel->efx;
1315 unsigned entries;
1316
1317 entries = channel->eventq_mask + 1;
1318 return efx_alloc_special_buffer(efx, &channel->eventq,
1319 entries * sizeof(efx_qword_t));
1320 }
1321
efx_nic_init_eventq(struct efx_channel * channel)1322 void efx_nic_init_eventq(struct efx_channel *channel)
1323 {
1324 efx_oword_t reg;
1325 struct efx_nic *efx = channel->efx;
1326
1327 netif_dbg(efx, hw, efx->net_dev,
1328 "channel %d event queue in special buffers %d-%d\n",
1329 channel->channel, channel->eventq.index,
1330 channel->eventq.index + channel->eventq.entries - 1);
1331
1332 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1333 EFX_POPULATE_OWORD_3(reg,
1334 FRF_CZ_TIMER_Q_EN, 1,
1335 FRF_CZ_HOST_NOTIFY_MODE, 0,
1336 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1337 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel);
1338 }
1339
1340 /* Pin event queue buffer */
1341 efx_init_special_buffer(efx, &channel->eventq);
1342
1343 /* Fill event queue with all ones (i.e. empty events) */
1344 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1345
1346 /* Push event queue to card */
1347 EFX_POPULATE_OWORD_3(reg,
1348 FRF_AZ_EVQ_EN, 1,
1349 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1350 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1351 efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base,
1352 channel->channel);
1353
1354 efx->type->push_irq_moderation(channel);
1355 }
1356
efx_nic_fini_eventq(struct efx_channel * channel)1357 void efx_nic_fini_eventq(struct efx_channel *channel)
1358 {
1359 efx_oword_t reg;
1360 struct efx_nic *efx = channel->efx;
1361
1362 /* Remove event queue from card */
1363 EFX_ZERO_OWORD(reg);
1364 efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base,
1365 channel->channel);
1366 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1367 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel);
1368
1369 /* Unpin event queue */
1370 efx_fini_special_buffer(efx, &channel->eventq);
1371 }
1372
1373 /* Free buffers backing event queue */
efx_nic_remove_eventq(struct efx_channel * channel)1374 void efx_nic_remove_eventq(struct efx_channel *channel)
1375 {
1376 efx_free_special_buffer(channel->efx, &channel->eventq);
1377 }
1378
1379
efx_nic_event_test_start(struct efx_channel * channel)1380 void efx_nic_event_test_start(struct efx_channel *channel)
1381 {
1382 channel->event_test_cpu = -1;
1383 smp_wmb();
1384 efx_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1385 }
1386
efx_nic_generate_fill_event(struct efx_rx_queue * rx_queue)1387 void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
1388 {
1389 efx_magic_event(efx_rx_queue_channel(rx_queue),
1390 EFX_CHANNEL_MAGIC_FILL(rx_queue));
1391 }
1392
1393 /**************************************************************************
1394 *
1395 * Hardware interrupts
1396 * The hardware interrupt handler does very little work; all the event
1397 * queue processing is carried out by per-channel tasklets.
1398 *
1399 **************************************************************************/
1400
1401 /* Enable/disable/generate interrupts */
efx_nic_interrupts(struct efx_nic * efx,bool enabled,bool force)1402 static inline void efx_nic_interrupts(struct efx_nic *efx,
1403 bool enabled, bool force)
1404 {
1405 efx_oword_t int_en_reg_ker;
1406
1407 EFX_POPULATE_OWORD_3(int_en_reg_ker,
1408 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1409 FRF_AZ_KER_INT_KER, force,
1410 FRF_AZ_DRV_INT_EN_KER, enabled);
1411 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1412 }
1413
efx_nic_enable_interrupts(struct efx_nic * efx)1414 void efx_nic_enable_interrupts(struct efx_nic *efx)
1415 {
1416 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1417 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1418
1419 efx_nic_interrupts(efx, true, false);
1420 }
1421
efx_nic_disable_interrupts(struct efx_nic * efx)1422 void efx_nic_disable_interrupts(struct efx_nic *efx)
1423 {
1424 /* Disable interrupts */
1425 efx_nic_interrupts(efx, false, false);
1426 }
1427
1428 /* Generate a test interrupt
1429 * Interrupt must already have been enabled, otherwise nasty things
1430 * may happen.
1431 */
efx_nic_irq_test_start(struct efx_nic * efx)1432 void efx_nic_irq_test_start(struct efx_nic *efx)
1433 {
1434 efx->last_irq_cpu = -1;
1435 smp_wmb();
1436 efx_nic_interrupts(efx, true, true);
1437 }
1438
1439 /* Process a fatal interrupt
1440 * Disable bus mastering ASAP and schedule a reset
1441 */
efx_nic_fatal_interrupt(struct efx_nic * efx)1442 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1443 {
1444 struct falcon_nic_data *nic_data = efx->nic_data;
1445 efx_oword_t *int_ker = efx->irq_status.addr;
1446 efx_oword_t fatal_intr;
1447 int error, mem_perr;
1448
1449 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1450 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1451
1452 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1453 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1454 EFX_OWORD_VAL(fatal_intr),
1455 error ? "disabling bus mastering" : "no recognised error");
1456
1457 /* If this is a memory parity error dump which blocks are offending */
1458 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1459 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1460 if (mem_perr) {
1461 efx_oword_t reg;
1462 efx_reado(efx, ®, FR_AZ_MEM_STAT);
1463 netif_err(efx, hw, efx->net_dev,
1464 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1465 EFX_OWORD_VAL(reg));
1466 }
1467
1468 /* Disable both devices */
1469 pci_clear_master(efx->pci_dev);
1470 if (efx_nic_is_dual_func(efx))
1471 pci_clear_master(nic_data->pci_dev2);
1472 efx_nic_disable_interrupts(efx);
1473
1474 /* Count errors and reset or disable the NIC accordingly */
1475 if (efx->int_error_count == 0 ||
1476 time_after(jiffies, efx->int_error_expire)) {
1477 efx->int_error_count = 0;
1478 efx->int_error_expire =
1479 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1480 }
1481 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1482 netif_err(efx, hw, efx->net_dev,
1483 "SYSTEM ERROR - reset scheduled\n");
1484 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1485 } else {
1486 netif_err(efx, hw, efx->net_dev,
1487 "SYSTEM ERROR - max number of errors seen."
1488 "NIC will be disabled\n");
1489 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1490 }
1491
1492 return IRQ_HANDLED;
1493 }
1494
1495 /* Handle a legacy interrupt
1496 * Acknowledges the interrupt and schedule event queue processing.
1497 */
efx_legacy_interrupt(int irq,void * dev_id)1498 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1499 {
1500 struct efx_nic *efx = dev_id;
1501 efx_oword_t *int_ker = efx->irq_status.addr;
1502 irqreturn_t result = IRQ_NONE;
1503 struct efx_channel *channel;
1504 efx_dword_t reg;
1505 u32 queues;
1506 int syserr;
1507
1508 /* Could this be ours? If interrupts are disabled then the
1509 * channel state may not be valid.
1510 */
1511 if (!efx->legacy_irq_enabled)
1512 return result;
1513
1514 /* Read the ISR which also ACKs the interrupts */
1515 efx_readd(efx, ®, FR_BZ_INT_ISR0);
1516 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1517
1518 /* Handle non-event-queue sources */
1519 if (queues & (1U << efx->irq_level)) {
1520 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1521 if (unlikely(syserr))
1522 return efx_nic_fatal_interrupt(efx);
1523 efx->last_irq_cpu = raw_smp_processor_id();
1524 }
1525
1526 if (queues != 0) {
1527 if (EFX_WORKAROUND_15783(efx))
1528 efx->irq_zero_count = 0;
1529
1530 /* Schedule processing of any interrupting queues */
1531 efx_for_each_channel(channel, efx) {
1532 if (queues & 1)
1533 efx_schedule_channel_irq(channel);
1534 queues >>= 1;
1535 }
1536 result = IRQ_HANDLED;
1537
1538 } else if (EFX_WORKAROUND_15783(efx)) {
1539 efx_qword_t *event;
1540
1541 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1542 * because this might be a shared interrupt. */
1543 if (efx->irq_zero_count++ == 0)
1544 result = IRQ_HANDLED;
1545
1546 /* Ensure we schedule or rearm all event queues */
1547 efx_for_each_channel(channel, efx) {
1548 event = efx_event(channel, channel->eventq_read_ptr);
1549 if (efx_event_present(event))
1550 efx_schedule_channel_irq(channel);
1551 else
1552 efx_nic_eventq_read_ack(channel);
1553 }
1554 }
1555
1556 if (result == IRQ_HANDLED)
1557 netif_vdbg(efx, intr, efx->net_dev,
1558 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1559 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1560
1561 return result;
1562 }
1563
1564 /* Handle an MSI interrupt
1565 *
1566 * Handle an MSI hardware interrupt. This routine schedules event
1567 * queue processing. No interrupt acknowledgement cycle is necessary.
1568 * Also, we never need to check that the interrupt is for us, since
1569 * MSI interrupts cannot be shared.
1570 */
efx_msi_interrupt(int irq,void * dev_id)1571 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1572 {
1573 struct efx_channel *channel = *(struct efx_channel **)dev_id;
1574 struct efx_nic *efx = channel->efx;
1575 efx_oword_t *int_ker = efx->irq_status.addr;
1576 int syserr;
1577
1578 netif_vdbg(efx, intr, efx->net_dev,
1579 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1580 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1581
1582 /* Handle non-event-queue sources */
1583 if (channel->channel == efx->irq_level) {
1584 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1585 if (unlikely(syserr))
1586 return efx_nic_fatal_interrupt(efx);
1587 efx->last_irq_cpu = raw_smp_processor_id();
1588 }
1589
1590 /* Schedule processing of the channel */
1591 efx_schedule_channel_irq(channel);
1592
1593 return IRQ_HANDLED;
1594 }
1595
1596
1597 /* Setup RSS indirection table.
1598 * This maps from the hash value of the packet to RXQ
1599 */
efx_nic_push_rx_indir_table(struct efx_nic * efx)1600 void efx_nic_push_rx_indir_table(struct efx_nic *efx)
1601 {
1602 size_t i = 0;
1603 efx_dword_t dword;
1604
1605 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1606 return;
1607
1608 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1609 FR_BZ_RX_INDIRECTION_TBL_ROWS);
1610
1611 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1612 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1613 efx->rx_indir_table[i]);
1614 efx_writed_table(efx, &dword, FR_BZ_RX_INDIRECTION_TBL, i);
1615 }
1616 }
1617
1618 /* Hook interrupt handler(s)
1619 * Try MSI and then legacy interrupts.
1620 */
efx_nic_init_interrupt(struct efx_nic * efx)1621 int efx_nic_init_interrupt(struct efx_nic *efx)
1622 {
1623 struct efx_channel *channel;
1624 int rc;
1625
1626 if (!EFX_INT_MODE_USE_MSI(efx)) {
1627 irq_handler_t handler;
1628 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1629 handler = efx_legacy_interrupt;
1630 else
1631 handler = falcon_legacy_interrupt_a1;
1632
1633 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1634 efx->name, efx);
1635 if (rc) {
1636 netif_err(efx, drv, efx->net_dev,
1637 "failed to hook legacy IRQ %d\n",
1638 efx->pci_dev->irq);
1639 goto fail1;
1640 }
1641 return 0;
1642 }
1643
1644 /* Hook MSI or MSI-X interrupt */
1645 efx_for_each_channel(channel, efx) {
1646 rc = request_irq(channel->irq, efx_msi_interrupt,
1647 IRQF_PROBE_SHARED, /* Not shared */
1648 efx->channel_name[channel->channel],
1649 &efx->channel[channel->channel]);
1650 if (rc) {
1651 netif_err(efx, drv, efx->net_dev,
1652 "failed to hook IRQ %d\n", channel->irq);
1653 goto fail2;
1654 }
1655 }
1656
1657 return 0;
1658
1659 fail2:
1660 efx_for_each_channel(channel, efx)
1661 free_irq(channel->irq, &efx->channel[channel->channel]);
1662 fail1:
1663 return rc;
1664 }
1665
efx_nic_fini_interrupt(struct efx_nic * efx)1666 void efx_nic_fini_interrupt(struct efx_nic *efx)
1667 {
1668 struct efx_channel *channel;
1669 efx_oword_t reg;
1670
1671 /* Disable MSI/MSI-X interrupts */
1672 efx_for_each_channel(channel, efx) {
1673 if (channel->irq)
1674 free_irq(channel->irq, &efx->channel[channel->channel]);
1675 }
1676
1677 /* ACK legacy interrupt */
1678 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1679 efx_reado(efx, ®, FR_BZ_INT_ISR0);
1680 else
1681 falcon_irq_ack_a1(efx);
1682
1683 /* Disable legacy interrupt */
1684 if (efx->legacy_irq)
1685 free_irq(efx->legacy_irq, efx);
1686 }
1687
1688 /* Looks at available SRAM resources and works out how many queues we
1689 * can support, and where things like descriptor caches should live.
1690 *
1691 * SRAM is split up as follows:
1692 * 0 buftbl entries for channels
1693 * efx->vf_buftbl_base buftbl entries for SR-IOV
1694 * efx->rx_dc_base RX descriptor caches
1695 * efx->tx_dc_base TX descriptor caches
1696 */
efx_nic_dimension_resources(struct efx_nic * efx,unsigned sram_lim_qw)1697 void efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1698 {
1699 unsigned vi_count, buftbl_min;
1700
1701 /* Account for the buffer table entries backing the datapath channels
1702 * and the descriptor caches for those channels.
1703 */
1704 buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1705 efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1706 efx->n_channels * EFX_MAX_EVQ_SIZE)
1707 * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1708 vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1709
1710 #ifdef CONFIG_SFC_SRIOV
1711 if (efx_sriov_wanted(efx)) {
1712 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit;
1713
1714 efx->vf_buftbl_base = buftbl_min;
1715
1716 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1717 vi_count = max(vi_count, EFX_VI_BASE);
1718 buftbl_free = (sram_lim_qw - buftbl_min -
1719 vi_count * vi_dc_entries);
1720
1721 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) *
1722 efx_vf_size(efx));
1723 vf_limit = min(buftbl_free / entries_per_vf,
1724 (1024U - EFX_VI_BASE) >> efx->vi_scale);
1725
1726 if (efx->vf_count > vf_limit) {
1727 netif_err(efx, probe, efx->net_dev,
1728 "Reducing VF count from from %d to %d\n",
1729 efx->vf_count, vf_limit);
1730 efx->vf_count = vf_limit;
1731 }
1732 vi_count += efx->vf_count * efx_vf_size(efx);
1733 }
1734 #endif
1735
1736 efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1737 efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1738 }
1739
efx_nic_fpga_ver(struct efx_nic * efx)1740 u32 efx_nic_fpga_ver(struct efx_nic *efx)
1741 {
1742 efx_oword_t altera_build;
1743 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1744 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1745 }
1746
efx_nic_init_common(struct efx_nic * efx)1747 void efx_nic_init_common(struct efx_nic *efx)
1748 {
1749 efx_oword_t temp;
1750
1751 /* Set positions of descriptor caches in SRAM. */
1752 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1753 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1754 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1755 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1756
1757 /* Set TX descriptor cache size. */
1758 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1759 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1760 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1761
1762 /* Set RX descriptor cache size. Set low watermark to size-8, as
1763 * this allows most efficient prefetching.
1764 */
1765 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1766 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1767 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1768 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1769 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1770
1771 /* Program INT_KER address */
1772 EFX_POPULATE_OWORD_2(temp,
1773 FRF_AZ_NORM_INT_VEC_DIS_KER,
1774 EFX_INT_MODE_USE_MSI(efx),
1775 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1776 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1777
1778 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1779 /* Use an interrupt level unused by event queues */
1780 efx->irq_level = 0x1f;
1781 else
1782 /* Use a valid MSI-X vector */
1783 efx->irq_level = 0;
1784
1785 /* Enable all the genuinely fatal interrupts. (They are still
1786 * masked by the overall interrupt mask, controlled by
1787 * falcon_interrupts()).
1788 *
1789 * Note: All other fatal interrupts are enabled
1790 */
1791 EFX_POPULATE_OWORD_3(temp,
1792 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1793 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1794 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1795 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1796 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1797 EFX_INVERT_OWORD(temp);
1798 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1799
1800 efx_nic_push_rx_indir_table(efx);
1801
1802 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1803 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1804 */
1805 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1806 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1807 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1808 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1809 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1810 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1811 /* Enable SW_EV to inherit in char driver - assume harmless here */
1812 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1813 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1814 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1815 /* Disable hardware watchdog which can misfire */
1816 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1817 /* Squash TX of packets of 16 bytes or less */
1818 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1819 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1820 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1821
1822 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1823 EFX_POPULATE_OWORD_4(temp,
1824 /* Default values */
1825 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1826 FRF_BZ_TX_PACE_SB_AF, 0xb,
1827 FRF_BZ_TX_PACE_FB_BASE, 0,
1828 /* Allow large pace values in the
1829 * fast bin. */
1830 FRF_BZ_TX_PACE_BIN_TH,
1831 FFE_BZ_TX_PACE_RESERVED);
1832 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1833 }
1834 }
1835
1836 /* Register dump */
1837
1838 #define REGISTER_REVISION_A 1
1839 #define REGISTER_REVISION_B 2
1840 #define REGISTER_REVISION_C 3
1841 #define REGISTER_REVISION_Z 3 /* latest revision */
1842
1843 struct efx_nic_reg {
1844 u32 offset:24;
1845 u32 min_revision:2, max_revision:2;
1846 };
1847
1848 #define REGISTER(name, min_rev, max_rev) { \
1849 FR_ ## min_rev ## max_rev ## _ ## name, \
1850 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \
1851 }
1852 #define REGISTER_AA(name) REGISTER(name, A, A)
1853 #define REGISTER_AB(name) REGISTER(name, A, B)
1854 #define REGISTER_AZ(name) REGISTER(name, A, Z)
1855 #define REGISTER_BB(name) REGISTER(name, B, B)
1856 #define REGISTER_BZ(name) REGISTER(name, B, Z)
1857 #define REGISTER_CZ(name) REGISTER(name, C, Z)
1858
1859 static const struct efx_nic_reg efx_nic_regs[] = {
1860 REGISTER_AZ(ADR_REGION),
1861 REGISTER_AZ(INT_EN_KER),
1862 REGISTER_BZ(INT_EN_CHAR),
1863 REGISTER_AZ(INT_ADR_KER),
1864 REGISTER_BZ(INT_ADR_CHAR),
1865 /* INT_ACK_KER is WO */
1866 /* INT_ISR0 is RC */
1867 REGISTER_AZ(HW_INIT),
1868 REGISTER_CZ(USR_EV_CFG),
1869 REGISTER_AB(EE_SPI_HCMD),
1870 REGISTER_AB(EE_SPI_HADR),
1871 REGISTER_AB(EE_SPI_HDATA),
1872 REGISTER_AB(EE_BASE_PAGE),
1873 REGISTER_AB(EE_VPD_CFG0),
1874 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
1875 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
1876 /* PCIE_CORE_INDIRECT is indirect */
1877 REGISTER_AB(NIC_STAT),
1878 REGISTER_AB(GPIO_CTL),
1879 REGISTER_AB(GLB_CTL),
1880 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
1881 REGISTER_BZ(DP_CTRL),
1882 REGISTER_AZ(MEM_STAT),
1883 REGISTER_AZ(CS_DEBUG),
1884 REGISTER_AZ(ALTERA_BUILD),
1885 REGISTER_AZ(CSR_SPARE),
1886 REGISTER_AB(PCIE_SD_CTL0123),
1887 REGISTER_AB(PCIE_SD_CTL45),
1888 REGISTER_AB(PCIE_PCS_CTL_STAT),
1889 /* DEBUG_DATA_OUT is not used */
1890 /* DRV_EV is WO */
1891 REGISTER_AZ(EVQ_CTL),
1892 REGISTER_AZ(EVQ_CNT1),
1893 REGISTER_AZ(EVQ_CNT2),
1894 REGISTER_AZ(BUF_TBL_CFG),
1895 REGISTER_AZ(SRM_RX_DC_CFG),
1896 REGISTER_AZ(SRM_TX_DC_CFG),
1897 REGISTER_AZ(SRM_CFG),
1898 /* BUF_TBL_UPD is WO */
1899 REGISTER_AZ(SRM_UPD_EVQ),
1900 REGISTER_AZ(SRAM_PARITY),
1901 REGISTER_AZ(RX_CFG),
1902 REGISTER_BZ(RX_FILTER_CTL),
1903 /* RX_FLUSH_DESCQ is WO */
1904 REGISTER_AZ(RX_DC_CFG),
1905 REGISTER_AZ(RX_DC_PF_WM),
1906 REGISTER_BZ(RX_RSS_TKEY),
1907 /* RX_NODESC_DROP is RC */
1908 REGISTER_AA(RX_SELF_RST),
1909 /* RX_DEBUG, RX_PUSH_DROP are not used */
1910 REGISTER_CZ(RX_RSS_IPV6_REG1),
1911 REGISTER_CZ(RX_RSS_IPV6_REG2),
1912 REGISTER_CZ(RX_RSS_IPV6_REG3),
1913 /* TX_FLUSH_DESCQ is WO */
1914 REGISTER_AZ(TX_DC_CFG),
1915 REGISTER_AA(TX_CHKSM_CFG),
1916 REGISTER_AZ(TX_CFG),
1917 /* TX_PUSH_DROP is not used */
1918 REGISTER_AZ(TX_RESERVED),
1919 REGISTER_BZ(TX_PACE),
1920 /* TX_PACE_DROP_QID is RC */
1921 REGISTER_BB(TX_VLAN),
1922 REGISTER_BZ(TX_IPFIL_PORTEN),
1923 REGISTER_AB(MD_TXD),
1924 REGISTER_AB(MD_RXD),
1925 REGISTER_AB(MD_CS),
1926 REGISTER_AB(MD_PHY_ADR),
1927 REGISTER_AB(MD_ID),
1928 /* MD_STAT is RC */
1929 REGISTER_AB(MAC_STAT_DMA),
1930 REGISTER_AB(MAC_CTRL),
1931 REGISTER_BB(GEN_MODE),
1932 REGISTER_AB(MAC_MC_HASH_REG0),
1933 REGISTER_AB(MAC_MC_HASH_REG1),
1934 REGISTER_AB(GM_CFG1),
1935 REGISTER_AB(GM_CFG2),
1936 /* GM_IPG and GM_HD are not used */
1937 REGISTER_AB(GM_MAX_FLEN),
1938 /* GM_TEST is not used */
1939 REGISTER_AB(GM_ADR1),
1940 REGISTER_AB(GM_ADR2),
1941 REGISTER_AB(GMF_CFG0),
1942 REGISTER_AB(GMF_CFG1),
1943 REGISTER_AB(GMF_CFG2),
1944 REGISTER_AB(GMF_CFG3),
1945 REGISTER_AB(GMF_CFG4),
1946 REGISTER_AB(GMF_CFG5),
1947 REGISTER_BB(TX_SRC_MAC_CTL),
1948 REGISTER_AB(XM_ADR_LO),
1949 REGISTER_AB(XM_ADR_HI),
1950 REGISTER_AB(XM_GLB_CFG),
1951 REGISTER_AB(XM_TX_CFG),
1952 REGISTER_AB(XM_RX_CFG),
1953 REGISTER_AB(XM_MGT_INT_MASK),
1954 REGISTER_AB(XM_FC),
1955 REGISTER_AB(XM_PAUSE_TIME),
1956 REGISTER_AB(XM_TX_PARAM),
1957 REGISTER_AB(XM_RX_PARAM),
1958 /* XM_MGT_INT_MSK (note no 'A') is RC */
1959 REGISTER_AB(XX_PWR_RST),
1960 REGISTER_AB(XX_SD_CTL),
1961 REGISTER_AB(XX_TXDRV_CTL),
1962 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
1963 /* XX_CORE_STAT is partly RC */
1964 };
1965
1966 struct efx_nic_reg_table {
1967 u32 offset:24;
1968 u32 min_revision:2, max_revision:2;
1969 u32 step:6, rows:21;
1970 };
1971
1972 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
1973 offset, \
1974 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \
1975 step, rows \
1976 }
1977 #define REGISTER_TABLE(name, min_rev, max_rev) \
1978 REGISTER_TABLE_DIMENSIONS( \
1979 name, FR_ ## min_rev ## max_rev ## _ ## name, \
1980 min_rev, max_rev, \
1981 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
1982 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
1983 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
1984 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
1985 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
1986 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
1987 #define REGISTER_TABLE_BB_CZ(name) \
1988 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \
1989 FR_BZ_ ## name ## _STEP, \
1990 FR_BB_ ## name ## _ROWS), \
1991 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \
1992 FR_BZ_ ## name ## _STEP, \
1993 FR_CZ_ ## name ## _ROWS)
1994 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
1995
1996 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
1997 /* DRIVER is not used */
1998 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
1999 REGISTER_TABLE_BB(TX_IPFIL_TBL),
2000 REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
2001 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
2002 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
2003 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
2004 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
2005 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
2006 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
2007 /* We can't reasonably read all of the buffer table (up to 8MB!).
2008 * However this driver will only use a few entries. Reading
2009 * 1K entries allows for some expansion of queue count and
2010 * size before we need to change the version. */
2011 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
2012 A, A, 8, 1024),
2013 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
2014 B, Z, 8, 1024),
2015 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
2016 REGISTER_TABLE_BB_CZ(TIMER_TBL),
2017 REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
2018 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
2019 /* TX_FILTER_TBL0 is huge and not used by this driver */
2020 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
2021 REGISTER_TABLE_CZ(MC_TREG_SMEM),
2022 /* MSIX_PBA_TABLE is not mapped */
2023 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
2024 REGISTER_TABLE_BZ(RX_FILTER_TBL0),
2025 };
2026
efx_nic_get_regs_len(struct efx_nic * efx)2027 size_t efx_nic_get_regs_len(struct efx_nic *efx)
2028 {
2029 const struct efx_nic_reg *reg;
2030 const struct efx_nic_reg_table *table;
2031 size_t len = 0;
2032
2033 for (reg = efx_nic_regs;
2034 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
2035 reg++)
2036 if (efx->type->revision >= reg->min_revision &&
2037 efx->type->revision <= reg->max_revision)
2038 len += sizeof(efx_oword_t);
2039
2040 for (table = efx_nic_reg_tables;
2041 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
2042 table++)
2043 if (efx->type->revision >= table->min_revision &&
2044 efx->type->revision <= table->max_revision)
2045 len += table->rows * min_t(size_t, table->step, 16);
2046
2047 return len;
2048 }
2049
efx_nic_get_regs(struct efx_nic * efx,void * buf)2050 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
2051 {
2052 const struct efx_nic_reg *reg;
2053 const struct efx_nic_reg_table *table;
2054
2055 for (reg = efx_nic_regs;
2056 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
2057 reg++) {
2058 if (efx->type->revision >= reg->min_revision &&
2059 efx->type->revision <= reg->max_revision) {
2060 efx_reado(efx, (efx_oword_t *)buf, reg->offset);
2061 buf += sizeof(efx_oword_t);
2062 }
2063 }
2064
2065 for (table = efx_nic_reg_tables;
2066 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
2067 table++) {
2068 size_t size, i;
2069
2070 if (!(efx->type->revision >= table->min_revision &&
2071 efx->type->revision <= table->max_revision))
2072 continue;
2073
2074 size = min_t(size_t, table->step, 16);
2075
2076 for (i = 0; i < table->rows; i++) {
2077 switch (table->step) {
2078 case 4: /* 32-bit register or SRAM */
2079 efx_readd_table(efx, buf, table->offset, i);
2080 break;
2081 case 8: /* 64-bit SRAM */
2082 efx_sram_readq(efx,
2083 efx->membase + table->offset,
2084 buf, i);
2085 break;
2086 case 16: /* 128-bit register */
2087 efx_reado_table(efx, buf, table->offset, i);
2088 break;
2089 case 32: /* 128-bit register, interleaved */
2090 efx_reado_table(efx, buf, table->offset, 2 * i);
2091 break;
2092 default:
2093 WARN_ON(1);
2094 return;
2095 }
2096 buf += size;
2097 }
2098 }
2099 }
2100