1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #include "e1000.h"
5 
6 /**
7  *  e1000e_get_bus_info_pcie - Get PCIe bus information
8  *  @hw: pointer to the HW structure
9  *
10  *  Determines and stores the system bus information for a particular
11  *  network interface.  The following bus information is determined and stored:
12  *  bus speed, bus width, type (PCIe), and PCIe function.
13  **/
e1000e_get_bus_info_pcie(struct e1000_hw * hw)14 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
15 {
16 	struct e1000_mac_info *mac = &hw->mac;
17 	struct e1000_bus_info *bus = &hw->bus;
18 	struct e1000_adapter *adapter = hw->adapter;
19 	u16 pcie_link_status, cap_offset;
20 
21 	cap_offset = adapter->pdev->pcie_cap;
22 	if (!cap_offset) {
23 		bus->width = e1000_bus_width_unknown;
24 	} else {
25 		pci_read_config_word(adapter->pdev,
26 				     cap_offset + PCIE_LINK_STATUS,
27 				     &pcie_link_status);
28 		bus->width = (enum e1000_bus_width)((pcie_link_status &
29 						     PCIE_LINK_WIDTH_MASK) >>
30 						    PCIE_LINK_WIDTH_SHIFT);
31 	}
32 
33 	mac->ops.set_lan_id(hw);
34 
35 	return 0;
36 }
37 
38 /**
39  *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
40  *
41  *  @hw: pointer to the HW structure
42  *
43  *  Determines the LAN function id by reading memory-mapped registers
44  *  and swaps the port value if requested.
45  **/
e1000_set_lan_id_multi_port_pcie(struct e1000_hw * hw)46 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
47 {
48 	struct e1000_bus_info *bus = &hw->bus;
49 	u32 reg;
50 
51 	/* The status register reports the correct function number
52 	 * for the device regardless of function swap state.
53 	 */
54 	reg = er32(STATUS);
55 	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
56 }
57 
58 /**
59  *  e1000_set_lan_id_single_port - Set LAN id for a single port device
60  *  @hw: pointer to the HW structure
61  *
62  *  Sets the LAN function id to zero for a single port device.
63  **/
e1000_set_lan_id_single_port(struct e1000_hw * hw)64 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
65 {
66 	struct e1000_bus_info *bus = &hw->bus;
67 
68 	bus->func = 0;
69 }
70 
71 /**
72  *  e1000_clear_vfta_generic - Clear VLAN filter table
73  *  @hw: pointer to the HW structure
74  *
75  *  Clears the register array which contains the VLAN filter table by
76  *  setting all the values to 0.
77  **/
e1000_clear_vfta_generic(struct e1000_hw * hw)78 void e1000_clear_vfta_generic(struct e1000_hw *hw)
79 {
80 	u32 offset;
81 
82 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
83 		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
84 		e1e_flush();
85 	}
86 }
87 
88 /**
89  *  e1000_write_vfta_generic - Write value to VLAN filter table
90  *  @hw: pointer to the HW structure
91  *  @offset: register offset in VLAN filter table
92  *  @value: register value written to VLAN filter table
93  *
94  *  Writes value at the given offset in the register array which stores
95  *  the VLAN filter table.
96  **/
e1000_write_vfta_generic(struct e1000_hw * hw,u32 offset,u32 value)97 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
98 {
99 	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
100 	e1e_flush();
101 }
102 
103 /**
104  *  e1000e_init_rx_addrs - Initialize receive address's
105  *  @hw: pointer to the HW structure
106  *  @rar_count: receive address registers
107  *
108  *  Setup the receive address registers by setting the base receive address
109  *  register to the devices MAC address and clearing all the other receive
110  *  address registers to 0.
111  **/
e1000e_init_rx_addrs(struct e1000_hw * hw,u16 rar_count)112 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
113 {
114 	u32 i;
115 	u8 mac_addr[ETH_ALEN] = { 0 };
116 
117 	/* Setup the receive address */
118 	e_dbg("Programming MAC Address into RAR[0]\n");
119 
120 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
121 
122 	/* Zero out the other (rar_entry_count - 1) receive addresses */
123 	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
124 	for (i = 1; i < rar_count; i++)
125 		hw->mac.ops.rar_set(hw, mac_addr, i);
126 }
127 
128 /**
129  *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
130  *  @hw: pointer to the HW structure
131  *
132  *  Checks the nvm for an alternate MAC address.  An alternate MAC address
133  *  can be setup by pre-boot software and must be treated like a permanent
134  *  address and must override the actual permanent MAC address. If an
135  *  alternate MAC address is found it is programmed into RAR0, replacing
136  *  the permanent address that was installed into RAR0 by the Si on reset.
137  *  This function will return SUCCESS unless it encounters an error while
138  *  reading the EEPROM.
139  **/
e1000_check_alt_mac_addr_generic(struct e1000_hw * hw)140 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
141 {
142 	u32 i;
143 	s32 ret_val;
144 	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
145 	u8 alt_mac_addr[ETH_ALEN];
146 
147 	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
148 	if (ret_val)
149 		return ret_val;
150 
151 	/* not supported on 82573 */
152 	if (hw->mac.type == e1000_82573)
153 		return 0;
154 
155 	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
156 				 &nvm_alt_mac_addr_offset);
157 	if (ret_val) {
158 		e_dbg("NVM Read Error\n");
159 		return ret_val;
160 	}
161 
162 	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
163 	    (nvm_alt_mac_addr_offset == 0x0000))
164 		/* There is no Alternate MAC Address */
165 		return 0;
166 
167 	if (hw->bus.func == E1000_FUNC_1)
168 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
169 	for (i = 0; i < ETH_ALEN; i += 2) {
170 		offset = nvm_alt_mac_addr_offset + (i >> 1);
171 		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
172 		if (ret_val) {
173 			e_dbg("NVM Read Error\n");
174 			return ret_val;
175 		}
176 
177 		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
178 		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
179 	}
180 
181 	/* if multicast bit is set, the alternate address will not be used */
182 	if (is_multicast_ether_addr(alt_mac_addr)) {
183 		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
184 		return 0;
185 	}
186 
187 	/* We have a valid alternate MAC address, and we want to treat it the
188 	 * same as the normal permanent MAC address stored by the HW into the
189 	 * RAR. Do this by mapping this address into RAR0.
190 	 */
191 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
192 
193 	return 0;
194 }
195 
e1000e_rar_get_count_generic(struct e1000_hw * hw)196 u32 e1000e_rar_get_count_generic(struct e1000_hw *hw)
197 {
198 	return hw->mac.rar_entry_count;
199 }
200 
201 /**
202  *  e1000e_rar_set_generic - Set receive address register
203  *  @hw: pointer to the HW structure
204  *  @addr: pointer to the receive address
205  *  @index: receive address array register
206  *
207  *  Sets the receive address array register at index to the address passed
208  *  in by addr.
209  **/
e1000e_rar_set_generic(struct e1000_hw * hw,u8 * addr,u32 index)210 int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
211 {
212 	u32 rar_low, rar_high;
213 
214 	/* HW expects these in little endian so we reverse the byte order
215 	 * from network order (big endian) to little endian
216 	 */
217 	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
218 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
219 
220 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
221 
222 	/* If MAC address zero, no need to set the AV bit */
223 	if (rar_low || rar_high)
224 		rar_high |= E1000_RAH_AV;
225 
226 	/* Some bridges will combine consecutive 32-bit writes into
227 	 * a single burst write, which will malfunction on some parts.
228 	 * The flushes avoid this.
229 	 */
230 	ew32(RAL(index), rar_low);
231 	e1e_flush();
232 	ew32(RAH(index), rar_high);
233 	e1e_flush();
234 
235 	return 0;
236 }
237 
238 /**
239  *  e1000_hash_mc_addr - Generate a multicast hash value
240  *  @hw: pointer to the HW structure
241  *  @mc_addr: pointer to a multicast address
242  *
243  *  Generates a multicast address hash value which is used to determine
244  *  the multicast filter table array address and new table value.
245  **/
e1000_hash_mc_addr(struct e1000_hw * hw,u8 * mc_addr)246 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
247 {
248 	u32 hash_value, hash_mask;
249 	u8 bit_shift = 0;
250 
251 	/* Register count multiplied by bits per register */
252 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
253 
254 	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts
255 	 * where 0xFF would still fall within the hash mask.
256 	 */
257 	while (hash_mask >> bit_shift != 0xFF)
258 		bit_shift++;
259 
260 	/* The portion of the address that is used for the hash table
261 	 * is determined by the mc_filter_type setting.
262 	 * The algorithm is such that there is a total of 8 bits of shifting.
263 	 * The bit_shift for a mc_filter_type of 0 represents the number of
264 	 * left-shifts where the MSB of mc_addr[5] would still fall within
265 	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
266 	 * of 8 bits of shifting, then mc_addr[4] will shift right the
267 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
268 	 * cases are a variation of this algorithm...essentially raising the
269 	 * number of bits to shift mc_addr[5] left, while still keeping the
270 	 * 8-bit shifting total.
271 	 *
272 	 * For example, given the following Destination MAC Address and an
273 	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
274 	 * we can see that the bit_shift for case 0 is 4.  These are the hash
275 	 * values resulting from each mc_filter_type...
276 	 * [0] [1] [2] [3] [4] [5]
277 	 * 01  AA  00  12  34  56
278 	 * LSB           MSB
279 	 *
280 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
281 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
282 	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
283 	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
284 	 */
285 	switch (hw->mac.mc_filter_type) {
286 	default:
287 	case 0:
288 		break;
289 	case 1:
290 		bit_shift += 1;
291 		break;
292 	case 2:
293 		bit_shift += 2;
294 		break;
295 	case 3:
296 		bit_shift += 4;
297 		break;
298 	}
299 
300 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
301 				   (((u16)mc_addr[5]) << bit_shift)));
302 
303 	return hash_value;
304 }
305 
306 /**
307  *  e1000e_update_mc_addr_list_generic - Update Multicast addresses
308  *  @hw: pointer to the HW structure
309  *  @mc_addr_list: array of multicast addresses to program
310  *  @mc_addr_count: number of multicast addresses to program
311  *
312  *  Updates entire Multicast Table Array.
313  *  The caller must have a packed mc_addr_list of multicast addresses.
314  **/
e1000e_update_mc_addr_list_generic(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)315 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
316 					u8 *mc_addr_list, u32 mc_addr_count)
317 {
318 	u32 hash_value, hash_bit, hash_reg;
319 	int i;
320 
321 	/* clear mta_shadow */
322 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
323 
324 	/* update mta_shadow from mc_addr_list */
325 	for (i = 0; (u32)i < mc_addr_count; i++) {
326 		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
327 
328 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
329 		hash_bit = hash_value & 0x1F;
330 
331 		hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
332 		mc_addr_list += (ETH_ALEN);
333 	}
334 
335 	/* replace the entire MTA table */
336 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
337 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
338 	e1e_flush();
339 }
340 
341 /**
342  *  e1000e_clear_hw_cntrs_base - Clear base hardware counters
343  *  @hw: pointer to the HW structure
344  *
345  *  Clears the base hardware counters by reading the counter registers.
346  **/
e1000e_clear_hw_cntrs_base(struct e1000_hw * hw)347 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
348 {
349 	er32(CRCERRS);
350 	er32(SYMERRS);
351 	er32(MPC);
352 	er32(SCC);
353 	er32(ECOL);
354 	er32(MCC);
355 	er32(LATECOL);
356 	er32(COLC);
357 	er32(DC);
358 	er32(SEC);
359 	er32(RLEC);
360 	er32(XONRXC);
361 	er32(XONTXC);
362 	er32(XOFFRXC);
363 	er32(XOFFTXC);
364 	er32(FCRUC);
365 	er32(GPRC);
366 	er32(BPRC);
367 	er32(MPRC);
368 	er32(GPTC);
369 	er32(GORCL);
370 	er32(GORCH);
371 	er32(GOTCL);
372 	er32(GOTCH);
373 	er32(RNBC);
374 	er32(RUC);
375 	er32(RFC);
376 	er32(ROC);
377 	er32(RJC);
378 	er32(TORL);
379 	er32(TORH);
380 	er32(TOTL);
381 	er32(TOTH);
382 	er32(TPR);
383 	er32(TPT);
384 	er32(MPTC);
385 	er32(BPTC);
386 }
387 
388 /**
389  *  e1000e_check_for_copper_link - Check for link (Copper)
390  *  @hw: pointer to the HW structure
391  *
392  *  Checks to see of the link status of the hardware has changed.  If a
393  *  change in link status has been detected, then we read the PHY registers
394  *  to get the current speed/duplex if link exists.
395  **/
e1000e_check_for_copper_link(struct e1000_hw * hw)396 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
397 {
398 	struct e1000_mac_info *mac = &hw->mac;
399 	s32 ret_val;
400 	bool link;
401 
402 	/* We only want to go out to the PHY registers to see if Auto-Neg
403 	 * has completed and/or if our link status has changed.  The
404 	 * get_link_status flag is set upon receiving a Link Status
405 	 * Change or Rx Sequence Error interrupt.
406 	 */
407 	if (!mac->get_link_status)
408 		return 0;
409 	mac->get_link_status = false;
410 
411 	/* First we want to see if the MII Status Register reports
412 	 * link.  If so, then we want to get the current speed/duplex
413 	 * of the PHY.
414 	 */
415 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
416 	if (ret_val || !link)
417 		goto out;
418 
419 	/* Check if there was DownShift, must be checked
420 	 * immediately after link-up
421 	 */
422 	e1000e_check_downshift(hw);
423 
424 	/* If we are forcing speed/duplex, then we simply return since
425 	 * we have already determined whether we have link or not.
426 	 */
427 	if (!mac->autoneg)
428 		return -E1000_ERR_CONFIG;
429 
430 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
431 	 * of MAC speed/duplex configuration.  So we only need to
432 	 * configure Collision Distance in the MAC.
433 	 */
434 	mac->ops.config_collision_dist(hw);
435 
436 	/* Configure Flow Control now that Auto-Neg has completed.
437 	 * First, we need to restore the desired flow control
438 	 * settings because we may have had to re-autoneg with a
439 	 * different link partner.
440 	 */
441 	ret_val = e1000e_config_fc_after_link_up(hw);
442 	if (ret_val)
443 		e_dbg("Error configuring flow control\n");
444 
445 	return ret_val;
446 
447 out:
448 	mac->get_link_status = true;
449 	return ret_val;
450 }
451 
452 /**
453  *  e1000e_check_for_fiber_link - Check for link (Fiber)
454  *  @hw: pointer to the HW structure
455  *
456  *  Checks for link up on the hardware.  If link is not up and we have
457  *  a signal, then we need to force link up.
458  **/
e1000e_check_for_fiber_link(struct e1000_hw * hw)459 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
460 {
461 	struct e1000_mac_info *mac = &hw->mac;
462 	u32 rxcw;
463 	u32 ctrl;
464 	u32 status;
465 	s32 ret_val;
466 
467 	ctrl = er32(CTRL);
468 	status = er32(STATUS);
469 	rxcw = er32(RXCW);
470 
471 	/* If we don't have link (auto-negotiation failed or link partner
472 	 * cannot auto-negotiate), the cable is plugged in (we have signal),
473 	 * and our link partner is not trying to auto-negotiate with us (we
474 	 * are receiving idles or data), we need to force link up. We also
475 	 * need to give auto-negotiation time to complete, in case the cable
476 	 * was just plugged in. The autoneg_failed flag does this.
477 	 */
478 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
479 	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
480 	    !(rxcw & E1000_RXCW_C)) {
481 		if (!mac->autoneg_failed) {
482 			mac->autoneg_failed = true;
483 			return 0;
484 		}
485 		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
486 
487 		/* Disable auto-negotiation in the TXCW register */
488 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
489 
490 		/* Force link-up and also force full-duplex. */
491 		ctrl = er32(CTRL);
492 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
493 		ew32(CTRL, ctrl);
494 
495 		/* Configure Flow Control after forcing link up. */
496 		ret_val = e1000e_config_fc_after_link_up(hw);
497 		if (ret_val) {
498 			e_dbg("Error configuring flow control\n");
499 			return ret_val;
500 		}
501 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
502 		/* If we are forcing link and we are receiving /C/ ordered
503 		 * sets, re-enable auto-negotiation in the TXCW register
504 		 * and disable forced link in the Device Control register
505 		 * in an attempt to auto-negotiate with our link partner.
506 		 */
507 		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
508 		ew32(TXCW, mac->txcw);
509 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
510 
511 		mac->serdes_has_link = true;
512 	}
513 
514 	return 0;
515 }
516 
517 /**
518  *  e1000e_check_for_serdes_link - Check for link (Serdes)
519  *  @hw: pointer to the HW structure
520  *
521  *  Checks for link up on the hardware.  If link is not up and we have
522  *  a signal, then we need to force link up.
523  **/
e1000e_check_for_serdes_link(struct e1000_hw * hw)524 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
525 {
526 	struct e1000_mac_info *mac = &hw->mac;
527 	u32 rxcw;
528 	u32 ctrl;
529 	u32 status;
530 	s32 ret_val;
531 
532 	ctrl = er32(CTRL);
533 	status = er32(STATUS);
534 	rxcw = er32(RXCW);
535 
536 	/* If we don't have link (auto-negotiation failed or link partner
537 	 * cannot auto-negotiate), and our link partner is not trying to
538 	 * auto-negotiate with us (we are receiving idles or data),
539 	 * we need to force link up. We also need to give auto-negotiation
540 	 * time to complete.
541 	 */
542 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
543 	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
544 		if (!mac->autoneg_failed) {
545 			mac->autoneg_failed = true;
546 			return 0;
547 		}
548 		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
549 
550 		/* Disable auto-negotiation in the TXCW register */
551 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
552 
553 		/* Force link-up and also force full-duplex. */
554 		ctrl = er32(CTRL);
555 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
556 		ew32(CTRL, ctrl);
557 
558 		/* Configure Flow Control after forcing link up. */
559 		ret_val = e1000e_config_fc_after_link_up(hw);
560 		if (ret_val) {
561 			e_dbg("Error configuring flow control\n");
562 			return ret_val;
563 		}
564 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
565 		/* If we are forcing link and we are receiving /C/ ordered
566 		 * sets, re-enable auto-negotiation in the TXCW register
567 		 * and disable forced link in the Device Control register
568 		 * in an attempt to auto-negotiate with our link partner.
569 		 */
570 		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
571 		ew32(TXCW, mac->txcw);
572 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
573 
574 		mac->serdes_has_link = true;
575 	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
576 		/* If we force link for non-auto-negotiation switch, check
577 		 * link status based on MAC synchronization for internal
578 		 * serdes media type.
579 		 */
580 		/* SYNCH bit and IV bit are sticky. */
581 		usleep_range(10, 20);
582 		rxcw = er32(RXCW);
583 		if (rxcw & E1000_RXCW_SYNCH) {
584 			if (!(rxcw & E1000_RXCW_IV)) {
585 				mac->serdes_has_link = true;
586 				e_dbg("SERDES: Link up - forced.\n");
587 			}
588 		} else {
589 			mac->serdes_has_link = false;
590 			e_dbg("SERDES: Link down - force failed.\n");
591 		}
592 	}
593 
594 	if (E1000_TXCW_ANE & er32(TXCW)) {
595 		status = er32(STATUS);
596 		if (status & E1000_STATUS_LU) {
597 			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
598 			usleep_range(10, 20);
599 			rxcw = er32(RXCW);
600 			if (rxcw & E1000_RXCW_SYNCH) {
601 				if (!(rxcw & E1000_RXCW_IV)) {
602 					mac->serdes_has_link = true;
603 					e_dbg("SERDES: Link up - autoneg completed successfully.\n");
604 				} else {
605 					mac->serdes_has_link = false;
606 					e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
607 				}
608 			} else {
609 				mac->serdes_has_link = false;
610 				e_dbg("SERDES: Link down - no sync.\n");
611 			}
612 		} else {
613 			mac->serdes_has_link = false;
614 			e_dbg("SERDES: Link down - autoneg failed\n");
615 		}
616 	}
617 
618 	return 0;
619 }
620 
621 /**
622  *  e1000_set_default_fc_generic - Set flow control default values
623  *  @hw: pointer to the HW structure
624  *
625  *  Read the EEPROM for the default values for flow control and store the
626  *  values.
627  **/
e1000_set_default_fc_generic(struct e1000_hw * hw)628 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
629 {
630 	s32 ret_val;
631 	u16 nvm_data;
632 
633 	/* Read and store word 0x0F of the EEPROM. This word contains bits
634 	 * that determine the hardware's default PAUSE (flow control) mode,
635 	 * a bit that determines whether the HW defaults to enabling or
636 	 * disabling auto-negotiation, and the direction of the
637 	 * SW defined pins. If there is no SW over-ride of the flow
638 	 * control setting, then the variable hw->fc will
639 	 * be initialized based on a value in the EEPROM.
640 	 */
641 	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
642 
643 	if (ret_val) {
644 		e_dbg("NVM Read Error\n");
645 		return ret_val;
646 	}
647 
648 	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
649 		hw->fc.requested_mode = e1000_fc_none;
650 	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
651 		hw->fc.requested_mode = e1000_fc_tx_pause;
652 	else
653 		hw->fc.requested_mode = e1000_fc_full;
654 
655 	return 0;
656 }
657 
658 /**
659  *  e1000e_setup_link_generic - Setup flow control and link settings
660  *  @hw: pointer to the HW structure
661  *
662  *  Determines which flow control settings to use, then configures flow
663  *  control.  Calls the appropriate media-specific link configuration
664  *  function.  Assuming the adapter has a valid link partner, a valid link
665  *  should be established.  Assumes the hardware has previously been reset
666  *  and the transmitter and receiver are not enabled.
667  **/
e1000e_setup_link_generic(struct e1000_hw * hw)668 s32 e1000e_setup_link_generic(struct e1000_hw *hw)
669 {
670 	s32 ret_val;
671 
672 	/* In the case of the phy reset being blocked, we already have a link.
673 	 * We do not need to set it up again.
674 	 */
675 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
676 		return 0;
677 
678 	/* If requested flow control is set to default, set flow control
679 	 * based on the EEPROM flow control settings.
680 	 */
681 	if (hw->fc.requested_mode == e1000_fc_default) {
682 		ret_val = e1000_set_default_fc_generic(hw);
683 		if (ret_val)
684 			return ret_val;
685 	}
686 
687 	/* Save off the requested flow control mode for use later.  Depending
688 	 * on the link partner's capabilities, we may or may not use this mode.
689 	 */
690 	hw->fc.current_mode = hw->fc.requested_mode;
691 
692 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
693 
694 	/* Call the necessary media_type subroutine to configure the link. */
695 	ret_val = hw->mac.ops.setup_physical_interface(hw);
696 	if (ret_val)
697 		return ret_val;
698 
699 	/* Initialize the flow control address, type, and PAUSE timer
700 	 * registers to their default values.  This is done even if flow
701 	 * control is disabled, because it does not hurt anything to
702 	 * initialize these registers.
703 	 */
704 	e_dbg("Initializing the Flow Control address, type and timer regs\n");
705 	ew32(FCT, FLOW_CONTROL_TYPE);
706 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
707 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
708 
709 	ew32(FCTTV, hw->fc.pause_time);
710 
711 	return e1000e_set_fc_watermarks(hw);
712 }
713 
714 /**
715  *  e1000_commit_fc_settings_generic - Configure flow control
716  *  @hw: pointer to the HW structure
717  *
718  *  Write the flow control settings to the Transmit Config Word Register (TXCW)
719  *  base on the flow control settings in e1000_mac_info.
720  **/
e1000_commit_fc_settings_generic(struct e1000_hw * hw)721 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
722 {
723 	struct e1000_mac_info *mac = &hw->mac;
724 	u32 txcw;
725 
726 	/* Check for a software override of the flow control settings, and
727 	 * setup the device accordingly.  If auto-negotiation is enabled, then
728 	 * software will have to set the "PAUSE" bits to the correct value in
729 	 * the Transmit Config Word Register (TXCW) and re-start auto-
730 	 * negotiation.  However, if auto-negotiation is disabled, then
731 	 * software will have to manually configure the two flow control enable
732 	 * bits in the CTRL register.
733 	 *
734 	 * The possible values of the "fc" parameter are:
735 	 *      0:  Flow control is completely disabled
736 	 *      1:  Rx flow control is enabled (we can receive pause frames,
737 	 *          but not send pause frames).
738 	 *      2:  Tx flow control is enabled (we can send pause frames but we
739 	 *          do not support receiving pause frames).
740 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
741 	 */
742 	switch (hw->fc.current_mode) {
743 	case e1000_fc_none:
744 		/* Flow control completely disabled by a software over-ride. */
745 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
746 		break;
747 	case e1000_fc_rx_pause:
748 		/* Rx Flow control is enabled and Tx Flow control is disabled
749 		 * by a software over-ride. Since there really isn't a way to
750 		 * advertise that we are capable of Rx Pause ONLY, we will
751 		 * advertise that we support both symmetric and asymmetric Rx
752 		 * PAUSE.  Later, we will disable the adapter's ability to send
753 		 * PAUSE frames.
754 		 */
755 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
756 		break;
757 	case e1000_fc_tx_pause:
758 		/* Tx Flow control is enabled, and Rx Flow control is disabled,
759 		 * by a software over-ride.
760 		 */
761 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
762 		break;
763 	case e1000_fc_full:
764 		/* Flow control (both Rx and Tx) is enabled by a software
765 		 * over-ride.
766 		 */
767 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
768 		break;
769 	default:
770 		e_dbg("Flow control param set incorrectly\n");
771 		return -E1000_ERR_CONFIG;
772 	}
773 
774 	ew32(TXCW, txcw);
775 	mac->txcw = txcw;
776 
777 	return 0;
778 }
779 
780 /**
781  *  e1000_poll_fiber_serdes_link_generic - Poll for link up
782  *  @hw: pointer to the HW structure
783  *
784  *  Polls for link up by reading the status register, if link fails to come
785  *  up with auto-negotiation, then the link is forced if a signal is detected.
786  **/
e1000_poll_fiber_serdes_link_generic(struct e1000_hw * hw)787 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
788 {
789 	struct e1000_mac_info *mac = &hw->mac;
790 	u32 i, status;
791 	s32 ret_val;
792 
793 	/* If we have a signal (the cable is plugged in, or assumed true for
794 	 * serdes media) then poll for a "Link-Up" indication in the Device
795 	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
796 	 * seconds (Auto-negotiation should complete in less than 500
797 	 * milliseconds even if the other end is doing it in SW).
798 	 */
799 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
800 		usleep_range(10000, 11000);
801 		status = er32(STATUS);
802 		if (status & E1000_STATUS_LU)
803 			break;
804 	}
805 	if (i == FIBER_LINK_UP_LIMIT) {
806 		e_dbg("Never got a valid link from auto-neg!!!\n");
807 		mac->autoneg_failed = true;
808 		/* AutoNeg failed to achieve a link, so we'll call
809 		 * mac->check_for_link. This routine will force the
810 		 * link up if we detect a signal. This will allow us to
811 		 * communicate with non-autonegotiating link partners.
812 		 */
813 		ret_val = mac->ops.check_for_link(hw);
814 		if (ret_val) {
815 			e_dbg("Error while checking for link\n");
816 			return ret_val;
817 		}
818 		mac->autoneg_failed = false;
819 	} else {
820 		mac->autoneg_failed = false;
821 		e_dbg("Valid Link Found\n");
822 	}
823 
824 	return 0;
825 }
826 
827 /**
828  *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
829  *  @hw: pointer to the HW structure
830  *
831  *  Configures collision distance and flow control for fiber and serdes
832  *  links.  Upon successful setup, poll for link.
833  **/
e1000e_setup_fiber_serdes_link(struct e1000_hw * hw)834 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
835 {
836 	u32 ctrl;
837 	s32 ret_val;
838 
839 	ctrl = er32(CTRL);
840 
841 	/* Take the link out of reset */
842 	ctrl &= ~E1000_CTRL_LRST;
843 
844 	hw->mac.ops.config_collision_dist(hw);
845 
846 	ret_val = e1000_commit_fc_settings_generic(hw);
847 	if (ret_val)
848 		return ret_val;
849 
850 	/* Since auto-negotiation is enabled, take the link out of reset (the
851 	 * link will be in reset, because we previously reset the chip). This
852 	 * will restart auto-negotiation.  If auto-negotiation is successful
853 	 * then the link-up status bit will be set and the flow control enable
854 	 * bits (RFCE and TFCE) will be set according to their negotiated value.
855 	 */
856 	e_dbg("Auto-negotiation enabled\n");
857 
858 	ew32(CTRL, ctrl);
859 	e1e_flush();
860 	usleep_range(1000, 2000);
861 
862 	/* For these adapters, the SW definable pin 1 is set when the optics
863 	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
864 	 * indication.
865 	 */
866 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
867 	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
868 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
869 	} else {
870 		e_dbg("No signal detected\n");
871 	}
872 
873 	return ret_val;
874 }
875 
876 /**
877  *  e1000e_config_collision_dist_generic - Configure collision distance
878  *  @hw: pointer to the HW structure
879  *
880  *  Configures the collision distance to the default value and is used
881  *  during link setup.
882  **/
e1000e_config_collision_dist_generic(struct e1000_hw * hw)883 void e1000e_config_collision_dist_generic(struct e1000_hw *hw)
884 {
885 	u32 tctl;
886 
887 	tctl = er32(TCTL);
888 
889 	tctl &= ~E1000_TCTL_COLD;
890 	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
891 
892 	ew32(TCTL, tctl);
893 	e1e_flush();
894 }
895 
896 /**
897  *  e1000e_set_fc_watermarks - Set flow control high/low watermarks
898  *  @hw: pointer to the HW structure
899  *
900  *  Sets the flow control high/low threshold (watermark) registers.  If
901  *  flow control XON frame transmission is enabled, then set XON frame
902  *  transmission as well.
903  **/
e1000e_set_fc_watermarks(struct e1000_hw * hw)904 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
905 {
906 	u32 fcrtl = 0, fcrth = 0;
907 
908 	/* Set the flow control receive threshold registers.  Normally,
909 	 * these registers will be set to a default threshold that may be
910 	 * adjusted later by the driver's runtime code.  However, if the
911 	 * ability to transmit pause frames is not enabled, then these
912 	 * registers will be set to 0.
913 	 */
914 	if (hw->fc.current_mode & e1000_fc_tx_pause) {
915 		/* We need to set up the Receive Threshold high and low water
916 		 * marks as well as (optionally) enabling the transmission of
917 		 * XON frames.
918 		 */
919 		fcrtl = hw->fc.low_water;
920 		if (hw->fc.send_xon)
921 			fcrtl |= E1000_FCRTL_XONE;
922 
923 		fcrth = hw->fc.high_water;
924 	}
925 	ew32(FCRTL, fcrtl);
926 	ew32(FCRTH, fcrth);
927 
928 	return 0;
929 }
930 
931 /**
932  *  e1000e_force_mac_fc - Force the MAC's flow control settings
933  *  @hw: pointer to the HW structure
934  *
935  *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
936  *  device control register to reflect the adapter settings.  TFCE and RFCE
937  *  need to be explicitly set by software when a copper PHY is used because
938  *  autonegotiation is managed by the PHY rather than the MAC.  Software must
939  *  also configure these bits when link is forced on a fiber connection.
940  **/
e1000e_force_mac_fc(struct e1000_hw * hw)941 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
942 {
943 	u32 ctrl;
944 
945 	ctrl = er32(CTRL);
946 
947 	/* Because we didn't get link via the internal auto-negotiation
948 	 * mechanism (we either forced link or we got link via PHY
949 	 * auto-neg), we have to manually enable/disable transmit an
950 	 * receive flow control.
951 	 *
952 	 * The "Case" statement below enables/disable flow control
953 	 * according to the "hw->fc.current_mode" parameter.
954 	 *
955 	 * The possible values of the "fc" parameter are:
956 	 *      0:  Flow control is completely disabled
957 	 *      1:  Rx flow control is enabled (we can receive pause
958 	 *          frames but not send pause frames).
959 	 *      2:  Tx flow control is enabled (we can send pause frames
960 	 *          but we do not receive pause frames).
961 	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
962 	 *  other:  No other values should be possible at this point.
963 	 */
964 	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
965 
966 	switch (hw->fc.current_mode) {
967 	case e1000_fc_none:
968 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
969 		break;
970 	case e1000_fc_rx_pause:
971 		ctrl &= (~E1000_CTRL_TFCE);
972 		ctrl |= E1000_CTRL_RFCE;
973 		break;
974 	case e1000_fc_tx_pause:
975 		ctrl &= (~E1000_CTRL_RFCE);
976 		ctrl |= E1000_CTRL_TFCE;
977 		break;
978 	case e1000_fc_full:
979 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
980 		break;
981 	default:
982 		e_dbg("Flow control param set incorrectly\n");
983 		return -E1000_ERR_CONFIG;
984 	}
985 
986 	ew32(CTRL, ctrl);
987 
988 	return 0;
989 }
990 
991 /**
992  *  e1000e_config_fc_after_link_up - Configures flow control after link
993  *  @hw: pointer to the HW structure
994  *
995  *  Checks the status of auto-negotiation after link up to ensure that the
996  *  speed and duplex were not forced.  If the link needed to be forced, then
997  *  flow control needs to be forced also.  If auto-negotiation is enabled
998  *  and did not fail, then we configure flow control based on our link
999  *  partner.
1000  **/
e1000e_config_fc_after_link_up(struct e1000_hw * hw)1001 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1002 {
1003 	struct e1000_mac_info *mac = &hw->mac;
1004 	s32 ret_val = 0;
1005 	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1006 	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1007 	u16 speed, duplex;
1008 
1009 	/* Check for the case where we have fiber media and auto-neg failed
1010 	 * so we had to force link.  In this case, we need to force the
1011 	 * configuration of the MAC to match the "fc" parameter.
1012 	 */
1013 	if (mac->autoneg_failed) {
1014 		if (hw->phy.media_type == e1000_media_type_fiber ||
1015 		    hw->phy.media_type == e1000_media_type_internal_serdes)
1016 			ret_val = e1000e_force_mac_fc(hw);
1017 	} else {
1018 		if (hw->phy.media_type == e1000_media_type_copper)
1019 			ret_val = e1000e_force_mac_fc(hw);
1020 	}
1021 
1022 	if (ret_val) {
1023 		e_dbg("Error forcing flow control settings\n");
1024 		return ret_val;
1025 	}
1026 
1027 	/* Check for the case where we have copper media and auto-neg is
1028 	 * enabled.  In this case, we need to check and see if Auto-Neg
1029 	 * has completed, and if so, how the PHY and link partner has
1030 	 * flow control configured.
1031 	 */
1032 	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1033 		/* Read the MII Status Register and check to see if AutoNeg
1034 		 * has completed.  We read this twice because this reg has
1035 		 * some "sticky" (latched) bits.
1036 		 */
1037 		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);
1038 		if (ret_val)
1039 			return ret_val;
1040 		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);
1041 		if (ret_val)
1042 			return ret_val;
1043 
1044 		if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) {
1045 			e_dbg("Copper PHY and Auto Neg has not completed.\n");
1046 			return ret_val;
1047 		}
1048 
1049 		/* The AutoNeg process has completed, so we now need to
1050 		 * read both the Auto Negotiation Advertisement
1051 		 * Register (Address 4) and the Auto_Negotiation Base
1052 		 * Page Ability Register (Address 5) to determine how
1053 		 * flow control was negotiated.
1054 		 */
1055 		ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_nway_adv_reg);
1056 		if (ret_val)
1057 			return ret_val;
1058 		ret_val = e1e_rphy(hw, MII_LPA, &mii_nway_lp_ability_reg);
1059 		if (ret_val)
1060 			return ret_val;
1061 
1062 		/* Two bits in the Auto Negotiation Advertisement Register
1063 		 * (Address 4) and two bits in the Auto Negotiation Base
1064 		 * Page Ability Register (Address 5) determine flow control
1065 		 * for both the PHY and the link partner.  The following
1066 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1067 		 * 1999, describes these PAUSE resolution bits and how flow
1068 		 * control is determined based upon these settings.
1069 		 * NOTE:  DC = Don't Care
1070 		 *
1071 		 *   LOCAL DEVICE  |   LINK PARTNER
1072 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1073 		 *-------|---------|-------|---------|--------------------
1074 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1075 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1076 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1077 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1078 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1079 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1080 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1081 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1082 		 *
1083 		 * Are both PAUSE bits set to 1?  If so, this implies
1084 		 * Symmetric Flow Control is enabled at both ends.  The
1085 		 * ASM_DIR bits are irrelevant per the spec.
1086 		 *
1087 		 * For Symmetric Flow Control:
1088 		 *
1089 		 *   LOCAL DEVICE  |   LINK PARTNER
1090 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1091 		 *-------|---------|-------|---------|--------------------
1092 		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
1093 		 *
1094 		 */
1095 		if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1096 		    (mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) {
1097 			/* Now we need to check if the user selected Rx ONLY
1098 			 * of pause frames.  In this case, we had to advertise
1099 			 * FULL flow control because we could not advertise Rx
1100 			 * ONLY. Hence, we must now check to see if we need to
1101 			 * turn OFF the TRANSMISSION of PAUSE frames.
1102 			 */
1103 			if (hw->fc.requested_mode == e1000_fc_full) {
1104 				hw->fc.current_mode = e1000_fc_full;
1105 				e_dbg("Flow Control = FULL.\n");
1106 			} else {
1107 				hw->fc.current_mode = e1000_fc_rx_pause;
1108 				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1109 			}
1110 		}
1111 		/* For receiving PAUSE frames ONLY.
1112 		 *
1113 		 *   LOCAL DEVICE  |   LINK PARTNER
1114 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1115 		 *-------|---------|-------|---------|--------------------
1116 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1117 		 */
1118 		else if (!(mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1119 			 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1120 			 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1121 			 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1122 			hw->fc.current_mode = e1000_fc_tx_pause;
1123 			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1124 		}
1125 		/* For transmitting PAUSE frames ONLY.
1126 		 *
1127 		 *   LOCAL DEVICE  |   LINK PARTNER
1128 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1129 		 *-------|---------|-------|---------|--------------------
1130 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1131 		 */
1132 		else if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1133 			 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1134 			 !(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1135 			 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1136 			hw->fc.current_mode = e1000_fc_rx_pause;
1137 			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1138 		} else {
1139 			/* Per the IEEE spec, at this point flow control
1140 			 * should be disabled.
1141 			 */
1142 			hw->fc.current_mode = e1000_fc_none;
1143 			e_dbg("Flow Control = NONE.\n");
1144 		}
1145 
1146 		/* Now we need to do one last check...  If we auto-
1147 		 * negotiated to HALF DUPLEX, flow control should not be
1148 		 * enabled per IEEE 802.3 spec.
1149 		 */
1150 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1151 		if (ret_val) {
1152 			e_dbg("Error getting link speed and duplex\n");
1153 			return ret_val;
1154 		}
1155 
1156 		if (duplex == HALF_DUPLEX)
1157 			hw->fc.current_mode = e1000_fc_none;
1158 
1159 		/* Now we call a subroutine to actually force the MAC
1160 		 * controller to use the correct flow control settings.
1161 		 */
1162 		ret_val = e1000e_force_mac_fc(hw);
1163 		if (ret_val) {
1164 			e_dbg("Error forcing flow control settings\n");
1165 			return ret_val;
1166 		}
1167 	}
1168 
1169 	/* Check for the case where we have SerDes media and auto-neg is
1170 	 * enabled.  In this case, we need to check and see if Auto-Neg
1171 	 * has completed, and if so, how the PHY and link partner has
1172 	 * flow control configured.
1173 	 */
1174 	if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1175 	    mac->autoneg) {
1176 		/* Read the PCS_LSTS and check to see if AutoNeg
1177 		 * has completed.
1178 		 */
1179 		pcs_status_reg = er32(PCS_LSTAT);
1180 
1181 		if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1182 			e_dbg("PCS Auto Neg has not completed.\n");
1183 			return ret_val;
1184 		}
1185 
1186 		/* The AutoNeg process has completed, so we now need to
1187 		 * read both the Auto Negotiation Advertisement
1188 		 * Register (PCS_ANADV) and the Auto_Negotiation Base
1189 		 * Page Ability Register (PCS_LPAB) to determine how
1190 		 * flow control was negotiated.
1191 		 */
1192 		pcs_adv_reg = er32(PCS_ANADV);
1193 		pcs_lp_ability_reg = er32(PCS_LPAB);
1194 
1195 		/* Two bits in the Auto Negotiation Advertisement Register
1196 		 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1197 		 * Page Ability Register (PCS_LPAB) determine flow control
1198 		 * for both the PHY and the link partner.  The following
1199 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1200 		 * 1999, describes these PAUSE resolution bits and how flow
1201 		 * control is determined based upon these settings.
1202 		 * NOTE:  DC = Don't Care
1203 		 *
1204 		 *   LOCAL DEVICE  |   LINK PARTNER
1205 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1206 		 *-------|---------|-------|---------|--------------------
1207 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1208 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1209 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1210 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1211 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1212 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1213 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1214 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1215 		 *
1216 		 * Are both PAUSE bits set to 1?  If so, this implies
1217 		 * Symmetric Flow Control is enabled at both ends.  The
1218 		 * ASM_DIR bits are irrelevant per the spec.
1219 		 *
1220 		 * For Symmetric Flow Control:
1221 		 *
1222 		 *   LOCAL DEVICE  |   LINK PARTNER
1223 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1224 		 *-------|---------|-------|---------|--------------------
1225 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1226 		 *
1227 		 */
1228 		if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1229 		    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1230 			/* Now we need to check if the user selected Rx ONLY
1231 			 * of pause frames.  In this case, we had to advertise
1232 			 * FULL flow control because we could not advertise Rx
1233 			 * ONLY. Hence, we must now check to see if we need to
1234 			 * turn OFF the TRANSMISSION of PAUSE frames.
1235 			 */
1236 			if (hw->fc.requested_mode == e1000_fc_full) {
1237 				hw->fc.current_mode = e1000_fc_full;
1238 				e_dbg("Flow Control = FULL.\n");
1239 			} else {
1240 				hw->fc.current_mode = e1000_fc_rx_pause;
1241 				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1242 			}
1243 		}
1244 		/* For receiving PAUSE frames ONLY.
1245 		 *
1246 		 *   LOCAL DEVICE  |   LINK PARTNER
1247 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1248 		 *-------|---------|-------|---------|--------------------
1249 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1250 		 */
1251 		else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1252 			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1253 			 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1254 			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1255 			hw->fc.current_mode = e1000_fc_tx_pause;
1256 			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1257 		}
1258 		/* For transmitting PAUSE frames ONLY.
1259 		 *
1260 		 *   LOCAL DEVICE  |   LINK PARTNER
1261 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1262 		 *-------|---------|-------|---------|--------------------
1263 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1264 		 */
1265 		else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1266 			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1267 			 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1268 			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1269 			hw->fc.current_mode = e1000_fc_rx_pause;
1270 			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1271 		} else {
1272 			/* Per the IEEE spec, at this point flow control
1273 			 * should be disabled.
1274 			 */
1275 			hw->fc.current_mode = e1000_fc_none;
1276 			e_dbg("Flow Control = NONE.\n");
1277 		}
1278 
1279 		/* Now we call a subroutine to actually force the MAC
1280 		 * controller to use the correct flow control settings.
1281 		 */
1282 		pcs_ctrl_reg = er32(PCS_LCTL);
1283 		pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1284 		ew32(PCS_LCTL, pcs_ctrl_reg);
1285 
1286 		ret_val = e1000e_force_mac_fc(hw);
1287 		if (ret_val) {
1288 			e_dbg("Error forcing flow control settings\n");
1289 			return ret_val;
1290 		}
1291 	}
1292 
1293 	return 0;
1294 }
1295 
1296 /**
1297  *  e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1298  *  @hw: pointer to the HW structure
1299  *  @speed: stores the current speed
1300  *  @duplex: stores the current duplex
1301  *
1302  *  Read the status register for the current speed/duplex and store the current
1303  *  speed and duplex for copper connections.
1304  **/
e1000e_get_speed_and_duplex_copper(struct e1000_hw * hw,u16 * speed,u16 * duplex)1305 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1306 				       u16 *duplex)
1307 {
1308 	u32 status;
1309 
1310 	status = er32(STATUS);
1311 	if (status & E1000_STATUS_SPEED_1000)
1312 		*speed = SPEED_1000;
1313 	else if (status & E1000_STATUS_SPEED_100)
1314 		*speed = SPEED_100;
1315 	else
1316 		*speed = SPEED_10;
1317 
1318 	if (status & E1000_STATUS_FD)
1319 		*duplex = FULL_DUPLEX;
1320 	else
1321 		*duplex = HALF_DUPLEX;
1322 
1323 	e_dbg("%u Mbps, %s Duplex\n",
1324 	      *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1325 	      *duplex == FULL_DUPLEX ? "Full" : "Half");
1326 
1327 	return 0;
1328 }
1329 
1330 /**
1331  *  e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1332  *  @hw: pointer to the HW structure
1333  *  @speed: stores the current speed
1334  *  @duplex: stores the current duplex
1335  *
1336  *  Sets the speed and duplex to gigabit full duplex (the only possible option)
1337  *  for fiber/serdes links.
1338  **/
e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused * hw,u16 * speed,u16 * duplex)1339 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused
1340 					     *hw, u16 *speed, u16 *duplex)
1341 {
1342 	*speed = SPEED_1000;
1343 	*duplex = FULL_DUPLEX;
1344 
1345 	return 0;
1346 }
1347 
1348 /**
1349  *  e1000e_get_hw_semaphore - Acquire hardware semaphore
1350  *  @hw: pointer to the HW structure
1351  *
1352  *  Acquire the HW semaphore to access the PHY or NVM
1353  **/
e1000e_get_hw_semaphore(struct e1000_hw * hw)1354 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1355 {
1356 	u32 swsm;
1357 	s32 timeout = hw->nvm.word_size + 1;
1358 	s32 i = 0;
1359 
1360 	/* Get the SW semaphore */
1361 	while (i < timeout) {
1362 		swsm = er32(SWSM);
1363 		if (!(swsm & E1000_SWSM_SMBI))
1364 			break;
1365 
1366 		udelay(100);
1367 		i++;
1368 	}
1369 
1370 	if (i == timeout) {
1371 		e_dbg("Driver can't access device - SMBI bit is set.\n");
1372 		return -E1000_ERR_NVM;
1373 	}
1374 
1375 	/* Get the FW semaphore. */
1376 	for (i = 0; i < timeout; i++) {
1377 		swsm = er32(SWSM);
1378 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1379 
1380 		/* Semaphore acquired if bit latched */
1381 		if (er32(SWSM) & E1000_SWSM_SWESMBI)
1382 			break;
1383 
1384 		udelay(100);
1385 	}
1386 
1387 	if (i == timeout) {
1388 		/* Release semaphores */
1389 		e1000e_put_hw_semaphore(hw);
1390 		e_dbg("Driver can't access the NVM\n");
1391 		return -E1000_ERR_NVM;
1392 	}
1393 
1394 	return 0;
1395 }
1396 
1397 /**
1398  *  e1000e_put_hw_semaphore - Release hardware semaphore
1399  *  @hw: pointer to the HW structure
1400  *
1401  *  Release hardware semaphore used to access the PHY or NVM
1402  **/
e1000e_put_hw_semaphore(struct e1000_hw * hw)1403 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1404 {
1405 	u32 swsm;
1406 
1407 	swsm = er32(SWSM);
1408 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1409 	ew32(SWSM, swsm);
1410 }
1411 
1412 /**
1413  *  e1000e_get_auto_rd_done - Check for auto read completion
1414  *  @hw: pointer to the HW structure
1415  *
1416  *  Check EEPROM for Auto Read done bit.
1417  **/
e1000e_get_auto_rd_done(struct e1000_hw * hw)1418 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1419 {
1420 	s32 i = 0;
1421 
1422 	while (i < AUTO_READ_DONE_TIMEOUT) {
1423 		if (er32(EECD) & E1000_EECD_AUTO_RD)
1424 			break;
1425 		usleep_range(1000, 2000);
1426 		i++;
1427 	}
1428 
1429 	if (i == AUTO_READ_DONE_TIMEOUT) {
1430 		e_dbg("Auto read by HW from NVM has not completed.\n");
1431 		return -E1000_ERR_RESET;
1432 	}
1433 
1434 	return 0;
1435 }
1436 
1437 /**
1438  *  e1000e_valid_led_default - Verify a valid default LED config
1439  *  @hw: pointer to the HW structure
1440  *  @data: pointer to the NVM (EEPROM)
1441  *
1442  *  Read the EEPROM for the current default LED configuration.  If the
1443  *  LED configuration is not valid, set to a valid LED configuration.
1444  **/
e1000e_valid_led_default(struct e1000_hw * hw,u16 * data)1445 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1446 {
1447 	s32 ret_val;
1448 
1449 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1450 	if (ret_val) {
1451 		e_dbg("NVM Read Error\n");
1452 		return ret_val;
1453 	}
1454 
1455 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1456 		*data = ID_LED_DEFAULT;
1457 
1458 	return 0;
1459 }
1460 
1461 /**
1462  *  e1000e_id_led_init_generic -
1463  *  @hw: pointer to the HW structure
1464  *
1465  **/
e1000e_id_led_init_generic(struct e1000_hw * hw)1466 s32 e1000e_id_led_init_generic(struct e1000_hw *hw)
1467 {
1468 	struct e1000_mac_info *mac = &hw->mac;
1469 	s32 ret_val;
1470 	const u32 ledctl_mask = 0x000000FF;
1471 	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1472 	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1473 	u16 data, i, temp;
1474 	const u16 led_mask = 0x0F;
1475 
1476 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1477 	if (ret_val)
1478 		return ret_val;
1479 
1480 	mac->ledctl_default = er32(LEDCTL);
1481 	mac->ledctl_mode1 = mac->ledctl_default;
1482 	mac->ledctl_mode2 = mac->ledctl_default;
1483 
1484 	for (i = 0; i < 4; i++) {
1485 		temp = (data >> (i << 2)) & led_mask;
1486 		switch (temp) {
1487 		case ID_LED_ON1_DEF2:
1488 		case ID_LED_ON1_ON2:
1489 		case ID_LED_ON1_OFF2:
1490 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1491 			mac->ledctl_mode1 |= ledctl_on << (i << 3);
1492 			break;
1493 		case ID_LED_OFF1_DEF2:
1494 		case ID_LED_OFF1_ON2:
1495 		case ID_LED_OFF1_OFF2:
1496 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1497 			mac->ledctl_mode1 |= ledctl_off << (i << 3);
1498 			break;
1499 		default:
1500 			/* Do nothing */
1501 			break;
1502 		}
1503 		switch (temp) {
1504 		case ID_LED_DEF1_ON2:
1505 		case ID_LED_ON1_ON2:
1506 		case ID_LED_OFF1_ON2:
1507 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1508 			mac->ledctl_mode2 |= ledctl_on << (i << 3);
1509 			break;
1510 		case ID_LED_DEF1_OFF2:
1511 		case ID_LED_ON1_OFF2:
1512 		case ID_LED_OFF1_OFF2:
1513 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1514 			mac->ledctl_mode2 |= ledctl_off << (i << 3);
1515 			break;
1516 		default:
1517 			/* Do nothing */
1518 			break;
1519 		}
1520 	}
1521 
1522 	return 0;
1523 }
1524 
1525 /**
1526  *  e1000e_setup_led_generic - Configures SW controllable LED
1527  *  @hw: pointer to the HW structure
1528  *
1529  *  This prepares the SW controllable LED for use and saves the current state
1530  *  of the LED so it can be later restored.
1531  **/
e1000e_setup_led_generic(struct e1000_hw * hw)1532 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1533 {
1534 	u32 ledctl;
1535 
1536 	if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1537 		return -E1000_ERR_CONFIG;
1538 
1539 	if (hw->phy.media_type == e1000_media_type_fiber) {
1540 		ledctl = er32(LEDCTL);
1541 		hw->mac.ledctl_default = ledctl;
1542 		/* Turn off LED0 */
1543 		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1544 			    E1000_LEDCTL_LED0_MODE_MASK);
1545 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1546 			   E1000_LEDCTL_LED0_MODE_SHIFT);
1547 		ew32(LEDCTL, ledctl);
1548 	} else if (hw->phy.media_type == e1000_media_type_copper) {
1549 		ew32(LEDCTL, hw->mac.ledctl_mode1);
1550 	}
1551 
1552 	return 0;
1553 }
1554 
1555 /**
1556  *  e1000e_cleanup_led_generic - Set LED config to default operation
1557  *  @hw: pointer to the HW structure
1558  *
1559  *  Remove the current LED configuration and set the LED configuration
1560  *  to the default value, saved from the EEPROM.
1561  **/
e1000e_cleanup_led_generic(struct e1000_hw * hw)1562 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1563 {
1564 	ew32(LEDCTL, hw->mac.ledctl_default);
1565 	return 0;
1566 }
1567 
1568 /**
1569  *  e1000e_blink_led_generic - Blink LED
1570  *  @hw: pointer to the HW structure
1571  *
1572  *  Blink the LEDs which are set to be on.
1573  **/
e1000e_blink_led_generic(struct e1000_hw * hw)1574 s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1575 {
1576 	u32 ledctl_blink = 0;
1577 	u32 i;
1578 
1579 	if (hw->phy.media_type == e1000_media_type_fiber) {
1580 		/* always blink LED0 for PCI-E fiber */
1581 		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1582 		    (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1583 	} else {
1584 		/* Set the blink bit for each LED that's "on" (0x0E)
1585 		 * (or "off" if inverted) in ledctl_mode2.  The blink
1586 		 * logic in hardware only works when mode is set to "on"
1587 		 * so it must be changed accordingly when the mode is
1588 		 * "off" and inverted.
1589 		 */
1590 		ledctl_blink = hw->mac.ledctl_mode2;
1591 		for (i = 0; i < 32; i += 8) {
1592 			u32 mode = (hw->mac.ledctl_mode2 >> i) &
1593 			    E1000_LEDCTL_LED0_MODE_MASK;
1594 			u32 led_default = hw->mac.ledctl_default >> i;
1595 
1596 			if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1597 			     (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1598 			    ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1599 			     (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1600 				ledctl_blink &=
1601 				    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1602 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1603 						 E1000_LEDCTL_MODE_LED_ON) << i;
1604 			}
1605 		}
1606 	}
1607 
1608 	ew32(LEDCTL, ledctl_blink);
1609 
1610 	return 0;
1611 }
1612 
1613 /**
1614  *  e1000e_led_on_generic - Turn LED on
1615  *  @hw: pointer to the HW structure
1616  *
1617  *  Turn LED on.
1618  **/
e1000e_led_on_generic(struct e1000_hw * hw)1619 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1620 {
1621 	u32 ctrl;
1622 
1623 	switch (hw->phy.media_type) {
1624 	case e1000_media_type_fiber:
1625 		ctrl = er32(CTRL);
1626 		ctrl &= ~E1000_CTRL_SWDPIN0;
1627 		ctrl |= E1000_CTRL_SWDPIO0;
1628 		ew32(CTRL, ctrl);
1629 		break;
1630 	case e1000_media_type_copper:
1631 		ew32(LEDCTL, hw->mac.ledctl_mode2);
1632 		break;
1633 	default:
1634 		break;
1635 	}
1636 
1637 	return 0;
1638 }
1639 
1640 /**
1641  *  e1000e_led_off_generic - Turn LED off
1642  *  @hw: pointer to the HW structure
1643  *
1644  *  Turn LED off.
1645  **/
e1000e_led_off_generic(struct e1000_hw * hw)1646 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1647 {
1648 	u32 ctrl;
1649 
1650 	switch (hw->phy.media_type) {
1651 	case e1000_media_type_fiber:
1652 		ctrl = er32(CTRL);
1653 		ctrl |= E1000_CTRL_SWDPIN0;
1654 		ctrl |= E1000_CTRL_SWDPIO0;
1655 		ew32(CTRL, ctrl);
1656 		break;
1657 	case e1000_media_type_copper:
1658 		ew32(LEDCTL, hw->mac.ledctl_mode1);
1659 		break;
1660 	default:
1661 		break;
1662 	}
1663 
1664 	return 0;
1665 }
1666 
1667 /**
1668  *  e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1669  *  @hw: pointer to the HW structure
1670  *  @no_snoop: bitmap of snoop events
1671  *
1672  *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1673  **/
e1000e_set_pcie_no_snoop(struct e1000_hw * hw,u32 no_snoop)1674 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1675 {
1676 	u32 gcr;
1677 
1678 	if (no_snoop) {
1679 		gcr = er32(GCR);
1680 		gcr &= ~(PCIE_NO_SNOOP_ALL);
1681 		gcr |= no_snoop;
1682 		ew32(GCR, gcr);
1683 	}
1684 }
1685 
1686 /**
1687  *  e1000e_disable_pcie_master - Disables PCI-express master access
1688  *  @hw: pointer to the HW structure
1689  *
1690  *  Returns 0 if successful, else returns -10
1691  *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1692  *  the master requests to be disabled.
1693  *
1694  *  Disables PCI-Express master access and verifies there are no pending
1695  *  requests.
1696  **/
e1000e_disable_pcie_master(struct e1000_hw * hw)1697 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1698 {
1699 	u32 ctrl;
1700 	s32 timeout = MASTER_DISABLE_TIMEOUT;
1701 
1702 	ctrl = er32(CTRL);
1703 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1704 	ew32(CTRL, ctrl);
1705 
1706 	while (timeout) {
1707 		if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1708 			break;
1709 		usleep_range(100, 200);
1710 		timeout--;
1711 	}
1712 
1713 	if (!timeout) {
1714 		e_dbg("Master requests are pending.\n");
1715 		return -E1000_ERR_MASTER_REQUESTS_PENDING;
1716 	}
1717 
1718 	return 0;
1719 }
1720 
1721 /**
1722  *  e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1723  *  @hw: pointer to the HW structure
1724  *
1725  *  Reset the Adaptive Interframe Spacing throttle to default values.
1726  **/
e1000e_reset_adaptive(struct e1000_hw * hw)1727 void e1000e_reset_adaptive(struct e1000_hw *hw)
1728 {
1729 	struct e1000_mac_info *mac = &hw->mac;
1730 
1731 	if (!mac->adaptive_ifs) {
1732 		e_dbg("Not in Adaptive IFS mode!\n");
1733 		return;
1734 	}
1735 
1736 	mac->current_ifs_val = 0;
1737 	mac->ifs_min_val = IFS_MIN;
1738 	mac->ifs_max_val = IFS_MAX;
1739 	mac->ifs_step_size = IFS_STEP;
1740 	mac->ifs_ratio = IFS_RATIO;
1741 
1742 	mac->in_ifs_mode = false;
1743 	ew32(AIT, 0);
1744 }
1745 
1746 /**
1747  *  e1000e_update_adaptive - Update Adaptive Interframe Spacing
1748  *  @hw: pointer to the HW structure
1749  *
1750  *  Update the Adaptive Interframe Spacing Throttle value based on the
1751  *  time between transmitted packets and time between collisions.
1752  **/
e1000e_update_adaptive(struct e1000_hw * hw)1753 void e1000e_update_adaptive(struct e1000_hw *hw)
1754 {
1755 	struct e1000_mac_info *mac = &hw->mac;
1756 
1757 	if (!mac->adaptive_ifs) {
1758 		e_dbg("Not in Adaptive IFS mode!\n");
1759 		return;
1760 	}
1761 
1762 	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1763 		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1764 			mac->in_ifs_mode = true;
1765 			if (mac->current_ifs_val < mac->ifs_max_val) {
1766 				if (!mac->current_ifs_val)
1767 					mac->current_ifs_val = mac->ifs_min_val;
1768 				else
1769 					mac->current_ifs_val +=
1770 					    mac->ifs_step_size;
1771 				ew32(AIT, mac->current_ifs_val);
1772 			}
1773 		}
1774 	} else {
1775 		if (mac->in_ifs_mode &&
1776 		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1777 			mac->current_ifs_val = 0;
1778 			mac->in_ifs_mode = false;
1779 			ew32(AIT, 0);
1780 		}
1781 	}
1782 }
1783