1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000.h"
30
31 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
32 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
33 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
34 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
35 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
36 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
37 u16 *data, bool read, bool page_set);
38 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
39 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read);
41
42 /* Cable length tables */
43 static const u16 e1000_m88_cable_length_table[] = {
44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46 ARRAY_SIZE(e1000_m88_cable_length_table)
47
48 static const u16 e1000_igp_2_cable_length_table[] = {
49 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
56 124};
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
59
60 #define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
66
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
74
75 /* 82577 specific PHY registers */
76 #define I82577_PHY_CTRL_2 18
77 #define I82577_PHY_STATUS_2 26
78 #define I82577_PHY_DIAG_STATUS 31
79
80 /* I82577 PHY Status 2 */
81 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
82 #define I82577_PHY_STATUS2_MDIX 0x0800
83 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
85
86 /* I82577 PHY Control 2 */
87 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
88 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
89
90 /* I82577 PHY Diagnostics Status */
91 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
92 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
93
94 /* BM PHY Copper Specific Control 1 */
95 #define BM_CS_CTRL1 16
96
97 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
98 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
99 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
100
101 /**
102 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
103 * @hw: pointer to the HW structure
104 *
105 * Read the PHY management control register and check whether a PHY reset
106 * is blocked. If a reset is not blocked return 0, otherwise
107 * return E1000_BLK_PHY_RESET (12).
108 **/
e1000e_check_reset_block_generic(struct e1000_hw * hw)109 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
110 {
111 u32 manc;
112
113 manc = er32(MANC);
114
115 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
116 E1000_BLK_PHY_RESET : 0;
117 }
118
119 /**
120 * e1000e_get_phy_id - Retrieve the PHY ID and revision
121 * @hw: pointer to the HW structure
122 *
123 * Reads the PHY registers and stores the PHY ID and possibly the PHY
124 * revision in the hardware structure.
125 **/
e1000e_get_phy_id(struct e1000_hw * hw)126 s32 e1000e_get_phy_id(struct e1000_hw *hw)
127 {
128 struct e1000_phy_info *phy = &hw->phy;
129 s32 ret_val = 0;
130 u16 phy_id;
131 u16 retry_count = 0;
132
133 if (!phy->ops.read_reg)
134 return 0;
135
136 while (retry_count < 2) {
137 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
138 if (ret_val)
139 return ret_val;
140
141 phy->id = (u32)(phy_id << 16);
142 udelay(20);
143 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
144 if (ret_val)
145 return ret_val;
146
147 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
148 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
149
150 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
151 return 0;
152
153 retry_count++;
154 }
155
156 return 0;
157 }
158
159 /**
160 * e1000e_phy_reset_dsp - Reset PHY DSP
161 * @hw: pointer to the HW structure
162 *
163 * Reset the digital signal processor.
164 **/
e1000e_phy_reset_dsp(struct e1000_hw * hw)165 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
166 {
167 s32 ret_val;
168
169 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
170 if (ret_val)
171 return ret_val;
172
173 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
174 }
175
176 /**
177 * e1000e_read_phy_reg_mdic - Read MDI control register
178 * @hw: pointer to the HW structure
179 * @offset: register offset to be read
180 * @data: pointer to the read data
181 *
182 * Reads the MDI control register in the PHY at offset and stores the
183 * information read to data.
184 **/
e1000e_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)185 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
186 {
187 struct e1000_phy_info *phy = &hw->phy;
188 u32 i, mdic = 0;
189
190 if (offset > MAX_PHY_REG_ADDRESS) {
191 e_dbg("PHY Address %d is out of range\n", offset);
192 return -E1000_ERR_PARAM;
193 }
194
195 /*
196 * Set up Op-code, Phy Address, and register offset in the MDI
197 * Control register. The MAC will take care of interfacing with the
198 * PHY to retrieve the desired data.
199 */
200 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
201 (phy->addr << E1000_MDIC_PHY_SHIFT) |
202 (E1000_MDIC_OP_READ));
203
204 ew32(MDIC, mdic);
205
206 /*
207 * Poll the ready bit to see if the MDI read completed
208 * Increasing the time out as testing showed failures with
209 * the lower time out
210 */
211 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
212 udelay(50);
213 mdic = er32(MDIC);
214 if (mdic & E1000_MDIC_READY)
215 break;
216 }
217 if (!(mdic & E1000_MDIC_READY)) {
218 e_dbg("MDI Read did not complete\n");
219 return -E1000_ERR_PHY;
220 }
221 if (mdic & E1000_MDIC_ERROR) {
222 e_dbg("MDI Error\n");
223 return -E1000_ERR_PHY;
224 }
225 *data = (u16) mdic;
226
227 /*
228 * Allow some time after each MDIC transaction to avoid
229 * reading duplicate data in the next MDIC transaction.
230 */
231 if (hw->mac.type == e1000_pch2lan)
232 udelay(100);
233
234 return 0;
235 }
236
237 /**
238 * e1000e_write_phy_reg_mdic - Write MDI control register
239 * @hw: pointer to the HW structure
240 * @offset: register offset to write to
241 * @data: data to write to register at offset
242 *
243 * Writes data to MDI control register in the PHY at offset.
244 **/
e1000e_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)245 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
246 {
247 struct e1000_phy_info *phy = &hw->phy;
248 u32 i, mdic = 0;
249
250 if (offset > MAX_PHY_REG_ADDRESS) {
251 e_dbg("PHY Address %d is out of range\n", offset);
252 return -E1000_ERR_PARAM;
253 }
254
255 /*
256 * Set up Op-code, Phy Address, and register offset in the MDI
257 * Control register. The MAC will take care of interfacing with the
258 * PHY to retrieve the desired data.
259 */
260 mdic = (((u32)data) |
261 (offset << E1000_MDIC_REG_SHIFT) |
262 (phy->addr << E1000_MDIC_PHY_SHIFT) |
263 (E1000_MDIC_OP_WRITE));
264
265 ew32(MDIC, mdic);
266
267 /*
268 * Poll the ready bit to see if the MDI read completed
269 * Increasing the time out as testing showed failures with
270 * the lower time out
271 */
272 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
273 udelay(50);
274 mdic = er32(MDIC);
275 if (mdic & E1000_MDIC_READY)
276 break;
277 }
278 if (!(mdic & E1000_MDIC_READY)) {
279 e_dbg("MDI Write did not complete\n");
280 return -E1000_ERR_PHY;
281 }
282 if (mdic & E1000_MDIC_ERROR) {
283 e_dbg("MDI Error\n");
284 return -E1000_ERR_PHY;
285 }
286
287 /*
288 * Allow some time after each MDIC transaction to avoid
289 * reading duplicate data in the next MDIC transaction.
290 */
291 if (hw->mac.type == e1000_pch2lan)
292 udelay(100);
293
294 return 0;
295 }
296
297 /**
298 * e1000e_read_phy_reg_m88 - Read m88 PHY register
299 * @hw: pointer to the HW structure
300 * @offset: register offset to be read
301 * @data: pointer to the read data
302 *
303 * Acquires semaphore, if necessary, then reads the PHY register at offset
304 * and storing the retrieved information in data. Release any acquired
305 * semaphores before exiting.
306 **/
e1000e_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)307 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
308 {
309 s32 ret_val;
310
311 ret_val = hw->phy.ops.acquire(hw);
312 if (ret_val)
313 return ret_val;
314
315 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
316 data);
317
318 hw->phy.ops.release(hw);
319
320 return ret_val;
321 }
322
323 /**
324 * e1000e_write_phy_reg_m88 - Write m88 PHY register
325 * @hw: pointer to the HW structure
326 * @offset: register offset to write to
327 * @data: data to write at register offset
328 *
329 * Acquires semaphore, if necessary, then writes the data to PHY register
330 * at the offset. Release any acquired semaphores before exiting.
331 **/
e1000e_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)332 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
333 {
334 s32 ret_val;
335
336 ret_val = hw->phy.ops.acquire(hw);
337 if (ret_val)
338 return ret_val;
339
340 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
341 data);
342
343 hw->phy.ops.release(hw);
344
345 return ret_val;
346 }
347
348 /**
349 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
350 * @hw: pointer to the HW structure
351 * @page: page to set (shifted left when necessary)
352 *
353 * Sets PHY page required for PHY register access. Assumes semaphore is
354 * already acquired. Note, this function sets phy.addr to 1 so the caller
355 * must set it appropriately (if necessary) after this function returns.
356 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)357 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
358 {
359 e_dbg("Setting page 0x%x\n", page);
360
361 hw->phy.addr = 1;
362
363 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
364 }
365
366 /**
367 * __e1000e_read_phy_reg_igp - Read igp PHY register
368 * @hw: pointer to the HW structure
369 * @offset: register offset to be read
370 * @data: pointer to the read data
371 * @locked: semaphore has already been acquired or not
372 *
373 * Acquires semaphore, if necessary, then reads the PHY register at offset
374 * and stores the retrieved information in data. Release any acquired
375 * semaphores before exiting.
376 **/
__e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)377 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
378 bool locked)
379 {
380 s32 ret_val = 0;
381
382 if (!locked) {
383 if (!hw->phy.ops.acquire)
384 return 0;
385
386 ret_val = hw->phy.ops.acquire(hw);
387 if (ret_val)
388 return ret_val;
389 }
390
391 if (offset > MAX_PHY_MULTI_PAGE_REG)
392 ret_val = e1000e_write_phy_reg_mdic(hw,
393 IGP01E1000_PHY_PAGE_SELECT,
394 (u16)offset);
395 if (!ret_val)
396 ret_val = e1000e_read_phy_reg_mdic(hw,
397 MAX_PHY_REG_ADDRESS & offset,
398 data);
399 if (!locked)
400 hw->phy.ops.release(hw);
401
402 return ret_val;
403 }
404
405 /**
406 * e1000e_read_phy_reg_igp - Read igp PHY register
407 * @hw: pointer to the HW structure
408 * @offset: register offset to be read
409 * @data: pointer to the read data
410 *
411 * Acquires semaphore then reads the PHY register at offset and stores the
412 * retrieved information in data.
413 * Release the acquired semaphore before exiting.
414 **/
e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)415 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
416 {
417 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
418 }
419
420 /**
421 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
422 * @hw: pointer to the HW structure
423 * @offset: register offset to be read
424 * @data: pointer to the read data
425 *
426 * Reads the PHY register at offset and stores the retrieved information
427 * in data. Assumes semaphore already acquired.
428 **/
e1000e_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)429 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
430 {
431 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
432 }
433
434 /**
435 * e1000e_write_phy_reg_igp - Write igp PHY register
436 * @hw: pointer to the HW structure
437 * @offset: register offset to write to
438 * @data: data to write at register offset
439 * @locked: semaphore has already been acquired or not
440 *
441 * Acquires semaphore, if necessary, then writes the data to PHY register
442 * at the offset. Release any acquired semaphores before exiting.
443 **/
__e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)444 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
445 bool locked)
446 {
447 s32 ret_val = 0;
448
449 if (!locked) {
450 if (!hw->phy.ops.acquire)
451 return 0;
452
453 ret_val = hw->phy.ops.acquire(hw);
454 if (ret_val)
455 return ret_val;
456 }
457
458 if (offset > MAX_PHY_MULTI_PAGE_REG)
459 ret_val = e1000e_write_phy_reg_mdic(hw,
460 IGP01E1000_PHY_PAGE_SELECT,
461 (u16)offset);
462 if (!ret_val)
463 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
464 offset,
465 data);
466 if (!locked)
467 hw->phy.ops.release(hw);
468
469 return ret_val;
470 }
471
472 /**
473 * e1000e_write_phy_reg_igp - Write igp PHY register
474 * @hw: pointer to the HW structure
475 * @offset: register offset to write to
476 * @data: data to write at register offset
477 *
478 * Acquires semaphore then writes the data to PHY register
479 * at the offset. Release any acquired semaphores before exiting.
480 **/
e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)481 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
482 {
483 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
484 }
485
486 /**
487 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
488 * @hw: pointer to the HW structure
489 * @offset: register offset to write to
490 * @data: data to write at register offset
491 *
492 * Writes the data to PHY register at the offset.
493 * Assumes semaphore already acquired.
494 **/
e1000e_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)495 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
496 {
497 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
498 }
499
500 /**
501 * __e1000_read_kmrn_reg - Read kumeran register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 * @locked: semaphore has already been acquired or not
506 *
507 * Acquires semaphore, if necessary. Then reads the PHY register at offset
508 * using the kumeran interface. The information retrieved is stored in data.
509 * Release any acquired semaphores before exiting.
510 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)511 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
512 bool locked)
513 {
514 u32 kmrnctrlsta;
515
516 if (!locked) {
517 s32 ret_val = 0;
518
519 if (!hw->phy.ops.acquire)
520 return 0;
521
522 ret_val = hw->phy.ops.acquire(hw);
523 if (ret_val)
524 return ret_val;
525 }
526
527 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
528 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
529 ew32(KMRNCTRLSTA, kmrnctrlsta);
530 e1e_flush();
531
532 udelay(2);
533
534 kmrnctrlsta = er32(KMRNCTRLSTA);
535 *data = (u16)kmrnctrlsta;
536
537 if (!locked)
538 hw->phy.ops.release(hw);
539
540 return 0;
541 }
542
543 /**
544 * e1000e_read_kmrn_reg - Read kumeran register
545 * @hw: pointer to the HW structure
546 * @offset: register offset to be read
547 * @data: pointer to the read data
548 *
549 * Acquires semaphore then reads the PHY register at offset using the
550 * kumeran interface. The information retrieved is stored in data.
551 * Release the acquired semaphore before exiting.
552 **/
e1000e_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data)553 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
554 {
555 return __e1000_read_kmrn_reg(hw, offset, data, false);
556 }
557
558 /**
559 * e1000e_read_kmrn_reg_locked - Read kumeran register
560 * @hw: pointer to the HW structure
561 * @offset: register offset to be read
562 * @data: pointer to the read data
563 *
564 * Reads the PHY register at offset using the kumeran interface. The
565 * information retrieved is stored in data.
566 * Assumes semaphore already acquired.
567 **/
e1000e_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)568 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
569 {
570 return __e1000_read_kmrn_reg(hw, offset, data, true);
571 }
572
573 /**
574 * __e1000_write_kmrn_reg - Write kumeran register
575 * @hw: pointer to the HW structure
576 * @offset: register offset to write to
577 * @data: data to write at register offset
578 * @locked: semaphore has already been acquired or not
579 *
580 * Acquires semaphore, if necessary. Then write the data to PHY register
581 * at the offset using the kumeran interface. Release any acquired semaphores
582 * before exiting.
583 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)584 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
585 bool locked)
586 {
587 u32 kmrnctrlsta;
588
589 if (!locked) {
590 s32 ret_val = 0;
591
592 if (!hw->phy.ops.acquire)
593 return 0;
594
595 ret_val = hw->phy.ops.acquire(hw);
596 if (ret_val)
597 return ret_val;
598 }
599
600 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
601 E1000_KMRNCTRLSTA_OFFSET) | data;
602 ew32(KMRNCTRLSTA, kmrnctrlsta);
603 e1e_flush();
604
605 udelay(2);
606
607 if (!locked)
608 hw->phy.ops.release(hw);
609
610 return 0;
611 }
612
613 /**
614 * e1000e_write_kmrn_reg - Write kumeran register
615 * @hw: pointer to the HW structure
616 * @offset: register offset to write to
617 * @data: data to write at register offset
618 *
619 * Acquires semaphore then writes the data to the PHY register at the offset
620 * using the kumeran interface. Release the acquired semaphore before exiting.
621 **/
e1000e_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data)622 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
623 {
624 return __e1000_write_kmrn_reg(hw, offset, data, false);
625 }
626
627 /**
628 * e1000e_write_kmrn_reg_locked - Write kumeran register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
632 *
633 * Write the data to PHY register at the offset using the kumeran interface.
634 * Assumes semaphore already acquired.
635 **/
e1000e_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)636 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
637 {
638 return __e1000_write_kmrn_reg(hw, offset, data, true);
639 }
640
641 /**
642 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
643 * @hw: pointer to the HW structure
644 *
645 * Sets up Carrier-sense on Transmit and downshift values.
646 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)647 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
648 {
649 s32 ret_val;
650 u16 phy_data;
651
652 /* Enable CRS on Tx. This must be set for half-duplex operation. */
653 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
654 if (ret_val)
655 return ret_val;
656
657 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
658
659 /* Enable downshift */
660 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
661
662 return e1e_wphy(hw, I82577_CFG_REG, phy_data);
663 }
664
665 /**
666 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
667 * @hw: pointer to the HW structure
668 *
669 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
670 * and downshift values are set also.
671 **/
e1000e_copper_link_setup_m88(struct e1000_hw * hw)672 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
673 {
674 struct e1000_phy_info *phy = &hw->phy;
675 s32 ret_val;
676 u16 phy_data;
677
678 /* Enable CRS on Tx. This must be set for half-duplex operation. */
679 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
680 if (ret_val)
681 return ret_val;
682
683 /* For BM PHY this bit is downshift enable */
684 if (phy->type != e1000_phy_bm)
685 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
686
687 /*
688 * Options:
689 * MDI/MDI-X = 0 (default)
690 * 0 - Auto for all speeds
691 * 1 - MDI mode
692 * 2 - MDI-X mode
693 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
694 */
695 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
696
697 switch (phy->mdix) {
698 case 1:
699 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
700 break;
701 case 2:
702 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
703 break;
704 case 3:
705 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
706 break;
707 case 0:
708 default:
709 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
710 break;
711 }
712
713 /*
714 * Options:
715 * disable_polarity_correction = 0 (default)
716 * Automatic Correction for Reversed Cable Polarity
717 * 0 - Disabled
718 * 1 - Enabled
719 */
720 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
721 if (phy->disable_polarity_correction == 1)
722 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
723
724 /* Enable downshift on BM (disabled by default) */
725 if (phy->type == e1000_phy_bm)
726 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
727
728 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
729 if (ret_val)
730 return ret_val;
731
732 if ((phy->type == e1000_phy_m88) &&
733 (phy->revision < E1000_REVISION_4) &&
734 (phy->id != BME1000_E_PHY_ID_R2)) {
735 /*
736 * Force TX_CLK in the Extended PHY Specific Control Register
737 * to 25MHz clock.
738 */
739 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
740 if (ret_val)
741 return ret_val;
742
743 phy_data |= M88E1000_EPSCR_TX_CLK_25;
744
745 if ((phy->revision == 2) &&
746 (phy->id == M88E1111_I_PHY_ID)) {
747 /* 82573L PHY - set the downshift counter to 5x. */
748 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
749 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
750 } else {
751 /* Configure Master and Slave downshift values */
752 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
753 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
754 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
755 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
756 }
757 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
758 if (ret_val)
759 return ret_val;
760 }
761
762 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
763 /* Set PHY page 0, register 29 to 0x0003 */
764 ret_val = e1e_wphy(hw, 29, 0x0003);
765 if (ret_val)
766 return ret_val;
767
768 /* Set PHY page 0, register 30 to 0x0000 */
769 ret_val = e1e_wphy(hw, 30, 0x0000);
770 if (ret_val)
771 return ret_val;
772 }
773
774 /* Commit the changes. */
775 ret_val = e1000e_commit_phy(hw);
776 if (ret_val) {
777 e_dbg("Error committing the PHY changes\n");
778 return ret_val;
779 }
780
781 if (phy->type == e1000_phy_82578) {
782 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
783 if (ret_val)
784 return ret_val;
785
786 /* 82578 PHY - set the downshift count to 1x. */
787 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
788 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
789 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
790 if (ret_val)
791 return ret_val;
792 }
793
794 return 0;
795 }
796
797 /**
798 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
799 * @hw: pointer to the HW structure
800 *
801 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
802 * igp PHY's.
803 **/
e1000e_copper_link_setup_igp(struct e1000_hw * hw)804 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
805 {
806 struct e1000_phy_info *phy = &hw->phy;
807 s32 ret_val;
808 u16 data;
809
810 ret_val = e1000_phy_hw_reset(hw);
811 if (ret_val) {
812 e_dbg("Error resetting the PHY.\n");
813 return ret_val;
814 }
815
816 /*
817 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
818 * timeout issues when LFS is enabled.
819 */
820 msleep(100);
821
822 /* disable lplu d0 during driver init */
823 ret_val = e1000_set_d0_lplu_state(hw, false);
824 if (ret_val) {
825 e_dbg("Error Disabling LPLU D0\n");
826 return ret_val;
827 }
828 /* Configure mdi-mdix settings */
829 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
830 if (ret_val)
831 return ret_val;
832
833 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
834
835 switch (phy->mdix) {
836 case 1:
837 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
838 break;
839 case 2:
840 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
841 break;
842 case 0:
843 default:
844 data |= IGP01E1000_PSCR_AUTO_MDIX;
845 break;
846 }
847 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
848 if (ret_val)
849 return ret_val;
850
851 /* set auto-master slave resolution settings */
852 if (hw->mac.autoneg) {
853 /*
854 * when autonegotiation advertisement is only 1000Mbps then we
855 * should disable SmartSpeed and enable Auto MasterSlave
856 * resolution as hardware default.
857 */
858 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
859 /* Disable SmartSpeed */
860 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
861 &data);
862 if (ret_val)
863 return ret_val;
864
865 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
866 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
867 data);
868 if (ret_val)
869 return ret_val;
870
871 /* Set auto Master/Slave resolution process */
872 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
873 if (ret_val)
874 return ret_val;
875
876 data &= ~CR_1000T_MS_ENABLE;
877 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
878 if (ret_val)
879 return ret_val;
880 }
881
882 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
883 if (ret_val)
884 return ret_val;
885
886 /* load defaults for future use */
887 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
888 ((data & CR_1000T_MS_VALUE) ?
889 e1000_ms_force_master :
890 e1000_ms_force_slave) :
891 e1000_ms_auto;
892
893 switch (phy->ms_type) {
894 case e1000_ms_force_master:
895 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
896 break;
897 case e1000_ms_force_slave:
898 data |= CR_1000T_MS_ENABLE;
899 data &= ~(CR_1000T_MS_VALUE);
900 break;
901 case e1000_ms_auto:
902 data &= ~CR_1000T_MS_ENABLE;
903 default:
904 break;
905 }
906 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
907 }
908
909 return ret_val;
910 }
911
912 /**
913 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
914 * @hw: pointer to the HW structure
915 *
916 * Reads the MII auto-neg advertisement register and/or the 1000T control
917 * register and if the PHY is already setup for auto-negotiation, then
918 * return successful. Otherwise, setup advertisement and flow control to
919 * the appropriate values for the wanted auto-negotiation.
920 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)921 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
922 {
923 struct e1000_phy_info *phy = &hw->phy;
924 s32 ret_val;
925 u16 mii_autoneg_adv_reg;
926 u16 mii_1000t_ctrl_reg = 0;
927
928 phy->autoneg_advertised &= phy->autoneg_mask;
929
930 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
931 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
932 if (ret_val)
933 return ret_val;
934
935 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
936 /* Read the MII 1000Base-T Control Register (Address 9). */
937 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
938 if (ret_val)
939 return ret_val;
940 }
941
942 /*
943 * Need to parse both autoneg_advertised and fc and set up
944 * the appropriate PHY registers. First we will parse for
945 * autoneg_advertised software override. Since we can advertise
946 * a plethora of combinations, we need to check each bit
947 * individually.
948 */
949
950 /*
951 * First we clear all the 10/100 mb speed bits in the Auto-Neg
952 * Advertisement Register (Address 4) and the 1000 mb speed bits in
953 * the 1000Base-T Control Register (Address 9).
954 */
955 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
956 NWAY_AR_100TX_HD_CAPS |
957 NWAY_AR_10T_FD_CAPS |
958 NWAY_AR_10T_HD_CAPS);
959 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
960
961 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
962
963 /* Do we want to advertise 10 Mb Half Duplex? */
964 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
965 e_dbg("Advertise 10mb Half duplex\n");
966 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
967 }
968
969 /* Do we want to advertise 10 Mb Full Duplex? */
970 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
971 e_dbg("Advertise 10mb Full duplex\n");
972 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
973 }
974
975 /* Do we want to advertise 100 Mb Half Duplex? */
976 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
977 e_dbg("Advertise 100mb Half duplex\n");
978 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
979 }
980
981 /* Do we want to advertise 100 Mb Full Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
983 e_dbg("Advertise 100mb Full duplex\n");
984 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
985 }
986
987 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
988 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
989 e_dbg("Advertise 1000mb Half duplex request denied!\n");
990
991 /* Do we want to advertise 1000 Mb Full Duplex? */
992 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
993 e_dbg("Advertise 1000mb Full duplex\n");
994 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
995 }
996
997 /*
998 * Check for a software override of the flow control settings, and
999 * setup the PHY advertisement registers accordingly. If
1000 * auto-negotiation is enabled, then software will have to set the
1001 * "PAUSE" bits to the correct value in the Auto-Negotiation
1002 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1003 * negotiation.
1004 *
1005 * The possible values of the "fc" parameter are:
1006 * 0: Flow control is completely disabled
1007 * 1: Rx flow control is enabled (we can receive pause frames
1008 * but not send pause frames).
1009 * 2: Tx flow control is enabled (we can send pause frames
1010 * but we do not support receiving pause frames).
1011 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1012 * other: No software override. The flow control configuration
1013 * in the EEPROM is used.
1014 */
1015 switch (hw->fc.current_mode) {
1016 case e1000_fc_none:
1017 /*
1018 * Flow control (Rx & Tx) is completely disabled by a
1019 * software over-ride.
1020 */
1021 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1022 break;
1023 case e1000_fc_rx_pause:
1024 /*
1025 * Rx Flow control is enabled, and Tx Flow control is
1026 * disabled, by a software over-ride.
1027 *
1028 * Since there really isn't a way to advertise that we are
1029 * capable of Rx Pause ONLY, we will advertise that we
1030 * support both symmetric and asymmetric Rx PAUSE. Later
1031 * (in e1000e_config_fc_after_link_up) we will disable the
1032 * hw's ability to send PAUSE frames.
1033 */
1034 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1035 break;
1036 case e1000_fc_tx_pause:
1037 /*
1038 * Tx Flow control is enabled, and Rx Flow control is
1039 * disabled, by a software over-ride.
1040 */
1041 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1042 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1043 break;
1044 case e1000_fc_full:
1045 /*
1046 * Flow control (both Rx and Tx) is enabled by a software
1047 * over-ride.
1048 */
1049 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1050 break;
1051 default:
1052 e_dbg("Flow control param set incorrectly\n");
1053 return -E1000_ERR_CONFIG;
1054 }
1055
1056 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1057 if (ret_val)
1058 return ret_val;
1059
1060 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1061
1062 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1063 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1064
1065 return ret_val;
1066 }
1067
1068 /**
1069 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1070 * @hw: pointer to the HW structure
1071 *
1072 * Performs initial bounds checking on autoneg advertisement parameter, then
1073 * configure to advertise the full capability. Setup the PHY to autoneg
1074 * and restart the negotiation process between the link partner. If
1075 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1076 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1077 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1078 {
1079 struct e1000_phy_info *phy = &hw->phy;
1080 s32 ret_val;
1081 u16 phy_ctrl;
1082
1083 /*
1084 * Perform some bounds checking on the autoneg advertisement
1085 * parameter.
1086 */
1087 phy->autoneg_advertised &= phy->autoneg_mask;
1088
1089 /*
1090 * If autoneg_advertised is zero, we assume it was not defaulted
1091 * by the calling code so we set to advertise full capability.
1092 */
1093 if (phy->autoneg_advertised == 0)
1094 phy->autoneg_advertised = phy->autoneg_mask;
1095
1096 e_dbg("Reconfiguring auto-neg advertisement params\n");
1097 ret_val = e1000_phy_setup_autoneg(hw);
1098 if (ret_val) {
1099 e_dbg("Error Setting up Auto-Negotiation\n");
1100 return ret_val;
1101 }
1102 e_dbg("Restarting Auto-Neg\n");
1103
1104 /*
1105 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1106 * the Auto Neg Restart bit in the PHY control register.
1107 */
1108 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1109 if (ret_val)
1110 return ret_val;
1111
1112 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1113 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1114 if (ret_val)
1115 return ret_val;
1116
1117 /*
1118 * Does the user want to wait for Auto-Neg to complete here, or
1119 * check at a later time (for example, callback routine).
1120 */
1121 if (phy->autoneg_wait_to_complete) {
1122 ret_val = e1000_wait_autoneg(hw);
1123 if (ret_val) {
1124 e_dbg("Error while waiting for autoneg to complete\n");
1125 return ret_val;
1126 }
1127 }
1128
1129 hw->mac.get_link_status = true;
1130
1131 return ret_val;
1132 }
1133
1134 /**
1135 * e1000e_setup_copper_link - Configure copper link settings
1136 * @hw: pointer to the HW structure
1137 *
1138 * Calls the appropriate function to configure the link for auto-neg or forced
1139 * speed and duplex. Then we check for link, once link is established calls
1140 * to configure collision distance and flow control are called. If link is
1141 * not established, we return -E1000_ERR_PHY (-2).
1142 **/
e1000e_setup_copper_link(struct e1000_hw * hw)1143 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1144 {
1145 s32 ret_val;
1146 bool link;
1147
1148 if (hw->mac.autoneg) {
1149 /*
1150 * Setup autoneg and flow control advertisement and perform
1151 * autonegotiation.
1152 */
1153 ret_val = e1000_copper_link_autoneg(hw);
1154 if (ret_val)
1155 return ret_val;
1156 } else {
1157 /*
1158 * PHY will be set to 10H, 10F, 100H or 100F
1159 * depending on user settings.
1160 */
1161 e_dbg("Forcing Speed and Duplex\n");
1162 ret_val = e1000_phy_force_speed_duplex(hw);
1163 if (ret_val) {
1164 e_dbg("Error Forcing Speed and Duplex\n");
1165 return ret_val;
1166 }
1167 }
1168
1169 /*
1170 * Check link status. Wait up to 100 microseconds for link to become
1171 * valid.
1172 */
1173 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1174 &link);
1175 if (ret_val)
1176 return ret_val;
1177
1178 if (link) {
1179 e_dbg("Valid link established!!!\n");
1180 hw->mac.ops.config_collision_dist(hw);
1181 ret_val = e1000e_config_fc_after_link_up(hw);
1182 } else {
1183 e_dbg("Unable to establish link!!!\n");
1184 }
1185
1186 return ret_val;
1187 }
1188
1189 /**
1190 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1191 * @hw: pointer to the HW structure
1192 *
1193 * Calls the PHY setup function to force speed and duplex. Clears the
1194 * auto-crossover to force MDI manually. Waits for link and returns
1195 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1196 **/
e1000e_phy_force_speed_duplex_igp(struct e1000_hw * hw)1197 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1198 {
1199 struct e1000_phy_info *phy = &hw->phy;
1200 s32 ret_val;
1201 u16 phy_data;
1202 bool link;
1203
1204 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1205 if (ret_val)
1206 return ret_val;
1207
1208 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1209
1210 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1211 if (ret_val)
1212 return ret_val;
1213
1214 /*
1215 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1216 * forced whenever speed and duplex are forced.
1217 */
1218 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1219 if (ret_val)
1220 return ret_val;
1221
1222 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1223 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1224
1225 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1226 if (ret_val)
1227 return ret_val;
1228
1229 e_dbg("IGP PSCR: %X\n", phy_data);
1230
1231 udelay(1);
1232
1233 if (phy->autoneg_wait_to_complete) {
1234 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1235
1236 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1237 100000, &link);
1238 if (ret_val)
1239 return ret_val;
1240
1241 if (!link)
1242 e_dbg("Link taking longer than expected.\n");
1243
1244 /* Try once more */
1245 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1246 100000, &link);
1247 }
1248
1249 return ret_val;
1250 }
1251
1252 /**
1253 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1254 * @hw: pointer to the HW structure
1255 *
1256 * Calls the PHY setup function to force speed and duplex. Clears the
1257 * auto-crossover to force MDI manually. Resets the PHY to commit the
1258 * changes. If time expires while waiting for link up, we reset the DSP.
1259 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1260 * successful completion, else return corresponding error code.
1261 **/
e1000e_phy_force_speed_duplex_m88(struct e1000_hw * hw)1262 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1263 {
1264 struct e1000_phy_info *phy = &hw->phy;
1265 s32 ret_val;
1266 u16 phy_data;
1267 bool link;
1268
1269 /*
1270 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1271 * forced whenever speed and duplex are forced.
1272 */
1273 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1274 if (ret_val)
1275 return ret_val;
1276
1277 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1278 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1279 if (ret_val)
1280 return ret_val;
1281
1282 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1283
1284 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1285 if (ret_val)
1286 return ret_val;
1287
1288 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1289
1290 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1291 if (ret_val)
1292 return ret_val;
1293
1294 /* Reset the phy to commit changes. */
1295 ret_val = e1000e_commit_phy(hw);
1296 if (ret_val)
1297 return ret_val;
1298
1299 if (phy->autoneg_wait_to_complete) {
1300 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1301
1302 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1303 100000, &link);
1304 if (ret_val)
1305 return ret_val;
1306
1307 if (!link) {
1308 if (hw->phy.type != e1000_phy_m88) {
1309 e_dbg("Link taking longer than expected.\n");
1310 } else {
1311 /*
1312 * We didn't get link.
1313 * Reset the DSP and cross our fingers.
1314 */
1315 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1316 0x001d);
1317 if (ret_val)
1318 return ret_val;
1319 ret_val = e1000e_phy_reset_dsp(hw);
1320 if (ret_val)
1321 return ret_val;
1322 }
1323 }
1324
1325 /* Try once more */
1326 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1327 100000, &link);
1328 if (ret_val)
1329 return ret_val;
1330 }
1331
1332 if (hw->phy.type != e1000_phy_m88)
1333 return 0;
1334
1335 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1336 if (ret_val)
1337 return ret_val;
1338
1339 /*
1340 * Resetting the phy means we need to re-force TX_CLK in the
1341 * Extended PHY Specific Control Register to 25MHz clock from
1342 * the reset value of 2.5MHz.
1343 */
1344 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1345 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1346 if (ret_val)
1347 return ret_val;
1348
1349 /*
1350 * In addition, we must re-enable CRS on Tx for both half and full
1351 * duplex.
1352 */
1353 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1354 if (ret_val)
1355 return ret_val;
1356
1357 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1358 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1359
1360 return ret_val;
1361 }
1362
1363 /**
1364 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1365 * @hw: pointer to the HW structure
1366 *
1367 * Forces the speed and duplex settings of the PHY.
1368 * This is a function pointer entry point only called by
1369 * PHY setup routines.
1370 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1371 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1372 {
1373 struct e1000_phy_info *phy = &hw->phy;
1374 s32 ret_val;
1375 u16 data;
1376 bool link;
1377
1378 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1379 if (ret_val)
1380 return ret_val;
1381
1382 e1000e_phy_force_speed_duplex_setup(hw, &data);
1383
1384 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1385 if (ret_val)
1386 return ret_val;
1387
1388 /* Disable MDI-X support for 10/100 */
1389 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1390 if (ret_val)
1391 return ret_val;
1392
1393 data &= ~IFE_PMC_AUTO_MDIX;
1394 data &= ~IFE_PMC_FORCE_MDIX;
1395
1396 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1397 if (ret_val)
1398 return ret_val;
1399
1400 e_dbg("IFE PMC: %X\n", data);
1401
1402 udelay(1);
1403
1404 if (phy->autoneg_wait_to_complete) {
1405 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1406
1407 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1408 100000, &link);
1409 if (ret_val)
1410 return ret_val;
1411
1412 if (!link)
1413 e_dbg("Link taking longer than expected.\n");
1414
1415 /* Try once more */
1416 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1417 100000, &link);
1418 if (ret_val)
1419 return ret_val;
1420 }
1421
1422 return 0;
1423 }
1424
1425 /**
1426 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1427 * @hw: pointer to the HW structure
1428 * @phy_ctrl: pointer to current value of PHY_CONTROL
1429 *
1430 * Forces speed and duplex on the PHY by doing the following: disable flow
1431 * control, force speed/duplex on the MAC, disable auto speed detection,
1432 * disable auto-negotiation, configure duplex, configure speed, configure
1433 * the collision distance, write configuration to CTRL register. The
1434 * caller must write to the PHY_CONTROL register for these settings to
1435 * take affect.
1436 **/
e1000e_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1437 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1438 {
1439 struct e1000_mac_info *mac = &hw->mac;
1440 u32 ctrl;
1441
1442 /* Turn off flow control when forcing speed/duplex */
1443 hw->fc.current_mode = e1000_fc_none;
1444
1445 /* Force speed/duplex on the mac */
1446 ctrl = er32(CTRL);
1447 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1448 ctrl &= ~E1000_CTRL_SPD_SEL;
1449
1450 /* Disable Auto Speed Detection */
1451 ctrl &= ~E1000_CTRL_ASDE;
1452
1453 /* Disable autoneg on the phy */
1454 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1455
1456 /* Forcing Full or Half Duplex? */
1457 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1458 ctrl &= ~E1000_CTRL_FD;
1459 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1460 e_dbg("Half Duplex\n");
1461 } else {
1462 ctrl |= E1000_CTRL_FD;
1463 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1464 e_dbg("Full Duplex\n");
1465 }
1466
1467 /* Forcing 10mb or 100mb? */
1468 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1469 ctrl |= E1000_CTRL_SPD_100;
1470 *phy_ctrl |= MII_CR_SPEED_100;
1471 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1472 e_dbg("Forcing 100mb\n");
1473 } else {
1474 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1475 *phy_ctrl |= MII_CR_SPEED_10;
1476 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1477 e_dbg("Forcing 10mb\n");
1478 }
1479
1480 hw->mac.ops.config_collision_dist(hw);
1481
1482 ew32(CTRL, ctrl);
1483 }
1484
1485 /**
1486 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1487 * @hw: pointer to the HW structure
1488 * @active: boolean used to enable/disable lplu
1489 *
1490 * Success returns 0, Failure returns 1
1491 *
1492 * The low power link up (lplu) state is set to the power management level D3
1493 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1494 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1495 * is used during Dx states where the power conservation is most important.
1496 * During driver activity, SmartSpeed should be enabled so performance is
1497 * maintained.
1498 **/
e1000e_set_d3_lplu_state(struct e1000_hw * hw,bool active)1499 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1500 {
1501 struct e1000_phy_info *phy = &hw->phy;
1502 s32 ret_val;
1503 u16 data;
1504
1505 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1506 if (ret_val)
1507 return ret_val;
1508
1509 if (!active) {
1510 data &= ~IGP02E1000_PM_D3_LPLU;
1511 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1512 if (ret_val)
1513 return ret_val;
1514 /*
1515 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1516 * during Dx states where the power conservation is most
1517 * important. During driver activity we should enable
1518 * SmartSpeed, so performance is maintained.
1519 */
1520 if (phy->smart_speed == e1000_smart_speed_on) {
1521 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1522 &data);
1523 if (ret_val)
1524 return ret_val;
1525
1526 data |= IGP01E1000_PSCFR_SMART_SPEED;
1527 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1528 data);
1529 if (ret_val)
1530 return ret_val;
1531 } else if (phy->smart_speed == e1000_smart_speed_off) {
1532 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1533 &data);
1534 if (ret_val)
1535 return ret_val;
1536
1537 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1538 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1539 data);
1540 if (ret_val)
1541 return ret_val;
1542 }
1543 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1544 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1545 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1546 data |= IGP02E1000_PM_D3_LPLU;
1547 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1548 if (ret_val)
1549 return ret_val;
1550
1551 /* When LPLU is enabled, we should disable SmartSpeed */
1552 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1553 if (ret_val)
1554 return ret_val;
1555
1556 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1557 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1558 }
1559
1560 return ret_val;
1561 }
1562
1563 /**
1564 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1565 * @hw: pointer to the HW structure
1566 *
1567 * Success returns 0, Failure returns 1
1568 *
1569 * A downshift is detected by querying the PHY link health.
1570 **/
e1000e_check_downshift(struct e1000_hw * hw)1571 s32 e1000e_check_downshift(struct e1000_hw *hw)
1572 {
1573 struct e1000_phy_info *phy = &hw->phy;
1574 s32 ret_val;
1575 u16 phy_data, offset, mask;
1576
1577 switch (phy->type) {
1578 case e1000_phy_m88:
1579 case e1000_phy_gg82563:
1580 case e1000_phy_bm:
1581 case e1000_phy_82578:
1582 offset = M88E1000_PHY_SPEC_STATUS;
1583 mask = M88E1000_PSSR_DOWNSHIFT;
1584 break;
1585 case e1000_phy_igp_2:
1586 case e1000_phy_igp_3:
1587 offset = IGP01E1000_PHY_LINK_HEALTH;
1588 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1589 break;
1590 default:
1591 /* speed downshift not supported */
1592 phy->speed_downgraded = false;
1593 return 0;
1594 }
1595
1596 ret_val = e1e_rphy(hw, offset, &phy_data);
1597
1598 if (!ret_val)
1599 phy->speed_downgraded = (phy_data & mask);
1600
1601 return ret_val;
1602 }
1603
1604 /**
1605 * e1000_check_polarity_m88 - Checks the polarity.
1606 * @hw: pointer to the HW structure
1607 *
1608 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1609 *
1610 * Polarity is determined based on the PHY specific status register.
1611 **/
e1000_check_polarity_m88(struct e1000_hw * hw)1612 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1613 {
1614 struct e1000_phy_info *phy = &hw->phy;
1615 s32 ret_val;
1616 u16 data;
1617
1618 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1619
1620 if (!ret_val)
1621 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1622 ? e1000_rev_polarity_reversed
1623 : e1000_rev_polarity_normal;
1624
1625 return ret_val;
1626 }
1627
1628 /**
1629 * e1000_check_polarity_igp - Checks the polarity.
1630 * @hw: pointer to the HW structure
1631 *
1632 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1633 *
1634 * Polarity is determined based on the PHY port status register, and the
1635 * current speed (since there is no polarity at 100Mbps).
1636 **/
e1000_check_polarity_igp(struct e1000_hw * hw)1637 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1638 {
1639 struct e1000_phy_info *phy = &hw->phy;
1640 s32 ret_val;
1641 u16 data, offset, mask;
1642
1643 /*
1644 * Polarity is determined based on the speed of
1645 * our connection.
1646 */
1647 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1648 if (ret_val)
1649 return ret_val;
1650
1651 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1652 IGP01E1000_PSSR_SPEED_1000MBPS) {
1653 offset = IGP01E1000_PHY_PCS_INIT_REG;
1654 mask = IGP01E1000_PHY_POLARITY_MASK;
1655 } else {
1656 /*
1657 * This really only applies to 10Mbps since
1658 * there is no polarity for 100Mbps (always 0).
1659 */
1660 offset = IGP01E1000_PHY_PORT_STATUS;
1661 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1662 }
1663
1664 ret_val = e1e_rphy(hw, offset, &data);
1665
1666 if (!ret_val)
1667 phy->cable_polarity = (data & mask)
1668 ? e1000_rev_polarity_reversed
1669 : e1000_rev_polarity_normal;
1670
1671 return ret_val;
1672 }
1673
1674 /**
1675 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1676 * @hw: pointer to the HW structure
1677 *
1678 * Polarity is determined on the polarity reversal feature being enabled.
1679 **/
e1000_check_polarity_ife(struct e1000_hw * hw)1680 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1681 {
1682 struct e1000_phy_info *phy = &hw->phy;
1683 s32 ret_val;
1684 u16 phy_data, offset, mask;
1685
1686 /*
1687 * Polarity is determined based on the reversal feature being enabled.
1688 */
1689 if (phy->polarity_correction) {
1690 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1691 mask = IFE_PESC_POLARITY_REVERSED;
1692 } else {
1693 offset = IFE_PHY_SPECIAL_CONTROL;
1694 mask = IFE_PSC_FORCE_POLARITY;
1695 }
1696
1697 ret_val = e1e_rphy(hw, offset, &phy_data);
1698
1699 if (!ret_val)
1700 phy->cable_polarity = (phy_data & mask)
1701 ? e1000_rev_polarity_reversed
1702 : e1000_rev_polarity_normal;
1703
1704 return ret_val;
1705 }
1706
1707 /**
1708 * e1000_wait_autoneg - Wait for auto-neg completion
1709 * @hw: pointer to the HW structure
1710 *
1711 * Waits for auto-negotiation to complete or for the auto-negotiation time
1712 * limit to expire, which ever happens first.
1713 **/
e1000_wait_autoneg(struct e1000_hw * hw)1714 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1715 {
1716 s32 ret_val = 0;
1717 u16 i, phy_status;
1718
1719 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1720 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1721 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1722 if (ret_val)
1723 break;
1724 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1725 if (ret_val)
1726 break;
1727 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1728 break;
1729 msleep(100);
1730 }
1731
1732 /*
1733 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1734 * has completed.
1735 */
1736 return ret_val;
1737 }
1738
1739 /**
1740 * e1000e_phy_has_link_generic - Polls PHY for link
1741 * @hw: pointer to the HW structure
1742 * @iterations: number of times to poll for link
1743 * @usec_interval: delay between polling attempts
1744 * @success: pointer to whether polling was successful or not
1745 *
1746 * Polls the PHY status register for link, 'iterations' number of times.
1747 **/
e1000e_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1748 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1749 u32 usec_interval, bool *success)
1750 {
1751 s32 ret_val = 0;
1752 u16 i, phy_status;
1753
1754 for (i = 0; i < iterations; i++) {
1755 /*
1756 * Some PHYs require the PHY_STATUS register to be read
1757 * twice due to the link bit being sticky. No harm doing
1758 * it across the board.
1759 */
1760 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1761 if (ret_val)
1762 /*
1763 * If the first read fails, another entity may have
1764 * ownership of the resources, wait and try again to
1765 * see if they have relinquished the resources yet.
1766 */
1767 udelay(usec_interval);
1768 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1769 if (ret_val)
1770 break;
1771 if (phy_status & MII_SR_LINK_STATUS)
1772 break;
1773 if (usec_interval >= 1000)
1774 mdelay(usec_interval/1000);
1775 else
1776 udelay(usec_interval);
1777 }
1778
1779 *success = (i < iterations);
1780
1781 return ret_val;
1782 }
1783
1784 /**
1785 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1786 * @hw: pointer to the HW structure
1787 *
1788 * Reads the PHY specific status register to retrieve the cable length
1789 * information. The cable length is determined by averaging the minimum and
1790 * maximum values to get the "average" cable length. The m88 PHY has four
1791 * possible cable length values, which are:
1792 * Register Value Cable Length
1793 * 0 < 50 meters
1794 * 1 50 - 80 meters
1795 * 2 80 - 110 meters
1796 * 3 110 - 140 meters
1797 * 4 > 140 meters
1798 **/
e1000e_get_cable_length_m88(struct e1000_hw * hw)1799 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1800 {
1801 struct e1000_phy_info *phy = &hw->phy;
1802 s32 ret_val;
1803 u16 phy_data, index;
1804
1805 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1806 if (ret_val)
1807 return ret_val;
1808
1809 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1810 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1811
1812 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1813 return -E1000_ERR_PHY;
1814
1815 phy->min_cable_length = e1000_m88_cable_length_table[index];
1816 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1817
1818 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1819
1820 return 0;
1821 }
1822
1823 /**
1824 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1825 * @hw: pointer to the HW structure
1826 *
1827 * The automatic gain control (agc) normalizes the amplitude of the
1828 * received signal, adjusting for the attenuation produced by the
1829 * cable. By reading the AGC registers, which represent the
1830 * combination of coarse and fine gain value, the value can be put
1831 * into a lookup table to obtain the approximate cable length
1832 * for each channel.
1833 **/
e1000e_get_cable_length_igp_2(struct e1000_hw * hw)1834 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1835 {
1836 struct e1000_phy_info *phy = &hw->phy;
1837 s32 ret_val;
1838 u16 phy_data, i, agc_value = 0;
1839 u16 cur_agc_index, max_agc_index = 0;
1840 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1841 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1842 IGP02E1000_PHY_AGC_A,
1843 IGP02E1000_PHY_AGC_B,
1844 IGP02E1000_PHY_AGC_C,
1845 IGP02E1000_PHY_AGC_D
1846 };
1847
1848 /* Read the AGC registers for all channels */
1849 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1850 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1851 if (ret_val)
1852 return ret_val;
1853
1854 /*
1855 * Getting bits 15:9, which represent the combination of
1856 * coarse and fine gain values. The result is a number
1857 * that can be put into the lookup table to obtain the
1858 * approximate cable length.
1859 */
1860 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1861 IGP02E1000_AGC_LENGTH_MASK;
1862
1863 /* Array index bound check. */
1864 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1865 (cur_agc_index == 0))
1866 return -E1000_ERR_PHY;
1867
1868 /* Remove min & max AGC values from calculation. */
1869 if (e1000_igp_2_cable_length_table[min_agc_index] >
1870 e1000_igp_2_cable_length_table[cur_agc_index])
1871 min_agc_index = cur_agc_index;
1872 if (e1000_igp_2_cable_length_table[max_agc_index] <
1873 e1000_igp_2_cable_length_table[cur_agc_index])
1874 max_agc_index = cur_agc_index;
1875
1876 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1877 }
1878
1879 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1880 e1000_igp_2_cable_length_table[max_agc_index]);
1881 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1882
1883 /* Calculate cable length with the error range of +/- 10 meters. */
1884 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1885 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1886 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1887
1888 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1889
1890 return 0;
1891 }
1892
1893 /**
1894 * e1000e_get_phy_info_m88 - Retrieve PHY information
1895 * @hw: pointer to the HW structure
1896 *
1897 * Valid for only copper links. Read the PHY status register (sticky read)
1898 * to verify that link is up. Read the PHY special control register to
1899 * determine the polarity and 10base-T extended distance. Read the PHY
1900 * special status register to determine MDI/MDIx and current speed. If
1901 * speed is 1000, then determine cable length, local and remote receiver.
1902 **/
e1000e_get_phy_info_m88(struct e1000_hw * hw)1903 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1904 {
1905 struct e1000_phy_info *phy = &hw->phy;
1906 s32 ret_val;
1907 u16 phy_data;
1908 bool link;
1909
1910 if (phy->media_type != e1000_media_type_copper) {
1911 e_dbg("Phy info is only valid for copper media\n");
1912 return -E1000_ERR_CONFIG;
1913 }
1914
1915 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1916 if (ret_val)
1917 return ret_val;
1918
1919 if (!link) {
1920 e_dbg("Phy info is only valid if link is up\n");
1921 return -E1000_ERR_CONFIG;
1922 }
1923
1924 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1925 if (ret_val)
1926 return ret_val;
1927
1928 phy->polarity_correction = (phy_data &
1929 M88E1000_PSCR_POLARITY_REVERSAL);
1930
1931 ret_val = e1000_check_polarity_m88(hw);
1932 if (ret_val)
1933 return ret_val;
1934
1935 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1936 if (ret_val)
1937 return ret_val;
1938
1939 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1940
1941 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1942 ret_val = e1000_get_cable_length(hw);
1943 if (ret_val)
1944 return ret_val;
1945
1946 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1951 ? e1000_1000t_rx_status_ok
1952 : e1000_1000t_rx_status_not_ok;
1953
1954 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1955 ? e1000_1000t_rx_status_ok
1956 : e1000_1000t_rx_status_not_ok;
1957 } else {
1958 /* Set values to "undefined" */
1959 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1960 phy->local_rx = e1000_1000t_rx_status_undefined;
1961 phy->remote_rx = e1000_1000t_rx_status_undefined;
1962 }
1963
1964 return ret_val;
1965 }
1966
1967 /**
1968 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1969 * @hw: pointer to the HW structure
1970 *
1971 * Read PHY status to determine if link is up. If link is up, then
1972 * set/determine 10base-T extended distance and polarity correction. Read
1973 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1974 * determine on the cable length, local and remote receiver.
1975 **/
e1000e_get_phy_info_igp(struct e1000_hw * hw)1976 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1977 {
1978 struct e1000_phy_info *phy = &hw->phy;
1979 s32 ret_val;
1980 u16 data;
1981 bool link;
1982
1983 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1984 if (ret_val)
1985 return ret_val;
1986
1987 if (!link) {
1988 e_dbg("Phy info is only valid if link is up\n");
1989 return -E1000_ERR_CONFIG;
1990 }
1991
1992 phy->polarity_correction = true;
1993
1994 ret_val = e1000_check_polarity_igp(hw);
1995 if (ret_val)
1996 return ret_val;
1997
1998 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1999 if (ret_val)
2000 return ret_val;
2001
2002 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2003
2004 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2005 IGP01E1000_PSSR_SPEED_1000MBPS) {
2006 ret_val = e1000_get_cable_length(hw);
2007 if (ret_val)
2008 return ret_val;
2009
2010 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2011 if (ret_val)
2012 return ret_val;
2013
2014 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2015 ? e1000_1000t_rx_status_ok
2016 : e1000_1000t_rx_status_not_ok;
2017
2018 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2019 ? e1000_1000t_rx_status_ok
2020 : e1000_1000t_rx_status_not_ok;
2021 } else {
2022 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2023 phy->local_rx = e1000_1000t_rx_status_undefined;
2024 phy->remote_rx = e1000_1000t_rx_status_undefined;
2025 }
2026
2027 return ret_val;
2028 }
2029
2030 /**
2031 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2032 * @hw: pointer to the HW structure
2033 *
2034 * Populates "phy" structure with various feature states.
2035 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2036 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2037 {
2038 struct e1000_phy_info *phy = &hw->phy;
2039 s32 ret_val;
2040 u16 data;
2041 bool link;
2042
2043 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2044 if (ret_val)
2045 return ret_val;
2046
2047 if (!link) {
2048 e_dbg("Phy info is only valid if link is up\n");
2049 return -E1000_ERR_CONFIG;
2050 }
2051
2052 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2053 if (ret_val)
2054 return ret_val;
2055 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2056 ? false : true;
2057
2058 if (phy->polarity_correction) {
2059 ret_val = e1000_check_polarity_ife(hw);
2060 if (ret_val)
2061 return ret_val;
2062 } else {
2063 /* Polarity is forced */
2064 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2065 ? e1000_rev_polarity_reversed
2066 : e1000_rev_polarity_normal;
2067 }
2068
2069 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2070 if (ret_val)
2071 return ret_val;
2072
2073 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2074
2075 /* The following parameters are undefined for 10/100 operation. */
2076 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2077 phy->local_rx = e1000_1000t_rx_status_undefined;
2078 phy->remote_rx = e1000_1000t_rx_status_undefined;
2079
2080 return 0;
2081 }
2082
2083 /**
2084 * e1000e_phy_sw_reset - PHY software reset
2085 * @hw: pointer to the HW structure
2086 *
2087 * Does a software reset of the PHY by reading the PHY control register and
2088 * setting/write the control register reset bit to the PHY.
2089 **/
e1000e_phy_sw_reset(struct e1000_hw * hw)2090 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2091 {
2092 s32 ret_val;
2093 u16 phy_ctrl;
2094
2095 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2096 if (ret_val)
2097 return ret_val;
2098
2099 phy_ctrl |= MII_CR_RESET;
2100 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2101 if (ret_val)
2102 return ret_val;
2103
2104 udelay(1);
2105
2106 return ret_val;
2107 }
2108
2109 /**
2110 * e1000e_phy_hw_reset_generic - PHY hardware reset
2111 * @hw: pointer to the HW structure
2112 *
2113 * Verify the reset block is not blocking us from resetting. Acquire
2114 * semaphore (if necessary) and read/set/write the device control reset
2115 * bit in the PHY. Wait the appropriate delay time for the device to
2116 * reset and release the semaphore (if necessary).
2117 **/
e1000e_phy_hw_reset_generic(struct e1000_hw * hw)2118 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2119 {
2120 struct e1000_phy_info *phy = &hw->phy;
2121 s32 ret_val;
2122 u32 ctrl;
2123
2124 if (phy->ops.check_reset_block) {
2125 ret_val = phy->ops.check_reset_block(hw);
2126 if (ret_val)
2127 return 0;
2128 }
2129
2130 ret_val = phy->ops.acquire(hw);
2131 if (ret_val)
2132 return ret_val;
2133
2134 ctrl = er32(CTRL);
2135 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2136 e1e_flush();
2137
2138 udelay(phy->reset_delay_us);
2139
2140 ew32(CTRL, ctrl);
2141 e1e_flush();
2142
2143 udelay(150);
2144
2145 phy->ops.release(hw);
2146
2147 return e1000_get_phy_cfg_done(hw);
2148 }
2149
2150 /**
2151 * e1000e_get_cfg_done - Generic configuration done
2152 * @hw: pointer to the HW structure
2153 *
2154 * Generic function to wait 10 milli-seconds for configuration to complete
2155 * and return success.
2156 **/
e1000e_get_cfg_done(struct e1000_hw * hw)2157 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2158 {
2159 mdelay(10);
2160
2161 return 0;
2162 }
2163
2164 /**
2165 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2166 * @hw: pointer to the HW structure
2167 *
2168 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2169 **/
e1000e_phy_init_script_igp3(struct e1000_hw * hw)2170 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2171 {
2172 e_dbg("Running IGP 3 PHY init script\n");
2173
2174 /* PHY init IGP 3 */
2175 /* Enable rise/fall, 10-mode work in class-A */
2176 e1e_wphy(hw, 0x2F5B, 0x9018);
2177 /* Remove all caps from Replica path filter */
2178 e1e_wphy(hw, 0x2F52, 0x0000);
2179 /* Bias trimming for ADC, AFE and Driver (Default) */
2180 e1e_wphy(hw, 0x2FB1, 0x8B24);
2181 /* Increase Hybrid poly bias */
2182 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2183 /* Add 4% to Tx amplitude in Gig mode */
2184 e1e_wphy(hw, 0x2010, 0x10B0);
2185 /* Disable trimming (TTT) */
2186 e1e_wphy(hw, 0x2011, 0x0000);
2187 /* Poly DC correction to 94.6% + 2% for all channels */
2188 e1e_wphy(hw, 0x20DD, 0x249A);
2189 /* ABS DC correction to 95.9% */
2190 e1e_wphy(hw, 0x20DE, 0x00D3);
2191 /* BG temp curve trim */
2192 e1e_wphy(hw, 0x28B4, 0x04CE);
2193 /* Increasing ADC OPAMP stage 1 currents to max */
2194 e1e_wphy(hw, 0x2F70, 0x29E4);
2195 /* Force 1000 ( required for enabling PHY regs configuration) */
2196 e1e_wphy(hw, 0x0000, 0x0140);
2197 /* Set upd_freq to 6 */
2198 e1e_wphy(hw, 0x1F30, 0x1606);
2199 /* Disable NPDFE */
2200 e1e_wphy(hw, 0x1F31, 0xB814);
2201 /* Disable adaptive fixed FFE (Default) */
2202 e1e_wphy(hw, 0x1F35, 0x002A);
2203 /* Enable FFE hysteresis */
2204 e1e_wphy(hw, 0x1F3E, 0x0067);
2205 /* Fixed FFE for short cable lengths */
2206 e1e_wphy(hw, 0x1F54, 0x0065);
2207 /* Fixed FFE for medium cable lengths */
2208 e1e_wphy(hw, 0x1F55, 0x002A);
2209 /* Fixed FFE for long cable lengths */
2210 e1e_wphy(hw, 0x1F56, 0x002A);
2211 /* Enable Adaptive Clip Threshold */
2212 e1e_wphy(hw, 0x1F72, 0x3FB0);
2213 /* AHT reset limit to 1 */
2214 e1e_wphy(hw, 0x1F76, 0xC0FF);
2215 /* Set AHT master delay to 127 msec */
2216 e1e_wphy(hw, 0x1F77, 0x1DEC);
2217 /* Set scan bits for AHT */
2218 e1e_wphy(hw, 0x1F78, 0xF9EF);
2219 /* Set AHT Preset bits */
2220 e1e_wphy(hw, 0x1F79, 0x0210);
2221 /* Change integ_factor of channel A to 3 */
2222 e1e_wphy(hw, 0x1895, 0x0003);
2223 /* Change prop_factor of channels BCD to 8 */
2224 e1e_wphy(hw, 0x1796, 0x0008);
2225 /* Change cg_icount + enable integbp for channels BCD */
2226 e1e_wphy(hw, 0x1798, 0xD008);
2227 /*
2228 * Change cg_icount + enable integbp + change prop_factor_master
2229 * to 8 for channel A
2230 */
2231 e1e_wphy(hw, 0x1898, 0xD918);
2232 /* Disable AHT in Slave mode on channel A */
2233 e1e_wphy(hw, 0x187A, 0x0800);
2234 /*
2235 * Enable LPLU and disable AN to 1000 in non-D0a states,
2236 * Enable SPD+B2B
2237 */
2238 e1e_wphy(hw, 0x0019, 0x008D);
2239 /* Enable restart AN on an1000_dis change */
2240 e1e_wphy(hw, 0x001B, 0x2080);
2241 /* Enable wh_fifo read clock in 10/100 modes */
2242 e1e_wphy(hw, 0x0014, 0x0045);
2243 /* Restart AN, Speed selection is 1000 */
2244 e1e_wphy(hw, 0x0000, 0x1340);
2245
2246 return 0;
2247 }
2248
2249 /* Internal function pointers */
2250
2251 /**
2252 * e1000_get_phy_cfg_done - Generic PHY configuration done
2253 * @hw: pointer to the HW structure
2254 *
2255 * Return success if silicon family did not implement a family specific
2256 * get_cfg_done function.
2257 **/
e1000_get_phy_cfg_done(struct e1000_hw * hw)2258 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2259 {
2260 if (hw->phy.ops.get_cfg_done)
2261 return hw->phy.ops.get_cfg_done(hw);
2262
2263 return 0;
2264 }
2265
2266 /**
2267 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2268 * @hw: pointer to the HW structure
2269 *
2270 * When the silicon family has not implemented a forced speed/duplex
2271 * function for the PHY, simply return 0.
2272 **/
e1000_phy_force_speed_duplex(struct e1000_hw * hw)2273 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2274 {
2275 if (hw->phy.ops.force_speed_duplex)
2276 return hw->phy.ops.force_speed_duplex(hw);
2277
2278 return 0;
2279 }
2280
2281 /**
2282 * e1000e_get_phy_type_from_id - Get PHY type from id
2283 * @phy_id: phy_id read from the phy
2284 *
2285 * Returns the phy type from the id.
2286 **/
e1000e_get_phy_type_from_id(u32 phy_id)2287 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2288 {
2289 enum e1000_phy_type phy_type = e1000_phy_unknown;
2290
2291 switch (phy_id) {
2292 case M88E1000_I_PHY_ID:
2293 case M88E1000_E_PHY_ID:
2294 case M88E1111_I_PHY_ID:
2295 case M88E1011_I_PHY_ID:
2296 phy_type = e1000_phy_m88;
2297 break;
2298 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2299 phy_type = e1000_phy_igp_2;
2300 break;
2301 case GG82563_E_PHY_ID:
2302 phy_type = e1000_phy_gg82563;
2303 break;
2304 case IGP03E1000_E_PHY_ID:
2305 phy_type = e1000_phy_igp_3;
2306 break;
2307 case IFE_E_PHY_ID:
2308 case IFE_PLUS_E_PHY_ID:
2309 case IFE_C_E_PHY_ID:
2310 phy_type = e1000_phy_ife;
2311 break;
2312 case BME1000_E_PHY_ID:
2313 case BME1000_E_PHY_ID_R2:
2314 phy_type = e1000_phy_bm;
2315 break;
2316 case I82578_E_PHY_ID:
2317 phy_type = e1000_phy_82578;
2318 break;
2319 case I82577_E_PHY_ID:
2320 phy_type = e1000_phy_82577;
2321 break;
2322 case I82579_E_PHY_ID:
2323 phy_type = e1000_phy_82579;
2324 break;
2325 default:
2326 phy_type = e1000_phy_unknown;
2327 break;
2328 }
2329 return phy_type;
2330 }
2331
2332 /**
2333 * e1000e_determine_phy_address - Determines PHY address.
2334 * @hw: pointer to the HW structure
2335 *
2336 * This uses a trial and error method to loop through possible PHY
2337 * addresses. It tests each by reading the PHY ID registers and
2338 * checking for a match.
2339 **/
e1000e_determine_phy_address(struct e1000_hw * hw)2340 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2341 {
2342 u32 phy_addr = 0;
2343 u32 i;
2344 enum e1000_phy_type phy_type = e1000_phy_unknown;
2345
2346 hw->phy.id = phy_type;
2347
2348 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2349 hw->phy.addr = phy_addr;
2350 i = 0;
2351
2352 do {
2353 e1000e_get_phy_id(hw);
2354 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2355
2356 /*
2357 * If phy_type is valid, break - we found our
2358 * PHY address
2359 */
2360 if (phy_type != e1000_phy_unknown)
2361 return 0;
2362
2363 usleep_range(1000, 2000);
2364 i++;
2365 } while (i < 10);
2366 }
2367
2368 return -E1000_ERR_PHY_TYPE;
2369 }
2370
2371 /**
2372 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2373 * @page: page to access
2374 *
2375 * Returns the phy address for the page requested.
2376 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)2377 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2378 {
2379 u32 phy_addr = 2;
2380
2381 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2382 phy_addr = 1;
2383
2384 return phy_addr;
2385 }
2386
2387 /**
2388 * e1000e_write_phy_reg_bm - Write BM PHY register
2389 * @hw: pointer to the HW structure
2390 * @offset: register offset to write to
2391 * @data: data to write at register offset
2392 *
2393 * Acquires semaphore, if necessary, then writes the data to PHY register
2394 * at the offset. Release any acquired semaphores before exiting.
2395 **/
e1000e_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)2396 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2397 {
2398 s32 ret_val;
2399 u32 page = offset >> IGP_PAGE_SHIFT;
2400
2401 ret_val = hw->phy.ops.acquire(hw);
2402 if (ret_val)
2403 return ret_val;
2404
2405 /* Page 800 works differently than the rest so it has its own func */
2406 if (page == BM_WUC_PAGE) {
2407 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2408 false, false);
2409 goto release;
2410 }
2411
2412 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2413
2414 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2415 u32 page_shift, page_select;
2416
2417 /*
2418 * Page select is register 31 for phy address 1 and 22 for
2419 * phy address 2 and 3. Page select is shifted only for
2420 * phy address 1.
2421 */
2422 if (hw->phy.addr == 1) {
2423 page_shift = IGP_PAGE_SHIFT;
2424 page_select = IGP01E1000_PHY_PAGE_SELECT;
2425 } else {
2426 page_shift = 0;
2427 page_select = BM_PHY_PAGE_SELECT;
2428 }
2429
2430 /* Page is shifted left, PHY expects (page x 32) */
2431 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2432 (page << page_shift));
2433 if (ret_val)
2434 goto release;
2435 }
2436
2437 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2438 data);
2439
2440 release:
2441 hw->phy.ops.release(hw);
2442 return ret_val;
2443 }
2444
2445 /**
2446 * e1000e_read_phy_reg_bm - Read BM PHY register
2447 * @hw: pointer to the HW structure
2448 * @offset: register offset to be read
2449 * @data: pointer to the read data
2450 *
2451 * Acquires semaphore, if necessary, then reads the PHY register at offset
2452 * and storing the retrieved information in data. Release any acquired
2453 * semaphores before exiting.
2454 **/
e1000e_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)2455 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2456 {
2457 s32 ret_val;
2458 u32 page = offset >> IGP_PAGE_SHIFT;
2459
2460 ret_val = hw->phy.ops.acquire(hw);
2461 if (ret_val)
2462 return ret_val;
2463
2464 /* Page 800 works differently than the rest so it has its own func */
2465 if (page == BM_WUC_PAGE) {
2466 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2467 true, false);
2468 goto release;
2469 }
2470
2471 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2472
2473 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2474 u32 page_shift, page_select;
2475
2476 /*
2477 * Page select is register 31 for phy address 1 and 22 for
2478 * phy address 2 and 3. Page select is shifted only for
2479 * phy address 1.
2480 */
2481 if (hw->phy.addr == 1) {
2482 page_shift = IGP_PAGE_SHIFT;
2483 page_select = IGP01E1000_PHY_PAGE_SELECT;
2484 } else {
2485 page_shift = 0;
2486 page_select = BM_PHY_PAGE_SELECT;
2487 }
2488
2489 /* Page is shifted left, PHY expects (page x 32) */
2490 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2491 (page << page_shift));
2492 if (ret_val)
2493 goto release;
2494 }
2495
2496 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2497 data);
2498 release:
2499 hw->phy.ops.release(hw);
2500 return ret_val;
2501 }
2502
2503 /**
2504 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2505 * @hw: pointer to the HW structure
2506 * @offset: register offset to be read
2507 * @data: pointer to the read data
2508 *
2509 * Acquires semaphore, if necessary, then reads the PHY register at offset
2510 * and storing the retrieved information in data. Release any acquired
2511 * semaphores before exiting.
2512 **/
e1000e_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)2513 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2514 {
2515 s32 ret_val;
2516 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2517
2518 ret_val = hw->phy.ops.acquire(hw);
2519 if (ret_val)
2520 return ret_val;
2521
2522 /* Page 800 works differently than the rest so it has its own func */
2523 if (page == BM_WUC_PAGE) {
2524 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2525 true, false);
2526 goto release;
2527 }
2528
2529 hw->phy.addr = 1;
2530
2531 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2532
2533 /* Page is shifted left, PHY expects (page x 32) */
2534 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2535 page);
2536
2537 if (ret_val)
2538 goto release;
2539 }
2540
2541 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2542 data);
2543 release:
2544 hw->phy.ops.release(hw);
2545 return ret_val;
2546 }
2547
2548 /**
2549 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2550 * @hw: pointer to the HW structure
2551 * @offset: register offset to write to
2552 * @data: data to write at register offset
2553 *
2554 * Acquires semaphore, if necessary, then writes the data to PHY register
2555 * at the offset. Release any acquired semaphores before exiting.
2556 **/
e1000e_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)2557 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2558 {
2559 s32 ret_val;
2560 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2561
2562 ret_val = hw->phy.ops.acquire(hw);
2563 if (ret_val)
2564 return ret_val;
2565
2566 /* Page 800 works differently than the rest so it has its own func */
2567 if (page == BM_WUC_PAGE) {
2568 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2569 false, false);
2570 goto release;
2571 }
2572
2573 hw->phy.addr = 1;
2574
2575 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2576 /* Page is shifted left, PHY expects (page x 32) */
2577 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2578 page);
2579
2580 if (ret_val)
2581 goto release;
2582 }
2583
2584 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2585 data);
2586
2587 release:
2588 hw->phy.ops.release(hw);
2589 return ret_val;
2590 }
2591
2592 /**
2593 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2594 * @hw: pointer to the HW structure
2595 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2596 *
2597 * Assumes semaphore already acquired and phy_reg points to a valid memory
2598 * address to store contents of the BM_WUC_ENABLE_REG register.
2599 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2600 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2601 {
2602 s32 ret_val;
2603 u16 temp;
2604
2605 /* All page select, port ctrl and wakeup registers use phy address 1 */
2606 hw->phy.addr = 1;
2607
2608 /* Select Port Control Registers page */
2609 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2610 if (ret_val) {
2611 e_dbg("Could not set Port Control page\n");
2612 return ret_val;
2613 }
2614
2615 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2616 if (ret_val) {
2617 e_dbg("Could not read PHY register %d.%d\n",
2618 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2619 return ret_val;
2620 }
2621
2622 /*
2623 * Enable both PHY wakeup mode and Wakeup register page writes.
2624 * Prevent a power state change by disabling ME and Host PHY wakeup.
2625 */
2626 temp = *phy_reg;
2627 temp |= BM_WUC_ENABLE_BIT;
2628 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2629
2630 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2631 if (ret_val) {
2632 e_dbg("Could not write PHY register %d.%d\n",
2633 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2634 return ret_val;
2635 }
2636
2637 /*
2638 * Select Host Wakeup Registers page - caller now able to write
2639 * registers on the Wakeup registers page
2640 */
2641 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2642 }
2643
2644 /**
2645 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2646 * @hw: pointer to the HW structure
2647 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2648 *
2649 * Restore BM_WUC_ENABLE_REG to its original value.
2650 *
2651 * Assumes semaphore already acquired and *phy_reg is the contents of the
2652 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2653 * caller.
2654 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2655 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2656 {
2657 s32 ret_val = 0;
2658
2659 /* Select Port Control Registers page */
2660 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2661 if (ret_val) {
2662 e_dbg("Could not set Port Control page\n");
2663 return ret_val;
2664 }
2665
2666 /* Restore 769.17 to its original value */
2667 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2668 if (ret_val)
2669 e_dbg("Could not restore PHY register %d.%d\n",
2670 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2671
2672 return ret_val;
2673 }
2674
2675 /**
2676 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2677 * @hw: pointer to the HW structure
2678 * @offset: register offset to be read or written
2679 * @data: pointer to the data to read or write
2680 * @read: determines if operation is read or write
2681 * @page_set: BM_WUC_PAGE already set and access enabled
2682 *
2683 * Read the PHY register at offset and store the retrieved information in
2684 * data, or write data to PHY register at offset. Note the procedure to
2685 * access the PHY wakeup registers is different than reading the other PHY
2686 * registers. It works as such:
2687 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2688 * 2) Set page to 800 for host (801 if we were manageability)
2689 * 3) Write the address using the address opcode (0x11)
2690 * 4) Read or write the data using the data opcode (0x12)
2691 * 5) Restore 769.17.2 to its original value
2692 *
2693 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2694 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2695 *
2696 * Assumes semaphore is already acquired. When page_set==true, assumes
2697 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2698 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2699 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)2700 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2701 u16 *data, bool read, bool page_set)
2702 {
2703 s32 ret_val;
2704 u16 reg = BM_PHY_REG_NUM(offset);
2705 u16 page = BM_PHY_REG_PAGE(offset);
2706 u16 phy_reg = 0;
2707
2708 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2709 if ((hw->mac.type == e1000_pchlan) &&
2710 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2711 e_dbg("Attempting to access page %d while gig enabled.\n",
2712 page);
2713
2714 if (!page_set) {
2715 /* Enable access to PHY wakeup registers */
2716 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2717 if (ret_val) {
2718 e_dbg("Could not enable PHY wakeup reg access\n");
2719 return ret_val;
2720 }
2721 }
2722
2723 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2724
2725 /* Write the Wakeup register page offset value using opcode 0x11 */
2726 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2727 if (ret_val) {
2728 e_dbg("Could not write address opcode to page %d\n", page);
2729 return ret_val;
2730 }
2731
2732 if (read) {
2733 /* Read the Wakeup register page value using opcode 0x12 */
2734 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2735 data);
2736 } else {
2737 /* Write the Wakeup register page value using opcode 0x12 */
2738 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2739 *data);
2740 }
2741
2742 if (ret_val) {
2743 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2744 return ret_val;
2745 }
2746
2747 if (!page_set)
2748 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2749
2750 return ret_val;
2751 }
2752
2753 /**
2754 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2755 * @hw: pointer to the HW structure
2756 *
2757 * In the case of a PHY power down to save power, or to turn off link during a
2758 * driver unload, or wake on lan is not enabled, restore the link to previous
2759 * settings.
2760 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)2761 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2762 {
2763 u16 mii_reg = 0;
2764
2765 /* The PHY will retain its settings across a power down/up cycle */
2766 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2767 mii_reg &= ~MII_CR_POWER_DOWN;
2768 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2769 }
2770
2771 /**
2772 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2773 * @hw: pointer to the HW structure
2774 *
2775 * In the case of a PHY power down to save power, or to turn off link during a
2776 * driver unload, or wake on lan is not enabled, restore the link to previous
2777 * settings.
2778 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)2779 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2780 {
2781 u16 mii_reg = 0;
2782
2783 /* The PHY will retain its settings across a power down/up cycle */
2784 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2785 mii_reg |= MII_CR_POWER_DOWN;
2786 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2787 usleep_range(1000, 2000);
2788 }
2789
2790 /**
2791 * e1000e_commit_phy - Soft PHY reset
2792 * @hw: pointer to the HW structure
2793 *
2794 * Performs a soft PHY reset on those that apply. This is a function pointer
2795 * entry point called by drivers.
2796 **/
e1000e_commit_phy(struct e1000_hw * hw)2797 s32 e1000e_commit_phy(struct e1000_hw *hw)
2798 {
2799 if (hw->phy.ops.commit)
2800 return hw->phy.ops.commit(hw);
2801
2802 return 0;
2803 }
2804
2805 /**
2806 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2807 * @hw: pointer to the HW structure
2808 * @active: boolean used to enable/disable lplu
2809 *
2810 * Success returns 0, Failure returns 1
2811 *
2812 * The low power link up (lplu) state is set to the power management level D0
2813 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2814 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2815 * is used during Dx states where the power conservation is most important.
2816 * During driver activity, SmartSpeed should be enabled so performance is
2817 * maintained. This is a function pointer entry point called by drivers.
2818 **/
e1000_set_d0_lplu_state(struct e1000_hw * hw,bool active)2819 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2820 {
2821 if (hw->phy.ops.set_d0_lplu_state)
2822 return hw->phy.ops.set_d0_lplu_state(hw, active);
2823
2824 return 0;
2825 }
2826
2827 /**
2828 * __e1000_read_phy_reg_hv - Read HV PHY register
2829 * @hw: pointer to the HW structure
2830 * @offset: register offset to be read
2831 * @data: pointer to the read data
2832 * @locked: semaphore has already been acquired or not
2833 *
2834 * Acquires semaphore, if necessary, then reads the PHY register at offset
2835 * and stores the retrieved information in data. Release any acquired
2836 * semaphore before exiting.
2837 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)2838 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2839 bool locked, bool page_set)
2840 {
2841 s32 ret_val;
2842 u16 page = BM_PHY_REG_PAGE(offset);
2843 u16 reg = BM_PHY_REG_NUM(offset);
2844 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2845
2846 if (!locked) {
2847 ret_val = hw->phy.ops.acquire(hw);
2848 if (ret_val)
2849 return ret_val;
2850 }
2851
2852 /* Page 800 works differently than the rest so it has its own func */
2853 if (page == BM_WUC_PAGE) {
2854 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2855 true, page_set);
2856 goto out;
2857 }
2858
2859 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2860 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2861 data, true);
2862 goto out;
2863 }
2864
2865 if (!page_set) {
2866 if (page == HV_INTC_FC_PAGE_START)
2867 page = 0;
2868
2869 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2870 /* Page is shifted left, PHY expects (page x 32) */
2871 ret_val = e1000_set_page_igp(hw,
2872 (page << IGP_PAGE_SHIFT));
2873
2874 hw->phy.addr = phy_addr;
2875
2876 if (ret_val)
2877 goto out;
2878 }
2879 }
2880
2881 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2882 page << IGP_PAGE_SHIFT, reg);
2883
2884 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2885 data);
2886 out:
2887 if (!locked)
2888 hw->phy.ops.release(hw);
2889
2890 return ret_val;
2891 }
2892
2893 /**
2894 * e1000_read_phy_reg_hv - Read HV PHY register
2895 * @hw: pointer to the HW structure
2896 * @offset: register offset to be read
2897 * @data: pointer to the read data
2898 *
2899 * Acquires semaphore then reads the PHY register at offset and stores
2900 * the retrieved information in data. Release the acquired semaphore
2901 * before exiting.
2902 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)2903 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2904 {
2905 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2906 }
2907
2908 /**
2909 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2910 * @hw: pointer to the HW structure
2911 * @offset: register offset to be read
2912 * @data: pointer to the read data
2913 *
2914 * Reads the PHY register at offset and stores the retrieved information
2915 * in data. Assumes semaphore already acquired.
2916 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)2917 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2918 {
2919 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2920 }
2921
2922 /**
2923 * e1000_read_phy_reg_page_hv - Read HV PHY register
2924 * @hw: pointer to the HW structure
2925 * @offset: register offset to write to
2926 * @data: data to write at register offset
2927 *
2928 * Reads the PHY register at offset and stores the retrieved information
2929 * in data. Assumes semaphore already acquired and page already set.
2930 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)2931 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2932 {
2933 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2934 }
2935
2936 /**
2937 * __e1000_write_phy_reg_hv - Write HV PHY register
2938 * @hw: pointer to the HW structure
2939 * @offset: register offset to write to
2940 * @data: data to write at register offset
2941 * @locked: semaphore has already been acquired or not
2942 *
2943 * Acquires semaphore, if necessary, then writes the data to PHY register
2944 * at the offset. Release any acquired semaphores before exiting.
2945 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)2946 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2947 bool locked, bool page_set)
2948 {
2949 s32 ret_val;
2950 u16 page = BM_PHY_REG_PAGE(offset);
2951 u16 reg = BM_PHY_REG_NUM(offset);
2952 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2953
2954 if (!locked) {
2955 ret_val = hw->phy.ops.acquire(hw);
2956 if (ret_val)
2957 return ret_val;
2958 }
2959
2960 /* Page 800 works differently than the rest so it has its own func */
2961 if (page == BM_WUC_PAGE) {
2962 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2963 false, page_set);
2964 goto out;
2965 }
2966
2967 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2968 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2969 &data, false);
2970 goto out;
2971 }
2972
2973 if (!page_set) {
2974 if (page == HV_INTC_FC_PAGE_START)
2975 page = 0;
2976
2977 /*
2978 * Workaround MDIO accesses being disabled after entering IEEE
2979 * Power Down (when bit 11 of the PHY Control register is set)
2980 */
2981 if ((hw->phy.type == e1000_phy_82578) &&
2982 (hw->phy.revision >= 1) &&
2983 (hw->phy.addr == 2) &&
2984 ((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) {
2985 u16 data2 = 0x7EFF;
2986 ret_val = e1000_access_phy_debug_regs_hv(hw,
2987 (1 << 6) | 0x3,
2988 &data2, false);
2989 if (ret_val)
2990 goto out;
2991 }
2992
2993 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2994 /* Page is shifted left, PHY expects (page x 32) */
2995 ret_val = e1000_set_page_igp(hw,
2996 (page << IGP_PAGE_SHIFT));
2997
2998 hw->phy.addr = phy_addr;
2999
3000 if (ret_val)
3001 goto out;
3002 }
3003 }
3004
3005 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3006 page << IGP_PAGE_SHIFT, reg);
3007
3008 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3009 data);
3010
3011 out:
3012 if (!locked)
3013 hw->phy.ops.release(hw);
3014
3015 return ret_val;
3016 }
3017
3018 /**
3019 * e1000_write_phy_reg_hv - Write HV PHY register
3020 * @hw: pointer to the HW structure
3021 * @offset: register offset to write to
3022 * @data: data to write at register offset
3023 *
3024 * Acquires semaphore then writes the data to PHY register at the offset.
3025 * Release the acquired semaphores before exiting.
3026 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)3027 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3028 {
3029 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3030 }
3031
3032 /**
3033 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3034 * @hw: pointer to the HW structure
3035 * @offset: register offset to write to
3036 * @data: data to write at register offset
3037 *
3038 * Writes the data to PHY register at the offset. Assumes semaphore
3039 * already acquired.
3040 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3041 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3042 {
3043 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3044 }
3045
3046 /**
3047 * e1000_write_phy_reg_page_hv - Write HV PHY register
3048 * @hw: pointer to the HW structure
3049 * @offset: register offset to write to
3050 * @data: data to write at register offset
3051 *
3052 * Writes the data to PHY register at the offset. Assumes semaphore
3053 * already acquired and page already set.
3054 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)3055 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3056 {
3057 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3058 }
3059
3060 /**
3061 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3062 * @page: page to be accessed
3063 **/
e1000_get_phy_addr_for_hv_page(u32 page)3064 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3065 {
3066 u32 phy_addr = 2;
3067
3068 if (page >= HV_INTC_FC_PAGE_START)
3069 phy_addr = 1;
3070
3071 return phy_addr;
3072 }
3073
3074 /**
3075 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3076 * @hw: pointer to the HW structure
3077 * @offset: register offset to be read or written
3078 * @data: pointer to the data to be read or written
3079 * @read: determines if operation is read or write
3080 *
3081 * Reads the PHY register at offset and stores the retreived information
3082 * in data. Assumes semaphore already acquired. Note that the procedure
3083 * to access these regs uses the address port and data port to read/write.
3084 * These accesses done with PHY address 2 and without using pages.
3085 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3086 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3087 u16 *data, bool read)
3088 {
3089 s32 ret_val;
3090 u32 addr_reg = 0;
3091 u32 data_reg = 0;
3092
3093 /* This takes care of the difference with desktop vs mobile phy */
3094 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3095 I82578_ADDR_REG : I82577_ADDR_REG;
3096 data_reg = addr_reg + 1;
3097
3098 /* All operations in this function are phy address 2 */
3099 hw->phy.addr = 2;
3100
3101 /* masking with 0x3F to remove the page from offset */
3102 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3103 if (ret_val) {
3104 e_dbg("Could not write the Address Offset port register\n");
3105 return ret_val;
3106 }
3107
3108 /* Read or write the data value next */
3109 if (read)
3110 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3111 else
3112 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3113
3114 if (ret_val)
3115 e_dbg("Could not access the Data port register\n");
3116
3117 return ret_val;
3118 }
3119
3120 /**
3121 * e1000_link_stall_workaround_hv - Si workaround
3122 * @hw: pointer to the HW structure
3123 *
3124 * This function works around a Si bug where the link partner can get
3125 * a link up indication before the PHY does. If small packets are sent
3126 * by the link partner they can be placed in the packet buffer without
3127 * being properly accounted for by the PHY and will stall preventing
3128 * further packets from being received. The workaround is to clear the
3129 * packet buffer after the PHY detects link up.
3130 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3131 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3132 {
3133 s32 ret_val = 0;
3134 u16 data;
3135
3136 if (hw->phy.type != e1000_phy_82578)
3137 return 0;
3138
3139 /* Do not apply workaround if in PHY loopback bit 14 set */
3140 e1e_rphy(hw, PHY_CONTROL, &data);
3141 if (data & PHY_CONTROL_LB)
3142 return 0;
3143
3144 /* check if link is up and at 1Gbps */
3145 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3146 if (ret_val)
3147 return ret_val;
3148
3149 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3150 BM_CS_STATUS_SPEED_MASK;
3151
3152 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3153 BM_CS_STATUS_SPEED_1000))
3154 return 0;
3155
3156 msleep(200);
3157
3158 /* flush the packets in the fifo buffer */
3159 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3160 HV_MUX_DATA_CTRL_FORCE_SPEED);
3161 if (ret_val)
3162 return ret_val;
3163
3164 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3165 }
3166
3167 /**
3168 * e1000_check_polarity_82577 - Checks the polarity.
3169 * @hw: pointer to the HW structure
3170 *
3171 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3172 *
3173 * Polarity is determined based on the PHY specific status register.
3174 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3175 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3176 {
3177 struct e1000_phy_info *phy = &hw->phy;
3178 s32 ret_val;
3179 u16 data;
3180
3181 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3182
3183 if (!ret_val)
3184 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3185 ? e1000_rev_polarity_reversed
3186 : e1000_rev_polarity_normal;
3187
3188 return ret_val;
3189 }
3190
3191 /**
3192 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3193 * @hw: pointer to the HW structure
3194 *
3195 * Calls the PHY setup function to force speed and duplex.
3196 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3197 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3198 {
3199 struct e1000_phy_info *phy = &hw->phy;
3200 s32 ret_val;
3201 u16 phy_data;
3202 bool link;
3203
3204 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3205 if (ret_val)
3206 return ret_val;
3207
3208 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3209
3210 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3211 if (ret_val)
3212 return ret_val;
3213
3214 udelay(1);
3215
3216 if (phy->autoneg_wait_to_complete) {
3217 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3218
3219 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3220 100000, &link);
3221 if (ret_val)
3222 return ret_val;
3223
3224 if (!link)
3225 e_dbg("Link taking longer than expected.\n");
3226
3227 /* Try once more */
3228 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3229 100000, &link);
3230 }
3231
3232 return ret_val;
3233 }
3234
3235 /**
3236 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3237 * @hw: pointer to the HW structure
3238 *
3239 * Read PHY status to determine if link is up. If link is up, then
3240 * set/determine 10base-T extended distance and polarity correction. Read
3241 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3242 * determine on the cable length, local and remote receiver.
3243 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3244 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3245 {
3246 struct e1000_phy_info *phy = &hw->phy;
3247 s32 ret_val;
3248 u16 data;
3249 bool link;
3250
3251 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3252 if (ret_val)
3253 return ret_val;
3254
3255 if (!link) {
3256 e_dbg("Phy info is only valid if link is up\n");
3257 return -E1000_ERR_CONFIG;
3258 }
3259
3260 phy->polarity_correction = true;
3261
3262 ret_val = e1000_check_polarity_82577(hw);
3263 if (ret_val)
3264 return ret_val;
3265
3266 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3267 if (ret_val)
3268 return ret_val;
3269
3270 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3271
3272 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3273 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3274 ret_val = hw->phy.ops.get_cable_length(hw);
3275 if (ret_val)
3276 return ret_val;
3277
3278 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3279 if (ret_val)
3280 return ret_val;
3281
3282 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3283 ? e1000_1000t_rx_status_ok
3284 : e1000_1000t_rx_status_not_ok;
3285
3286 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3287 ? e1000_1000t_rx_status_ok
3288 : e1000_1000t_rx_status_not_ok;
3289 } else {
3290 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3291 phy->local_rx = e1000_1000t_rx_status_undefined;
3292 phy->remote_rx = e1000_1000t_rx_status_undefined;
3293 }
3294
3295 return 0;
3296 }
3297
3298 /**
3299 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3300 * @hw: pointer to the HW structure
3301 *
3302 * Reads the diagnostic status register and verifies result is valid before
3303 * placing it in the phy_cable_length field.
3304 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)3305 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3306 {
3307 struct e1000_phy_info *phy = &hw->phy;
3308 s32 ret_val;
3309 u16 phy_data, length;
3310
3311 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3312 if (ret_val)
3313 return ret_val;
3314
3315 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3316 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3317
3318 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3319 ret_val = -E1000_ERR_PHY;
3320
3321 phy->cable_length = length;
3322
3323 return 0;
3324 }
3325