1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #include "e1000.h"
5 #include <linux/ethtool.h>
6 
7 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 					  u16 *data, bool read, bool page_set);
10 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 					  u16 *data, bool read);
13 
14 /* Cable length tables */
15 static const u16 e1000_m88_cable_length_table[] = {
16 	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
17 };
18 
19 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 		ARRAY_SIZE(e1000_m88_cable_length_table)
21 
22 static const u16 e1000_igp_2_cable_length_table[] = {
23 	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
24 	6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
25 	26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
26 	44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
27 	66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
28 	87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
29 	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 	124
31 };
32 
33 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
34 		ARRAY_SIZE(e1000_igp_2_cable_length_table)
35 
36 /**
37  *  e1000e_check_reset_block_generic - Check if PHY reset is blocked
38  *  @hw: pointer to the HW structure
39  *
40  *  Read the PHY management control register and check whether a PHY reset
41  *  is blocked.  If a reset is not blocked return 0, otherwise
42  *  return E1000_BLK_PHY_RESET (12).
43  **/
e1000e_check_reset_block_generic(struct e1000_hw * hw)44 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
45 {
46 	u32 manc;
47 
48 	manc = er32(MANC);
49 
50 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
51 }
52 
53 /**
54  *  e1000e_get_phy_id - Retrieve the PHY ID and revision
55  *  @hw: pointer to the HW structure
56  *
57  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
58  *  revision in the hardware structure.
59  **/
e1000e_get_phy_id(struct e1000_hw * hw)60 s32 e1000e_get_phy_id(struct e1000_hw *hw)
61 {
62 	struct e1000_phy_info *phy = &hw->phy;
63 	s32 ret_val = 0;
64 	u16 phy_id;
65 	u16 retry_count = 0;
66 
67 	if (!phy->ops.read_reg)
68 		return 0;
69 
70 	while (retry_count < 2) {
71 		ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
72 		if (ret_val)
73 			return ret_val;
74 
75 		phy->id = (u32)(phy_id << 16);
76 		usleep_range(20, 40);
77 		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
78 		if (ret_val)
79 			return ret_val;
80 
81 		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
82 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
83 
84 		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
85 			return 0;
86 
87 		retry_count++;
88 	}
89 
90 	return 0;
91 }
92 
93 /**
94  *  e1000e_phy_reset_dsp - Reset PHY DSP
95  *  @hw: pointer to the HW structure
96  *
97  *  Reset the digital signal processor.
98  **/
e1000e_phy_reset_dsp(struct e1000_hw * hw)99 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
100 {
101 	s32 ret_val;
102 
103 	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
104 	if (ret_val)
105 		return ret_val;
106 
107 	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
108 }
109 
110 /**
111  *  e1000e_read_phy_reg_mdic - Read MDI control register
112  *  @hw: pointer to the HW structure
113  *  @offset: register offset to be read
114  *  @data: pointer to the read data
115  *
116  *  Reads the MDI control register in the PHY at offset and stores the
117  *  information read to data.
118  **/
e1000e_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)119 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
120 {
121 	struct e1000_phy_info *phy = &hw->phy;
122 	u32 i, mdic = 0;
123 
124 	if (offset > MAX_PHY_REG_ADDRESS) {
125 		e_dbg("PHY Address %d is out of range\n", offset);
126 		return -E1000_ERR_PARAM;
127 	}
128 
129 	/* Set up Op-code, Phy Address, and register offset in the MDI
130 	 * Control register.  The MAC will take care of interfacing with the
131 	 * PHY to retrieve the desired data.
132 	 */
133 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
134 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
135 		(E1000_MDIC_OP_READ));
136 
137 	ew32(MDIC, mdic);
138 
139 	/* Poll the ready bit to see if the MDI read completed
140 	 * Increasing the time out as testing showed failures with
141 	 * the lower time out
142 	 */
143 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
144 		udelay(50);
145 		mdic = er32(MDIC);
146 		if (mdic & E1000_MDIC_READY)
147 			break;
148 	}
149 	if (!(mdic & E1000_MDIC_READY)) {
150 		e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
151 		return -E1000_ERR_PHY;
152 	}
153 	if (mdic & E1000_MDIC_ERROR) {
154 		e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
155 		return -E1000_ERR_PHY;
156 	}
157 	if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
158 		e_dbg("MDI Read offset error - requested %d, returned %d\n",
159 		      offset,
160 		      (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
161 		return -E1000_ERR_PHY;
162 	}
163 	*data = (u16)mdic;
164 
165 	/* Allow some time after each MDIC transaction to avoid
166 	 * reading duplicate data in the next MDIC transaction.
167 	 */
168 	if (hw->mac.type == e1000_pch2lan)
169 		udelay(100);
170 
171 	return 0;
172 }
173 
174 /**
175  *  e1000e_write_phy_reg_mdic - Write MDI control register
176  *  @hw: pointer to the HW structure
177  *  @offset: register offset to write to
178  *  @data: data to write to register at offset
179  *
180  *  Writes data to MDI control register in the PHY at offset.
181  **/
e1000e_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)182 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
183 {
184 	struct e1000_phy_info *phy = &hw->phy;
185 	u32 i, mdic = 0;
186 
187 	if (offset > MAX_PHY_REG_ADDRESS) {
188 		e_dbg("PHY Address %d is out of range\n", offset);
189 		return -E1000_ERR_PARAM;
190 	}
191 
192 	/* Set up Op-code, Phy Address, and register offset in the MDI
193 	 * Control register.  The MAC will take care of interfacing with the
194 	 * PHY to retrieve the desired data.
195 	 */
196 	mdic = (((u32)data) |
197 		(offset << E1000_MDIC_REG_SHIFT) |
198 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
199 		(E1000_MDIC_OP_WRITE));
200 
201 	ew32(MDIC, mdic);
202 
203 	/* Poll the ready bit to see if the MDI read completed
204 	 * Increasing the time out as testing showed failures with
205 	 * the lower time out
206 	 */
207 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
208 		udelay(50);
209 		mdic = er32(MDIC);
210 		if (mdic & E1000_MDIC_READY)
211 			break;
212 	}
213 	if (!(mdic & E1000_MDIC_READY)) {
214 		e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
215 		return -E1000_ERR_PHY;
216 	}
217 	if (mdic & E1000_MDIC_ERROR) {
218 		e_dbg("MDI Write PHY Red Address %d Error\n", offset);
219 		return -E1000_ERR_PHY;
220 	}
221 	if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
222 		e_dbg("MDI Write offset error - requested %d, returned %d\n",
223 		      offset,
224 		      (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
225 		return -E1000_ERR_PHY;
226 	}
227 
228 	/* Allow some time after each MDIC transaction to avoid
229 	 * reading duplicate data in the next MDIC transaction.
230 	 */
231 	if (hw->mac.type == e1000_pch2lan)
232 		udelay(100);
233 
234 	return 0;
235 }
236 
237 /**
238  *  e1000e_read_phy_reg_m88 - Read m88 PHY register
239  *  @hw: pointer to the HW structure
240  *  @offset: register offset to be read
241  *  @data: pointer to the read data
242  *
243  *  Acquires semaphore, if necessary, then reads the PHY register at offset
244  *  and storing the retrieved information in data.  Release any acquired
245  *  semaphores before exiting.
246  **/
e1000e_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)247 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
248 {
249 	s32 ret_val;
250 
251 	ret_val = hw->phy.ops.acquire(hw);
252 	if (ret_val)
253 		return ret_val;
254 
255 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
256 					   data);
257 
258 	hw->phy.ops.release(hw);
259 
260 	return ret_val;
261 }
262 
263 /**
264  *  e1000e_write_phy_reg_m88 - Write m88 PHY register
265  *  @hw: pointer to the HW structure
266  *  @offset: register offset to write to
267  *  @data: data to write at register offset
268  *
269  *  Acquires semaphore, if necessary, then writes the data to PHY register
270  *  at the offset.  Release any acquired semaphores before exiting.
271  **/
e1000e_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)272 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
273 {
274 	s32 ret_val;
275 
276 	ret_val = hw->phy.ops.acquire(hw);
277 	if (ret_val)
278 		return ret_val;
279 
280 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
281 					    data);
282 
283 	hw->phy.ops.release(hw);
284 
285 	return ret_val;
286 }
287 
288 /**
289  *  e1000_set_page_igp - Set page as on IGP-like PHY(s)
290  *  @hw: pointer to the HW structure
291  *  @page: page to set (shifted left when necessary)
292  *
293  *  Sets PHY page required for PHY register access.  Assumes semaphore is
294  *  already acquired.  Note, this function sets phy.addr to 1 so the caller
295  *  must set it appropriately (if necessary) after this function returns.
296  **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)297 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
298 {
299 	e_dbg("Setting page 0x%x\n", page);
300 
301 	hw->phy.addr = 1;
302 
303 	return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
304 }
305 
306 /**
307  *  __e1000e_read_phy_reg_igp - Read igp PHY register
308  *  @hw: pointer to the HW structure
309  *  @offset: register offset to be read
310  *  @data: pointer to the read data
311  *  @locked: semaphore has already been acquired or not
312  *
313  *  Acquires semaphore, if necessary, then reads the PHY register at offset
314  *  and stores the retrieved information in data.  Release any acquired
315  *  semaphores before exiting.
316  **/
__e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)317 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
318 				     bool locked)
319 {
320 	s32 ret_val = 0;
321 
322 	if (!locked) {
323 		if (!hw->phy.ops.acquire)
324 			return 0;
325 
326 		ret_val = hw->phy.ops.acquire(hw);
327 		if (ret_val)
328 			return ret_val;
329 	}
330 
331 	if (offset > MAX_PHY_MULTI_PAGE_REG)
332 		ret_val = e1000e_write_phy_reg_mdic(hw,
333 						    IGP01E1000_PHY_PAGE_SELECT,
334 						    (u16)offset);
335 	if (!ret_val)
336 		ret_val = e1000e_read_phy_reg_mdic(hw,
337 						   MAX_PHY_REG_ADDRESS & offset,
338 						   data);
339 	if (!locked)
340 		hw->phy.ops.release(hw);
341 
342 	return ret_val;
343 }
344 
345 /**
346  *  e1000e_read_phy_reg_igp - Read igp PHY register
347  *  @hw: pointer to the HW structure
348  *  @offset: register offset to be read
349  *  @data: pointer to the read data
350  *
351  *  Acquires semaphore then reads the PHY register at offset and stores the
352  *  retrieved information in data.
353  *  Release the acquired semaphore before exiting.
354  **/
e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)355 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
356 {
357 	return __e1000e_read_phy_reg_igp(hw, offset, data, false);
358 }
359 
360 /**
361  *  e1000e_read_phy_reg_igp_locked - Read igp PHY register
362  *  @hw: pointer to the HW structure
363  *  @offset: register offset to be read
364  *  @data: pointer to the read data
365  *
366  *  Reads the PHY register at offset and stores the retrieved information
367  *  in data.  Assumes semaphore already acquired.
368  **/
e1000e_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)369 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
370 {
371 	return __e1000e_read_phy_reg_igp(hw, offset, data, true);
372 }
373 
374 /**
375  *  __e1000e_write_phy_reg_igp - Write igp PHY register
376  *  @hw: pointer to the HW structure
377  *  @offset: register offset to write to
378  *  @data: data to write at register offset
379  *  @locked: semaphore has already been acquired or not
380  *
381  *  Acquires semaphore, if necessary, then writes the data to PHY register
382  *  at the offset.  Release any acquired semaphores before exiting.
383  **/
__e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)384 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
385 				      bool locked)
386 {
387 	s32 ret_val = 0;
388 
389 	if (!locked) {
390 		if (!hw->phy.ops.acquire)
391 			return 0;
392 
393 		ret_val = hw->phy.ops.acquire(hw);
394 		if (ret_val)
395 			return ret_val;
396 	}
397 
398 	if (offset > MAX_PHY_MULTI_PAGE_REG)
399 		ret_val = e1000e_write_phy_reg_mdic(hw,
400 						    IGP01E1000_PHY_PAGE_SELECT,
401 						    (u16)offset);
402 	if (!ret_val)
403 		ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
404 						    offset, data);
405 	if (!locked)
406 		hw->phy.ops.release(hw);
407 
408 	return ret_val;
409 }
410 
411 /**
412  *  e1000e_write_phy_reg_igp - Write igp PHY register
413  *  @hw: pointer to the HW structure
414  *  @offset: register offset to write to
415  *  @data: data to write at register offset
416  *
417  *  Acquires semaphore then writes the data to PHY register
418  *  at the offset.  Release any acquired semaphores before exiting.
419  **/
e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)420 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
421 {
422 	return __e1000e_write_phy_reg_igp(hw, offset, data, false);
423 }
424 
425 /**
426  *  e1000e_write_phy_reg_igp_locked - Write igp PHY register
427  *  @hw: pointer to the HW structure
428  *  @offset: register offset to write to
429  *  @data: data to write at register offset
430  *
431  *  Writes the data to PHY register at the offset.
432  *  Assumes semaphore already acquired.
433  **/
e1000e_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)434 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
435 {
436 	return __e1000e_write_phy_reg_igp(hw, offset, data, true);
437 }
438 
439 /**
440  *  __e1000_read_kmrn_reg - Read kumeran register
441  *  @hw: pointer to the HW structure
442  *  @offset: register offset to be read
443  *  @data: pointer to the read data
444  *  @locked: semaphore has already been acquired or not
445  *
446  *  Acquires semaphore, if necessary.  Then reads the PHY register at offset
447  *  using the kumeran interface.  The information retrieved is stored in data.
448  *  Release any acquired semaphores before exiting.
449  **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)450 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
451 				 bool locked)
452 {
453 	u32 kmrnctrlsta;
454 
455 	if (!locked) {
456 		s32 ret_val = 0;
457 
458 		if (!hw->phy.ops.acquire)
459 			return 0;
460 
461 		ret_val = hw->phy.ops.acquire(hw);
462 		if (ret_val)
463 			return ret_val;
464 	}
465 
466 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
467 		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
468 	ew32(KMRNCTRLSTA, kmrnctrlsta);
469 	e1e_flush();
470 
471 	udelay(2);
472 
473 	kmrnctrlsta = er32(KMRNCTRLSTA);
474 	*data = (u16)kmrnctrlsta;
475 
476 	if (!locked)
477 		hw->phy.ops.release(hw);
478 
479 	return 0;
480 }
481 
482 /**
483  *  e1000e_read_kmrn_reg -  Read kumeran register
484  *  @hw: pointer to the HW structure
485  *  @offset: register offset to be read
486  *  @data: pointer to the read data
487  *
488  *  Acquires semaphore then reads the PHY register at offset using the
489  *  kumeran interface.  The information retrieved is stored in data.
490  *  Release the acquired semaphore before exiting.
491  **/
e1000e_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data)492 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
493 {
494 	return __e1000_read_kmrn_reg(hw, offset, data, false);
495 }
496 
497 /**
498  *  e1000e_read_kmrn_reg_locked -  Read kumeran register
499  *  @hw: pointer to the HW structure
500  *  @offset: register offset to be read
501  *  @data: pointer to the read data
502  *
503  *  Reads the PHY register at offset using the kumeran interface.  The
504  *  information retrieved is stored in data.
505  *  Assumes semaphore already acquired.
506  **/
e1000e_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)507 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
508 {
509 	return __e1000_read_kmrn_reg(hw, offset, data, true);
510 }
511 
512 /**
513  *  __e1000_write_kmrn_reg - Write kumeran register
514  *  @hw: pointer to the HW structure
515  *  @offset: register offset to write to
516  *  @data: data to write at register offset
517  *  @locked: semaphore has already been acquired or not
518  *
519  *  Acquires semaphore, if necessary.  Then write the data to PHY register
520  *  at the offset using the kumeran interface.  Release any acquired semaphores
521  *  before exiting.
522  **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)523 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
524 				  bool locked)
525 {
526 	u32 kmrnctrlsta;
527 
528 	if (!locked) {
529 		s32 ret_val = 0;
530 
531 		if (!hw->phy.ops.acquire)
532 			return 0;
533 
534 		ret_val = hw->phy.ops.acquire(hw);
535 		if (ret_val)
536 			return ret_val;
537 	}
538 
539 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
540 		       E1000_KMRNCTRLSTA_OFFSET) | data;
541 	ew32(KMRNCTRLSTA, kmrnctrlsta);
542 	e1e_flush();
543 
544 	udelay(2);
545 
546 	if (!locked)
547 		hw->phy.ops.release(hw);
548 
549 	return 0;
550 }
551 
552 /**
553  *  e1000e_write_kmrn_reg -  Write kumeran register
554  *  @hw: pointer to the HW structure
555  *  @offset: register offset to write to
556  *  @data: data to write at register offset
557  *
558  *  Acquires semaphore then writes the data to the PHY register at the offset
559  *  using the kumeran interface.  Release the acquired semaphore before exiting.
560  **/
e1000e_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data)561 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
562 {
563 	return __e1000_write_kmrn_reg(hw, offset, data, false);
564 }
565 
566 /**
567  *  e1000e_write_kmrn_reg_locked -  Write kumeran register
568  *  @hw: pointer to the HW structure
569  *  @offset: register offset to write to
570  *  @data: data to write at register offset
571  *
572  *  Write the data to PHY register at the offset using the kumeran interface.
573  *  Assumes semaphore already acquired.
574  **/
e1000e_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)575 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
576 {
577 	return __e1000_write_kmrn_reg(hw, offset, data, true);
578 }
579 
580 /**
581  *  e1000_set_master_slave_mode - Setup PHY for Master/slave mode
582  *  @hw: pointer to the HW structure
583  *
584  *  Sets up Master/slave mode
585  **/
e1000_set_master_slave_mode(struct e1000_hw * hw)586 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
587 {
588 	s32 ret_val;
589 	u16 phy_data;
590 
591 	/* Resolve Master/Slave mode */
592 	ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
593 	if (ret_val)
594 		return ret_val;
595 
596 	/* load defaults for future use */
597 	hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
598 	    ((phy_data & CTL1000_AS_MASTER) ?
599 	     e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
600 
601 	switch (hw->phy.ms_type) {
602 	case e1000_ms_force_master:
603 		phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
604 		break;
605 	case e1000_ms_force_slave:
606 		phy_data |= CTL1000_ENABLE_MASTER;
607 		phy_data &= ~(CTL1000_AS_MASTER);
608 		break;
609 	case e1000_ms_auto:
610 		phy_data &= ~CTL1000_ENABLE_MASTER;
611 		fallthrough;
612 	default:
613 		break;
614 	}
615 
616 	return e1e_wphy(hw, MII_CTRL1000, phy_data);
617 }
618 
619 /**
620  *  e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
621  *  @hw: pointer to the HW structure
622  *
623  *  Sets up Carrier-sense on Transmit and downshift values.
624  **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)625 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
626 {
627 	s32 ret_val;
628 	u16 phy_data;
629 
630 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
631 	ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
632 	if (ret_val)
633 		return ret_val;
634 
635 	phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
636 
637 	/* Enable downshift */
638 	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
639 
640 	ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
641 	if (ret_val)
642 		return ret_val;
643 
644 	/* Set MDI/MDIX mode */
645 	ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
646 	if (ret_val)
647 		return ret_val;
648 	phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
649 	/* Options:
650 	 *   0 - Auto (default)
651 	 *   1 - MDI mode
652 	 *   2 - MDI-X mode
653 	 */
654 	switch (hw->phy.mdix) {
655 	case 1:
656 		break;
657 	case 2:
658 		phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
659 		break;
660 	case 0:
661 	default:
662 		phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
663 		break;
664 	}
665 	ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
666 	if (ret_val)
667 		return ret_val;
668 
669 	return e1000_set_master_slave_mode(hw);
670 }
671 
672 /**
673  *  e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
674  *  @hw: pointer to the HW structure
675  *
676  *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
677  *  and downshift values are set also.
678  **/
e1000e_copper_link_setup_m88(struct e1000_hw * hw)679 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
680 {
681 	struct e1000_phy_info *phy = &hw->phy;
682 	s32 ret_val;
683 	u16 phy_data;
684 
685 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
686 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
687 	if (ret_val)
688 		return ret_val;
689 
690 	/* For BM PHY this bit is downshift enable */
691 	if (phy->type != e1000_phy_bm)
692 		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
693 
694 	/* Options:
695 	 *   MDI/MDI-X = 0 (default)
696 	 *   0 - Auto for all speeds
697 	 *   1 - MDI mode
698 	 *   2 - MDI-X mode
699 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
700 	 */
701 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
702 
703 	switch (phy->mdix) {
704 	case 1:
705 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
706 		break;
707 	case 2:
708 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
709 		break;
710 	case 3:
711 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
712 		break;
713 	case 0:
714 	default:
715 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
716 		break;
717 	}
718 
719 	/* Options:
720 	 *   disable_polarity_correction = 0 (default)
721 	 *       Automatic Correction for Reversed Cable Polarity
722 	 *   0 - Disabled
723 	 *   1 - Enabled
724 	 */
725 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
726 	if (phy->disable_polarity_correction)
727 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
728 
729 	/* Enable downshift on BM (disabled by default) */
730 	if (phy->type == e1000_phy_bm) {
731 		/* For 82574/82583, first disable then enable downshift */
732 		if (phy->id == BME1000_E_PHY_ID_R2) {
733 			phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
734 			ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
735 					   phy_data);
736 			if (ret_val)
737 				return ret_val;
738 			/* Commit the changes. */
739 			ret_val = phy->ops.commit(hw);
740 			if (ret_val) {
741 				e_dbg("Error committing the PHY changes\n");
742 				return ret_val;
743 			}
744 		}
745 
746 		phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
747 	}
748 
749 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
750 	if (ret_val)
751 		return ret_val;
752 
753 	if ((phy->type == e1000_phy_m88) &&
754 	    (phy->revision < E1000_REVISION_4) &&
755 	    (phy->id != BME1000_E_PHY_ID_R2)) {
756 		/* Force TX_CLK in the Extended PHY Specific Control Register
757 		 * to 25MHz clock.
758 		 */
759 		ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
760 		if (ret_val)
761 			return ret_val;
762 
763 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
764 
765 		if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
766 			/* 82573L PHY - set the downshift counter to 5x. */
767 			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
768 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
769 		} else {
770 			/* Configure Master and Slave downshift values */
771 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
772 				      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
773 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
774 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
775 		}
776 		ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
777 		if (ret_val)
778 			return ret_val;
779 	}
780 
781 	if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
782 		/* Set PHY page 0, register 29 to 0x0003 */
783 		ret_val = e1e_wphy(hw, 29, 0x0003);
784 		if (ret_val)
785 			return ret_val;
786 
787 		/* Set PHY page 0, register 30 to 0x0000 */
788 		ret_val = e1e_wphy(hw, 30, 0x0000);
789 		if (ret_val)
790 			return ret_val;
791 	}
792 
793 	/* Commit the changes. */
794 	if (phy->ops.commit) {
795 		ret_val = phy->ops.commit(hw);
796 		if (ret_val) {
797 			e_dbg("Error committing the PHY changes\n");
798 			return ret_val;
799 		}
800 	}
801 
802 	if (phy->type == e1000_phy_82578) {
803 		ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
804 		if (ret_val)
805 			return ret_val;
806 
807 		/* 82578 PHY - set the downshift count to 1x. */
808 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
809 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
810 		ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
811 		if (ret_val)
812 			return ret_val;
813 	}
814 
815 	return 0;
816 }
817 
818 /**
819  *  e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
820  *  @hw: pointer to the HW structure
821  *
822  *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
823  *  igp PHY's.
824  **/
e1000e_copper_link_setup_igp(struct e1000_hw * hw)825 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
826 {
827 	struct e1000_phy_info *phy = &hw->phy;
828 	s32 ret_val;
829 	u16 data;
830 
831 	ret_val = e1000_phy_hw_reset(hw);
832 	if (ret_val) {
833 		e_dbg("Error resetting the PHY.\n");
834 		return ret_val;
835 	}
836 
837 	/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
838 	 * timeout issues when LFS is enabled.
839 	 */
840 	msleep(100);
841 
842 	/* disable lplu d0 during driver init */
843 	if (hw->phy.ops.set_d0_lplu_state) {
844 		ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
845 		if (ret_val) {
846 			e_dbg("Error Disabling LPLU D0\n");
847 			return ret_val;
848 		}
849 	}
850 	/* Configure mdi-mdix settings */
851 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
852 	if (ret_val)
853 		return ret_val;
854 
855 	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
856 
857 	switch (phy->mdix) {
858 	case 1:
859 		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
860 		break;
861 	case 2:
862 		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
863 		break;
864 	case 0:
865 	default:
866 		data |= IGP01E1000_PSCR_AUTO_MDIX;
867 		break;
868 	}
869 	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
870 	if (ret_val)
871 		return ret_val;
872 
873 	/* set auto-master slave resolution settings */
874 	if (hw->mac.autoneg) {
875 		/* when autonegotiation advertisement is only 1000Mbps then we
876 		 * should disable SmartSpeed and enable Auto MasterSlave
877 		 * resolution as hardware default.
878 		 */
879 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
880 			/* Disable SmartSpeed */
881 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
882 					   &data);
883 			if (ret_val)
884 				return ret_val;
885 
886 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
887 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
888 					   data);
889 			if (ret_val)
890 				return ret_val;
891 
892 			/* Set auto Master/Slave resolution process */
893 			ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
894 			if (ret_val)
895 				return ret_val;
896 
897 			data &= ~CTL1000_ENABLE_MASTER;
898 			ret_val = e1e_wphy(hw, MII_CTRL1000, data);
899 			if (ret_val)
900 				return ret_val;
901 		}
902 
903 		ret_val = e1000_set_master_slave_mode(hw);
904 	}
905 
906 	return ret_val;
907 }
908 
909 /**
910  *  e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
911  *  @hw: pointer to the HW structure
912  *
913  *  Reads the MII auto-neg advertisement register and/or the 1000T control
914  *  register and if the PHY is already setup for auto-negotiation, then
915  *  return successful.  Otherwise, setup advertisement and flow control to
916  *  the appropriate values for the wanted auto-negotiation.
917  **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)918 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
919 {
920 	struct e1000_phy_info *phy = &hw->phy;
921 	s32 ret_val;
922 	u16 mii_autoneg_adv_reg;
923 	u16 mii_1000t_ctrl_reg = 0;
924 
925 	phy->autoneg_advertised &= phy->autoneg_mask;
926 
927 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
928 	ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
929 	if (ret_val)
930 		return ret_val;
931 
932 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
933 		/* Read the MII 1000Base-T Control Register (Address 9). */
934 		ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
935 		if (ret_val)
936 			return ret_val;
937 	}
938 
939 	/* Need to parse both autoneg_advertised and fc and set up
940 	 * the appropriate PHY registers.  First we will parse for
941 	 * autoneg_advertised software override.  Since we can advertise
942 	 * a plethora of combinations, we need to check each bit
943 	 * individually.
944 	 */
945 
946 	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
947 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
948 	 * the  1000Base-T Control Register (Address 9).
949 	 */
950 	mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
951 				 ADVERTISE_100HALF |
952 				 ADVERTISE_10FULL | ADVERTISE_10HALF);
953 	mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
954 
955 	e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
956 
957 	/* Do we want to advertise 10 Mb Half Duplex? */
958 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
959 		e_dbg("Advertise 10mb Half duplex\n");
960 		mii_autoneg_adv_reg |= ADVERTISE_10HALF;
961 	}
962 
963 	/* Do we want to advertise 10 Mb Full Duplex? */
964 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
965 		e_dbg("Advertise 10mb Full duplex\n");
966 		mii_autoneg_adv_reg |= ADVERTISE_10FULL;
967 	}
968 
969 	/* Do we want to advertise 100 Mb Half Duplex? */
970 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
971 		e_dbg("Advertise 100mb Half duplex\n");
972 		mii_autoneg_adv_reg |= ADVERTISE_100HALF;
973 	}
974 
975 	/* Do we want to advertise 100 Mb Full Duplex? */
976 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
977 		e_dbg("Advertise 100mb Full duplex\n");
978 		mii_autoneg_adv_reg |= ADVERTISE_100FULL;
979 	}
980 
981 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
982 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
983 		e_dbg("Advertise 1000mb Half duplex request denied!\n");
984 
985 	/* Do we want to advertise 1000 Mb Full Duplex? */
986 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
987 		e_dbg("Advertise 1000mb Full duplex\n");
988 		mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
989 	}
990 
991 	/* Check for a software override of the flow control settings, and
992 	 * setup the PHY advertisement registers accordingly.  If
993 	 * auto-negotiation is enabled, then software will have to set the
994 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
995 	 * Advertisement Register (MII_ADVERTISE) and re-start auto-
996 	 * negotiation.
997 	 *
998 	 * The possible values of the "fc" parameter are:
999 	 *      0:  Flow control is completely disabled
1000 	 *      1:  Rx flow control is enabled (we can receive pause frames
1001 	 *          but not send pause frames).
1002 	 *      2:  Tx flow control is enabled (we can send pause frames
1003 	 *          but we do not support receiving pause frames).
1004 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
1005 	 *  other:  No software override.  The flow control configuration
1006 	 *          in the EEPROM is used.
1007 	 */
1008 	switch (hw->fc.current_mode) {
1009 	case e1000_fc_none:
1010 		/* Flow control (Rx & Tx) is completely disabled by a
1011 		 * software over-ride.
1012 		 */
1013 		mii_autoneg_adv_reg &=
1014 		    ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1015 		phy->autoneg_advertised &=
1016 		    ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1017 		break;
1018 	case e1000_fc_rx_pause:
1019 		/* Rx Flow control is enabled, and Tx Flow control is
1020 		 * disabled, by a software over-ride.
1021 		 *
1022 		 * Since there really isn't a way to advertise that we are
1023 		 * capable of Rx Pause ONLY, we will advertise that we
1024 		 * support both symmetric and asymmetric Rx PAUSE.  Later
1025 		 * (in e1000e_config_fc_after_link_up) we will disable the
1026 		 * hw's ability to send PAUSE frames.
1027 		 */
1028 		mii_autoneg_adv_reg |=
1029 		    (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1030 		phy->autoneg_advertised |=
1031 		    (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1032 		break;
1033 	case e1000_fc_tx_pause:
1034 		/* Tx Flow control is enabled, and Rx Flow control is
1035 		 * disabled, by a software over-ride.
1036 		 */
1037 		mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1038 		mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1039 		phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
1040 		phy->autoneg_advertised &= ~ADVERTISED_Pause;
1041 		break;
1042 	case e1000_fc_full:
1043 		/* Flow control (both Rx and Tx) is enabled by a software
1044 		 * over-ride.
1045 		 */
1046 		mii_autoneg_adv_reg |=
1047 		    (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1048 		phy->autoneg_advertised |=
1049 		    (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1050 		break;
1051 	default:
1052 		e_dbg("Flow control param set incorrectly\n");
1053 		return -E1000_ERR_CONFIG;
1054 	}
1055 
1056 	ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1057 	if (ret_val)
1058 		return ret_val;
1059 
1060 	e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1061 
1062 	if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1063 		ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1064 
1065 	return ret_val;
1066 }
1067 
1068 /**
1069  *  e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1070  *  @hw: pointer to the HW structure
1071  *
1072  *  Performs initial bounds checking on autoneg advertisement parameter, then
1073  *  configure to advertise the full capability.  Setup the PHY to autoneg
1074  *  and restart the negotiation process between the link partner.  If
1075  *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1076  **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1077 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1078 {
1079 	struct e1000_phy_info *phy = &hw->phy;
1080 	s32 ret_val;
1081 	u16 phy_ctrl;
1082 
1083 	/* Perform some bounds checking on the autoneg advertisement
1084 	 * parameter.
1085 	 */
1086 	phy->autoneg_advertised &= phy->autoneg_mask;
1087 
1088 	/* If autoneg_advertised is zero, we assume it was not defaulted
1089 	 * by the calling code so we set to advertise full capability.
1090 	 */
1091 	if (!phy->autoneg_advertised)
1092 		phy->autoneg_advertised = phy->autoneg_mask;
1093 
1094 	e_dbg("Reconfiguring auto-neg advertisement params\n");
1095 	ret_val = e1000_phy_setup_autoneg(hw);
1096 	if (ret_val) {
1097 		e_dbg("Error Setting up Auto-Negotiation\n");
1098 		return ret_val;
1099 	}
1100 	e_dbg("Restarting Auto-Neg\n");
1101 
1102 	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
1103 	 * the Auto Neg Restart bit in the PHY control register.
1104 	 */
1105 	ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1106 	if (ret_val)
1107 		return ret_val;
1108 
1109 	phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1110 	ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1111 	if (ret_val)
1112 		return ret_val;
1113 
1114 	/* Does the user want to wait for Auto-Neg to complete here, or
1115 	 * check at a later time (for example, callback routine).
1116 	 */
1117 	if (phy->autoneg_wait_to_complete) {
1118 		ret_val = e1000_wait_autoneg(hw);
1119 		if (ret_val) {
1120 			e_dbg("Error while waiting for autoneg to complete\n");
1121 			return ret_val;
1122 		}
1123 	}
1124 
1125 	hw->mac.get_link_status = true;
1126 
1127 	return ret_val;
1128 }
1129 
1130 /**
1131  *  e1000e_setup_copper_link - Configure copper link settings
1132  *  @hw: pointer to the HW structure
1133  *
1134  *  Calls the appropriate function to configure the link for auto-neg or forced
1135  *  speed and duplex.  Then we check for link, once link is established calls
1136  *  to configure collision distance and flow control are called.  If link is
1137  *  not established, we return -E1000_ERR_PHY (-2).
1138  **/
e1000e_setup_copper_link(struct e1000_hw * hw)1139 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1140 {
1141 	s32 ret_val;
1142 	bool link;
1143 
1144 	if (hw->mac.autoneg) {
1145 		/* Setup autoneg and flow control advertisement and perform
1146 		 * autonegotiation.
1147 		 */
1148 		ret_val = e1000_copper_link_autoneg(hw);
1149 		if (ret_val)
1150 			return ret_val;
1151 	} else {
1152 		/* PHY will be set to 10H, 10F, 100H or 100F
1153 		 * depending on user settings.
1154 		 */
1155 		e_dbg("Forcing Speed and Duplex\n");
1156 		ret_val = hw->phy.ops.force_speed_duplex(hw);
1157 		if (ret_val) {
1158 			e_dbg("Error Forcing Speed and Duplex\n");
1159 			return ret_val;
1160 		}
1161 	}
1162 
1163 	/* Check link status. Wait up to 100 microseconds for link to become
1164 	 * valid.
1165 	 */
1166 	ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1167 					      &link);
1168 	if (ret_val)
1169 		return ret_val;
1170 
1171 	if (link) {
1172 		e_dbg("Valid link established!!!\n");
1173 		hw->mac.ops.config_collision_dist(hw);
1174 		ret_val = e1000e_config_fc_after_link_up(hw);
1175 	} else {
1176 		e_dbg("Unable to establish link!!!\n");
1177 	}
1178 
1179 	return ret_val;
1180 }
1181 
1182 /**
1183  *  e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1184  *  @hw: pointer to the HW structure
1185  *
1186  *  Calls the PHY setup function to force speed and duplex.  Clears the
1187  *  auto-crossover to force MDI manually.  Waits for link and returns
1188  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
1189  **/
e1000e_phy_force_speed_duplex_igp(struct e1000_hw * hw)1190 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1191 {
1192 	struct e1000_phy_info *phy = &hw->phy;
1193 	s32 ret_val;
1194 	u16 phy_data;
1195 	bool link;
1196 
1197 	ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1198 	if (ret_val)
1199 		return ret_val;
1200 
1201 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1202 
1203 	ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1204 	if (ret_val)
1205 		return ret_val;
1206 
1207 	/* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
1208 	 * forced whenever speed and duplex are forced.
1209 	 */
1210 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1211 	if (ret_val)
1212 		return ret_val;
1213 
1214 	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1215 	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1216 
1217 	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1218 	if (ret_val)
1219 		return ret_val;
1220 
1221 	e_dbg("IGP PSCR: %X\n", phy_data);
1222 
1223 	udelay(1);
1224 
1225 	if (phy->autoneg_wait_to_complete) {
1226 		e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1227 
1228 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1229 						      100000, &link);
1230 		if (ret_val)
1231 			return ret_val;
1232 
1233 		if (!link)
1234 			e_dbg("Link taking longer than expected.\n");
1235 
1236 		/* Try once more */
1237 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1238 						      100000, &link);
1239 	}
1240 
1241 	return ret_val;
1242 }
1243 
1244 /**
1245  *  e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1246  *  @hw: pointer to the HW structure
1247  *
1248  *  Calls the PHY setup function to force speed and duplex.  Clears the
1249  *  auto-crossover to force MDI manually.  Resets the PHY to commit the
1250  *  changes.  If time expires while waiting for link up, we reset the DSP.
1251  *  After reset, TX_CLK and CRS on Tx must be set.  Return successful upon
1252  *  successful completion, else return corresponding error code.
1253  **/
e1000e_phy_force_speed_duplex_m88(struct e1000_hw * hw)1254 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1255 {
1256 	struct e1000_phy_info *phy = &hw->phy;
1257 	s32 ret_val;
1258 	u16 phy_data;
1259 	bool link;
1260 
1261 	/* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
1262 	 * forced whenever speed and duplex are forced.
1263 	 */
1264 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1265 	if (ret_val)
1266 		return ret_val;
1267 
1268 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1269 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1270 	if (ret_val)
1271 		return ret_val;
1272 
1273 	e_dbg("M88E1000 PSCR: %X\n", phy_data);
1274 
1275 	ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1276 	if (ret_val)
1277 		return ret_val;
1278 
1279 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1280 
1281 	ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1282 	if (ret_val)
1283 		return ret_val;
1284 
1285 	/* Reset the phy to commit changes. */
1286 	if (hw->phy.ops.commit) {
1287 		ret_val = hw->phy.ops.commit(hw);
1288 		if (ret_val)
1289 			return ret_val;
1290 	}
1291 
1292 	if (phy->autoneg_wait_to_complete) {
1293 		e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1294 
1295 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1296 						      100000, &link);
1297 		if (ret_val)
1298 			return ret_val;
1299 
1300 		if (!link) {
1301 			if (hw->phy.type != e1000_phy_m88) {
1302 				e_dbg("Link taking longer than expected.\n");
1303 			} else {
1304 				/* We didn't get link.
1305 				 * Reset the DSP and cross our fingers.
1306 				 */
1307 				ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1308 						   0x001d);
1309 				if (ret_val)
1310 					return ret_val;
1311 				ret_val = e1000e_phy_reset_dsp(hw);
1312 				if (ret_val)
1313 					return ret_val;
1314 			}
1315 		}
1316 
1317 		/* Try once more */
1318 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1319 						      100000, &link);
1320 		if (ret_val)
1321 			return ret_val;
1322 	}
1323 
1324 	if (hw->phy.type != e1000_phy_m88)
1325 		return 0;
1326 
1327 	ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1328 	if (ret_val)
1329 		return ret_val;
1330 
1331 	/* Resetting the phy means we need to re-force TX_CLK in the
1332 	 * Extended PHY Specific Control Register to 25MHz clock from
1333 	 * the reset value of 2.5MHz.
1334 	 */
1335 	phy_data |= M88E1000_EPSCR_TX_CLK_25;
1336 	ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1337 	if (ret_val)
1338 		return ret_val;
1339 
1340 	/* In addition, we must re-enable CRS on Tx for both half and full
1341 	 * duplex.
1342 	 */
1343 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1344 	if (ret_val)
1345 		return ret_val;
1346 
1347 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1348 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1349 
1350 	return ret_val;
1351 }
1352 
1353 /**
1354  *  e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1355  *  @hw: pointer to the HW structure
1356  *
1357  *  Forces the speed and duplex settings of the PHY.
1358  *  This is a function pointer entry point only called by
1359  *  PHY setup routines.
1360  **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1361 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1362 {
1363 	struct e1000_phy_info *phy = &hw->phy;
1364 	s32 ret_val;
1365 	u16 data;
1366 	bool link;
1367 
1368 	ret_val = e1e_rphy(hw, MII_BMCR, &data);
1369 	if (ret_val)
1370 		return ret_val;
1371 
1372 	e1000e_phy_force_speed_duplex_setup(hw, &data);
1373 
1374 	ret_val = e1e_wphy(hw, MII_BMCR, data);
1375 	if (ret_val)
1376 		return ret_val;
1377 
1378 	/* Disable MDI-X support for 10/100 */
1379 	ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1380 	if (ret_val)
1381 		return ret_val;
1382 
1383 	data &= ~IFE_PMC_AUTO_MDIX;
1384 	data &= ~IFE_PMC_FORCE_MDIX;
1385 
1386 	ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1387 	if (ret_val)
1388 		return ret_val;
1389 
1390 	e_dbg("IFE PMC: %X\n", data);
1391 
1392 	udelay(1);
1393 
1394 	if (phy->autoneg_wait_to_complete) {
1395 		e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1396 
1397 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1398 						      100000, &link);
1399 		if (ret_val)
1400 			return ret_val;
1401 
1402 		if (!link)
1403 			e_dbg("Link taking longer than expected.\n");
1404 
1405 		/* Try once more */
1406 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1407 						      100000, &link);
1408 		if (ret_val)
1409 			return ret_val;
1410 	}
1411 
1412 	return 0;
1413 }
1414 
1415 /**
1416  *  e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1417  *  @hw: pointer to the HW structure
1418  *  @phy_ctrl: pointer to current value of MII_BMCR
1419  *
1420  *  Forces speed and duplex on the PHY by doing the following: disable flow
1421  *  control, force speed/duplex on the MAC, disable auto speed detection,
1422  *  disable auto-negotiation, configure duplex, configure speed, configure
1423  *  the collision distance, write configuration to CTRL register.  The
1424  *  caller must write to the MII_BMCR register for these settings to
1425  *  take affect.
1426  **/
e1000e_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1427 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1428 {
1429 	struct e1000_mac_info *mac = &hw->mac;
1430 	u32 ctrl;
1431 
1432 	/* Turn off flow control when forcing speed/duplex */
1433 	hw->fc.current_mode = e1000_fc_none;
1434 
1435 	/* Force speed/duplex on the mac */
1436 	ctrl = er32(CTRL);
1437 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1438 	ctrl &= ~E1000_CTRL_SPD_SEL;
1439 
1440 	/* Disable Auto Speed Detection */
1441 	ctrl &= ~E1000_CTRL_ASDE;
1442 
1443 	/* Disable autoneg on the phy */
1444 	*phy_ctrl &= ~BMCR_ANENABLE;
1445 
1446 	/* Forcing Full or Half Duplex? */
1447 	if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1448 		ctrl &= ~E1000_CTRL_FD;
1449 		*phy_ctrl &= ~BMCR_FULLDPLX;
1450 		e_dbg("Half Duplex\n");
1451 	} else {
1452 		ctrl |= E1000_CTRL_FD;
1453 		*phy_ctrl |= BMCR_FULLDPLX;
1454 		e_dbg("Full Duplex\n");
1455 	}
1456 
1457 	/* Forcing 10mb or 100mb? */
1458 	if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1459 		ctrl |= E1000_CTRL_SPD_100;
1460 		*phy_ctrl |= BMCR_SPEED100;
1461 		*phy_ctrl &= ~BMCR_SPEED1000;
1462 		e_dbg("Forcing 100mb\n");
1463 	} else {
1464 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1465 		*phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1466 		e_dbg("Forcing 10mb\n");
1467 	}
1468 
1469 	hw->mac.ops.config_collision_dist(hw);
1470 
1471 	ew32(CTRL, ctrl);
1472 }
1473 
1474 /**
1475  *  e1000e_set_d3_lplu_state - Sets low power link up state for D3
1476  *  @hw: pointer to the HW structure
1477  *  @active: boolean used to enable/disable lplu
1478  *
1479  *  Success returns 0, Failure returns 1
1480  *
1481  *  The low power link up (lplu) state is set to the power management level D3
1482  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1483  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1484  *  is used during Dx states where the power conservation is most important.
1485  *  During driver activity, SmartSpeed should be enabled so performance is
1486  *  maintained.
1487  **/
e1000e_set_d3_lplu_state(struct e1000_hw * hw,bool active)1488 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1489 {
1490 	struct e1000_phy_info *phy = &hw->phy;
1491 	s32 ret_val;
1492 	u16 data;
1493 
1494 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1495 	if (ret_val)
1496 		return ret_val;
1497 
1498 	if (!active) {
1499 		data &= ~IGP02E1000_PM_D3_LPLU;
1500 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1501 		if (ret_val)
1502 			return ret_val;
1503 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1504 		 * during Dx states where the power conservation is most
1505 		 * important.  During driver activity we should enable
1506 		 * SmartSpeed, so performance is maintained.
1507 		 */
1508 		if (phy->smart_speed == e1000_smart_speed_on) {
1509 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1510 					   &data);
1511 			if (ret_val)
1512 				return ret_val;
1513 
1514 			data |= IGP01E1000_PSCFR_SMART_SPEED;
1515 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1516 					   data);
1517 			if (ret_val)
1518 				return ret_val;
1519 		} else if (phy->smart_speed == e1000_smart_speed_off) {
1520 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1521 					   &data);
1522 			if (ret_val)
1523 				return ret_val;
1524 
1525 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1526 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1527 					   data);
1528 			if (ret_val)
1529 				return ret_val;
1530 		}
1531 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1532 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1533 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1534 		data |= IGP02E1000_PM_D3_LPLU;
1535 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1536 		if (ret_val)
1537 			return ret_val;
1538 
1539 		/* When LPLU is enabled, we should disable SmartSpeed */
1540 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1541 		if (ret_val)
1542 			return ret_val;
1543 
1544 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1545 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1546 	}
1547 
1548 	return ret_val;
1549 }
1550 
1551 /**
1552  *  e1000e_check_downshift - Checks whether a downshift in speed occurred
1553  *  @hw: pointer to the HW structure
1554  *
1555  *  Success returns 0, Failure returns 1
1556  *
1557  *  A downshift is detected by querying the PHY link health.
1558  **/
e1000e_check_downshift(struct e1000_hw * hw)1559 s32 e1000e_check_downshift(struct e1000_hw *hw)
1560 {
1561 	struct e1000_phy_info *phy = &hw->phy;
1562 	s32 ret_val;
1563 	u16 phy_data, offset, mask;
1564 
1565 	switch (phy->type) {
1566 	case e1000_phy_m88:
1567 	case e1000_phy_gg82563:
1568 	case e1000_phy_bm:
1569 	case e1000_phy_82578:
1570 		offset = M88E1000_PHY_SPEC_STATUS;
1571 		mask = M88E1000_PSSR_DOWNSHIFT;
1572 		break;
1573 	case e1000_phy_igp_2:
1574 	case e1000_phy_igp_3:
1575 		offset = IGP01E1000_PHY_LINK_HEALTH;
1576 		mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1577 		break;
1578 	default:
1579 		/* speed downshift not supported */
1580 		phy->speed_downgraded = false;
1581 		return 0;
1582 	}
1583 
1584 	ret_val = e1e_rphy(hw, offset, &phy_data);
1585 
1586 	if (!ret_val)
1587 		phy->speed_downgraded = !!(phy_data & mask);
1588 
1589 	return ret_val;
1590 }
1591 
1592 /**
1593  *  e1000_check_polarity_m88 - Checks the polarity.
1594  *  @hw: pointer to the HW structure
1595  *
1596  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1597  *
1598  *  Polarity is determined based on the PHY specific status register.
1599  **/
e1000_check_polarity_m88(struct e1000_hw * hw)1600 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1601 {
1602 	struct e1000_phy_info *phy = &hw->phy;
1603 	s32 ret_val;
1604 	u16 data;
1605 
1606 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1607 
1608 	if (!ret_val)
1609 		phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1610 				       ? e1000_rev_polarity_reversed
1611 				       : e1000_rev_polarity_normal);
1612 
1613 	return ret_val;
1614 }
1615 
1616 /**
1617  *  e1000_check_polarity_igp - Checks the polarity.
1618  *  @hw: pointer to the HW structure
1619  *
1620  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1621  *
1622  *  Polarity is determined based on the PHY port status register, and the
1623  *  current speed (since there is no polarity at 100Mbps).
1624  **/
e1000_check_polarity_igp(struct e1000_hw * hw)1625 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1626 {
1627 	struct e1000_phy_info *phy = &hw->phy;
1628 	s32 ret_val;
1629 	u16 data, offset, mask;
1630 
1631 	/* Polarity is determined based on the speed of
1632 	 * our connection.
1633 	 */
1634 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1635 	if (ret_val)
1636 		return ret_val;
1637 
1638 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1639 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
1640 		offset = IGP01E1000_PHY_PCS_INIT_REG;
1641 		mask = IGP01E1000_PHY_POLARITY_MASK;
1642 	} else {
1643 		/* This really only applies to 10Mbps since
1644 		 * there is no polarity for 100Mbps (always 0).
1645 		 */
1646 		offset = IGP01E1000_PHY_PORT_STATUS;
1647 		mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1648 	}
1649 
1650 	ret_val = e1e_rphy(hw, offset, &data);
1651 
1652 	if (!ret_val)
1653 		phy->cable_polarity = ((data & mask)
1654 				       ? e1000_rev_polarity_reversed
1655 				       : e1000_rev_polarity_normal);
1656 
1657 	return ret_val;
1658 }
1659 
1660 /**
1661  *  e1000_check_polarity_ife - Check cable polarity for IFE PHY
1662  *  @hw: pointer to the HW structure
1663  *
1664  *  Polarity is determined on the polarity reversal feature being enabled.
1665  **/
e1000_check_polarity_ife(struct e1000_hw * hw)1666 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1667 {
1668 	struct e1000_phy_info *phy = &hw->phy;
1669 	s32 ret_val;
1670 	u16 phy_data, offset, mask;
1671 
1672 	/* Polarity is determined based on the reversal feature being enabled.
1673 	 */
1674 	if (phy->polarity_correction) {
1675 		offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1676 		mask = IFE_PESC_POLARITY_REVERSED;
1677 	} else {
1678 		offset = IFE_PHY_SPECIAL_CONTROL;
1679 		mask = IFE_PSC_FORCE_POLARITY;
1680 	}
1681 
1682 	ret_val = e1e_rphy(hw, offset, &phy_data);
1683 
1684 	if (!ret_val)
1685 		phy->cable_polarity = ((phy_data & mask)
1686 				       ? e1000_rev_polarity_reversed
1687 				       : e1000_rev_polarity_normal);
1688 
1689 	return ret_val;
1690 }
1691 
1692 /**
1693  *  e1000_wait_autoneg - Wait for auto-neg completion
1694  *  @hw: pointer to the HW structure
1695  *
1696  *  Waits for auto-negotiation to complete or for the auto-negotiation time
1697  *  limit to expire, which ever happens first.
1698  **/
e1000_wait_autoneg(struct e1000_hw * hw)1699 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1700 {
1701 	s32 ret_val = 0;
1702 	u16 i, phy_status;
1703 
1704 	/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1705 	for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1706 		ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1707 		if (ret_val)
1708 			break;
1709 		ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1710 		if (ret_val)
1711 			break;
1712 		if (phy_status & BMSR_ANEGCOMPLETE)
1713 			break;
1714 		msleep(100);
1715 	}
1716 
1717 	/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1718 	 * has completed.
1719 	 */
1720 	return ret_val;
1721 }
1722 
1723 /**
1724  *  e1000e_phy_has_link_generic - Polls PHY for link
1725  *  @hw: pointer to the HW structure
1726  *  @iterations: number of times to poll for link
1727  *  @usec_interval: delay between polling attempts
1728  *  @success: pointer to whether polling was successful or not
1729  *
1730  *  Polls the PHY status register for link, 'iterations' number of times.
1731  **/
e1000e_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1732 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1733 				u32 usec_interval, bool *success)
1734 {
1735 	s32 ret_val = 0;
1736 	u16 i, phy_status;
1737 
1738 	*success = false;
1739 	for (i = 0; i < iterations; i++) {
1740 		/* Some PHYs require the MII_BMSR register to be read
1741 		 * twice due to the link bit being sticky.  No harm doing
1742 		 * it across the board.
1743 		 */
1744 		ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1745 		if (ret_val) {
1746 			/* If the first read fails, another entity may have
1747 			 * ownership of the resources, wait and try again to
1748 			 * see if they have relinquished the resources yet.
1749 			 */
1750 			if (usec_interval >= 1000)
1751 				msleep(usec_interval / 1000);
1752 			else
1753 				udelay(usec_interval);
1754 		}
1755 		ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1756 		if (ret_val)
1757 			break;
1758 		if (phy_status & BMSR_LSTATUS) {
1759 			*success = true;
1760 			break;
1761 		}
1762 		if (usec_interval >= 1000)
1763 			msleep(usec_interval / 1000);
1764 		else
1765 			udelay(usec_interval);
1766 	}
1767 
1768 	return ret_val;
1769 }
1770 
1771 /**
1772  *  e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1773  *  @hw: pointer to the HW structure
1774  *
1775  *  Reads the PHY specific status register to retrieve the cable length
1776  *  information.  The cable length is determined by averaging the minimum and
1777  *  maximum values to get the "average" cable length.  The m88 PHY has four
1778  *  possible cable length values, which are:
1779  *	Register Value		Cable Length
1780  *	0			< 50 meters
1781  *	1			50 - 80 meters
1782  *	2			80 - 110 meters
1783  *	3			110 - 140 meters
1784  *	4			> 140 meters
1785  **/
e1000e_get_cable_length_m88(struct e1000_hw * hw)1786 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1787 {
1788 	struct e1000_phy_info *phy = &hw->phy;
1789 	s32 ret_val;
1790 	u16 phy_data, index;
1791 
1792 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1793 	if (ret_val)
1794 		return ret_val;
1795 
1796 	index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1797 		 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1798 
1799 	if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1800 		return -E1000_ERR_PHY;
1801 
1802 	phy->min_cable_length = e1000_m88_cable_length_table[index];
1803 	phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1804 
1805 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1806 
1807 	return 0;
1808 }
1809 
1810 /**
1811  *  e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1812  *  @hw: pointer to the HW structure
1813  *
1814  *  The automatic gain control (agc) normalizes the amplitude of the
1815  *  received signal, adjusting for the attenuation produced by the
1816  *  cable.  By reading the AGC registers, which represent the
1817  *  combination of coarse and fine gain value, the value can be put
1818  *  into a lookup table to obtain the approximate cable length
1819  *  for each channel.
1820  **/
e1000e_get_cable_length_igp_2(struct e1000_hw * hw)1821 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1822 {
1823 	struct e1000_phy_info *phy = &hw->phy;
1824 	s32 ret_val;
1825 	u16 phy_data, i, agc_value = 0;
1826 	u16 cur_agc_index, max_agc_index = 0;
1827 	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1828 	static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1829 		IGP02E1000_PHY_AGC_A,
1830 		IGP02E1000_PHY_AGC_B,
1831 		IGP02E1000_PHY_AGC_C,
1832 		IGP02E1000_PHY_AGC_D
1833 	};
1834 
1835 	/* Read the AGC registers for all channels */
1836 	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1837 		ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1838 		if (ret_val)
1839 			return ret_val;
1840 
1841 		/* Getting bits 15:9, which represent the combination of
1842 		 * coarse and fine gain values.  The result is a number
1843 		 * that can be put into the lookup table to obtain the
1844 		 * approximate cable length.
1845 		 */
1846 		cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1847 				 IGP02E1000_AGC_LENGTH_MASK);
1848 
1849 		/* Array index bound check. */
1850 		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1851 		    (cur_agc_index == 0))
1852 			return -E1000_ERR_PHY;
1853 
1854 		/* Remove min & max AGC values from calculation. */
1855 		if (e1000_igp_2_cable_length_table[min_agc_index] >
1856 		    e1000_igp_2_cable_length_table[cur_agc_index])
1857 			min_agc_index = cur_agc_index;
1858 		if (e1000_igp_2_cable_length_table[max_agc_index] <
1859 		    e1000_igp_2_cable_length_table[cur_agc_index])
1860 			max_agc_index = cur_agc_index;
1861 
1862 		agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1863 	}
1864 
1865 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1866 		      e1000_igp_2_cable_length_table[max_agc_index]);
1867 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1868 
1869 	/* Calculate cable length with the error range of +/- 10 meters. */
1870 	phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1871 				 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1872 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1873 
1874 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1875 
1876 	return 0;
1877 }
1878 
1879 /**
1880  *  e1000e_get_phy_info_m88 - Retrieve PHY information
1881  *  @hw: pointer to the HW structure
1882  *
1883  *  Valid for only copper links.  Read the PHY status register (sticky read)
1884  *  to verify that link is up.  Read the PHY special control register to
1885  *  determine the polarity and 10base-T extended distance.  Read the PHY
1886  *  special status register to determine MDI/MDIx and current speed.  If
1887  *  speed is 1000, then determine cable length, local and remote receiver.
1888  **/
e1000e_get_phy_info_m88(struct e1000_hw * hw)1889 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1890 {
1891 	struct e1000_phy_info *phy = &hw->phy;
1892 	s32 ret_val;
1893 	u16 phy_data;
1894 	bool link;
1895 
1896 	if (phy->media_type != e1000_media_type_copper) {
1897 		e_dbg("Phy info is only valid for copper media\n");
1898 		return -E1000_ERR_CONFIG;
1899 	}
1900 
1901 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1902 	if (ret_val)
1903 		return ret_val;
1904 
1905 	if (!link) {
1906 		e_dbg("Phy info is only valid if link is up\n");
1907 		return -E1000_ERR_CONFIG;
1908 	}
1909 
1910 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1911 	if (ret_val)
1912 		return ret_val;
1913 
1914 	phy->polarity_correction = !!(phy_data &
1915 				      M88E1000_PSCR_POLARITY_REVERSAL);
1916 
1917 	ret_val = e1000_check_polarity_m88(hw);
1918 	if (ret_val)
1919 		return ret_val;
1920 
1921 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1922 	if (ret_val)
1923 		return ret_val;
1924 
1925 	phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1926 
1927 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1928 		ret_val = hw->phy.ops.get_cable_length(hw);
1929 		if (ret_val)
1930 			return ret_val;
1931 
1932 		ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1933 		if (ret_val)
1934 			return ret_val;
1935 
1936 		phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1937 		    ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1938 
1939 		phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1940 		    ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1941 	} else {
1942 		/* Set values to "undefined" */
1943 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1944 		phy->local_rx = e1000_1000t_rx_status_undefined;
1945 		phy->remote_rx = e1000_1000t_rx_status_undefined;
1946 	}
1947 
1948 	return ret_val;
1949 }
1950 
1951 /**
1952  *  e1000e_get_phy_info_igp - Retrieve igp PHY information
1953  *  @hw: pointer to the HW structure
1954  *
1955  *  Read PHY status to determine if link is up.  If link is up, then
1956  *  set/determine 10base-T extended distance and polarity correction.  Read
1957  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
1958  *  determine on the cable length, local and remote receiver.
1959  **/
e1000e_get_phy_info_igp(struct e1000_hw * hw)1960 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1961 {
1962 	struct e1000_phy_info *phy = &hw->phy;
1963 	s32 ret_val;
1964 	u16 data;
1965 	bool link;
1966 
1967 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1968 	if (ret_val)
1969 		return ret_val;
1970 
1971 	if (!link) {
1972 		e_dbg("Phy info is only valid if link is up\n");
1973 		return -E1000_ERR_CONFIG;
1974 	}
1975 
1976 	phy->polarity_correction = true;
1977 
1978 	ret_val = e1000_check_polarity_igp(hw);
1979 	if (ret_val)
1980 		return ret_val;
1981 
1982 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1983 	if (ret_val)
1984 		return ret_val;
1985 
1986 	phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1987 
1988 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1989 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
1990 		ret_val = phy->ops.get_cable_length(hw);
1991 		if (ret_val)
1992 			return ret_val;
1993 
1994 		ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1995 		if (ret_val)
1996 			return ret_val;
1997 
1998 		phy->local_rx = (data & LPA_1000LOCALRXOK)
1999 		    ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2000 
2001 		phy->remote_rx = (data & LPA_1000REMRXOK)
2002 		    ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2003 	} else {
2004 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2005 		phy->local_rx = e1000_1000t_rx_status_undefined;
2006 		phy->remote_rx = e1000_1000t_rx_status_undefined;
2007 	}
2008 
2009 	return ret_val;
2010 }
2011 
2012 /**
2013  *  e1000_get_phy_info_ife - Retrieves various IFE PHY states
2014  *  @hw: pointer to the HW structure
2015  *
2016  *  Populates "phy" structure with various feature states.
2017  **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2018 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2019 {
2020 	struct e1000_phy_info *phy = &hw->phy;
2021 	s32 ret_val;
2022 	u16 data;
2023 	bool link;
2024 
2025 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2026 	if (ret_val)
2027 		return ret_val;
2028 
2029 	if (!link) {
2030 		e_dbg("Phy info is only valid if link is up\n");
2031 		return -E1000_ERR_CONFIG;
2032 	}
2033 
2034 	ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2035 	if (ret_val)
2036 		return ret_val;
2037 	phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2038 
2039 	if (phy->polarity_correction) {
2040 		ret_val = e1000_check_polarity_ife(hw);
2041 		if (ret_val)
2042 			return ret_val;
2043 	} else {
2044 		/* Polarity is forced */
2045 		phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2046 				       ? e1000_rev_polarity_reversed
2047 				       : e1000_rev_polarity_normal);
2048 	}
2049 
2050 	ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2051 	if (ret_val)
2052 		return ret_val;
2053 
2054 	phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2055 
2056 	/* The following parameters are undefined for 10/100 operation. */
2057 	phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2058 	phy->local_rx = e1000_1000t_rx_status_undefined;
2059 	phy->remote_rx = e1000_1000t_rx_status_undefined;
2060 
2061 	return 0;
2062 }
2063 
2064 /**
2065  *  e1000e_phy_sw_reset - PHY software reset
2066  *  @hw: pointer to the HW structure
2067  *
2068  *  Does a software reset of the PHY by reading the PHY control register and
2069  *  setting/write the control register reset bit to the PHY.
2070  **/
e1000e_phy_sw_reset(struct e1000_hw * hw)2071 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2072 {
2073 	s32 ret_val;
2074 	u16 phy_ctrl;
2075 
2076 	ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2077 	if (ret_val)
2078 		return ret_val;
2079 
2080 	phy_ctrl |= BMCR_RESET;
2081 	ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2082 	if (ret_val)
2083 		return ret_val;
2084 
2085 	udelay(1);
2086 
2087 	return ret_val;
2088 }
2089 
2090 /**
2091  *  e1000e_phy_hw_reset_generic - PHY hardware reset
2092  *  @hw: pointer to the HW structure
2093  *
2094  *  Verify the reset block is not blocking us from resetting.  Acquire
2095  *  semaphore (if necessary) and read/set/write the device control reset
2096  *  bit in the PHY.  Wait the appropriate delay time for the device to
2097  *  reset and release the semaphore (if necessary).
2098  **/
e1000e_phy_hw_reset_generic(struct e1000_hw * hw)2099 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2100 {
2101 	struct e1000_phy_info *phy = &hw->phy;
2102 	s32 ret_val;
2103 	u32 ctrl;
2104 
2105 	if (phy->ops.check_reset_block) {
2106 		ret_val = phy->ops.check_reset_block(hw);
2107 		if (ret_val)
2108 			return 0;
2109 	}
2110 
2111 	ret_val = phy->ops.acquire(hw);
2112 	if (ret_val)
2113 		return ret_val;
2114 
2115 	ctrl = er32(CTRL);
2116 	ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2117 	e1e_flush();
2118 
2119 	udelay(phy->reset_delay_us);
2120 
2121 	ew32(CTRL, ctrl);
2122 	e1e_flush();
2123 
2124 	usleep_range(150, 300);
2125 
2126 	phy->ops.release(hw);
2127 
2128 	return phy->ops.get_cfg_done(hw);
2129 }
2130 
2131 /**
2132  *  e1000e_get_cfg_done_generic - Generic configuration done
2133  *  @hw: pointer to the HW structure
2134  *
2135  *  Generic function to wait 10 milli-seconds for configuration to complete
2136  *  and return success.
2137  **/
e1000e_get_cfg_done_generic(struct e1000_hw __always_unused * hw)2138 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2139 {
2140 	mdelay(10);
2141 
2142 	return 0;
2143 }
2144 
2145 /**
2146  *  e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2147  *  @hw: pointer to the HW structure
2148  *
2149  *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2150  **/
e1000e_phy_init_script_igp3(struct e1000_hw * hw)2151 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2152 {
2153 	e_dbg("Running IGP 3 PHY init script\n");
2154 
2155 	/* PHY init IGP 3 */
2156 	/* Enable rise/fall, 10-mode work in class-A */
2157 	e1e_wphy(hw, 0x2F5B, 0x9018);
2158 	/* Remove all caps from Replica path filter */
2159 	e1e_wphy(hw, 0x2F52, 0x0000);
2160 	/* Bias trimming for ADC, AFE and Driver (Default) */
2161 	e1e_wphy(hw, 0x2FB1, 0x8B24);
2162 	/* Increase Hybrid poly bias */
2163 	e1e_wphy(hw, 0x2FB2, 0xF8F0);
2164 	/* Add 4% to Tx amplitude in Gig mode */
2165 	e1e_wphy(hw, 0x2010, 0x10B0);
2166 	/* Disable trimming (TTT) */
2167 	e1e_wphy(hw, 0x2011, 0x0000);
2168 	/* Poly DC correction to 94.6% + 2% for all channels */
2169 	e1e_wphy(hw, 0x20DD, 0x249A);
2170 	/* ABS DC correction to 95.9% */
2171 	e1e_wphy(hw, 0x20DE, 0x00D3);
2172 	/* BG temp curve trim */
2173 	e1e_wphy(hw, 0x28B4, 0x04CE);
2174 	/* Increasing ADC OPAMP stage 1 currents to max */
2175 	e1e_wphy(hw, 0x2F70, 0x29E4);
2176 	/* Force 1000 ( required for enabling PHY regs configuration) */
2177 	e1e_wphy(hw, 0x0000, 0x0140);
2178 	/* Set upd_freq to 6 */
2179 	e1e_wphy(hw, 0x1F30, 0x1606);
2180 	/* Disable NPDFE */
2181 	e1e_wphy(hw, 0x1F31, 0xB814);
2182 	/* Disable adaptive fixed FFE (Default) */
2183 	e1e_wphy(hw, 0x1F35, 0x002A);
2184 	/* Enable FFE hysteresis */
2185 	e1e_wphy(hw, 0x1F3E, 0x0067);
2186 	/* Fixed FFE for short cable lengths */
2187 	e1e_wphy(hw, 0x1F54, 0x0065);
2188 	/* Fixed FFE for medium cable lengths */
2189 	e1e_wphy(hw, 0x1F55, 0x002A);
2190 	/* Fixed FFE for long cable lengths */
2191 	e1e_wphy(hw, 0x1F56, 0x002A);
2192 	/* Enable Adaptive Clip Threshold */
2193 	e1e_wphy(hw, 0x1F72, 0x3FB0);
2194 	/* AHT reset limit to 1 */
2195 	e1e_wphy(hw, 0x1F76, 0xC0FF);
2196 	/* Set AHT master delay to 127 msec */
2197 	e1e_wphy(hw, 0x1F77, 0x1DEC);
2198 	/* Set scan bits for AHT */
2199 	e1e_wphy(hw, 0x1F78, 0xF9EF);
2200 	/* Set AHT Preset bits */
2201 	e1e_wphy(hw, 0x1F79, 0x0210);
2202 	/* Change integ_factor of channel A to 3 */
2203 	e1e_wphy(hw, 0x1895, 0x0003);
2204 	/* Change prop_factor of channels BCD to 8 */
2205 	e1e_wphy(hw, 0x1796, 0x0008);
2206 	/* Change cg_icount + enable integbp for channels BCD */
2207 	e1e_wphy(hw, 0x1798, 0xD008);
2208 	/* Change cg_icount + enable integbp + change prop_factor_master
2209 	 * to 8 for channel A
2210 	 */
2211 	e1e_wphy(hw, 0x1898, 0xD918);
2212 	/* Disable AHT in Slave mode on channel A */
2213 	e1e_wphy(hw, 0x187A, 0x0800);
2214 	/* Enable LPLU and disable AN to 1000 in non-D0a states,
2215 	 * Enable SPD+B2B
2216 	 */
2217 	e1e_wphy(hw, 0x0019, 0x008D);
2218 	/* Enable restart AN on an1000_dis change */
2219 	e1e_wphy(hw, 0x001B, 0x2080);
2220 	/* Enable wh_fifo read clock in 10/100 modes */
2221 	e1e_wphy(hw, 0x0014, 0x0045);
2222 	/* Restart AN, Speed selection is 1000 */
2223 	e1e_wphy(hw, 0x0000, 0x1340);
2224 
2225 	return 0;
2226 }
2227 
2228 /**
2229  *  e1000e_get_phy_type_from_id - Get PHY type from id
2230  *  @phy_id: phy_id read from the phy
2231  *
2232  *  Returns the phy type from the id.
2233  **/
e1000e_get_phy_type_from_id(u32 phy_id)2234 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2235 {
2236 	enum e1000_phy_type phy_type = e1000_phy_unknown;
2237 
2238 	switch (phy_id) {
2239 	case M88E1000_I_PHY_ID:
2240 	case M88E1000_E_PHY_ID:
2241 	case M88E1111_I_PHY_ID:
2242 	case M88E1011_I_PHY_ID:
2243 		phy_type = e1000_phy_m88;
2244 		break;
2245 	case IGP01E1000_I_PHY_ID:	/* IGP 1 & 2 share this */
2246 		phy_type = e1000_phy_igp_2;
2247 		break;
2248 	case GG82563_E_PHY_ID:
2249 		phy_type = e1000_phy_gg82563;
2250 		break;
2251 	case IGP03E1000_E_PHY_ID:
2252 		phy_type = e1000_phy_igp_3;
2253 		break;
2254 	case IFE_E_PHY_ID:
2255 	case IFE_PLUS_E_PHY_ID:
2256 	case IFE_C_E_PHY_ID:
2257 		phy_type = e1000_phy_ife;
2258 		break;
2259 	case BME1000_E_PHY_ID:
2260 	case BME1000_E_PHY_ID_R2:
2261 		phy_type = e1000_phy_bm;
2262 		break;
2263 	case I82578_E_PHY_ID:
2264 		phy_type = e1000_phy_82578;
2265 		break;
2266 	case I82577_E_PHY_ID:
2267 		phy_type = e1000_phy_82577;
2268 		break;
2269 	case I82579_E_PHY_ID:
2270 		phy_type = e1000_phy_82579;
2271 		break;
2272 	case I217_E_PHY_ID:
2273 		phy_type = e1000_phy_i217;
2274 		break;
2275 	default:
2276 		phy_type = e1000_phy_unknown;
2277 		break;
2278 	}
2279 	return phy_type;
2280 }
2281 
2282 /**
2283  *  e1000e_determine_phy_address - Determines PHY address.
2284  *  @hw: pointer to the HW structure
2285  *
2286  *  This uses a trial and error method to loop through possible PHY
2287  *  addresses. It tests each by reading the PHY ID registers and
2288  *  checking for a match.
2289  **/
e1000e_determine_phy_address(struct e1000_hw * hw)2290 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2291 {
2292 	u32 phy_addr = 0;
2293 	u32 i;
2294 	enum e1000_phy_type phy_type = e1000_phy_unknown;
2295 
2296 	hw->phy.id = phy_type;
2297 
2298 	for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2299 		hw->phy.addr = phy_addr;
2300 		i = 0;
2301 
2302 		do {
2303 			e1000e_get_phy_id(hw);
2304 			phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2305 
2306 			/* If phy_type is valid, break - we found our
2307 			 * PHY address
2308 			 */
2309 			if (phy_type != e1000_phy_unknown)
2310 				return 0;
2311 
2312 			usleep_range(1000, 2000);
2313 			i++;
2314 		} while (i < 10);
2315 	}
2316 
2317 	return -E1000_ERR_PHY_TYPE;
2318 }
2319 
2320 /**
2321  *  e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2322  *  @page: page to access
2323  *  @reg: register to check
2324  *
2325  *  Returns the phy address for the page requested.
2326  **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)2327 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2328 {
2329 	u32 phy_addr = 2;
2330 
2331 	if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2332 		phy_addr = 1;
2333 
2334 	return phy_addr;
2335 }
2336 
2337 /**
2338  *  e1000e_write_phy_reg_bm - Write BM PHY register
2339  *  @hw: pointer to the HW structure
2340  *  @offset: register offset to write to
2341  *  @data: data to write at register offset
2342  *
2343  *  Acquires semaphore, if necessary, then writes the data to PHY register
2344  *  at the offset.  Release any acquired semaphores before exiting.
2345  **/
e1000e_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)2346 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2347 {
2348 	s32 ret_val;
2349 	u32 page = offset >> IGP_PAGE_SHIFT;
2350 
2351 	ret_val = hw->phy.ops.acquire(hw);
2352 	if (ret_val)
2353 		return ret_val;
2354 
2355 	/* Page 800 works differently than the rest so it has its own func */
2356 	if (page == BM_WUC_PAGE) {
2357 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2358 							 false, false);
2359 		goto release;
2360 	}
2361 
2362 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2363 
2364 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
2365 		u32 page_shift, page_select;
2366 
2367 		/* Page select is register 31 for phy address 1 and 22 for
2368 		 * phy address 2 and 3. Page select is shifted only for
2369 		 * phy address 1.
2370 		 */
2371 		if (hw->phy.addr == 1) {
2372 			page_shift = IGP_PAGE_SHIFT;
2373 			page_select = IGP01E1000_PHY_PAGE_SELECT;
2374 		} else {
2375 			page_shift = 0;
2376 			page_select = BM_PHY_PAGE_SELECT;
2377 		}
2378 
2379 		/* Page is shifted left, PHY expects (page x 32) */
2380 		ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2381 						    (page << page_shift));
2382 		if (ret_val)
2383 			goto release;
2384 	}
2385 
2386 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2387 					    data);
2388 
2389 release:
2390 	hw->phy.ops.release(hw);
2391 	return ret_val;
2392 }
2393 
2394 /**
2395  *  e1000e_read_phy_reg_bm - Read BM PHY register
2396  *  @hw: pointer to the HW structure
2397  *  @offset: register offset to be read
2398  *  @data: pointer to the read data
2399  *
2400  *  Acquires semaphore, if necessary, then reads the PHY register at offset
2401  *  and storing the retrieved information in data.  Release any acquired
2402  *  semaphores before exiting.
2403  **/
e1000e_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)2404 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2405 {
2406 	s32 ret_val;
2407 	u32 page = offset >> IGP_PAGE_SHIFT;
2408 
2409 	ret_val = hw->phy.ops.acquire(hw);
2410 	if (ret_val)
2411 		return ret_val;
2412 
2413 	/* Page 800 works differently than the rest so it has its own func */
2414 	if (page == BM_WUC_PAGE) {
2415 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2416 							 true, false);
2417 		goto release;
2418 	}
2419 
2420 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2421 
2422 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
2423 		u32 page_shift, page_select;
2424 
2425 		/* Page select is register 31 for phy address 1 and 22 for
2426 		 * phy address 2 and 3. Page select is shifted only for
2427 		 * phy address 1.
2428 		 */
2429 		if (hw->phy.addr == 1) {
2430 			page_shift = IGP_PAGE_SHIFT;
2431 			page_select = IGP01E1000_PHY_PAGE_SELECT;
2432 		} else {
2433 			page_shift = 0;
2434 			page_select = BM_PHY_PAGE_SELECT;
2435 		}
2436 
2437 		/* Page is shifted left, PHY expects (page x 32) */
2438 		ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2439 						    (page << page_shift));
2440 		if (ret_val)
2441 			goto release;
2442 	}
2443 
2444 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2445 					   data);
2446 release:
2447 	hw->phy.ops.release(hw);
2448 	return ret_val;
2449 }
2450 
2451 /**
2452  *  e1000e_read_phy_reg_bm2 - Read BM PHY register
2453  *  @hw: pointer to the HW structure
2454  *  @offset: register offset to be read
2455  *  @data: pointer to the read data
2456  *
2457  *  Acquires semaphore, if necessary, then reads the PHY register at offset
2458  *  and storing the retrieved information in data.  Release any acquired
2459  *  semaphores before exiting.
2460  **/
e1000e_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)2461 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2462 {
2463 	s32 ret_val;
2464 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2465 
2466 	ret_val = hw->phy.ops.acquire(hw);
2467 	if (ret_val)
2468 		return ret_val;
2469 
2470 	/* Page 800 works differently than the rest so it has its own func */
2471 	if (page == BM_WUC_PAGE) {
2472 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2473 							 true, false);
2474 		goto release;
2475 	}
2476 
2477 	hw->phy.addr = 1;
2478 
2479 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
2480 		/* Page is shifted left, PHY expects (page x 32) */
2481 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2482 						    page);
2483 
2484 		if (ret_val)
2485 			goto release;
2486 	}
2487 
2488 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2489 					   data);
2490 release:
2491 	hw->phy.ops.release(hw);
2492 	return ret_val;
2493 }
2494 
2495 /**
2496  *  e1000e_write_phy_reg_bm2 - Write BM PHY register
2497  *  @hw: pointer to the HW structure
2498  *  @offset: register offset to write to
2499  *  @data: data to write at register offset
2500  *
2501  *  Acquires semaphore, if necessary, then writes the data to PHY register
2502  *  at the offset.  Release any acquired semaphores before exiting.
2503  **/
e1000e_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)2504 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2505 {
2506 	s32 ret_val;
2507 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2508 
2509 	ret_val = hw->phy.ops.acquire(hw);
2510 	if (ret_val)
2511 		return ret_val;
2512 
2513 	/* Page 800 works differently than the rest so it has its own func */
2514 	if (page == BM_WUC_PAGE) {
2515 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2516 							 false, false);
2517 		goto release;
2518 	}
2519 
2520 	hw->phy.addr = 1;
2521 
2522 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
2523 		/* Page is shifted left, PHY expects (page x 32) */
2524 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2525 						    page);
2526 
2527 		if (ret_val)
2528 			goto release;
2529 	}
2530 
2531 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2532 					    data);
2533 
2534 release:
2535 	hw->phy.ops.release(hw);
2536 	return ret_val;
2537 }
2538 
2539 /**
2540  *  e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2541  *  @hw: pointer to the HW structure
2542  *  @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2543  *
2544  *  Assumes semaphore already acquired and phy_reg points to a valid memory
2545  *  address to store contents of the BM_WUC_ENABLE_REG register.
2546  **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2547 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2548 {
2549 	s32 ret_val;
2550 	u16 temp;
2551 
2552 	/* All page select, port ctrl and wakeup registers use phy address 1 */
2553 	hw->phy.addr = 1;
2554 
2555 	/* Select Port Control Registers page */
2556 	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2557 	if (ret_val) {
2558 		e_dbg("Could not set Port Control page\n");
2559 		return ret_val;
2560 	}
2561 
2562 	ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2563 	if (ret_val) {
2564 		e_dbg("Could not read PHY register %d.%d\n",
2565 		      BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2566 		return ret_val;
2567 	}
2568 
2569 	/* Enable both PHY wakeup mode and Wakeup register page writes.
2570 	 * Prevent a power state change by disabling ME and Host PHY wakeup.
2571 	 */
2572 	temp = *phy_reg;
2573 	temp |= BM_WUC_ENABLE_BIT;
2574 	temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2575 
2576 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2577 	if (ret_val) {
2578 		e_dbg("Could not write PHY register %d.%d\n",
2579 		      BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2580 		return ret_val;
2581 	}
2582 
2583 	/* Select Host Wakeup Registers page - caller now able to write
2584 	 * registers on the Wakeup registers page
2585 	 */
2586 	return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2587 }
2588 
2589 /**
2590  *  e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2591  *  @hw: pointer to the HW structure
2592  *  @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2593  *
2594  *  Restore BM_WUC_ENABLE_REG to its original value.
2595  *
2596  *  Assumes semaphore already acquired and *phy_reg is the contents of the
2597  *  BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2598  *  caller.
2599  **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2600 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2601 {
2602 	s32 ret_val;
2603 
2604 	/* Select Port Control Registers page */
2605 	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2606 	if (ret_val) {
2607 		e_dbg("Could not set Port Control page\n");
2608 		return ret_val;
2609 	}
2610 
2611 	/* Restore 769.17 to its original value */
2612 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2613 	if (ret_val)
2614 		e_dbg("Could not restore PHY register %d.%d\n",
2615 		      BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2616 
2617 	return ret_val;
2618 }
2619 
2620 /**
2621  *  e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2622  *  @hw: pointer to the HW structure
2623  *  @offset: register offset to be read or written
2624  *  @data: pointer to the data to read or write
2625  *  @read: determines if operation is read or write
2626  *  @page_set: BM_WUC_PAGE already set and access enabled
2627  *
2628  *  Read the PHY register at offset and store the retrieved information in
2629  *  data, or write data to PHY register at offset.  Note the procedure to
2630  *  access the PHY wakeup registers is different than reading the other PHY
2631  *  registers. It works as such:
2632  *  1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2633  *  2) Set page to 800 for host (801 if we were manageability)
2634  *  3) Write the address using the address opcode (0x11)
2635  *  4) Read or write the data using the data opcode (0x12)
2636  *  5) Restore 769.17.2 to its original value
2637  *
2638  *  Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2639  *  step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2640  *
2641  *  Assumes semaphore is already acquired.  When page_set==true, assumes
2642  *  the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2643  *  is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2644  **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)2645 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2646 					  u16 *data, bool read, bool page_set)
2647 {
2648 	s32 ret_val;
2649 	u16 reg = BM_PHY_REG_NUM(offset);
2650 	u16 page = BM_PHY_REG_PAGE(offset);
2651 	u16 phy_reg = 0;
2652 
2653 	/* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2654 	if ((hw->mac.type == e1000_pchlan) &&
2655 	    (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2656 		e_dbg("Attempting to access page %d while gig enabled.\n",
2657 		      page);
2658 
2659 	if (!page_set) {
2660 		/* Enable access to PHY wakeup registers */
2661 		ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2662 		if (ret_val) {
2663 			e_dbg("Could not enable PHY wakeup reg access\n");
2664 			return ret_val;
2665 		}
2666 	}
2667 
2668 	e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2669 
2670 	/* Write the Wakeup register page offset value using opcode 0x11 */
2671 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2672 	if (ret_val) {
2673 		e_dbg("Could not write address opcode to page %d\n", page);
2674 		return ret_val;
2675 	}
2676 
2677 	if (read) {
2678 		/* Read the Wakeup register page value using opcode 0x12 */
2679 		ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2680 						   data);
2681 	} else {
2682 		/* Write the Wakeup register page value using opcode 0x12 */
2683 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2684 						    *data);
2685 	}
2686 
2687 	if (ret_val) {
2688 		e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2689 		return ret_val;
2690 	}
2691 
2692 	if (!page_set)
2693 		ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2694 
2695 	return ret_val;
2696 }
2697 
2698 /**
2699  * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2700  * @hw: pointer to the HW structure
2701  *
2702  * In the case of a PHY power down to save power, or to turn off link during a
2703  * driver unload, or wake on lan is not enabled, restore the link to previous
2704  * settings.
2705  **/
e1000_power_up_phy_copper(struct e1000_hw * hw)2706 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2707 {
2708 	u16 mii_reg = 0;
2709 	int ret;
2710 
2711 	/* The PHY will retain its settings across a power down/up cycle */
2712 	ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2713 	if (ret) {
2714 		e_dbg("Error reading PHY register\n");
2715 		return;
2716 	}
2717 	mii_reg &= ~BMCR_PDOWN;
2718 	e1e_wphy(hw, MII_BMCR, mii_reg);
2719 }
2720 
2721 /**
2722  * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2723  * @hw: pointer to the HW structure
2724  *
2725  * In the case of a PHY power down to save power, or to turn off link during a
2726  * driver unload, or wake on lan is not enabled, restore the link to previous
2727  * settings.
2728  **/
e1000_power_down_phy_copper(struct e1000_hw * hw)2729 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2730 {
2731 	u16 mii_reg = 0;
2732 	int ret;
2733 
2734 	/* The PHY will retain its settings across a power down/up cycle */
2735 	ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2736 	if (ret) {
2737 		e_dbg("Error reading PHY register\n");
2738 		return;
2739 	}
2740 	mii_reg |= BMCR_PDOWN;
2741 	e1e_wphy(hw, MII_BMCR, mii_reg);
2742 	usleep_range(1000, 2000);
2743 }
2744 
2745 /**
2746  *  __e1000_read_phy_reg_hv -  Read HV PHY register
2747  *  @hw: pointer to the HW structure
2748  *  @offset: register offset to be read
2749  *  @data: pointer to the read data
2750  *  @locked: semaphore has already been acquired or not
2751  *  @page_set: BM_WUC_PAGE already set and access enabled
2752  *
2753  *  Acquires semaphore, if necessary, then reads the PHY register at offset
2754  *  and stores the retrieved information in data.  Release any acquired
2755  *  semaphore before exiting.
2756  **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)2757 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2758 				   bool locked, bool page_set)
2759 {
2760 	s32 ret_val;
2761 	u16 page = BM_PHY_REG_PAGE(offset);
2762 	u16 reg = BM_PHY_REG_NUM(offset);
2763 	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2764 
2765 	if (!locked) {
2766 		ret_val = hw->phy.ops.acquire(hw);
2767 		if (ret_val)
2768 			return ret_val;
2769 	}
2770 
2771 	/* Page 800 works differently than the rest so it has its own func */
2772 	if (page == BM_WUC_PAGE) {
2773 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2774 							 true, page_set);
2775 		goto out;
2776 	}
2777 
2778 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2779 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2780 							 data, true);
2781 		goto out;
2782 	}
2783 
2784 	if (!page_set) {
2785 		if (page == HV_INTC_FC_PAGE_START)
2786 			page = 0;
2787 
2788 		if (reg > MAX_PHY_MULTI_PAGE_REG) {
2789 			/* Page is shifted left, PHY expects (page x 32) */
2790 			ret_val = e1000_set_page_igp(hw,
2791 						     (page << IGP_PAGE_SHIFT));
2792 
2793 			hw->phy.addr = phy_addr;
2794 
2795 			if (ret_val)
2796 				goto out;
2797 		}
2798 	}
2799 
2800 	e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2801 	      page << IGP_PAGE_SHIFT, reg);
2802 
2803 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2804 out:
2805 	if (!locked)
2806 		hw->phy.ops.release(hw);
2807 
2808 	return ret_val;
2809 }
2810 
2811 /**
2812  *  e1000_read_phy_reg_hv -  Read HV PHY register
2813  *  @hw: pointer to the HW structure
2814  *  @offset: register offset to be read
2815  *  @data: pointer to the read data
2816  *
2817  *  Acquires semaphore then reads the PHY register at offset and stores
2818  *  the retrieved information in data.  Release the acquired semaphore
2819  *  before exiting.
2820  **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)2821 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2822 {
2823 	return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2824 }
2825 
2826 /**
2827  *  e1000_read_phy_reg_hv_locked -  Read HV PHY register
2828  *  @hw: pointer to the HW structure
2829  *  @offset: register offset to be read
2830  *  @data: pointer to the read data
2831  *
2832  *  Reads the PHY register at offset and stores the retrieved information
2833  *  in data.  Assumes semaphore already acquired.
2834  **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)2835 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2836 {
2837 	return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2838 }
2839 
2840 /**
2841  *  e1000_read_phy_reg_page_hv - Read HV PHY register
2842  *  @hw: pointer to the HW structure
2843  *  @offset: register offset to write to
2844  *  @data: data to write at register offset
2845  *
2846  *  Reads the PHY register at offset and stores the retrieved information
2847  *  in data.  Assumes semaphore already acquired and page already set.
2848  **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)2849 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2850 {
2851 	return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2852 }
2853 
2854 /**
2855  *  __e1000_write_phy_reg_hv - Write HV PHY register
2856  *  @hw: pointer to the HW structure
2857  *  @offset: register offset to write to
2858  *  @data: data to write at register offset
2859  *  @locked: semaphore has already been acquired or not
2860  *  @page_set: BM_WUC_PAGE already set and access enabled
2861  *
2862  *  Acquires semaphore, if necessary, then writes the data to PHY register
2863  *  at the offset.  Release any acquired semaphores before exiting.
2864  **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)2865 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2866 				    bool locked, bool page_set)
2867 {
2868 	s32 ret_val;
2869 	u16 page = BM_PHY_REG_PAGE(offset);
2870 	u16 reg = BM_PHY_REG_NUM(offset);
2871 	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2872 
2873 	if (!locked) {
2874 		ret_val = hw->phy.ops.acquire(hw);
2875 		if (ret_val)
2876 			return ret_val;
2877 	}
2878 
2879 	/* Page 800 works differently than the rest so it has its own func */
2880 	if (page == BM_WUC_PAGE) {
2881 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2882 							 false, page_set);
2883 		goto out;
2884 	}
2885 
2886 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2887 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2888 							 &data, false);
2889 		goto out;
2890 	}
2891 
2892 	if (!page_set) {
2893 		if (page == HV_INTC_FC_PAGE_START)
2894 			page = 0;
2895 
2896 		/* Workaround MDIO accesses being disabled after entering IEEE
2897 		 * Power Down (when bit 11 of the PHY Control register is set)
2898 		 */
2899 		if ((hw->phy.type == e1000_phy_82578) &&
2900 		    (hw->phy.revision >= 1) &&
2901 		    (hw->phy.addr == 2) &&
2902 		    !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2903 			u16 data2 = 0x7EFF;
2904 
2905 			ret_val = e1000_access_phy_debug_regs_hv(hw,
2906 								 BIT(6) | 0x3,
2907 								 &data2, false);
2908 			if (ret_val)
2909 				goto out;
2910 		}
2911 
2912 		if (reg > MAX_PHY_MULTI_PAGE_REG) {
2913 			/* Page is shifted left, PHY expects (page x 32) */
2914 			ret_val = e1000_set_page_igp(hw,
2915 						     (page << IGP_PAGE_SHIFT));
2916 
2917 			hw->phy.addr = phy_addr;
2918 
2919 			if (ret_val)
2920 				goto out;
2921 		}
2922 	}
2923 
2924 	e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2925 	      page << IGP_PAGE_SHIFT, reg);
2926 
2927 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2928 					    data);
2929 
2930 out:
2931 	if (!locked)
2932 		hw->phy.ops.release(hw);
2933 
2934 	return ret_val;
2935 }
2936 
2937 /**
2938  *  e1000_write_phy_reg_hv - Write HV PHY register
2939  *  @hw: pointer to the HW structure
2940  *  @offset: register offset to write to
2941  *  @data: data to write at register offset
2942  *
2943  *  Acquires semaphore then writes the data to PHY register at the offset.
2944  *  Release the acquired semaphores before exiting.
2945  **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)2946 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2947 {
2948 	return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2949 }
2950 
2951 /**
2952  *  e1000_write_phy_reg_hv_locked - Write HV PHY register
2953  *  @hw: pointer to the HW structure
2954  *  @offset: register offset to write to
2955  *  @data: data to write at register offset
2956  *
2957  *  Writes the data to PHY register at the offset.  Assumes semaphore
2958  *  already acquired.
2959  **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)2960 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2961 {
2962 	return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2963 }
2964 
2965 /**
2966  *  e1000_write_phy_reg_page_hv - Write HV PHY register
2967  *  @hw: pointer to the HW structure
2968  *  @offset: register offset to write to
2969  *  @data: data to write at register offset
2970  *
2971  *  Writes the data to PHY register at the offset.  Assumes semaphore
2972  *  already acquired and page already set.
2973  **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)2974 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2975 {
2976 	return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2977 }
2978 
2979 /**
2980  *  e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2981  *  @page: page to be accessed
2982  **/
e1000_get_phy_addr_for_hv_page(u32 page)2983 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2984 {
2985 	u32 phy_addr = 2;
2986 
2987 	if (page >= HV_INTC_FC_PAGE_START)
2988 		phy_addr = 1;
2989 
2990 	return phy_addr;
2991 }
2992 
2993 /**
2994  *  e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2995  *  @hw: pointer to the HW structure
2996  *  @offset: register offset to be read or written
2997  *  @data: pointer to the data to be read or written
2998  *  @read: determines if operation is read or write
2999  *
3000  *  Reads the PHY register at offset and stores the retrieved information
3001  *  in data.  Assumes semaphore already acquired.  Note that the procedure
3002  *  to access these regs uses the address port and data port to read/write.
3003  *  These accesses done with PHY address 2 and without using pages.
3004  **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3005 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3006 					  u16 *data, bool read)
3007 {
3008 	s32 ret_val;
3009 	u32 addr_reg;
3010 	u32 data_reg;
3011 
3012 	/* This takes care of the difference with desktop vs mobile phy */
3013 	addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3014 		    I82578_ADDR_REG : I82577_ADDR_REG);
3015 	data_reg = addr_reg + 1;
3016 
3017 	/* All operations in this function are phy address 2 */
3018 	hw->phy.addr = 2;
3019 
3020 	/* masking with 0x3F to remove the page from offset */
3021 	ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3022 	if (ret_val) {
3023 		e_dbg("Could not write the Address Offset port register\n");
3024 		return ret_val;
3025 	}
3026 
3027 	/* Read or write the data value next */
3028 	if (read)
3029 		ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3030 	else
3031 		ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3032 
3033 	if (ret_val)
3034 		e_dbg("Could not access the Data port register\n");
3035 
3036 	return ret_val;
3037 }
3038 
3039 /**
3040  *  e1000_link_stall_workaround_hv - Si workaround
3041  *  @hw: pointer to the HW structure
3042  *
3043  *  This function works around a Si bug where the link partner can get
3044  *  a link up indication before the PHY does.  If small packets are sent
3045  *  by the link partner they can be placed in the packet buffer without
3046  *  being properly accounted for by the PHY and will stall preventing
3047  *  further packets from being received.  The workaround is to clear the
3048  *  packet buffer after the PHY detects link up.
3049  **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3050 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3051 {
3052 	s32 ret_val = 0;
3053 	u16 data;
3054 
3055 	if (hw->phy.type != e1000_phy_82578)
3056 		return 0;
3057 
3058 	/* Do not apply workaround if in PHY loopback bit 14 set */
3059 	ret_val = e1e_rphy(hw, MII_BMCR, &data);
3060 	if (ret_val) {
3061 		e_dbg("Error reading PHY register\n");
3062 		return ret_val;
3063 	}
3064 	if (data & BMCR_LOOPBACK)
3065 		return 0;
3066 
3067 	/* check if link is up and at 1Gbps */
3068 	ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3069 	if (ret_val)
3070 		return ret_val;
3071 
3072 	data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3073 		 BM_CS_STATUS_SPEED_MASK);
3074 
3075 	if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3076 		     BM_CS_STATUS_SPEED_1000))
3077 		return 0;
3078 
3079 	msleep(200);
3080 
3081 	/* flush the packets in the fifo buffer */
3082 	ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3083 			   (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3084 			    HV_MUX_DATA_CTRL_FORCE_SPEED));
3085 	if (ret_val)
3086 		return ret_val;
3087 
3088 	return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3089 }
3090 
3091 /**
3092  *  e1000_check_polarity_82577 - Checks the polarity.
3093  *  @hw: pointer to the HW structure
3094  *
3095  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3096  *
3097  *  Polarity is determined based on the PHY specific status register.
3098  **/
e1000_check_polarity_82577(struct e1000_hw * hw)3099 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3100 {
3101 	struct e1000_phy_info *phy = &hw->phy;
3102 	s32 ret_val;
3103 	u16 data;
3104 
3105 	ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3106 
3107 	if (!ret_val)
3108 		phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3109 				       ? e1000_rev_polarity_reversed
3110 				       : e1000_rev_polarity_normal);
3111 
3112 	return ret_val;
3113 }
3114 
3115 /**
3116  *  e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3117  *  @hw: pointer to the HW structure
3118  *
3119  *  Calls the PHY setup function to force speed and duplex.
3120  **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3121 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3122 {
3123 	struct e1000_phy_info *phy = &hw->phy;
3124 	s32 ret_val;
3125 	u16 phy_data;
3126 	bool link;
3127 
3128 	ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3129 	if (ret_val)
3130 		return ret_val;
3131 
3132 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3133 
3134 	ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3135 	if (ret_val)
3136 		return ret_val;
3137 
3138 	udelay(1);
3139 
3140 	if (phy->autoneg_wait_to_complete) {
3141 		e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3142 
3143 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3144 						      100000, &link);
3145 		if (ret_val)
3146 			return ret_val;
3147 
3148 		if (!link)
3149 			e_dbg("Link taking longer than expected.\n");
3150 
3151 		/* Try once more */
3152 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3153 						      100000, &link);
3154 	}
3155 
3156 	return ret_val;
3157 }
3158 
3159 /**
3160  *  e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3161  *  @hw: pointer to the HW structure
3162  *
3163  *  Read PHY status to determine if link is up.  If link is up, then
3164  *  set/determine 10base-T extended distance and polarity correction.  Read
3165  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
3166  *  determine on the cable length, local and remote receiver.
3167  **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3168 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3169 {
3170 	struct e1000_phy_info *phy = &hw->phy;
3171 	s32 ret_val;
3172 	u16 data;
3173 	bool link;
3174 
3175 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3176 	if (ret_val)
3177 		return ret_val;
3178 
3179 	if (!link) {
3180 		e_dbg("Phy info is only valid if link is up\n");
3181 		return -E1000_ERR_CONFIG;
3182 	}
3183 
3184 	phy->polarity_correction = true;
3185 
3186 	ret_val = e1000_check_polarity_82577(hw);
3187 	if (ret_val)
3188 		return ret_val;
3189 
3190 	ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3191 	if (ret_val)
3192 		return ret_val;
3193 
3194 	phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3195 
3196 	if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3197 	    I82577_PHY_STATUS2_SPEED_1000MBPS) {
3198 		ret_val = hw->phy.ops.get_cable_length(hw);
3199 		if (ret_val)
3200 			return ret_val;
3201 
3202 		ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3203 		if (ret_val)
3204 			return ret_val;
3205 
3206 		phy->local_rx = (data & LPA_1000LOCALRXOK)
3207 		    ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3208 
3209 		phy->remote_rx = (data & LPA_1000REMRXOK)
3210 		    ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3211 	} else {
3212 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3213 		phy->local_rx = e1000_1000t_rx_status_undefined;
3214 		phy->remote_rx = e1000_1000t_rx_status_undefined;
3215 	}
3216 
3217 	return 0;
3218 }
3219 
3220 /**
3221  *  e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3222  *  @hw: pointer to the HW structure
3223  *
3224  * Reads the diagnostic status register and verifies result is valid before
3225  * placing it in the phy_cable_length field.
3226  **/
e1000_get_cable_length_82577(struct e1000_hw * hw)3227 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3228 {
3229 	struct e1000_phy_info *phy = &hw->phy;
3230 	s32 ret_val;
3231 	u16 phy_data, length;
3232 
3233 	ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3234 	if (ret_val)
3235 		return ret_val;
3236 
3237 	length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3238 		  I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3239 
3240 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
3241 		return -E1000_ERR_PHY;
3242 
3243 	phy->cable_length = length;
3244 
3245 	return 0;
3246 }
3247