1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33
34
35 #include "e1000_hw.h"
36
37 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
38 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
39 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
40 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
41 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
42 static void e1000_release_software_semaphore(struct e1000_hw *hw);
43
44 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
45 static int32_t e1000_check_downshift(struct e1000_hw *hw);
46 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60 static int32_t e1000_id_led_init(struct e1000_hw *hw);
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63 static void e1000_init_rx_addrs(struct e1000_hw *hw);
64 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86 static void e1000_release_software_flag(struct e1000_hw *hw);
87 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
93 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94 static void e1000_phy_init_script(struct e1000_hw *hw);
95 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 uint16_t count);
104 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
110 uint16_t *data);
111 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 uint16_t count);
116 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t phy_data);
118 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 uint16_t *phy_data);
120 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122 static void e1000_release_eeprom(struct e1000_hw *hw);
123 static void e1000_standby_eeprom(struct e1000_hw *hw);
124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
127 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
129 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 uint16_t duplex);
131 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
132 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
133
134 /* IGP cable length table */
135 static const
136 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
137 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
138 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
139 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
140 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
141 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
142 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
143 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
145
146 static const
147 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
148 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
149 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
150 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
151 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
152 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
153 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
154 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
155 104, 109, 114, 118, 121, 124};
156
157 /******************************************************************************
158 * Set the phy type member in the hw struct.
159 *
160 * hw - Struct containing variables accessed by shared code
161 *****************************************************************************/
162 static int32_t
e1000_set_phy_type(struct e1000_hw * hw)163 e1000_set_phy_type(struct e1000_hw *hw)
164 {
165 DEBUGFUNC("e1000_set_phy_type");
166
167 if (hw->mac_type == e1000_undefined)
168 return -E1000_ERR_PHY_TYPE;
169
170 switch (hw->phy_id) {
171 case M88E1000_E_PHY_ID:
172 case M88E1000_I_PHY_ID:
173 case M88E1011_I_PHY_ID:
174 case M88E1111_I_PHY_ID:
175 hw->phy_type = e1000_phy_m88;
176 break;
177 case IGP01E1000_I_PHY_ID:
178 if (hw->mac_type == e1000_82541 ||
179 hw->mac_type == e1000_82541_rev_2 ||
180 hw->mac_type == e1000_82547 ||
181 hw->mac_type == e1000_82547_rev_2) {
182 hw->phy_type = e1000_phy_igp;
183 break;
184 }
185 case IGP03E1000_E_PHY_ID:
186 hw->phy_type = e1000_phy_igp_3;
187 break;
188 case IFE_E_PHY_ID:
189 case IFE_PLUS_E_PHY_ID:
190 case IFE_C_E_PHY_ID:
191 hw->phy_type = e1000_phy_ife;
192 break;
193 case GG82563_E_PHY_ID:
194 if (hw->mac_type == e1000_80003es2lan) {
195 hw->phy_type = e1000_phy_gg82563;
196 break;
197 }
198 /* Fall Through */
199 default:
200 /* Should never have loaded on this device */
201 hw->phy_type = e1000_phy_undefined;
202 return -E1000_ERR_PHY_TYPE;
203 }
204
205 return E1000_SUCCESS;
206 }
207
208 /******************************************************************************
209 * IGP phy init script - initializes the GbE PHY
210 *
211 * hw - Struct containing variables accessed by shared code
212 *****************************************************************************/
213 static void
e1000_phy_init_script(struct e1000_hw * hw)214 e1000_phy_init_script(struct e1000_hw *hw)
215 {
216 uint32_t ret_val;
217 uint16_t phy_saved_data;
218
219 DEBUGFUNC("e1000_phy_init_script");
220
221 if (hw->phy_init_script) {
222 msec_delay(20);
223
224 /* Save off the current value of register 0x2F5B to be restored at
225 * the end of this routine. */
226 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
227
228 /* Disabled the PHY transmitter */
229 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
230
231 msec_delay(20);
232
233 e1000_write_phy_reg(hw,0x0000,0x0140);
234
235 msec_delay(5);
236
237 switch (hw->mac_type) {
238 case e1000_82541:
239 case e1000_82547:
240 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
241
242 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
243
244 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
245
246 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
247
248 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
249
250 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
251
252 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
253
254 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
255
256 e1000_write_phy_reg(hw, 0x2010, 0x0008);
257 break;
258
259 case e1000_82541_rev_2:
260 case e1000_82547_rev_2:
261 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
262 break;
263 default:
264 break;
265 }
266
267 e1000_write_phy_reg(hw, 0x0000, 0x3300);
268
269 msec_delay(20);
270
271 /* Now enable the transmitter */
272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
273
274 if (hw->mac_type == e1000_82547) {
275 uint16_t fused, fine, coarse;
276
277 /* Move to analog registers page */
278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
279
280 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
281 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
282
283 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
284 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
285
286 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
287 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
288 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
289 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
290 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
291
292 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
293 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
294 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
295
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
297 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
298 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
299 }
300 }
301 }
302 }
303
304 /******************************************************************************
305 * Set the mac type member in the hw struct.
306 *
307 * hw - Struct containing variables accessed by shared code
308 *****************************************************************************/
309 int32_t
e1000_set_mac_type(struct e1000_hw * hw)310 e1000_set_mac_type(struct e1000_hw *hw)
311 {
312 DEBUGFUNC("e1000_set_mac_type");
313
314 switch (hw->device_id) {
315 case E1000_DEV_ID_82542:
316 switch (hw->revision_id) {
317 case E1000_82542_2_0_REV_ID:
318 hw->mac_type = e1000_82542_rev2_0;
319 break;
320 case E1000_82542_2_1_REV_ID:
321 hw->mac_type = e1000_82542_rev2_1;
322 break;
323 default:
324 /* Invalid 82542 revision ID */
325 return -E1000_ERR_MAC_TYPE;
326 }
327 break;
328 case E1000_DEV_ID_82543GC_FIBER:
329 case E1000_DEV_ID_82543GC_COPPER:
330 hw->mac_type = e1000_82543;
331 break;
332 case E1000_DEV_ID_82544EI_COPPER:
333 case E1000_DEV_ID_82544EI_FIBER:
334 case E1000_DEV_ID_82544GC_COPPER:
335 case E1000_DEV_ID_82544GC_LOM:
336 hw->mac_type = e1000_82544;
337 break;
338 case E1000_DEV_ID_82540EM:
339 case E1000_DEV_ID_82540EM_LOM:
340 case E1000_DEV_ID_82540EP:
341 case E1000_DEV_ID_82540EP_LOM:
342 case E1000_DEV_ID_82540EP_LP:
343 hw->mac_type = e1000_82540;
344 break;
345 case E1000_DEV_ID_82545EM_COPPER:
346 case E1000_DEV_ID_82545EM_FIBER:
347 hw->mac_type = e1000_82545;
348 break;
349 case E1000_DEV_ID_82545GM_COPPER:
350 case E1000_DEV_ID_82545GM_FIBER:
351 case E1000_DEV_ID_82545GM_SERDES:
352 hw->mac_type = e1000_82545_rev_3;
353 break;
354 case E1000_DEV_ID_82546EB_COPPER:
355 case E1000_DEV_ID_82546EB_FIBER:
356 case E1000_DEV_ID_82546EB_QUAD_COPPER:
357 hw->mac_type = e1000_82546;
358 break;
359 case E1000_DEV_ID_82546GB_COPPER:
360 case E1000_DEV_ID_82546GB_FIBER:
361 case E1000_DEV_ID_82546GB_SERDES:
362 case E1000_DEV_ID_82546GB_PCIE:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER:
364 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
365 hw->mac_type = e1000_82546_rev_3;
366 break;
367 case E1000_DEV_ID_82541EI:
368 case E1000_DEV_ID_82541EI_MOBILE:
369 case E1000_DEV_ID_82541ER_LOM:
370 hw->mac_type = e1000_82541;
371 break;
372 case E1000_DEV_ID_82541ER:
373 case E1000_DEV_ID_82541GI:
374 case E1000_DEV_ID_82541GI_LF:
375 case E1000_DEV_ID_82541GI_MOBILE:
376 hw->mac_type = e1000_82541_rev_2;
377 break;
378 case E1000_DEV_ID_82547EI:
379 case E1000_DEV_ID_82547EI_MOBILE:
380 hw->mac_type = e1000_82547;
381 break;
382 case E1000_DEV_ID_82547GI:
383 hw->mac_type = e1000_82547_rev_2;
384 break;
385 case E1000_DEV_ID_82571EB_COPPER:
386 case E1000_DEV_ID_82571EB_FIBER:
387 case E1000_DEV_ID_82571EB_SERDES:
388 case E1000_DEV_ID_82571EB_QUAD_COPPER:
389 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
390 hw->mac_type = e1000_82571;
391 break;
392 case E1000_DEV_ID_82572EI_COPPER:
393 case E1000_DEV_ID_82572EI_FIBER:
394 case E1000_DEV_ID_82572EI_SERDES:
395 case E1000_DEV_ID_82572EI:
396 hw->mac_type = e1000_82572;
397 break;
398 case E1000_DEV_ID_82573E:
399 case E1000_DEV_ID_82573E_IAMT:
400 case E1000_DEV_ID_82573L:
401 hw->mac_type = e1000_82573;
402 break;
403 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
404 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
405 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
406 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
407 hw->mac_type = e1000_80003es2lan;
408 break;
409 case E1000_DEV_ID_ICH8_IGP_M_AMT:
410 case E1000_DEV_ID_ICH8_IGP_AMT:
411 case E1000_DEV_ID_ICH8_IGP_C:
412 case E1000_DEV_ID_ICH8_IFE:
413 case E1000_DEV_ID_ICH8_IFE_GT:
414 case E1000_DEV_ID_ICH8_IFE_G:
415 case E1000_DEV_ID_ICH8_IGP_M:
416 hw->mac_type = e1000_ich8lan;
417 hw->is_ich = TRUE;
418 break;
419
420
421 default:
422 /* Should never have loaded on this device */
423 return -E1000_ERR_MAC_TYPE;
424 }
425
426 switch (hw->mac_type) {
427 case e1000_ich8lan:
428 hw->swfwhw_semaphore_present = TRUE;
429 hw->asf_firmware_present = TRUE;
430 break;
431 case e1000_80003es2lan:
432 hw->swfw_sync_present = TRUE;
433 /* fall through */
434 case e1000_82571:
435 case e1000_82572:
436 case e1000_82573:
437 hw->eeprom_semaphore_present = TRUE;
438 /* fall through */
439 case e1000_82541:
440 case e1000_82547:
441 case e1000_82541_rev_2:
442 case e1000_82547_rev_2:
443 hw->asf_firmware_present = TRUE;
444 break;
445 default:
446 break;
447 }
448
449 return E1000_SUCCESS;
450 }
451
452 /*****************************************************************************
453 * Set media type and TBI compatibility.
454 *
455 * hw - Struct containing variables accessed by shared code
456 * **************************************************************************/
457 void
e1000_set_media_type(struct e1000_hw * hw)458 e1000_set_media_type(struct e1000_hw *hw)
459 {
460 uint32_t status;
461
462 DEBUGFUNC("e1000_set_media_type");
463
464 if (hw->mac_type != e1000_82543) {
465 /* tbi_compatibility is only valid on 82543 */
466 hw->tbi_compatibility_en = FALSE;
467 }
468
469 switch (hw->device_id) {
470 case E1000_DEV_ID_82545GM_SERDES:
471 case E1000_DEV_ID_82546GB_SERDES:
472 case E1000_DEV_ID_82571EB_SERDES:
473 case E1000_DEV_ID_82572EI_SERDES:
474 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
475 hw->media_type = e1000_media_type_internal_serdes;
476 break;
477 default:
478 switch (hw->mac_type) {
479 case e1000_82542_rev2_0:
480 case e1000_82542_rev2_1:
481 hw->media_type = e1000_media_type_fiber;
482 break;
483 case e1000_ich8lan:
484 case e1000_82573:
485 /* The STATUS_TBIMODE bit is reserved or reused for the this
486 * device.
487 */
488 hw->media_type = e1000_media_type_copper;
489 break;
490 default:
491 status = E1000_READ_REG(hw, STATUS);
492 if (status & E1000_STATUS_TBIMODE) {
493 hw->media_type = e1000_media_type_fiber;
494 /* tbi_compatibility not valid on fiber */
495 hw->tbi_compatibility_en = FALSE;
496 } else {
497 hw->media_type = e1000_media_type_copper;
498 }
499 break;
500 }
501 }
502 }
503
504 /******************************************************************************
505 * Reset the transmit and receive units; mask and clear all interrupts.
506 *
507 * hw - Struct containing variables accessed by shared code
508 *****************************************************************************/
509 int32_t
e1000_reset_hw(struct e1000_hw * hw)510 e1000_reset_hw(struct e1000_hw *hw)
511 {
512 uint32_t ctrl;
513 uint32_t ctrl_ext;
514 uint32_t icr;
515 uint32_t manc;
516 uint32_t led_ctrl;
517 uint32_t timeout;
518 uint32_t extcnf_ctrl;
519 int32_t ret_val;
520
521 DEBUGFUNC("e1000_reset_hw");
522
523 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
524 if (hw->mac_type == e1000_82542_rev2_0) {
525 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
526 e1000_pci_clear_mwi(hw);
527 }
528
529 if (hw->bus_type == e1000_bus_type_pci_express) {
530 /* Prevent the PCI-E bus from sticking if there is no TLP connection
531 * on the last TLP read/write transaction when MAC is reset.
532 */
533 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
534 DEBUGOUT("PCI-E Master disable polling has failed.\n");
535 }
536 }
537
538 /* Clear interrupt mask to stop board from generating interrupts */
539 DEBUGOUT("Masking off all interrupts\n");
540 E1000_WRITE_REG(hw, IMC, 0xffffffff);
541
542 /* Disable the Transmit and Receive units. Then delay to allow
543 * any pending transactions to complete before we hit the MAC with
544 * the global reset.
545 */
546 E1000_WRITE_REG(hw, RCTL, 0);
547 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
548 E1000_WRITE_FLUSH(hw);
549
550 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
551 hw->tbi_compatibility_on = FALSE;
552
553 /* Delay to allow any outstanding PCI transactions to complete before
554 * resetting the device
555 */
556 msec_delay(10);
557
558 ctrl = E1000_READ_REG(hw, CTRL);
559
560 /* Must reset the PHY before resetting the MAC */
561 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
562 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
563 msec_delay(5);
564 }
565
566 /* Must acquire the MDIO ownership before MAC reset.
567 * Ownership defaults to firmware after a reset. */
568 if (hw->mac_type == e1000_82573) {
569 timeout = 10;
570
571 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
572 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
573
574 do {
575 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
576 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
577
578 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
579 break;
580 else
581 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
582
583 msec_delay(2);
584 timeout--;
585 } while (timeout);
586 }
587
588 /* Workaround for ICH8 bit corruption issue in FIFO memory */
589 if (hw->mac_type == e1000_ich8lan)
590 {
591 /* Set Tx and Rx buffer allocation to 8k apiece. */
592 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
593 /* Set Packet Buffer Size to 16k. */
594 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
595 }
596
597 /* Issue a global reset to the MAC. This will reset the chip's
598 * transmit, receive, DMA, and link units. It will not effect
599 * the current PCI configuration. The global reset bit is self-
600 * clearing, and should clear within a microsecond.
601 */
602 DEBUGOUT("Issuing a global reset to MAC\n");
603
604 switch (hw->mac_type) {
605 case e1000_82544:
606 case e1000_82540:
607 case e1000_82545:
608 case e1000_82546:
609 case e1000_82541:
610 case e1000_82541_rev_2:
611 /* These controllers can't ack the 64-bit write when issuing the
612 * reset, so use IO-mapping as a workaround to issue the reset */
613 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
614 break;
615 case e1000_82545_rev_3:
616 case e1000_82546_rev_3:
617 /* Reset is performed on a shadow of the control register */
618 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
619 break;
620 case e1000_ich8lan:
621 if (!hw->phy_reset_disable &&
622 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
623 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
624 * at the same time to make sure the interface between
625 * MAC and the external PHY is reset.
626 */
627 ctrl |= E1000_CTRL_PHY_RST;
628 }
629
630 e1000_get_software_flag(hw);
631 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
632 msec_delay(5);
633 break;
634 default:
635 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
636 break;
637 }
638
639 /* After MAC reset, force reload of EEPROM to restore power-on settings to
640 * device. Later controllers reload the EEPROM automatically, so just wait
641 * for reload to complete.
642 */
643 switch (hw->mac_type) {
644 case e1000_82542_rev2_0:
645 case e1000_82542_rev2_1:
646 case e1000_82543:
647 case e1000_82544:
648 /* Wait for reset to complete */
649 usec_delay(10);
650 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
651 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
652 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
653 E1000_WRITE_FLUSH(hw);
654 /* Wait for EEPROM reload */
655 msec_delay(2);
656 break;
657 case e1000_82541:
658 case e1000_82541_rev_2:
659 case e1000_82547:
660 case e1000_82547_rev_2:
661 /* Wait for EEPROM reload */
662 msec_delay(20);
663 break;
664 case e1000_82573:
665 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
666 usec_delay(10);
667 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
668 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
669 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
670 E1000_WRITE_FLUSH(hw);
671 }
672 /* fall through */
673 default:
674 /* Auto read done will delay 5ms or poll based on mac type */
675 ret_val = e1000_get_auto_rd_done(hw);
676 if (ret_val)
677 return ret_val;
678 break;
679 }
680
681 /* Disable HW ARPs on ASF enabled adapters */
682 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
683 manc = E1000_READ_REG(hw, MANC);
684 manc &= ~(E1000_MANC_ARP_EN);
685 E1000_WRITE_REG(hw, MANC, manc);
686 }
687
688 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
689 e1000_phy_init_script(hw);
690
691 /* Configure activity LED after PHY reset */
692 led_ctrl = E1000_READ_REG(hw, LEDCTL);
693 led_ctrl &= IGP_ACTIVITY_LED_MASK;
694 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
695 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
696 }
697
698 /* Clear interrupt mask to stop board from generating interrupts */
699 DEBUGOUT("Masking off all interrupts\n");
700 E1000_WRITE_REG(hw, IMC, 0xffffffff);
701
702 /* Clear any pending interrupt events. */
703 icr = E1000_READ_REG(hw, ICR);
704
705 /* If MWI was previously enabled, reenable it. */
706 if (hw->mac_type == e1000_82542_rev2_0) {
707 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
708 e1000_pci_set_mwi(hw);
709 }
710
711 if (hw->is_ich) {
712 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
713 kab |= E1000_KABGTXD_BGSQLBIAS;
714 E1000_WRITE_REG(hw, KABGTXD, kab);
715 }
716
717 return E1000_SUCCESS;
718 }
719
720 /******************************************************************************
721 *
722 * Initialize a number of hardware-dependent bits
723 *
724 * hw: Struct containing variables accessed by shared code
725 *
726 *****************************************************************************/
727 static void
e1000_initialize_hardware_bits(struct e1000_hw * hw)728 e1000_initialize_hardware_bits(struct e1000_hw *hw)
729 {
730 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
731 /* Settings common to all PCI-express silicon */
732 uint32_t reg_ctrl, reg_ctrl_ext;
733 uint32_t reg_tarc0, reg_tarc1;
734 uint32_t reg_tctl;
735 uint32_t reg_txdctl, reg_txdctl1;
736
737 reg_tarc0 = E1000_READ_REG(hw, TARC0);
738 /* link autonegotiation/sync workarounds */
739 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
740
741 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
742 /* Enable not-done TX descriptor counting */
743 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
744 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
745
746 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
747 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
748 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
749
750 switch (hw->mac_type) {
751 case e1000_82571:
752 case e1000_82572:
753 reg_tarc1 = E1000_READ_REG(hw, TARC1);
754 reg_tctl = E1000_READ_REG(hw, TCTL);
755
756 /* Clear PHY TX compatible mode bits */
757 reg_tarc1 &= ~((1 << 30)|(1 << 29));
758
759 /* link autonegotiation/sync workarounds */
760 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
761 /* TX ring control fixes */
762 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
763
764 /* Multiple read bit is reversed polarity */
765 if (reg_tctl & E1000_TCTL_MULR)
766 reg_tarc1 &= ~(1 << 28);
767 else
768 reg_tarc1 |= (1 << 28);
769
770 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
771 break;
772 case e1000_82573:
773 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
774 reg_ctrl = E1000_READ_REG(hw, CTRL);
775
776 reg_ctrl_ext &= ~(1 << 23);
777 reg_ctrl_ext |= (1 << 22);
778 /* TX byte count fix */
779 reg_ctrl &= ~(1 << 29);
780
781 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
782 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
783 break;
784 case e1000_80003es2lan:
785 /* improve small packet performance for fiber/serdes */
786 if ((hw->media_type == e1000_media_type_fiber) ||
787 (hw->media_type == e1000_media_type_internal_serdes)) {
788 reg_tarc0 &= ~(1 << 20);
789 }
790
791 /* Multiple read bit is reversed polarity */
792 reg_tctl = E1000_READ_REG(hw, TCTL);
793 reg_tarc1 = E1000_READ_REG(hw, TARC1);
794 if (reg_tctl & E1000_TCTL_MULR)
795 reg_tarc1 &= ~(1 << 28);
796 else
797 reg_tarc1 |= (1 << 28);
798
799 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
800 break;
801 case e1000_ich8lan:
802 /* Reduce concurrent DMA requests to 3 from 4 */
803 if ((hw->revision_id < 3) ||
804 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
805 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
806 reg_tarc0 |= ((1 << 29)|(1 << 28));
807 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
808 reg_ctrl_ext |= (1 << 22);
809 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
810
811 /* workaround TX hang with TSO=on */
812 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
813
814 reg_tarc1 = E1000_READ_REG(hw, TARC1);
815 reg_tctl = E1000_READ_REG(hw, TCTL);
816
817 /* Multiple read bit is reversed polarity */
818 if (reg_tctl & E1000_TCTL_MULR)
819 reg_tarc1 &= ~(1 << 28);
820 else
821 reg_tarc1 |= (1 << 28);
822
823 /* workaround TX hang and TSO=on */
824 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
825
826 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
827 break;
828 default:
829 break;
830 }
831
832 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
833 }
834 }
835
836 /******************************************************************************
837 * Performs basic configuration of the adapter.
838 *
839 * hw - Struct containing variables accessed by shared code
840 *
841 * Assumes that the controller has previously been reset and is in a
842 * post-reset uninitialized state. Initializes the receive address registers,
843 * multicast table, and VLAN filter table. Calls routines to setup link
844 * configuration and flow control settings. Clears all on-chip counters. Leaves
845 * the transmit and receive units disabled and uninitialized.
846 *****************************************************************************/
847 int32_t
e1000_init_hw(struct e1000_hw * hw)848 e1000_init_hw(struct e1000_hw *hw)
849 {
850 uint32_t ctrl;
851 uint32_t i;
852 int32_t ret_val;
853 uint16_t pcix_cmd_word;
854 uint16_t pcix_stat_hi_word;
855 uint16_t cmd_mmrbc;
856 uint16_t stat_mmrbc;
857 uint32_t mta_size;
858 uint32_t reg_data;
859 uint32_t ctrl_ext;
860
861 DEBUGFUNC("e1000_init_hw");
862
863 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
864 if ((hw->mac_type == e1000_ich8lan) &&
865 ((hw->revision_id < 3) ||
866 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
867 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
868 reg_data = E1000_READ_REG(hw, STATUS);
869 reg_data &= ~0x80000000;
870 E1000_WRITE_REG(hw, STATUS, reg_data);
871 }
872
873 /* Initialize Identification LED */
874 ret_val = e1000_id_led_init(hw);
875 if (ret_val) {
876 DEBUGOUT("Error Initializing Identification LED\n");
877 return ret_val;
878 }
879
880 /* Set the media type and TBI compatibility */
881 e1000_set_media_type(hw);
882
883 /* Must be called after e1000_set_media_type because media_type is used */
884 e1000_initialize_hardware_bits(hw);
885 /* Disabling VLAN filtering. */
886 DEBUGOUT("Initializing the IEEE VLAN\n");
887 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
888 if (hw->is_ich == FALSE) {
889 if (hw->mac_type < e1000_82545_rev_3)
890 E1000_WRITE_REG(hw, VET, 0);
891 e1000_clear_vfta(hw);
892 }
893
894 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
895 if (hw->mac_type == e1000_82542_rev2_0) {
896 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
897 e1000_pci_clear_mwi(hw);
898 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
899 E1000_WRITE_FLUSH(hw);
900 msec_delay(5);
901 }
902
903 /* Setup the receive address. This involves initializing all of the Receive
904 * Address Registers (RARs 0 - 15).
905 */
906 e1000_init_rx_addrs(hw);
907
908 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
909 if (hw->mac_type == e1000_82542_rev2_0) {
910 E1000_WRITE_REG(hw, RCTL, 0);
911 E1000_WRITE_FLUSH(hw);
912 msec_delay(1);
913 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
914 e1000_pci_set_mwi(hw);
915 }
916
917 /* Zero out the Multicast HASH table */
918 DEBUGOUT("Zeroing the MTA\n");
919 mta_size = E1000_MC_TBL_SIZE;
920 if (hw->is_ich == TRUE)
921 mta_size = E1000_MC_TBL_SIZE_ICHXLAN;
922 for (i = 0; i < mta_size; i++) {
923 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
924 /* use write flush to prevent Memory Write Block (MWB) from
925 * occuring when accessing our register space */
926 E1000_WRITE_FLUSH(hw);
927 }
928
929 /* Set the PCI priority bit correctly in the CTRL register. This
930 * determines if the adapter gives priority to receives, or if it
931 * gives equal priority to transmits and receives. Valid only on
932 * 82542 and 82543 silicon.
933 */
934 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
935 ctrl = E1000_READ_REG(hw, CTRL);
936 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
937 }
938
939 switch (hw->mac_type) {
940 case e1000_82545_rev_3:
941 case e1000_82546_rev_3:
942 break;
943 default:
944 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
945 if (hw->bus_type == e1000_bus_type_pcix) {
946 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
947 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
948 &pcix_stat_hi_word);
949 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
950 PCIX_COMMAND_MMRBC_SHIFT;
951 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
952 PCIX_STATUS_HI_MMRBC_SHIFT;
953 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
954 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
955 if (cmd_mmrbc > stat_mmrbc) {
956 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
957 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
958 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
959 &pcix_cmd_word);
960 }
961 }
962 break;
963 }
964
965 /* More time needed for PHY to initialize */
966 if (hw->is_ich == TRUE)
967 msec_delay(15);
968
969 /* Call a subroutine to configure the link and setup flow control. */
970 ret_val = e1000_setup_link(hw);
971
972 /* Set the transmit descriptor write-back policy */
973 if (hw->mac_type > e1000_82544) {
974 ctrl = E1000_READ_REG(hw, TXDCTL);
975 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
976 E1000_WRITE_REG(hw, TXDCTL, ctrl);
977 }
978
979 if (hw->mac_type == e1000_82573) {
980 e1000_enable_tx_pkt_filtering(hw);
981 }
982
983 switch (hw->mac_type) {
984 default:
985 break;
986 case e1000_80003es2lan:
987 /* Enable retransmit on late collisions */
988 reg_data = E1000_READ_REG(hw, TCTL);
989 reg_data |= E1000_TCTL_RTLC;
990 E1000_WRITE_REG(hw, TCTL, reg_data);
991
992 /* Configure Gigabit Carry Extend Padding */
993 reg_data = E1000_READ_REG(hw, TCTL_EXT);
994 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
995 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
996 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
997
998 /* Configure Transmit Inter-Packet Gap */
999 reg_data = E1000_READ_REG(hw, TIPG);
1000 reg_data &= ~E1000_TIPG_IPGT_MASK;
1001 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1002 E1000_WRITE_REG(hw, TIPG, reg_data);
1003
1004 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1005 reg_data &= ~0x00100000;
1006 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1007 /* Fall through */
1008 case e1000_82571:
1009 case e1000_82572:
1010 case e1000_ich8lan:
1011 ctrl = E1000_READ_REG(hw, TXDCTL1);
1012 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1013 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1014 break;
1015 }
1016
1017
1018 if (hw->mac_type == e1000_82573) {
1019 uint32_t gcr = E1000_READ_REG(hw, GCR);
1020 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1021 E1000_WRITE_REG(hw, GCR, gcr);
1022 }
1023
1024 /* Clear all of the statistics registers (clear on read). It is
1025 * important that we do this after we have tried to establish link
1026 * because the symbol error count will increment wildly if there
1027 * is no link.
1028 */
1029 e1000_clear_hw_cntrs(hw);
1030
1031 /* ICH8 No-snoop bits are opposite polarity.
1032 * Set to snoop by default after reset. */
1033 if (hw->mac_type == e1000_ich8lan)
1034 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1035
1036 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1037 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1038 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1039 /* Relaxed ordering must be disabled to avoid a parity
1040 * error crash in a PCI slot. */
1041 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1042 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1043 }
1044
1045 return ret_val;
1046 }
1047
1048 /******************************************************************************
1049 * Adjust SERDES output amplitude based on EEPROM setting.
1050 *
1051 * hw - Struct containing variables accessed by shared code.
1052 *****************************************************************************/
1053 static int32_t
e1000_adjust_serdes_amplitude(struct e1000_hw * hw)1054 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1055 {
1056 uint16_t eeprom_data;
1057 int32_t ret_val;
1058
1059 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1060
1061 if (hw->media_type != e1000_media_type_internal_serdes)
1062 return E1000_SUCCESS;
1063
1064 switch (hw->mac_type) {
1065 case e1000_82545_rev_3:
1066 case e1000_82546_rev_3:
1067 break;
1068 default:
1069 return E1000_SUCCESS;
1070 }
1071
1072 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1073 if (ret_val) {
1074 return ret_val;
1075 }
1076
1077 if (eeprom_data != EEPROM_RESERVED_WORD) {
1078 /* Adjust SERDES output amplitude only. */
1079 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1080 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1081 if (ret_val)
1082 return ret_val;
1083 }
1084
1085 return E1000_SUCCESS;
1086 }
1087
1088 /******************************************************************************
1089 * Configures flow control and link settings.
1090 *
1091 * hw - Struct containing variables accessed by shared code
1092 *
1093 * Determines which flow control settings to use. Calls the apropriate media-
1094 * specific link configuration function. Configures the flow control settings.
1095 * Assuming the adapter has a valid link partner, a valid link should be
1096 * established. Assumes the hardware has previously been reset and the
1097 * transmitter and receiver are not enabled.
1098 *****************************************************************************/
1099 int32_t
e1000_setup_link(struct e1000_hw * hw)1100 e1000_setup_link(struct e1000_hw *hw)
1101 {
1102 uint32_t ctrl_ext;
1103 int32_t ret_val;
1104 uint16_t eeprom_data;
1105
1106 DEBUGFUNC("e1000_setup_link");
1107
1108 /* In the case of the phy reset being blocked, we already have a link.
1109 * We do not have to set it up again. */
1110 if (e1000_check_phy_reset_block(hw))
1111 return E1000_SUCCESS;
1112
1113 /* Read and store word 0x0F of the EEPROM. This word contains bits
1114 * that determine the hardware's default PAUSE (flow control) mode,
1115 * a bit that determines whether the HW defaults to enabling or
1116 * disabling auto-negotiation, and the direction of the
1117 * SW defined pins. If there is no SW over-ride of the flow
1118 * control setting, then the variable hw->fc will
1119 * be initialized based on a value in the EEPROM.
1120 */
1121 if (hw->fc == E1000_FC_DEFAULT) {
1122 switch (hw->mac_type) {
1123 case e1000_ich8lan:
1124 case e1000_82573:
1125 hw->fc = E1000_FC_FULL;
1126 break;
1127 default:
1128 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1129 1, &eeprom_data);
1130 if (ret_val) {
1131 DEBUGOUT("EEPROM Read Error\n");
1132 return -E1000_ERR_EEPROM;
1133 }
1134 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1135 hw->fc = E1000_FC_NONE;
1136 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1137 EEPROM_WORD0F_ASM_DIR)
1138 hw->fc = E1000_FC_TX_PAUSE;
1139 else
1140 hw->fc = E1000_FC_FULL;
1141 break;
1142 }
1143 }
1144
1145 /* We want to save off the original Flow Control configuration just
1146 * in case we get disconnected and then reconnected into a different
1147 * hub or switch with different Flow Control capabilities.
1148 */
1149 if (hw->mac_type == e1000_82542_rev2_0)
1150 hw->fc &= (~E1000_FC_TX_PAUSE);
1151
1152 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1153 hw->fc &= (~E1000_FC_RX_PAUSE);
1154
1155 hw->original_fc = hw->fc;
1156
1157 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1158
1159 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1160 * polarity value for the SW controlled pins, and setup the
1161 * Extended Device Control reg with that info.
1162 * This is needed because one of the SW controlled pins is used for
1163 * signal detection. So this should be done before e1000_setup_pcs_link()
1164 * or e1000_phy_setup() is called.
1165 */
1166 if (hw->mac_type == e1000_82543) {
1167 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1168 1, &eeprom_data);
1169 if (ret_val) {
1170 DEBUGOUT("EEPROM Read Error\n");
1171 return -E1000_ERR_EEPROM;
1172 }
1173 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1174 SWDPIO__EXT_SHIFT);
1175 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1176 }
1177
1178 /* Call the necessary subroutine to configure the link. */
1179 ret_val = (hw->media_type == e1000_media_type_copper) ?
1180 e1000_setup_copper_link(hw) :
1181 e1000_setup_fiber_serdes_link(hw);
1182
1183 /* Initialize the flow control address, type, and PAUSE timer
1184 * registers to their default values. This is done even if flow
1185 * control is disabled, because it does not hurt anything to
1186 * initialize these registers.
1187 */
1188 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1189
1190 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1191 if (hw->is_ich == FALSE) {
1192 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1193 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1194 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1195 }
1196
1197 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1198
1199 /* Set the flow control receive threshold registers. Normally,
1200 * these registers will be set to a default threshold that may be
1201 * adjusted later by the driver's runtime code. However, if the
1202 * ability to transmit pause frames in not enabled, then these
1203 * registers will be set to 0.
1204 */
1205 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1206 E1000_WRITE_REG(hw, FCRTL, 0);
1207 E1000_WRITE_REG(hw, FCRTH, 0);
1208 } else {
1209 /* We need to set up the Receive Threshold high and low water marks
1210 * as well as (optionally) enabling the transmission of XON frames.
1211 */
1212 if (hw->fc_send_xon) {
1213 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1214 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1215 } else {
1216 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1217 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1218 }
1219 }
1220 return ret_val;
1221 }
1222
1223 /******************************************************************************
1224 * Sets up link for a fiber based or serdes based adapter
1225 *
1226 * hw - Struct containing variables accessed by shared code
1227 *
1228 * Manipulates Physical Coding Sublayer functions in order to configure
1229 * link. Assumes the hardware has been previously reset and the transmitter
1230 * and receiver are not enabled.
1231 *****************************************************************************/
1232 static int32_t
e1000_setup_fiber_serdes_link(struct e1000_hw * hw)1233 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1234 {
1235 uint32_t ctrl;
1236 uint32_t status;
1237 uint32_t txcw = 0;
1238 uint32_t i;
1239 uint32_t signal = 0;
1240 int32_t ret_val;
1241
1242 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1243
1244 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1245 * until explicitly turned off or a power cycle is performed. A read to
1246 * the register does not indicate its status. Therefore, we ensure
1247 * loopback mode is disabled during initialization.
1248 */
1249 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1250 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1251
1252 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1253 * set when the optics detect a signal. On older adapters, it will be
1254 * cleared when there is a signal. This applies to fiber media only.
1255 * If we're on serdes media, adjust the output amplitude to value
1256 * set in the EEPROM.
1257 */
1258 ctrl = E1000_READ_REG(hw, CTRL);
1259 if (hw->media_type == e1000_media_type_fiber)
1260 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1261
1262 ret_val = e1000_adjust_serdes_amplitude(hw);
1263 if (ret_val)
1264 return ret_val;
1265
1266 /* Take the link out of reset */
1267 ctrl &= ~(E1000_CTRL_LRST);
1268
1269 /* Adjust VCO speed to improve BER performance */
1270 ret_val = e1000_set_vco_speed(hw);
1271 if (ret_val)
1272 return ret_val;
1273
1274 e1000_config_collision_dist(hw);
1275
1276 /* Check for a software override of the flow control settings, and setup
1277 * the device accordingly. If auto-negotiation is enabled, then software
1278 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1279 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1280 * auto-negotiation is disabled, then software will have to manually
1281 * configure the two flow control enable bits in the CTRL register.
1282 *
1283 * The possible values of the "fc" parameter are:
1284 * 0: Flow control is completely disabled
1285 * 1: Rx flow control is enabled (we can receive pause frames, but
1286 * not send pause frames).
1287 * 2: Tx flow control is enabled (we can send pause frames but we do
1288 * not support receiving pause frames).
1289 * 3: Both Rx and TX flow control (symmetric) are enabled.
1290 */
1291 switch (hw->fc) {
1292 case E1000_FC_NONE:
1293 /* Flow control is completely disabled by a software over-ride. */
1294 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1295 break;
1296 case E1000_FC_RX_PAUSE:
1297 /* RX Flow control is enabled and TX Flow control is disabled by a
1298 * software over-ride. Since there really isn't a way to advertise
1299 * that we are capable of RX Pause ONLY, we will advertise that we
1300 * support both symmetric and asymmetric RX PAUSE. Later, we will
1301 * disable the adapter's ability to send PAUSE frames.
1302 */
1303 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1304 break;
1305 case E1000_FC_TX_PAUSE:
1306 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1307 * software over-ride.
1308 */
1309 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1310 break;
1311 case E1000_FC_FULL:
1312 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1313 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1314 break;
1315 default:
1316 DEBUGOUT("Flow control param set incorrectly\n");
1317 return -E1000_ERR_CONFIG;
1318 break;
1319 }
1320
1321 /* Since auto-negotiation is enabled, take the link out of reset (the link
1322 * will be in reset, because we previously reset the chip). This will
1323 * restart auto-negotiation. If auto-neogtiation is successful then the
1324 * link-up status bit will be set and the flow control enable bits (RFCE
1325 * and TFCE) will be set according to their negotiated value.
1326 */
1327 DEBUGOUT("Auto-negotiation enabled\n");
1328
1329 E1000_WRITE_REG(hw, TXCW, txcw);
1330 E1000_WRITE_REG(hw, CTRL, ctrl);
1331 E1000_WRITE_FLUSH(hw);
1332
1333 hw->txcw = txcw;
1334 msec_delay(1);
1335
1336 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1337 * indication in the Device Status Register. Time-out if a link isn't
1338 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1339 * less than 500 milliseconds even if the other end is doing it in SW).
1340 * For internal serdes, we just assume a signal is present, then poll.
1341 */
1342 if (hw->media_type == e1000_media_type_internal_serdes ||
1343 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1344 DEBUGOUT("Looking for Link\n");
1345 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1346 msec_delay(10);
1347 status = E1000_READ_REG(hw, STATUS);
1348 if (status & E1000_STATUS_LU) break;
1349 }
1350 if (i == (LINK_UP_TIMEOUT / 10)) {
1351 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1352 hw->autoneg_failed = 1;
1353 /* AutoNeg failed to achieve a link, so we'll call
1354 * e1000_check_for_link. This routine will force the link up if
1355 * we detect a signal. This will allow us to communicate with
1356 * non-autonegotiating link partners.
1357 */
1358 ret_val = e1000_check_for_link(hw);
1359 if (ret_val) {
1360 DEBUGOUT("Error while checking for link\n");
1361 return ret_val;
1362 }
1363 hw->autoneg_failed = 0;
1364 } else {
1365 hw->autoneg_failed = 0;
1366 DEBUGOUT("Valid Link Found\n");
1367 }
1368 } else {
1369 DEBUGOUT("No Signal Detected\n");
1370 }
1371 return E1000_SUCCESS;
1372 }
1373
1374 /******************************************************************************
1375 * Make sure we have a valid PHY and change PHY mode before link setup.
1376 *
1377 * hw - Struct containing variables accessed by shared code
1378 ******************************************************************************/
1379 static int32_t
e1000_copper_link_preconfig(struct e1000_hw * hw)1380 e1000_copper_link_preconfig(struct e1000_hw *hw)
1381 {
1382 uint32_t ctrl;
1383 int32_t ret_val;
1384 uint16_t phy_data;
1385
1386 DEBUGFUNC("e1000_copper_link_preconfig");
1387
1388 ctrl = E1000_READ_REG(hw, CTRL);
1389 /* With 82543, we need to force speed and duplex on the MAC equal to what
1390 * the PHY speed and duplex configuration is. In addition, we need to
1391 * perform a hardware reset on the PHY to take it out of reset.
1392 */
1393 if (hw->mac_type > e1000_82543) {
1394 ctrl |= E1000_CTRL_SLU;
1395 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1396 E1000_WRITE_REG(hw, CTRL, ctrl);
1397 } else {
1398 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1399 E1000_WRITE_REG(hw, CTRL, ctrl);
1400 ret_val = e1000_phy_hw_reset(hw);
1401 if (ret_val)
1402 return ret_val;
1403 }
1404
1405 /* Make sure we have a valid PHY */
1406 ret_val = e1000_detect_gig_phy(hw);
1407 if (ret_val) {
1408 DEBUGOUT("Error, did not detect valid phy.\n");
1409 return ret_val;
1410 }
1411 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1412
1413 /* Set PHY to class A mode (if necessary) */
1414 ret_val = e1000_set_phy_mode(hw);
1415 if (ret_val)
1416 return ret_val;
1417
1418 if ((hw->mac_type == e1000_82545_rev_3) ||
1419 (hw->mac_type == e1000_82546_rev_3)) {
1420 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1421 phy_data |= 0x00000008;
1422 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1423 }
1424
1425 if (hw->mac_type <= e1000_82543 ||
1426 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1427 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1428 hw->phy_reset_disable = FALSE;
1429
1430 return E1000_SUCCESS;
1431 }
1432
1433
1434 /********************************************************************
1435 * Copper link setup for e1000_phy_igp series.
1436 *
1437 * hw - Struct containing variables accessed by shared code
1438 *********************************************************************/
1439 static int32_t
e1000_copper_link_igp_setup(struct e1000_hw * hw)1440 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1441 {
1442 uint32_t led_ctrl;
1443 int32_t ret_val;
1444 uint16_t phy_data;
1445
1446 DEBUGFUNC("e1000_copper_link_igp_setup");
1447
1448 if (hw->phy_reset_disable)
1449 return E1000_SUCCESS;
1450
1451 ret_val = e1000_phy_reset(hw);
1452 if (ret_val) {
1453 DEBUGOUT("Error Resetting the PHY\n");
1454 return ret_val;
1455 }
1456
1457 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1458 msec_delay(15);
1459 if (hw->is_ich == FALSE) {
1460 /* Configure activity LED after PHY reset */
1461 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1462 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1463 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1464 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1465 }
1466
1467 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1468 if (hw->phy_type == e1000_phy_igp) {
1469 /* disable lplu d3 during driver init */
1470 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1471 if (ret_val) {
1472 DEBUGOUT("Error Disabling LPLU D3\n");
1473 return ret_val;
1474 }
1475 }
1476
1477 /* disable lplu d0 during driver init */
1478 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1479 if (ret_val) {
1480 DEBUGOUT("Error Disabling LPLU D0\n");
1481 return ret_val;
1482 }
1483 /* Configure mdi-mdix settings */
1484 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1485 if (ret_val)
1486 return ret_val;
1487
1488 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1489 hw->dsp_config_state = e1000_dsp_config_disabled;
1490 /* Force MDI for earlier revs of the IGP PHY */
1491 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1492 hw->mdix = 1;
1493
1494 } else {
1495 hw->dsp_config_state = e1000_dsp_config_enabled;
1496 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1497
1498 switch (hw->mdix) {
1499 case 1:
1500 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1501 break;
1502 case 2:
1503 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1504 break;
1505 case 0:
1506 default:
1507 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1508 break;
1509 }
1510 }
1511 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1512 if (ret_val)
1513 return ret_val;
1514
1515 /* set auto-master slave resolution settings */
1516 if (hw->autoneg) {
1517 e1000_ms_type phy_ms_setting = hw->master_slave;
1518
1519 if (hw->ffe_config_state == e1000_ffe_config_active)
1520 hw->ffe_config_state = e1000_ffe_config_enabled;
1521
1522 if (hw->dsp_config_state == e1000_dsp_config_activated)
1523 hw->dsp_config_state = e1000_dsp_config_enabled;
1524
1525 /* when autonegotiation advertisment is only 1000Mbps then we
1526 * should disable SmartSpeed and enable Auto MasterSlave
1527 * resolution as hardware default. */
1528 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1529 /* Disable SmartSpeed */
1530 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1531 &phy_data);
1532 if (ret_val)
1533 return ret_val;
1534 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1535 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1536 phy_data);
1537 if (ret_val)
1538 return ret_val;
1539 /* Set auto Master/Slave resolution process */
1540 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1541 if (ret_val)
1542 return ret_val;
1543 phy_data &= ~CR_1000T_MS_ENABLE;
1544 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1545 if (ret_val)
1546 return ret_val;
1547 }
1548
1549 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1550 if (ret_val)
1551 return ret_val;
1552
1553 /* load defaults for future use */
1554 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1555 ((phy_data & CR_1000T_MS_VALUE) ?
1556 e1000_ms_force_master :
1557 e1000_ms_force_slave) :
1558 e1000_ms_auto;
1559
1560 switch (phy_ms_setting) {
1561 case e1000_ms_force_master:
1562 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1563 break;
1564 case e1000_ms_force_slave:
1565 phy_data |= CR_1000T_MS_ENABLE;
1566 phy_data &= ~(CR_1000T_MS_VALUE);
1567 break;
1568 case e1000_ms_auto:
1569 phy_data &= ~CR_1000T_MS_ENABLE;
1570 default:
1571 break;
1572 }
1573 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1574 if (ret_val)
1575 return ret_val;
1576 }
1577
1578 return E1000_SUCCESS;
1579 }
1580
1581 /********************************************************************
1582 * Copper link setup for e1000_phy_gg82563 series.
1583 *
1584 * hw - Struct containing variables accessed by shared code
1585 *********************************************************************/
1586 static int32_t
e1000_copper_link_ggp_setup(struct e1000_hw * hw)1587 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1588 {
1589 int32_t ret_val;
1590 uint16_t phy_data;
1591 uint32_t reg_data;
1592
1593 DEBUGFUNC("e1000_copper_link_ggp_setup");
1594
1595 if (!hw->phy_reset_disable) {
1596
1597 /* Enable CRS on TX for half-duplex operation. */
1598 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1599 &phy_data);
1600 if (ret_val)
1601 return ret_val;
1602
1603 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1604 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1605 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1606
1607 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1608 phy_data);
1609 if (ret_val)
1610 return ret_val;
1611
1612 /* Options:
1613 * MDI/MDI-X = 0 (default)
1614 * 0 - Auto for all speeds
1615 * 1 - MDI mode
1616 * 2 - MDI-X mode
1617 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1618 */
1619 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1620 if (ret_val)
1621 return ret_val;
1622
1623 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1624
1625 switch (hw->mdix) {
1626 case 1:
1627 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1628 break;
1629 case 2:
1630 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1631 break;
1632 case 0:
1633 default:
1634 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1635 break;
1636 }
1637
1638 /* Options:
1639 * disable_polarity_correction = 0 (default)
1640 * Automatic Correction for Reversed Cable Polarity
1641 * 0 - Disabled
1642 * 1 - Enabled
1643 */
1644 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1645 if (hw->disable_polarity_correction == 1)
1646 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1647 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1648
1649 if (ret_val)
1650 return ret_val;
1651
1652 /* SW Reset the PHY so all changes take effect */
1653 ret_val = e1000_phy_reset(hw);
1654 if (ret_val) {
1655 DEBUGOUT("Error Resetting the PHY\n");
1656 return ret_val;
1657 }
1658 } /* phy_reset_disable */
1659
1660 if (hw->mac_type == e1000_80003es2lan) {
1661 /* Bypass RX and TX FIFO's */
1662 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1663 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1664 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1665 if (ret_val)
1666 return ret_val;
1667
1668 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1669 if (ret_val)
1670 return ret_val;
1671
1672 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1673 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1674
1675 if (ret_val)
1676 return ret_val;
1677
1678 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1679 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1680 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1681
1682 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1683 &phy_data);
1684 if (ret_val)
1685 return ret_val;
1686
1687 /* Do not init these registers when the HW is in IAMT mode, since the
1688 * firmware will have already initialized them. We only initialize
1689 * them if the HW is not in IAMT mode.
1690 */
1691 if (e1000_check_mng_mode(hw) == FALSE) {
1692 /* Enable Electrical Idle on the PHY */
1693 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1694 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1695 phy_data);
1696 if (ret_val)
1697 return ret_val;
1698
1699 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1700 &phy_data);
1701 if (ret_val)
1702 return ret_val;
1703
1704 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1705 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1706 phy_data);
1707
1708 if (ret_val)
1709 return ret_val;
1710 }
1711
1712 /* Workaround: Disable padding in Kumeran interface in the MAC
1713 * and in the PHY to avoid CRC errors.
1714 */
1715 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1716 &phy_data);
1717 if (ret_val)
1718 return ret_val;
1719 phy_data |= GG82563_ICR_DIS_PADDING;
1720 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1721 phy_data);
1722 if (ret_val)
1723 return ret_val;
1724 }
1725
1726 return E1000_SUCCESS;
1727 }
1728
1729 /********************************************************************
1730 * Copper link setup for e1000_phy_m88 series.
1731 *
1732 * hw - Struct containing variables accessed by shared code
1733 *********************************************************************/
1734 static int32_t
e1000_copper_link_mgp_setup(struct e1000_hw * hw)1735 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1736 {
1737 int32_t ret_val;
1738 uint16_t phy_data;
1739
1740 DEBUGFUNC("e1000_copper_link_mgp_setup");
1741
1742 if (hw->phy_reset_disable)
1743 return E1000_SUCCESS;
1744
1745 /* Enable CRS on TX. This must be set for half-duplex operation. */
1746 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1747 if (ret_val)
1748 return ret_val;
1749
1750 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1751
1752 /* Options:
1753 * MDI/MDI-X = 0 (default)
1754 * 0 - Auto for all speeds
1755 * 1 - MDI mode
1756 * 2 - MDI-X mode
1757 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1758 */
1759 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1760
1761 switch (hw->mdix) {
1762 case 1:
1763 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1764 break;
1765 case 2:
1766 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1767 break;
1768 case 3:
1769 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1770 break;
1771 case 0:
1772 default:
1773 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1774 break;
1775 }
1776
1777 /* Options:
1778 * disable_polarity_correction = 0 (default)
1779 * Automatic Correction for Reversed Cable Polarity
1780 * 0 - Disabled
1781 * 1 - Enabled
1782 */
1783 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1784 if (hw->disable_polarity_correction == 1)
1785 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1786 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1787 if (ret_val)
1788 return ret_val;
1789
1790 if (hw->phy_revision < M88E1011_I_REV_4) {
1791 /* Force TX_CLK in the Extended PHY Specific Control Register
1792 * to 25MHz clock.
1793 */
1794 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1795 if (ret_val)
1796 return ret_val;
1797
1798 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1799
1800 if ((hw->phy_revision == E1000_REVISION_2) &&
1801 (hw->phy_id == M88E1111_I_PHY_ID)) {
1802 /* Vidalia Phy, set the downshift counter to 5x */
1803 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1804 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1805 ret_val = e1000_write_phy_reg(hw,
1806 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1807 if (ret_val)
1808 return ret_val;
1809 } else {
1810 /* Configure Master and Slave downshift values */
1811 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1812 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1813 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1814 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1815 ret_val = e1000_write_phy_reg(hw,
1816 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1817 if (ret_val)
1818 return ret_val;
1819 }
1820 }
1821
1822 /* SW Reset the PHY so all changes take effect */
1823 ret_val = e1000_phy_reset(hw);
1824 if (ret_val) {
1825 DEBUGOUT("Error Resetting the PHY\n");
1826 return ret_val;
1827 }
1828
1829 return E1000_SUCCESS;
1830 }
1831
1832 /********************************************************************
1833 * Setup auto-negotiation and flow control advertisements,
1834 * and then perform auto-negotiation.
1835 *
1836 * hw - Struct containing variables accessed by shared code
1837 *********************************************************************/
1838 static int32_t
e1000_copper_link_autoneg(struct e1000_hw * hw)1839 e1000_copper_link_autoneg(struct e1000_hw *hw)
1840 {
1841 int32_t ret_val;
1842 uint16_t phy_data;
1843
1844 DEBUGFUNC("e1000_copper_link_autoneg");
1845
1846 /* Perform some bounds checking on the hw->autoneg_advertised
1847 * parameter. If this variable is zero, then set it to the default.
1848 */
1849 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1850
1851 /* If autoneg_advertised is zero, we assume it was not defaulted
1852 * by the calling code so we set to advertise full capability.
1853 */
1854 if (hw->autoneg_advertised == 0)
1855 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1856
1857 /* IFE phy only supports 10/100 */
1858 if (hw->phy_type == e1000_phy_ife)
1859 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1860
1861 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1862 ret_val = e1000_phy_setup_autoneg(hw);
1863 if (ret_val) {
1864 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1865 return ret_val;
1866 }
1867 DEBUGOUT("Restarting Auto-Neg\n");
1868
1869 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1870 * the Auto Neg Restart bit in the PHY control register.
1871 */
1872 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1873 if (ret_val)
1874 return ret_val;
1875
1876 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1877 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1878 if (ret_val)
1879 return ret_val;
1880
1881 /* Does the user want to wait for Auto-Neg to complete here, or
1882 * check at a later time (for example, callback routine).
1883 */
1884 if (hw->wait_autoneg_complete) {
1885 ret_val = e1000_wait_autoneg(hw);
1886 if (ret_val) {
1887 DEBUGOUT("Error while waiting for autoneg to complete\n");
1888 return ret_val;
1889 }
1890 }
1891
1892 hw->get_link_status = TRUE;
1893
1894 return E1000_SUCCESS;
1895 }
1896
1897 /******************************************************************************
1898 * Config the MAC and the PHY after link is up.
1899 * 1) Set up the MAC to the current PHY speed/duplex
1900 * if we are on 82543. If we
1901 * are on newer silicon, we only need to configure
1902 * collision distance in the Transmit Control Register.
1903 * 2) Set up flow control on the MAC to that established with
1904 * the link partner.
1905 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1906 *
1907 * hw - Struct containing variables accessed by shared code
1908 ******************************************************************************/
1909 static int32_t
e1000_copper_link_postconfig(struct e1000_hw * hw)1910 e1000_copper_link_postconfig(struct e1000_hw *hw)
1911 {
1912 int32_t ret_val;
1913 DEBUGFUNC("e1000_copper_link_postconfig");
1914
1915 if (hw->mac_type >= e1000_82544) {
1916 e1000_config_collision_dist(hw);
1917 } else {
1918 ret_val = e1000_config_mac_to_phy(hw);
1919 if (ret_val) {
1920 DEBUGOUT("Error configuring MAC to PHY settings\n");
1921 return ret_val;
1922 }
1923 }
1924 ret_val = e1000_config_fc_after_link_up(hw);
1925 if (ret_val) {
1926 DEBUGOUT("Error Configuring Flow Control\n");
1927 return ret_val;
1928 }
1929
1930 /* Config DSP to improve Giga link quality */
1931 if (hw->phy_type == e1000_phy_igp) {
1932 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1933 if (ret_val) {
1934 DEBUGOUT("Error Configuring DSP after link up\n");
1935 return ret_val;
1936 }
1937 }
1938
1939 return E1000_SUCCESS;
1940 }
1941
1942 /******************************************************************************
1943 * Detects which PHY is present and setup the speed and duplex
1944 *
1945 * hw - Struct containing variables accessed by shared code
1946 ******************************************************************************/
1947 static int32_t
e1000_setup_copper_link(struct e1000_hw * hw)1948 e1000_setup_copper_link(struct e1000_hw *hw)
1949 {
1950 int32_t ret_val;
1951 uint16_t i;
1952 uint16_t phy_data;
1953 uint16_t reg_data;
1954
1955 DEBUGFUNC("e1000_setup_copper_link");
1956
1957 switch (hw->mac_type) {
1958 case e1000_80003es2lan:
1959 case e1000_ich8lan:
1960 /* Set the mac to wait the maximum time between each
1961 * iteration and increase the max iterations when
1962 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1963 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1964 if (ret_val)
1965 return ret_val;
1966 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1967 if (ret_val)
1968 return ret_val;
1969 reg_data |= 0x3F;
1970 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1971 if (ret_val)
1972 return ret_val;
1973 default:
1974 break;
1975 }
1976
1977 /* Check if it is a valid PHY and set PHY mode if necessary. */
1978 ret_val = e1000_copper_link_preconfig(hw);
1979 if (ret_val)
1980 return ret_val;
1981
1982 switch (hw->mac_type) {
1983 case e1000_80003es2lan:
1984 /* Kumeran registers are written-only */
1985 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1986 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1987 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1988 reg_data);
1989 if (ret_val)
1990 return ret_val;
1991 break;
1992 default:
1993 break;
1994 }
1995
1996 if (hw->phy_type == e1000_phy_igp ||
1997 hw->phy_type == e1000_phy_igp_3 ||
1998 hw->phy_type == e1000_phy_igp_2) {
1999 ret_val = e1000_copper_link_igp_setup(hw);
2000 if (ret_val)
2001 return ret_val;
2002 } else if (hw->phy_type == e1000_phy_m88) {
2003 ret_val = e1000_copper_link_mgp_setup(hw);
2004 if (ret_val)
2005 return ret_val;
2006 } else if (hw->phy_type == e1000_phy_gg82563) {
2007 ret_val = e1000_copper_link_ggp_setup(hw);
2008 if (ret_val)
2009 return ret_val;
2010 }
2011
2012 if (hw->autoneg) {
2013 /* Setup autoneg and flow control advertisement
2014 * and perform autonegotiation */
2015 ret_val = e1000_copper_link_autoneg(hw);
2016 if (ret_val)
2017 return ret_val;
2018 } else {
2019 /* PHY will be set to 10H, 10F, 100H,or 100F
2020 * depending on value from forced_speed_duplex. */
2021 DEBUGOUT("Forcing speed and duplex\n");
2022 ret_val = e1000_phy_force_speed_duplex(hw);
2023 if (ret_val) {
2024 DEBUGOUT("Error Forcing Speed and Duplex\n");
2025 return ret_val;
2026 }
2027 }
2028
2029 /* Check link status. Wait up to 100 microseconds for link to become
2030 * valid.
2031 */
2032 for (i = 0; i < 10; i++) {
2033 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2034 if (ret_val)
2035 return ret_val;
2036 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2037 if (ret_val)
2038 return ret_val;
2039
2040 if (phy_data & MII_SR_LINK_STATUS) {
2041 /* Config the MAC and PHY after link is up */
2042 ret_val = e1000_copper_link_postconfig(hw);
2043 if (ret_val)
2044 return ret_val;
2045
2046 DEBUGOUT("Valid link established!!!\n");
2047 return E1000_SUCCESS;
2048 }
2049 usec_delay(10);
2050 }
2051
2052 DEBUGOUT("Unable to establish link!!!\n");
2053 return E1000_SUCCESS;
2054 }
2055
2056 /******************************************************************************
2057 * Configure the MAC-to-PHY interface for 10/100Mbps
2058 *
2059 * hw - Struct containing variables accessed by shared code
2060 ******************************************************************************/
2061 static int32_t
e1000_configure_kmrn_for_10_100(struct e1000_hw * hw,uint16_t duplex)2062 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2063 {
2064 int32_t ret_val = E1000_SUCCESS;
2065 uint32_t tipg;
2066 uint16_t reg_data;
2067
2068 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2069
2070 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2071 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2072 reg_data);
2073 if (ret_val)
2074 return ret_val;
2075
2076 /* Configure Transmit Inter-Packet Gap */
2077 tipg = E1000_READ_REG(hw, TIPG);
2078 tipg &= ~E1000_TIPG_IPGT_MASK;
2079 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2080 E1000_WRITE_REG(hw, TIPG, tipg);
2081
2082 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2083
2084 if (ret_val)
2085 return ret_val;
2086
2087 if (duplex == HALF_DUPLEX)
2088 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2089 else
2090 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2091
2092 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2093
2094 return ret_val;
2095 }
2096
2097 static int32_t
e1000_configure_kmrn_for_1000(struct e1000_hw * hw)2098 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2099 {
2100 int32_t ret_val = E1000_SUCCESS;
2101 uint16_t reg_data;
2102 uint32_t tipg;
2103
2104 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2105
2106 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2107 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2108 reg_data);
2109 if (ret_val)
2110 return ret_val;
2111
2112 /* Configure Transmit Inter-Packet Gap */
2113 tipg = E1000_READ_REG(hw, TIPG);
2114 tipg &= ~E1000_TIPG_IPGT_MASK;
2115 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2116 E1000_WRITE_REG(hw, TIPG, tipg);
2117
2118 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2119
2120 if (ret_val)
2121 return ret_val;
2122
2123 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2124 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2125
2126 return ret_val;
2127 }
2128
2129 /******************************************************************************
2130 * Configures PHY autoneg and flow control advertisement settings
2131 *
2132 * hw - Struct containing variables accessed by shared code
2133 ******************************************************************************/
2134 int32_t
e1000_phy_setup_autoneg(struct e1000_hw * hw)2135 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2136 {
2137 int32_t ret_val;
2138 uint16_t mii_autoneg_adv_reg;
2139 uint16_t mii_1000t_ctrl_reg;
2140
2141 DEBUGFUNC("e1000_phy_setup_autoneg");
2142
2143 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2144 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2145 if (ret_val)
2146 return ret_val;
2147
2148 if (hw->phy_type != e1000_phy_ife) {
2149 /* Read the MII 1000Base-T Control Register (Address 9). */
2150 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2151 if (ret_val)
2152 return ret_val;
2153 } else
2154 mii_1000t_ctrl_reg=0;
2155
2156 /* Need to parse both autoneg_advertised and fc and set up
2157 * the appropriate PHY registers. First we will parse for
2158 * autoneg_advertised software override. Since we can advertise
2159 * a plethora of combinations, we need to check each bit
2160 * individually.
2161 */
2162
2163 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2164 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2165 * the 1000Base-T Control Register (Address 9).
2166 */
2167 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2168 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2169
2170 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2171
2172 /* Do we want to advertise 10 Mb Half Duplex? */
2173 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2174 DEBUGOUT("Advertise 10mb Half duplex\n");
2175 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2176 }
2177
2178 /* Do we want to advertise 10 Mb Full Duplex? */
2179 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2180 DEBUGOUT("Advertise 10mb Full duplex\n");
2181 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2182 }
2183
2184 /* Do we want to advertise 100 Mb Half Duplex? */
2185 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2186 DEBUGOUT("Advertise 100mb Half duplex\n");
2187 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2188 }
2189
2190 /* Do we want to advertise 100 Mb Full Duplex? */
2191 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2192 DEBUGOUT("Advertise 100mb Full duplex\n");
2193 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2194 }
2195
2196 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2197 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2198 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2199 }
2200
2201 /* Do we want to advertise 1000 Mb Full Duplex? */
2202 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2203 DEBUGOUT("Advertise 1000mb Full duplex\n");
2204 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2205 if (hw->phy_type == e1000_phy_ife) {
2206 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2207 }
2208 }
2209
2210 /* Check for a software override of the flow control settings, and
2211 * setup the PHY advertisement registers accordingly. If
2212 * auto-negotiation is enabled, then software will have to set the
2213 * "PAUSE" bits to the correct value in the Auto-Negotiation
2214 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2215 *
2216 * The possible values of the "fc" parameter are:
2217 * 0: Flow control is completely disabled
2218 * 1: Rx flow control is enabled (we can receive pause frames
2219 * but not send pause frames).
2220 * 2: Tx flow control is enabled (we can send pause frames
2221 * but we do not support receiving pause frames).
2222 * 3: Both Rx and TX flow control (symmetric) are enabled.
2223 * other: No software override. The flow control configuration
2224 * in the EEPROM is used.
2225 */
2226 switch (hw->fc) {
2227 case E1000_FC_NONE: /* 0 */
2228 /* Flow control (RX & TX) is completely disabled by a
2229 * software over-ride.
2230 */
2231 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2232 break;
2233 case E1000_FC_RX_PAUSE: /* 1 */
2234 /* RX Flow control is enabled, and TX Flow control is
2235 * disabled, by a software over-ride.
2236 */
2237 /* Since there really isn't a way to advertise that we are
2238 * capable of RX Pause ONLY, we will advertise that we
2239 * support both symmetric and asymmetric RX PAUSE. Later
2240 * (in e1000_config_fc_after_link_up) we will disable the
2241 *hw's ability to send PAUSE frames.
2242 */
2243 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2244 break;
2245 case E1000_FC_TX_PAUSE: /* 2 */
2246 /* TX Flow control is enabled, and RX Flow control is
2247 * disabled, by a software over-ride.
2248 */
2249 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2250 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2251 break;
2252 case E1000_FC_FULL: /* 3 */
2253 /* Flow control (both RX and TX) is enabled by a software
2254 * over-ride.
2255 */
2256 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2257 break;
2258 default:
2259 DEBUGOUT("Flow control param set incorrectly\n");
2260 return -E1000_ERR_CONFIG;
2261 }
2262
2263 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2264 if (ret_val)
2265 return ret_val;
2266
2267 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2268
2269 if (hw->phy_type != e1000_phy_ife) {
2270 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2271 if (ret_val)
2272 return ret_val;
2273 }
2274
2275 return E1000_SUCCESS;
2276 }
2277
2278 /******************************************************************************
2279 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2280 *
2281 * hw - Struct containing variables accessed by shared code
2282 ******************************************************************************/
2283 static int32_t
e1000_phy_force_speed_duplex(struct e1000_hw * hw)2284 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2285 {
2286 uint32_t ctrl;
2287 int32_t ret_val;
2288 uint16_t mii_ctrl_reg;
2289 uint16_t mii_status_reg;
2290 uint16_t phy_data;
2291 uint16_t i;
2292
2293 DEBUGFUNC("e1000_phy_force_speed_duplex");
2294
2295 /* Turn off Flow control if we are forcing speed and duplex. */
2296 hw->fc = E1000_FC_NONE;
2297
2298 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2299
2300 /* Read the Device Control Register. */
2301 ctrl = E1000_READ_REG(hw, CTRL);
2302
2303 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2304 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2305 ctrl &= ~(DEVICE_SPEED_MASK);
2306
2307 /* Clear the Auto Speed Detect Enable bit. */
2308 ctrl &= ~E1000_CTRL_ASDE;
2309
2310 /* Read the MII Control Register. */
2311 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2312 if (ret_val)
2313 return ret_val;
2314
2315 /* We need to disable autoneg in order to force link and duplex. */
2316
2317 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2318
2319 /* Are we forcing Full or Half Duplex? */
2320 if (hw->forced_speed_duplex == e1000_100_full ||
2321 hw->forced_speed_duplex == e1000_10_full) {
2322 /* We want to force full duplex so we SET the full duplex bits in the
2323 * Device and MII Control Registers.
2324 */
2325 ctrl |= E1000_CTRL_FD;
2326 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2327 DEBUGOUT("Full Duplex\n");
2328 } else {
2329 /* We want to force half duplex so we CLEAR the full duplex bits in
2330 * the Device and MII Control Registers.
2331 */
2332 ctrl &= ~E1000_CTRL_FD;
2333 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2334 DEBUGOUT("Half Duplex\n");
2335 }
2336
2337 /* Are we forcing 100Mbps??? */
2338 if (hw->forced_speed_duplex == e1000_100_full ||
2339 hw->forced_speed_duplex == e1000_100_half) {
2340 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2341 ctrl |= E1000_CTRL_SPD_100;
2342 mii_ctrl_reg |= MII_CR_SPEED_100;
2343 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2344 DEBUGOUT("Forcing 100mb ");
2345 } else {
2346 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2347 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2348 mii_ctrl_reg |= MII_CR_SPEED_10;
2349 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2350 DEBUGOUT("Forcing 10mb ");
2351 }
2352
2353 e1000_config_collision_dist(hw);
2354
2355 /* Write the configured values back to the Device Control Reg. */
2356 E1000_WRITE_REG(hw, CTRL, ctrl);
2357
2358 if ((hw->phy_type == e1000_phy_m88) ||
2359 (hw->phy_type == e1000_phy_gg82563)) {
2360 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2361 if (ret_val)
2362 return ret_val;
2363
2364 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2365 * forced whenever speed are duplex are forced.
2366 */
2367 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2368 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2369 if (ret_val)
2370 return ret_val;
2371
2372 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2373
2374 /* Need to reset the PHY or these changes will be ignored */
2375 mii_ctrl_reg |= MII_CR_RESET;
2376
2377 /* Disable MDI-X support for 10/100 */
2378 } else if (hw->phy_type == e1000_phy_ife) {
2379 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2380 if (ret_val)
2381 return ret_val;
2382
2383 phy_data &= ~IFE_PMC_AUTO_MDIX;
2384 phy_data &= ~IFE_PMC_FORCE_MDIX;
2385
2386 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2387 if (ret_val)
2388 return ret_val;
2389
2390 } else {
2391 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2392 * forced whenever speed or duplex are forced.
2393 */
2394 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2395 if (ret_val)
2396 return ret_val;
2397
2398 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2399 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2400
2401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2402 if (ret_val)
2403 return ret_val;
2404 }
2405
2406 /* Write back the modified PHY MII control register. */
2407 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2408 if (ret_val)
2409 return ret_val;
2410
2411 usec_delay(1);
2412
2413 /* The wait_autoneg_complete flag may be a little misleading here.
2414 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2415 * But we do want to delay for a period while forcing only so we
2416 * don't generate false No Link messages. So we will wait here
2417 * only if the user has set wait_autoneg_complete to 1, which is
2418 * the default.
2419 */
2420 if (hw->wait_autoneg_complete) {
2421 /* We will wait for autoneg to complete. */
2422 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2423 mii_status_reg = 0;
2424
2425 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2426 for (i = PHY_FORCE_TIME; i > 0; i--) {
2427 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2428 * to be set.
2429 */
2430 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2431 if (ret_val)
2432 return ret_val;
2433
2434 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2435 if (ret_val)
2436 return ret_val;
2437
2438 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2439 msec_delay(100);
2440 }
2441 if ((i == 0) &&
2442 ((hw->phy_type == e1000_phy_m88) ||
2443 (hw->phy_type == e1000_phy_gg82563))) {
2444 /* We didn't get link. Reset the DSP and wait again for link. */
2445 ret_val = e1000_phy_reset_dsp(hw);
2446 if (ret_val) {
2447 DEBUGOUT("Error Resetting PHY DSP\n");
2448 return ret_val;
2449 }
2450 }
2451 /* This loop will early-out if the link condition has been met. */
2452 for (i = PHY_FORCE_TIME; i > 0; i--) {
2453 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2454 msec_delay(100);
2455 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2456 * to be set.
2457 */
2458 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2459 if (ret_val)
2460 return ret_val;
2461
2462 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2463 if (ret_val)
2464 return ret_val;
2465 }
2466 }
2467
2468 if (hw->phy_type == e1000_phy_m88) {
2469 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2470 * Extended PHY Specific Control Register to 25MHz clock. This value
2471 * defaults back to a 2.5MHz clock when the PHY is reset.
2472 */
2473 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2474 if (ret_val)
2475 return ret_val;
2476
2477 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2478 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2479 if (ret_val)
2480 return ret_val;
2481
2482 /* In addition, because of the s/w reset above, we need to enable CRS on
2483 * TX. This must be set for both full and half duplex operation.
2484 */
2485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2486 if (ret_val)
2487 return ret_val;
2488
2489 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2490 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2491 if (ret_val)
2492 return ret_val;
2493
2494 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2495 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2496 hw->forced_speed_duplex == e1000_10_half)) {
2497 ret_val = e1000_polarity_reversal_workaround(hw);
2498 if (ret_val)
2499 return ret_val;
2500 }
2501 } else if (hw->phy_type == e1000_phy_gg82563) {
2502 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2503 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2504 * we're not in a forced 10/duplex configuration. */
2505 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2506 if (ret_val)
2507 return ret_val;
2508
2509 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2510 if ((hw->forced_speed_duplex == e1000_10_full) ||
2511 (hw->forced_speed_duplex == e1000_10_half))
2512 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2513 else
2514 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2515
2516 /* Also due to the reset, we need to enable CRS on Tx. */
2517 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2518
2519 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2520 if (ret_val)
2521 return ret_val;
2522 }
2523 return E1000_SUCCESS;
2524 }
2525
2526 /******************************************************************************
2527 * Sets the collision distance in the Transmit Control register
2528 *
2529 * hw - Struct containing variables accessed by shared code
2530 *
2531 * Link should have been established previously. Reads the speed and duplex
2532 * information from the Device Status register.
2533 ******************************************************************************/
2534 void
e1000_config_collision_dist(struct e1000_hw * hw)2535 e1000_config_collision_dist(struct e1000_hw *hw)
2536 {
2537 uint32_t tctl, coll_dist;
2538
2539 DEBUGFUNC("e1000_config_collision_dist");
2540
2541 if (hw->mac_type < e1000_82543)
2542 coll_dist = E1000_COLLISION_DISTANCE_82542;
2543 else
2544 coll_dist = E1000_COLLISION_DISTANCE;
2545
2546 tctl = E1000_READ_REG(hw, TCTL);
2547
2548 tctl &= ~E1000_TCTL_COLD;
2549 tctl |= coll_dist << E1000_COLD_SHIFT;
2550
2551 E1000_WRITE_REG(hw, TCTL, tctl);
2552 E1000_WRITE_FLUSH(hw);
2553 }
2554
2555 /******************************************************************************
2556 * Sets MAC speed and duplex settings to reflect the those in the PHY
2557 *
2558 * hw - Struct containing variables accessed by shared code
2559 * mii_reg - data to write to the MII control register
2560 *
2561 * The contents of the PHY register containing the needed information need to
2562 * be passed in.
2563 ******************************************************************************/
2564 static int32_t
e1000_config_mac_to_phy(struct e1000_hw * hw)2565 e1000_config_mac_to_phy(struct e1000_hw *hw)
2566 {
2567 uint32_t ctrl;
2568 int32_t ret_val;
2569 uint16_t phy_data;
2570
2571 DEBUGFUNC("e1000_config_mac_to_phy");
2572
2573 /* 82544 or newer MAC, Auto Speed Detection takes care of
2574 * MAC speed/duplex configuration.*/
2575 if (hw->mac_type >= e1000_82544)
2576 return E1000_SUCCESS;
2577
2578 /* Read the Device Control Register and set the bits to Force Speed
2579 * and Duplex.
2580 */
2581 ctrl = E1000_READ_REG(hw, CTRL);
2582 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2583 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2584
2585 /* Set up duplex in the Device Control and Transmit Control
2586 * registers depending on negotiated values.
2587 */
2588 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2589 if (ret_val)
2590 return ret_val;
2591
2592 if (phy_data & M88E1000_PSSR_DPLX)
2593 ctrl |= E1000_CTRL_FD;
2594 else
2595 ctrl &= ~E1000_CTRL_FD;
2596
2597 e1000_config_collision_dist(hw);
2598
2599 /* Set up speed in the Device Control register depending on
2600 * negotiated values.
2601 */
2602 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2603 ctrl |= E1000_CTRL_SPD_1000;
2604 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2605 ctrl |= E1000_CTRL_SPD_100;
2606
2607 /* Write the configured values back to the Device Control Reg. */
2608 E1000_WRITE_REG(hw, CTRL, ctrl);
2609 return E1000_SUCCESS;
2610 }
2611
2612 /******************************************************************************
2613 * Forces the MAC's flow control settings.
2614 *
2615 * hw - Struct containing variables accessed by shared code
2616 *
2617 * Sets the TFCE and RFCE bits in the device control register to reflect
2618 * the adapter settings. TFCE and RFCE need to be explicitly set by
2619 * software when a Copper PHY is used because autonegotiation is managed
2620 * by the PHY rather than the MAC. Software must also configure these
2621 * bits when link is forced on a fiber connection.
2622 *****************************************************************************/
2623 int32_t
e1000_force_mac_fc(struct e1000_hw * hw)2624 e1000_force_mac_fc(struct e1000_hw *hw)
2625 {
2626 uint32_t ctrl;
2627
2628 DEBUGFUNC("e1000_force_mac_fc");
2629
2630 /* Get the current configuration of the Device Control Register */
2631 ctrl = E1000_READ_REG(hw, CTRL);
2632
2633 /* Because we didn't get link via the internal auto-negotiation
2634 * mechanism (we either forced link or we got link via PHY
2635 * auto-neg), we have to manually enable/disable transmit an
2636 * receive flow control.
2637 *
2638 * The "Case" statement below enables/disable flow control
2639 * according to the "hw->fc" parameter.
2640 *
2641 * The possible values of the "fc" parameter are:
2642 * 0: Flow control is completely disabled
2643 * 1: Rx flow control is enabled (we can receive pause
2644 * frames but not send pause frames).
2645 * 2: Tx flow control is enabled (we can send pause frames
2646 * frames but we do not receive pause frames).
2647 * 3: Both Rx and TX flow control (symmetric) is enabled.
2648 * other: No other values should be possible at this point.
2649 */
2650
2651 switch (hw->fc) {
2652 case E1000_FC_NONE:
2653 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2654 break;
2655 case E1000_FC_RX_PAUSE:
2656 ctrl &= (~E1000_CTRL_TFCE);
2657 ctrl |= E1000_CTRL_RFCE;
2658 break;
2659 case E1000_FC_TX_PAUSE:
2660 ctrl &= (~E1000_CTRL_RFCE);
2661 ctrl |= E1000_CTRL_TFCE;
2662 break;
2663 case E1000_FC_FULL:
2664 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2665 break;
2666 default:
2667 DEBUGOUT("Flow control param set incorrectly\n");
2668 return -E1000_ERR_CONFIG;
2669 }
2670
2671 /* Disable TX Flow Control for 82542 (rev 2.0) */
2672 if (hw->mac_type == e1000_82542_rev2_0)
2673 ctrl &= (~E1000_CTRL_TFCE);
2674
2675 E1000_WRITE_REG(hw, CTRL, ctrl);
2676 return E1000_SUCCESS;
2677 }
2678
2679 /******************************************************************************
2680 * Configures flow control settings after link is established
2681 *
2682 * hw - Struct containing variables accessed by shared code
2683 *
2684 * Should be called immediately after a valid link has been established.
2685 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2686 * and autonegotiation is enabled, the MAC flow control settings will be set
2687 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2688 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2689 *****************************************************************************/
2690 static int32_t
e1000_config_fc_after_link_up(struct e1000_hw * hw)2691 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2692 {
2693 int32_t ret_val;
2694 uint16_t mii_status_reg;
2695 uint16_t mii_nway_adv_reg;
2696 uint16_t mii_nway_lp_ability_reg;
2697 uint16_t speed;
2698 uint16_t duplex;
2699
2700 DEBUGFUNC("e1000_config_fc_after_link_up");
2701
2702 /* Check for the case where we have fiber media and auto-neg failed
2703 * so we had to force link. In this case, we need to force the
2704 * configuration of the MAC to match the "fc" parameter.
2705 */
2706 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2707 ((hw->media_type == e1000_media_type_internal_serdes) &&
2708 (hw->autoneg_failed)) ||
2709 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2710 ret_val = e1000_force_mac_fc(hw);
2711 if (ret_val) {
2712 DEBUGOUT("Error forcing flow control settings\n");
2713 return ret_val;
2714 }
2715 }
2716
2717 /* Check for the case where we have copper media and auto-neg is
2718 * enabled. In this case, we need to check and see if Auto-Neg
2719 * has completed, and if so, how the PHY and link partner has
2720 * flow control configured.
2721 */
2722 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2723 /* Read the MII Status Register and check to see if AutoNeg
2724 * has completed. We read this twice because this reg has
2725 * some "sticky" (latched) bits.
2726 */
2727 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2728 if (ret_val)
2729 return ret_val;
2730 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2731 if (ret_val)
2732 return ret_val;
2733
2734 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2735 /* The AutoNeg process has completed, so we now need to
2736 * read both the Auto Negotiation Advertisement Register
2737 * (Address 4) and the Auto_Negotiation Base Page Ability
2738 * Register (Address 5) to determine how flow control was
2739 * negotiated.
2740 */
2741 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2742 &mii_nway_adv_reg);
2743 if (ret_val)
2744 return ret_val;
2745 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2746 &mii_nway_lp_ability_reg);
2747 if (ret_val)
2748 return ret_val;
2749
2750 /* Two bits in the Auto Negotiation Advertisement Register
2751 * (Address 4) and two bits in the Auto Negotiation Base
2752 * Page Ability Register (Address 5) determine flow control
2753 * for both the PHY and the link partner. The following
2754 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2755 * 1999, describes these PAUSE resolution bits and how flow
2756 * control is determined based upon these settings.
2757 * NOTE: DC = Don't Care
2758 *
2759 * LOCAL DEVICE | LINK PARTNER
2760 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2761 *-------|---------|-------|---------|--------------------
2762 * 0 | 0 | DC | DC | E1000_FC_NONE
2763 * 0 | 1 | 0 | DC | E1000_FC_NONE
2764 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2765 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2766 * 1 | 0 | 0 | DC | E1000_FC_NONE
2767 * 1 | DC | 1 | DC | E1000_FC_FULL
2768 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2769 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2770 *
2771 */
2772 /* Are both PAUSE bits set to 1? If so, this implies
2773 * Symmetric Flow Control is enabled at both ends. The
2774 * ASM_DIR bits are irrelevant per the spec.
2775 *
2776 * For Symmetric Flow Control:
2777 *
2778 * LOCAL DEVICE | LINK PARTNER
2779 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2780 *-------|---------|-------|---------|--------------------
2781 * 1 | DC | 1 | DC | E1000_FC_FULL
2782 *
2783 */
2784 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2785 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2786 /* Now we need to check if the user selected RX ONLY
2787 * of pause frames. In this case, we had to advertise
2788 * FULL flow control because we could not advertise RX
2789 * ONLY. Hence, we must now check to see if we need to
2790 * turn OFF the TRANSMISSION of PAUSE frames.
2791 */
2792 if (hw->original_fc == E1000_FC_FULL) {
2793 hw->fc = E1000_FC_FULL;
2794 DEBUGOUT("Flow Control = FULL.\n");
2795 } else {
2796 hw->fc = E1000_FC_RX_PAUSE;
2797 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2798 }
2799 }
2800 /* For receiving PAUSE frames ONLY.
2801 *
2802 * LOCAL DEVICE | LINK PARTNER
2803 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2804 *-------|---------|-------|---------|--------------------
2805 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2806 *
2807 */
2808 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2809 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2810 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2811 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2812 hw->fc = E1000_FC_TX_PAUSE;
2813 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2814 }
2815 /* For transmitting PAUSE frames ONLY.
2816 *
2817 * LOCAL DEVICE | LINK PARTNER
2818 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2819 *-------|---------|-------|---------|--------------------
2820 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2821 *
2822 */
2823 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2824 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2825 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2826 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2827 hw->fc = E1000_FC_RX_PAUSE;
2828 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2829 }
2830 /* Per the IEEE spec, at this point flow control should be
2831 * disabled. However, we want to consider that we could
2832 * be connected to a legacy switch that doesn't advertise
2833 * desired flow control, but can be forced on the link
2834 * partner. So if we advertised no flow control, that is
2835 * what we will resolve to. If we advertised some kind of
2836 * receive capability (Rx Pause Only or Full Flow Control)
2837 * and the link partner advertised none, we will configure
2838 * ourselves to enable Rx Flow Control only. We can do
2839 * this safely for two reasons: If the link partner really
2840 * didn't want flow control enabled, and we enable Rx, no
2841 * harm done since we won't be receiving any PAUSE frames
2842 * anyway. If the intent on the link partner was to have
2843 * flow control enabled, then by us enabling RX only, we
2844 * can at least receive pause frames and process them.
2845 * This is a good idea because in most cases, since we are
2846 * predominantly a server NIC, more times than not we will
2847 * be asked to delay transmission of packets than asking
2848 * our link partner to pause transmission of frames.
2849 */
2850 else if ((hw->original_fc == E1000_FC_NONE||
2851 hw->original_fc == E1000_FC_TX_PAUSE) ||
2852 hw->fc_strict_ieee) {
2853 hw->fc = E1000_FC_NONE;
2854 DEBUGOUT("Flow Control = NONE.\n");
2855 } else {
2856 hw->fc = E1000_FC_RX_PAUSE;
2857 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2858 }
2859
2860 /* Now we need to do one last check... If we auto-
2861 * negotiated to HALF DUPLEX, flow control should not be
2862 * enabled per IEEE 802.3 spec.
2863 */
2864 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2865 if (ret_val) {
2866 DEBUGOUT("Error getting link speed and duplex\n");
2867 return ret_val;
2868 }
2869
2870 if (duplex == HALF_DUPLEX)
2871 hw->fc = E1000_FC_NONE;
2872
2873 /* Now we call a subroutine to actually force the MAC
2874 * controller to use the correct flow control settings.
2875 */
2876 ret_val = e1000_force_mac_fc(hw);
2877 if (ret_val) {
2878 DEBUGOUT("Error forcing flow control settings\n");
2879 return ret_val;
2880 }
2881 } else {
2882 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2883 }
2884 }
2885 return E1000_SUCCESS;
2886 }
2887
2888 /******************************************************************************
2889 * Checks to see if the link status of the hardware has changed.
2890 *
2891 * hw - Struct containing variables accessed by shared code
2892 *
2893 * Called by any function that needs to check the link status of the adapter.
2894 *****************************************************************************/
2895 int32_t
e1000_check_for_link(struct e1000_hw * hw)2896 e1000_check_for_link(struct e1000_hw *hw)
2897 {
2898 uint32_t rxcw = 0;
2899 uint32_t ctrl;
2900 uint32_t status;
2901 uint32_t rctl;
2902 uint32_t icr;
2903 uint32_t signal = 0;
2904 int32_t ret_val;
2905 uint16_t phy_data;
2906
2907 DEBUGFUNC("e1000_check_for_link");
2908
2909 ctrl = E1000_READ_REG(hw, CTRL);
2910 status = E1000_READ_REG(hw, STATUS);
2911
2912 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2913 * set when the optics detect a signal. On older adapters, it will be
2914 * cleared when there is a signal. This applies to fiber media only.
2915 */
2916 if ((hw->media_type == e1000_media_type_fiber) ||
2917 (hw->media_type == e1000_media_type_internal_serdes)) {
2918 rxcw = E1000_READ_REG(hw, RXCW);
2919
2920 if (hw->media_type == e1000_media_type_fiber) {
2921 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2922 if (status & E1000_STATUS_LU)
2923 hw->get_link_status = FALSE;
2924 }
2925 }
2926
2927 /* If we have a copper PHY then we only want to go out to the PHY
2928 * registers to see if Auto-Neg has completed and/or if our link
2929 * status has changed. The get_link_status flag will be set if we
2930 * receive a Link Status Change interrupt or we have Rx Sequence
2931 * Errors.
2932 */
2933 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2934 /* First we want to see if the MII Status Register reports
2935 * link. If so, then we want to get the current speed/duplex
2936 * of the PHY.
2937 * Read the register twice since the link bit is sticky.
2938 */
2939 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2940 if (ret_val)
2941 return ret_val;
2942 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2943 if (ret_val)
2944 return ret_val;
2945
2946 if (phy_data & MII_SR_LINK_STATUS) {
2947 hw->get_link_status = FALSE;
2948 /* Check if there was DownShift, must be checked immediately after
2949 * link-up */
2950 e1000_check_downshift(hw);
2951
2952 /* If we are on 82544 or 82543 silicon and speed/duplex
2953 * are forced to 10H or 10F, then we will implement the polarity
2954 * reversal workaround. We disable interrupts first, and upon
2955 * returning, place the devices interrupt state to its previous
2956 * value except for the link status change interrupt which will
2957 * happen due to the execution of this workaround.
2958 */
2959
2960 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2961 (!hw->autoneg) &&
2962 (hw->forced_speed_duplex == e1000_10_full ||
2963 hw->forced_speed_duplex == e1000_10_half)) {
2964 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2965 ret_val = e1000_polarity_reversal_workaround(hw);
2966 icr = E1000_READ_REG(hw, ICR);
2967 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2968 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2969 }
2970
2971 } else {
2972 /* No link detected */
2973 e1000_config_dsp_after_link_change(hw, FALSE);
2974 return 0;
2975 }
2976
2977 /* If we are forcing speed/duplex, then we simply return since
2978 * we have already determined whether we have link or not.
2979 */
2980 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2981
2982 /* optimize the dsp settings for the igp phy */
2983 e1000_config_dsp_after_link_change(hw, TRUE);
2984
2985 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2986 * have Si on board that is 82544 or newer, Auto
2987 * Speed Detection takes care of MAC speed/duplex
2988 * configuration. So we only need to configure Collision
2989 * Distance in the MAC. Otherwise, we need to force
2990 * speed/duplex on the MAC to the current PHY speed/duplex
2991 * settings.
2992 */
2993 if (hw->mac_type >= e1000_82544)
2994 e1000_config_collision_dist(hw);
2995 else {
2996 ret_val = e1000_config_mac_to_phy(hw);
2997 if (ret_val) {
2998 DEBUGOUT("Error configuring MAC to PHY settings\n");
2999 return ret_val;
3000 }
3001 }
3002
3003 /* Configure Flow Control now that Auto-Neg has completed. First, we
3004 * need to restore the desired flow control settings because we may
3005 * have had to re-autoneg with a different link partner.
3006 */
3007 ret_val = e1000_config_fc_after_link_up(hw);
3008 if (ret_val) {
3009 DEBUGOUT("Error configuring flow control\n");
3010 return ret_val;
3011 }
3012
3013 /* At this point we know that we are on copper and we have
3014 * auto-negotiated link. These are conditions for checking the link
3015 * partner capability register. We use the link speed to determine if
3016 * TBI compatibility needs to be turned on or off. If the link is not
3017 * at gigabit speed, then TBI compatibility is not needed. If we are
3018 * at gigabit speed, we turn on TBI compatibility.
3019 */
3020 if (hw->tbi_compatibility_en) {
3021 uint16_t speed, duplex;
3022 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3023 if (ret_val) {
3024 DEBUGOUT("Error getting link speed and duplex\n");
3025 return ret_val;
3026 }
3027 if (speed != SPEED_1000) {
3028 /* If link speed is not set to gigabit speed, we do not need
3029 * to enable TBI compatibility.
3030 */
3031 if (hw->tbi_compatibility_on) {
3032 /* If we previously were in the mode, turn it off. */
3033 rctl = E1000_READ_REG(hw, RCTL);
3034 rctl &= ~E1000_RCTL_SBP;
3035 E1000_WRITE_REG(hw, RCTL, rctl);
3036 hw->tbi_compatibility_on = FALSE;
3037 }
3038 } else {
3039 /* If TBI compatibility is was previously off, turn it on. For
3040 * compatibility with a TBI link partner, we will store bad
3041 * packets. Some frames have an additional byte on the end and
3042 * will look like CRC errors to to the hardware.
3043 */
3044 if (!hw->tbi_compatibility_on) {
3045 hw->tbi_compatibility_on = TRUE;
3046 rctl = E1000_READ_REG(hw, RCTL);
3047 rctl |= E1000_RCTL_SBP;
3048 E1000_WRITE_REG(hw, RCTL, rctl);
3049 }
3050 }
3051 }
3052 }
3053 /* If we don't have link (auto-negotiation failed or link partner cannot
3054 * auto-negotiate), the cable is plugged in (we have signal), and our
3055 * link partner is not trying to auto-negotiate with us (we are receiving
3056 * idles or data), we need to force link up. We also need to give
3057 * auto-negotiation time to complete, in case the cable was just plugged
3058 * in. The autoneg_failed flag does this.
3059 */
3060 else if ((((hw->media_type == e1000_media_type_fiber) &&
3061 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3062 (hw->media_type == e1000_media_type_internal_serdes)) &&
3063 (!(status & E1000_STATUS_LU)) &&
3064 (!(rxcw & E1000_RXCW_C))) {
3065 if (hw->autoneg_failed == 0) {
3066 hw->autoneg_failed = 1;
3067 return 0;
3068 }
3069 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3070
3071 /* Disable auto-negotiation in the TXCW register */
3072 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3073
3074 /* Force link-up and also force full-duplex. */
3075 ctrl = E1000_READ_REG(hw, CTRL);
3076 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3077 E1000_WRITE_REG(hw, CTRL, ctrl);
3078
3079 /* Configure Flow Control after forcing link up. */
3080 ret_val = e1000_config_fc_after_link_up(hw);
3081 if (ret_val) {
3082 DEBUGOUT("Error configuring flow control\n");
3083 return ret_val;
3084 }
3085 }
3086 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3087 * auto-negotiation in the TXCW register and disable forced link in the
3088 * Device Control register in an attempt to auto-negotiate with our link
3089 * partner.
3090 */
3091 else if (((hw->media_type == e1000_media_type_fiber) ||
3092 (hw->media_type == e1000_media_type_internal_serdes)) &&
3093 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3094 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3095 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3096 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3097
3098 hw->serdes_link_down = FALSE;
3099 }
3100 /* If we force link for non-auto-negotiation switch, check link status
3101 * based on MAC synchronization for internal serdes media type.
3102 */
3103 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3104 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3105 /* SYNCH bit and IV bit are sticky. */
3106 usec_delay(10);
3107 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3108 if (!(rxcw & E1000_RXCW_IV)) {
3109 hw->serdes_link_down = FALSE;
3110 DEBUGOUT("SERDES: Link is up.\n");
3111 }
3112 } else {
3113 hw->serdes_link_down = TRUE;
3114 DEBUGOUT("SERDES: Link is down.\n");
3115 }
3116 }
3117 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3118 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3119 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3120 }
3121 return E1000_SUCCESS;
3122 }
3123
3124 /******************************************************************************
3125 * Detects the current speed and duplex settings of the hardware.
3126 *
3127 * hw - Struct containing variables accessed by shared code
3128 * speed - Speed of the connection
3129 * duplex - Duplex setting of the connection
3130 *****************************************************************************/
3131 int32_t
e1000_get_speed_and_duplex(struct e1000_hw * hw,uint16_t * speed,uint16_t * duplex)3132 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3133 uint16_t *speed,
3134 uint16_t *duplex)
3135 {
3136 uint32_t status;
3137 int32_t ret_val;
3138 uint16_t phy_data;
3139
3140 DEBUGFUNC("e1000_get_speed_and_duplex");
3141
3142 if (hw->mac_type >= e1000_82543) {
3143 status = E1000_READ_REG(hw, STATUS);
3144 if (status & E1000_STATUS_SPEED_1000) {
3145 *speed = SPEED_1000;
3146 DEBUGOUT("1000 Mbs, ");
3147 } else if (status & E1000_STATUS_SPEED_100) {
3148 *speed = SPEED_100;
3149 DEBUGOUT("100 Mbs, ");
3150 } else {
3151 *speed = SPEED_10;
3152 DEBUGOUT("10 Mbs, ");
3153 }
3154
3155 if (status & E1000_STATUS_FD) {
3156 *duplex = FULL_DUPLEX;
3157 DEBUGOUT("Full Duplex\n");
3158 } else {
3159 *duplex = HALF_DUPLEX;
3160 DEBUGOUT(" Half Duplex\n");
3161 }
3162 } else {
3163 DEBUGOUT("1000 Mbs, Full Duplex\n");
3164 *speed = SPEED_1000;
3165 *duplex = FULL_DUPLEX;
3166 }
3167
3168 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3169 * if it is operating at half duplex. Here we set the duplex settings to
3170 * match the duplex in the link partner's capabilities.
3171 */
3172 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3173 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3174 if (ret_val)
3175 return ret_val;
3176
3177 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3178 *duplex = HALF_DUPLEX;
3179 else {
3180 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3181 if (ret_val)
3182 return ret_val;
3183 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3184 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3185 *duplex = HALF_DUPLEX;
3186 }
3187 }
3188
3189 if ((hw->mac_type == e1000_80003es2lan) &&
3190 (hw->media_type == e1000_media_type_copper)) {
3191 if (*speed == SPEED_1000)
3192 ret_val = e1000_configure_kmrn_for_1000(hw);
3193 else
3194 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3195 if (ret_val)
3196 return ret_val;
3197 }
3198
3199 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3200 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3201 if (ret_val)
3202 return ret_val;
3203 }
3204
3205 return E1000_SUCCESS;
3206 }
3207
3208 /******************************************************************************
3209 * Blocks until autoneg completes or times out (~4.5 seconds)
3210 *
3211 * hw - Struct containing variables accessed by shared code
3212 ******************************************************************************/
3213 static int32_t
e1000_wait_autoneg(struct e1000_hw * hw)3214 e1000_wait_autoneg(struct e1000_hw *hw)
3215 {
3216 int32_t ret_val;
3217 uint16_t i;
3218 uint16_t phy_data;
3219
3220 DEBUGFUNC("e1000_wait_autoneg");
3221 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3222
3223 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3224 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3225 /* Read the MII Status Register and wait for Auto-Neg
3226 * Complete bit to be set.
3227 */
3228 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3229 if (ret_val)
3230 return ret_val;
3231 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3232 if (ret_val)
3233 return ret_val;
3234 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3235 return E1000_SUCCESS;
3236 }
3237 msec_delay(100);
3238 }
3239 return E1000_SUCCESS;
3240 }
3241
3242 /******************************************************************************
3243 * Raises the Management Data Clock
3244 *
3245 * hw - Struct containing variables accessed by shared code
3246 * ctrl - Device control register's current value
3247 ******************************************************************************/
3248 static void
e1000_raise_mdi_clk(struct e1000_hw * hw,uint32_t * ctrl)3249 e1000_raise_mdi_clk(struct e1000_hw *hw,
3250 uint32_t *ctrl)
3251 {
3252 /* Raise the clock input to the Management Data Clock (by setting the MDC
3253 * bit), and then delay 10 microseconds.
3254 */
3255 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3256 E1000_WRITE_FLUSH(hw);
3257 usec_delay(10);
3258 }
3259
3260 /******************************************************************************
3261 * Lowers the Management Data Clock
3262 *
3263 * hw - Struct containing variables accessed by shared code
3264 * ctrl - Device control register's current value
3265 ******************************************************************************/
3266 static void
e1000_lower_mdi_clk(struct e1000_hw * hw,uint32_t * ctrl)3267 e1000_lower_mdi_clk(struct e1000_hw *hw,
3268 uint32_t *ctrl)
3269 {
3270 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3271 * bit), and then delay 10 microseconds.
3272 */
3273 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3274 E1000_WRITE_FLUSH(hw);
3275 usec_delay(10);
3276 }
3277
3278 /******************************************************************************
3279 * Shifts data bits out to the PHY
3280 *
3281 * hw - Struct containing variables accessed by shared code
3282 * data - Data to send out to the PHY
3283 * count - Number of bits to shift out
3284 *
3285 * Bits are shifted out in MSB to LSB order.
3286 ******************************************************************************/
3287 static void
e1000_shift_out_mdi_bits(struct e1000_hw * hw,uint32_t data,uint16_t count)3288 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3289 uint32_t data,
3290 uint16_t count)
3291 {
3292 uint32_t ctrl;
3293 uint32_t mask;
3294
3295 /* We need to shift "count" number of bits out to the PHY. So, the value
3296 * in the "data" parameter will be shifted out to the PHY one bit at a
3297 * time. In order to do this, "data" must be broken down into bits.
3298 */
3299 mask = 0x01;
3300 mask <<= (count - 1);
3301
3302 ctrl = E1000_READ_REG(hw, CTRL);
3303
3304 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3305 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3306
3307 while (mask) {
3308 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3309 * then raising and lowering the Management Data Clock. A "0" is
3310 * shifted out to the PHY by setting the MDIO bit to "0" and then
3311 * raising and lowering the clock.
3312 */
3313 if (data & mask)
3314 ctrl |= E1000_CTRL_MDIO;
3315 else
3316 ctrl &= ~E1000_CTRL_MDIO;
3317
3318 E1000_WRITE_REG(hw, CTRL, ctrl);
3319 E1000_WRITE_FLUSH(hw);
3320
3321 usec_delay(10);
3322
3323 e1000_raise_mdi_clk(hw, &ctrl);
3324 e1000_lower_mdi_clk(hw, &ctrl);
3325
3326 mask = mask >> 1;
3327 }
3328 }
3329
3330 /******************************************************************************
3331 * Shifts data bits in from the PHY
3332 *
3333 * hw - Struct containing variables accessed by shared code
3334 *
3335 * Bits are shifted in in MSB to LSB order.
3336 ******************************************************************************/
3337 static uint16_t
e1000_shift_in_mdi_bits(struct e1000_hw * hw)3338 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3339 {
3340 uint32_t ctrl;
3341 uint16_t data = 0;
3342 uint8_t i;
3343
3344 /* In order to read a register from the PHY, we need to shift in a total
3345 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3346 * to avoid contention on the MDIO pin when a read operation is performed.
3347 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3348 * by raising the input to the Management Data Clock (setting the MDC bit),
3349 * and then reading the value of the MDIO bit.
3350 */
3351 ctrl = E1000_READ_REG(hw, CTRL);
3352
3353 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3354 ctrl &= ~E1000_CTRL_MDIO_DIR;
3355 ctrl &= ~E1000_CTRL_MDIO;
3356
3357 E1000_WRITE_REG(hw, CTRL, ctrl);
3358 E1000_WRITE_FLUSH(hw);
3359
3360 /* Raise and Lower the clock before reading in the data. This accounts for
3361 * the turnaround bits. The first clock occurred when we clocked out the
3362 * last bit of the Register Address.
3363 */
3364 e1000_raise_mdi_clk(hw, &ctrl);
3365 e1000_lower_mdi_clk(hw, &ctrl);
3366
3367 for (data = 0, i = 0; i < 16; i++) {
3368 data = data << 1;
3369 e1000_raise_mdi_clk(hw, &ctrl);
3370 ctrl = E1000_READ_REG(hw, CTRL);
3371 /* Check to see if we shifted in a "1". */
3372 if (ctrl & E1000_CTRL_MDIO)
3373 data |= 1;
3374 e1000_lower_mdi_clk(hw, &ctrl);
3375 }
3376
3377 e1000_raise_mdi_clk(hw, &ctrl);
3378 e1000_lower_mdi_clk(hw, &ctrl);
3379
3380 return data;
3381 }
3382
3383 static int32_t
e1000_swfw_sync_acquire(struct e1000_hw * hw,uint16_t mask)3384 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3385 {
3386 uint32_t swfw_sync = 0;
3387 uint32_t swmask = mask;
3388 uint32_t fwmask = mask << 16;
3389 int32_t timeout = 200;
3390
3391 DEBUGFUNC("e1000_swfw_sync_acquire");
3392
3393 if (hw->swfwhw_semaphore_present)
3394 return e1000_get_software_flag(hw);
3395
3396 if (!hw->swfw_sync_present)
3397 return e1000_get_hw_eeprom_semaphore(hw);
3398
3399 while (timeout) {
3400 if (e1000_get_hw_eeprom_semaphore(hw))
3401 return -E1000_ERR_SWFW_SYNC;
3402
3403 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3404 if (!(swfw_sync & (fwmask | swmask))) {
3405 break;
3406 }
3407
3408 /* firmware currently using resource (fwmask) */
3409 /* or other software thread currently using resource (swmask) */
3410 e1000_put_hw_eeprom_semaphore(hw);
3411 msec_delay_irq(5);
3412 timeout--;
3413 }
3414
3415 if (!timeout) {
3416 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3417 return -E1000_ERR_SWFW_SYNC;
3418 }
3419
3420 swfw_sync |= swmask;
3421 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3422
3423 e1000_put_hw_eeprom_semaphore(hw);
3424 return E1000_SUCCESS;
3425 }
3426
3427 static void
e1000_swfw_sync_release(struct e1000_hw * hw,uint16_t mask)3428 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3429 {
3430 uint32_t swfw_sync;
3431 uint32_t swmask = mask;
3432
3433 DEBUGFUNC("e1000_swfw_sync_release");
3434
3435 if (hw->swfwhw_semaphore_present) {
3436 e1000_release_software_flag(hw);
3437 return;
3438 }
3439
3440 if (!hw->swfw_sync_present) {
3441 e1000_put_hw_eeprom_semaphore(hw);
3442 return;
3443 }
3444
3445 /* if (e1000_get_hw_eeprom_semaphore(hw))
3446 * return -E1000_ERR_SWFW_SYNC; */
3447 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3448 /* empty */
3449
3450 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3451 swfw_sync &= ~swmask;
3452 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3453
3454 e1000_put_hw_eeprom_semaphore(hw);
3455 }
3456
3457 /*****************************************************************************
3458 * Reads the value from a PHY register, if the value is on a specific non zero
3459 * page, sets the page first.
3460 * hw - Struct containing variables accessed by shared code
3461 * reg_addr - address of the PHY register to read
3462 ******************************************************************************/
3463 int32_t
e1000_read_phy_reg(struct e1000_hw * hw,uint32_t reg_addr,uint16_t * phy_data)3464 e1000_read_phy_reg(struct e1000_hw *hw,
3465 uint32_t reg_addr,
3466 uint16_t *phy_data)
3467 {
3468 uint32_t ret_val;
3469 uint16_t swfw;
3470
3471 DEBUGFUNC("e1000_read_phy_reg");
3472
3473 if ((hw->mac_type == e1000_80003es2lan) &&
3474 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3475 swfw = E1000_SWFW_PHY1_SM;
3476 } else {
3477 swfw = E1000_SWFW_PHY0_SM;
3478 }
3479 if (e1000_swfw_sync_acquire(hw, swfw))
3480 return -E1000_ERR_SWFW_SYNC;
3481
3482 if ((hw->phy_type == e1000_phy_igp ||
3483 hw->phy_type == e1000_phy_igp_3 ||
3484 hw->phy_type == e1000_phy_igp_2) &&
3485 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3486 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3487 (uint16_t)reg_addr);
3488 if (ret_val) {
3489 e1000_swfw_sync_release(hw, swfw);
3490 return ret_val;
3491 }
3492 } else if (hw->phy_type == e1000_phy_gg82563) {
3493 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3494 (hw->mac_type == e1000_80003es2lan)) {
3495 /* Select Configuration Page */
3496 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3497 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3498 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3499 } else {
3500 /* Use Alternative Page Select register to access
3501 * registers 30 and 31
3502 */
3503 ret_val = e1000_write_phy_reg_ex(hw,
3504 GG82563_PHY_PAGE_SELECT_ALT,
3505 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3506 }
3507
3508 if (ret_val) {
3509 e1000_swfw_sync_release(hw, swfw);
3510 return ret_val;
3511 }
3512 }
3513 }
3514
3515 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3516 phy_data);
3517
3518 e1000_swfw_sync_release(hw, swfw);
3519 return ret_val;
3520 }
3521
3522 static int32_t
e1000_read_phy_reg_ex(struct e1000_hw * hw,uint32_t reg_addr,uint16_t * phy_data)3523 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3524 uint16_t *phy_data)
3525 {
3526 uint32_t i;
3527 uint32_t mdic = 0;
3528 const uint32_t phy_addr = 1;
3529
3530 DEBUGFUNC("e1000_read_phy_reg_ex");
3531
3532 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3533 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3534 return -E1000_ERR_PARAM;
3535 }
3536
3537 if (hw->mac_type > e1000_82543) {
3538 /* Set up Op-code, Phy Address, and register address in the MDI
3539 * Control register. The MAC will take care of interfacing with the
3540 * PHY to retrieve the desired data.
3541 */
3542 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3543 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3544 (E1000_MDIC_OP_READ));
3545
3546 E1000_WRITE_REG(hw, MDIC, mdic);
3547
3548 /* Poll the ready bit to see if the MDI read completed */
3549 for (i = 0; i < 64; i++) {
3550 usec_delay(50);
3551 mdic = E1000_READ_REG(hw, MDIC);
3552 if (mdic & E1000_MDIC_READY) break;
3553 }
3554 if (!(mdic & E1000_MDIC_READY)) {
3555 DEBUGOUT("MDI Read did not complete\n");
3556 return -E1000_ERR_PHY;
3557 }
3558 if (mdic & E1000_MDIC_ERROR) {
3559 DEBUGOUT("MDI Error\n");
3560 return -E1000_ERR_PHY;
3561 }
3562 *phy_data = (uint16_t) mdic;
3563 } else {
3564 /* We must first send a preamble through the MDIO pin to signal the
3565 * beginning of an MII instruction. This is done by sending 32
3566 * consecutive "1" bits.
3567 */
3568 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3569
3570 /* Now combine the next few fields that are required for a read
3571 * operation. We use this method instead of calling the
3572 * e1000_shift_out_mdi_bits routine five different times. The format of
3573 * a MII read instruction consists of a shift out of 14 bits and is
3574 * defined as follows:
3575 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3576 * followed by a shift in of 18 bits. This first two bits shifted in
3577 * are TurnAround bits used to avoid contention on the MDIO pin when a
3578 * READ operation is performed. These two bits are thrown away
3579 * followed by a shift in of 16 bits which contains the desired data.
3580 */
3581 mdic = ((reg_addr) | (phy_addr << 5) |
3582 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3583
3584 e1000_shift_out_mdi_bits(hw, mdic, 14);
3585
3586 /* Now that we've shifted out the read command to the MII, we need to
3587 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3588 * register address.
3589 */
3590 *phy_data = e1000_shift_in_mdi_bits(hw);
3591 }
3592 return E1000_SUCCESS;
3593 }
3594
3595 /******************************************************************************
3596 * Writes a value to a PHY register
3597 *
3598 * hw - Struct containing variables accessed by shared code
3599 * reg_addr - address of the PHY register to write
3600 * data - data to write to the PHY
3601 ******************************************************************************/
3602 int32_t
e1000_write_phy_reg(struct e1000_hw * hw,uint32_t reg_addr,uint16_t phy_data)3603 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3604 uint16_t phy_data)
3605 {
3606 uint32_t ret_val;
3607 uint16_t swfw;
3608
3609 DEBUGFUNC("e1000_write_phy_reg");
3610
3611 if ((hw->mac_type == e1000_80003es2lan) &&
3612 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3613 swfw = E1000_SWFW_PHY1_SM;
3614 } else {
3615 swfw = E1000_SWFW_PHY0_SM;
3616 }
3617 if (e1000_swfw_sync_acquire(hw, swfw))
3618 return -E1000_ERR_SWFW_SYNC;
3619
3620 if ((hw->phy_type == e1000_phy_igp ||
3621 hw->phy_type == e1000_phy_igp_3 ||
3622 hw->phy_type == e1000_phy_igp_2) &&
3623 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3624 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3625 (uint16_t)reg_addr);
3626 if (ret_val) {
3627 e1000_swfw_sync_release(hw, swfw);
3628 return ret_val;
3629 }
3630 } else if (hw->phy_type == e1000_phy_gg82563) {
3631 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3632 (hw->mac_type == e1000_80003es2lan)) {
3633 /* Select Configuration Page */
3634 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3635 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3636 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3637 } else {
3638 /* Use Alternative Page Select register to access
3639 * registers 30 and 31
3640 */
3641 ret_val = e1000_write_phy_reg_ex(hw,
3642 GG82563_PHY_PAGE_SELECT_ALT,
3643 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3644 }
3645
3646 if (ret_val) {
3647 e1000_swfw_sync_release(hw, swfw);
3648 return ret_val;
3649 }
3650 }
3651 }
3652
3653 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3654 phy_data);
3655
3656 e1000_swfw_sync_release(hw, swfw);
3657 return ret_val;
3658 }
3659
3660 static int32_t
e1000_write_phy_reg_ex(struct e1000_hw * hw,uint32_t reg_addr,uint16_t phy_data)3661 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3662 uint16_t phy_data)
3663 {
3664 uint32_t i;
3665 uint32_t mdic = 0;
3666 const uint32_t phy_addr = 1;
3667
3668 DEBUGFUNC("e1000_write_phy_reg_ex");
3669
3670 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3671 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3672 return -E1000_ERR_PARAM;
3673 }
3674
3675 if (hw->mac_type > e1000_82543) {
3676 /* Set up Op-code, Phy Address, register address, and data intended
3677 * for the PHY register in the MDI Control register. The MAC will take
3678 * care of interfacing with the PHY to send the desired data.
3679 */
3680 mdic = (((uint32_t) phy_data) |
3681 (reg_addr << E1000_MDIC_REG_SHIFT) |
3682 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3683 (E1000_MDIC_OP_WRITE));
3684
3685 E1000_WRITE_REG(hw, MDIC, mdic);
3686
3687 /* Poll the ready bit to see if the MDI read completed */
3688 for (i = 0; i < 641; i++) {
3689 usec_delay(5);
3690 mdic = E1000_READ_REG(hw, MDIC);
3691 if (mdic & E1000_MDIC_READY) break;
3692 }
3693 if (!(mdic & E1000_MDIC_READY)) {
3694 DEBUGOUT("MDI Write did not complete\n");
3695 return -E1000_ERR_PHY;
3696 }
3697 } else {
3698 /* We'll need to use the SW defined pins to shift the write command
3699 * out to the PHY. We first send a preamble to the PHY to signal the
3700 * beginning of the MII instruction. This is done by sending 32
3701 * consecutive "1" bits.
3702 */
3703 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3704
3705 /* Now combine the remaining required fields that will indicate a
3706 * write operation. We use this method instead of calling the
3707 * e1000_shift_out_mdi_bits routine for each field in the command. The
3708 * format of a MII write instruction is as follows:
3709 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3710 */
3711 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3712 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3713 mdic <<= 16;
3714 mdic |= (uint32_t) phy_data;
3715
3716 e1000_shift_out_mdi_bits(hw, mdic, 32);
3717 }
3718
3719 return E1000_SUCCESS;
3720 }
3721
3722 static int32_t
e1000_read_kmrn_reg(struct e1000_hw * hw,uint32_t reg_addr,uint16_t * data)3723 e1000_read_kmrn_reg(struct e1000_hw *hw,
3724 uint32_t reg_addr,
3725 uint16_t *data)
3726 {
3727 uint32_t reg_val;
3728 uint16_t swfw;
3729 DEBUGFUNC("e1000_read_kmrn_reg");
3730
3731 if ((hw->mac_type == e1000_80003es2lan) &&
3732 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3733 swfw = E1000_SWFW_PHY1_SM;
3734 } else {
3735 swfw = E1000_SWFW_PHY0_SM;
3736 }
3737 if (e1000_swfw_sync_acquire(hw, swfw))
3738 return -E1000_ERR_SWFW_SYNC;
3739
3740 /* Write register address */
3741 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3742 E1000_KUMCTRLSTA_OFFSET) |
3743 E1000_KUMCTRLSTA_REN;
3744 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3745 usec_delay(2);
3746
3747 /* Read the data returned */
3748 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3749 *data = (uint16_t)reg_val;
3750
3751 e1000_swfw_sync_release(hw, swfw);
3752 return E1000_SUCCESS;
3753 }
3754
3755 static int32_t
e1000_write_kmrn_reg(struct e1000_hw * hw,uint32_t reg_addr,uint16_t data)3756 e1000_write_kmrn_reg(struct e1000_hw *hw,
3757 uint32_t reg_addr,
3758 uint16_t data)
3759 {
3760 uint32_t reg_val;
3761 uint16_t swfw;
3762 DEBUGFUNC("e1000_write_kmrn_reg");
3763
3764 if ((hw->mac_type == e1000_80003es2lan) &&
3765 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3766 swfw = E1000_SWFW_PHY1_SM;
3767 } else {
3768 swfw = E1000_SWFW_PHY0_SM;
3769 }
3770 if (e1000_swfw_sync_acquire(hw, swfw))
3771 return -E1000_ERR_SWFW_SYNC;
3772
3773 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3774 E1000_KUMCTRLSTA_OFFSET) | data;
3775 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3776 usec_delay(2);
3777
3778 e1000_swfw_sync_release(hw, swfw);
3779 return E1000_SUCCESS;
3780 }
3781
3782 /******************************************************************************
3783 * Returns the PHY to the power-on reset state
3784 *
3785 * hw - Struct containing variables accessed by shared code
3786 ******************************************************************************/
3787 int32_t
e1000_phy_hw_reset(struct e1000_hw * hw)3788 e1000_phy_hw_reset(struct e1000_hw *hw)
3789 {
3790 uint32_t ctrl, ctrl_ext;
3791 uint32_t led_ctrl;
3792 int32_t ret_val;
3793 uint16_t swfw;
3794
3795 DEBUGFUNC("e1000_phy_hw_reset");
3796
3797 /* In the case of the phy reset being blocked, it's not an error, we
3798 * simply return success without performing the reset. */
3799 ret_val = e1000_check_phy_reset_block(hw);
3800 if (ret_val)
3801 return E1000_SUCCESS;
3802
3803 DEBUGOUT("Resetting Phy...\n");
3804
3805 if (hw->mac_type > e1000_82543) {
3806 if ((hw->mac_type == e1000_80003es2lan) &&
3807 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3808 swfw = E1000_SWFW_PHY1_SM;
3809 } else {
3810 swfw = E1000_SWFW_PHY0_SM;
3811 }
3812 if (e1000_swfw_sync_acquire(hw, swfw)) {
3813 DEBUGOUT("Unable to acquire swfw sync\n");
3814 return -E1000_ERR_SWFW_SYNC;
3815 }
3816 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3817 * bit. Then, take it out of reset.
3818 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3819 * and deassert. For e1000_82571 hardware and later, we instead delay
3820 * for 50us between and 10ms after the deassertion.
3821 */
3822 ctrl = E1000_READ_REG(hw, CTRL);
3823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3824 E1000_WRITE_FLUSH(hw);
3825
3826 if (hw->mac_type < e1000_82571)
3827 msec_delay(10);
3828 else
3829 usec_delay(100);
3830
3831 E1000_WRITE_REG(hw, CTRL, ctrl);
3832 E1000_WRITE_FLUSH(hw);
3833
3834 if (hw->mac_type >= e1000_82571)
3835 msec_delay_irq(10);
3836
3837 e1000_swfw_sync_release(hw, swfw);
3838 } else {
3839 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3840 * bit to put the PHY into reset. Then, take it out of reset.
3841 */
3842 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3843 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3844 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3845 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3846 E1000_WRITE_FLUSH(hw);
3847 msec_delay(10);
3848 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3849 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3850 E1000_WRITE_FLUSH(hw);
3851 }
3852 usec_delay(150);
3853
3854 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3855 /* Configure activity LED after PHY reset */
3856 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3857 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3858 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3859 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3860 }
3861
3862 /* Wait for FW to finish PHY configuration. */
3863 ret_val = e1000_get_phy_cfg_done(hw);
3864 if (ret_val != E1000_SUCCESS)
3865 return ret_val;
3866 e1000_release_software_semaphore(hw);
3867
3868 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3869 ret_val = e1000_init_lcd_from_nvm(hw);
3870
3871 return ret_val;
3872 }
3873
3874 /******************************************************************************
3875 * Resets the PHY
3876 *
3877 * hw - Struct containing variables accessed by shared code
3878 *
3879 * Sets bit 15 of the MII Control regiser
3880 ******************************************************************************/
3881 int32_t
e1000_phy_reset(struct e1000_hw * hw)3882 e1000_phy_reset(struct e1000_hw *hw)
3883 {
3884 int32_t ret_val;
3885 uint16_t phy_data;
3886
3887 DEBUGFUNC("e1000_phy_reset");
3888
3889 /* In the case of the phy reset being blocked, it's not an error, we
3890 * simply return success without performing the reset. */
3891 ret_val = e1000_check_phy_reset_block(hw);
3892 if (ret_val)
3893 return E1000_SUCCESS;
3894
3895 switch (hw->phy_type) {
3896 case e1000_phy_igp:
3897 case e1000_phy_igp_2:
3898 case e1000_phy_igp_3:
3899 case e1000_phy_ife:
3900 ret_val = e1000_phy_hw_reset(hw);
3901 if (ret_val)
3902 return ret_val;
3903 break;
3904 default:
3905 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3906 if (ret_val)
3907 return ret_val;
3908
3909 phy_data |= MII_CR_RESET;
3910 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3911 if (ret_val)
3912 return ret_val;
3913
3914 usec_delay(1);
3915 break;
3916 }
3917
3918 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3919 e1000_phy_init_script(hw);
3920
3921 return E1000_SUCCESS;
3922 }
3923
3924 /******************************************************************************
3925 * Work-around for 82566 power-down: on D3 entry-
3926 * 1) disable gigabit link
3927 * 2) write VR power-down enable
3928 * 3) read it back
3929 * if successful continue, else issue LCD reset and repeat
3930 *
3931 * hw - struct containing variables accessed by shared code
3932 ******************************************************************************/
3933 void
e1000_phy_powerdown_workaround(struct e1000_hw * hw)3934 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3935 {
3936 int32_t reg;
3937 uint16_t phy_data;
3938 int32_t retry = 0;
3939
3940 DEBUGFUNC("e1000_phy_powerdown_workaround");
3941
3942 if (hw->phy_type != e1000_phy_igp_3)
3943 return;
3944
3945 do {
3946 /* Disable link */
3947 reg = E1000_READ_REG(hw, PHY_CTRL);
3948 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3949 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3950
3951 /* Write VR power-down enable - bits 9:8 should be 10b */
3952 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3953 phy_data |= (1 << 9);
3954 phy_data &= ~(1 << 8);
3955 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3956
3957 /* Read it back and test */
3958 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3959 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3960 break;
3961
3962 /* Issue PHY reset and repeat at most one more time */
3963 reg = E1000_READ_REG(hw, CTRL);
3964 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3965 retry++;
3966 } while (retry);
3967
3968 return;
3969
3970 }
3971
3972 /******************************************************************************
3973 * Work-around for 82566 Kumeran PCS lock loss:
3974 * On link status change (i.e. PCI reset, speed change) and link is up and
3975 * speed is gigabit-
3976 * 0) if workaround is optionally disabled do nothing
3977 * 1) wait 1ms for Kumeran link to come up
3978 * 2) check Kumeran Diagnostic register PCS lock loss bit
3979 * 3) if not set the link is locked (all is good), otherwise...
3980 * 4) reset the PHY
3981 * 5) repeat up to 10 times
3982 * Note: this is only called for IGP3 copper when speed is 1gb.
3983 *
3984 * hw - struct containing variables accessed by shared code
3985 ******************************************************************************/
3986 static int32_t
e1000_kumeran_lock_loss_workaround(struct e1000_hw * hw)3987 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3988 {
3989 int32_t ret_val;
3990 int32_t reg;
3991 int32_t cnt;
3992 uint16_t phy_data;
3993
3994 if (hw->kmrn_lock_loss_workaround_disabled)
3995 return E1000_SUCCESS;
3996
3997 /* Make sure link is up before proceeding. If not just return.
3998 * Attempting this while link is negotiating fouled up link
3999 * stability */
4000 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4001 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4002
4003 if (phy_data & MII_SR_LINK_STATUS) {
4004 for (cnt = 0; cnt < 10; cnt++) {
4005 /* read once to clear */
4006 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4007 if (ret_val)
4008 return ret_val;
4009 /* and again to get new status */
4010 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4011 if (ret_val)
4012 return ret_val;
4013
4014 /* check for PCS lock */
4015 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4016 return E1000_SUCCESS;
4017
4018 /* Issue PHY reset */
4019 e1000_phy_hw_reset(hw);
4020 msec_delay_irq(5);
4021 }
4022 /* Disable GigE link negotiation */
4023 reg = E1000_READ_REG(hw, PHY_CTRL);
4024 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4025 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4026
4027 /* unable to acquire PCS lock */
4028 return E1000_ERR_PHY;
4029 }
4030
4031 return E1000_SUCCESS;
4032 }
4033
4034 /******************************************************************************
4035 * Probes the expected PHY address for known PHY IDs
4036 *
4037 * hw - Struct containing variables accessed by shared code
4038 ******************************************************************************/
4039 static int32_t
e1000_detect_gig_phy(struct e1000_hw * hw)4040 e1000_detect_gig_phy(struct e1000_hw *hw)
4041 {
4042 int32_t phy_init_status, ret_val;
4043 uint16_t phy_id_high, phy_id_low;
4044 boolean_t match = FALSE;
4045
4046 DEBUGFUNC("e1000_detect_gig_phy");
4047
4048 if (hw->phy_id != 0)
4049 return E1000_SUCCESS;
4050
4051 /* The 82571 firmware may still be configuring the PHY. In this
4052 * case, we cannot access the PHY until the configuration is done. So
4053 * we explicitly set the PHY values. */
4054 if (hw->mac_type == e1000_82571 ||
4055 hw->mac_type == e1000_82572) {
4056 hw->phy_id = IGP01E1000_I_PHY_ID;
4057 hw->phy_type = e1000_phy_igp_2;
4058 return E1000_SUCCESS;
4059 }
4060
4061 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4062 * around that forces PHY page 0 to be set or the reads fail. The rest of
4063 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4064 * So for ESB-2 we need to have this set so our reads won't fail. If the
4065 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4066 * this out as well. */
4067 if (hw->mac_type == e1000_80003es2lan)
4068 hw->phy_type = e1000_phy_gg82563;
4069
4070 /* Read the PHY ID Registers to identify which PHY is onboard. */
4071 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4072 if (ret_val)
4073 return ret_val;
4074
4075 hw->phy_id = (uint32_t) (phy_id_high << 16);
4076 usec_delay(20);
4077 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4078 if (ret_val)
4079 return ret_val;
4080
4081 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4082 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4083
4084 switch (hw->mac_type) {
4085 case e1000_82543:
4086 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4087 break;
4088 case e1000_82544:
4089 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4090 break;
4091 case e1000_82540:
4092 case e1000_82545:
4093 case e1000_82545_rev_3:
4094 case e1000_82546:
4095 case e1000_82546_rev_3:
4096 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4097 break;
4098 case e1000_82541:
4099 case e1000_82541_rev_2:
4100 case e1000_82547:
4101 case e1000_82547_rev_2:
4102 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4103 break;
4104 case e1000_82573:
4105 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4106 break;
4107 case e1000_80003es2lan:
4108 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4109 break;
4110 case e1000_ich8lan:
4111 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4112 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4113 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4114 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4115 break;
4116 default:
4117 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4118 return -E1000_ERR_CONFIG;
4119 }
4120 phy_init_status = e1000_set_phy_type(hw);
4121
4122 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4123 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4124 return E1000_SUCCESS;
4125 }
4126 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4127 return -E1000_ERR_PHY;
4128 }
4129
4130 /******************************************************************************
4131 * Resets the PHY's DSP
4132 *
4133 * hw - Struct containing variables accessed by shared code
4134 ******************************************************************************/
4135 static int32_t
e1000_phy_reset_dsp(struct e1000_hw * hw)4136 e1000_phy_reset_dsp(struct e1000_hw *hw)
4137 {
4138 int32_t ret_val;
4139 DEBUGFUNC("e1000_phy_reset_dsp");
4140
4141 do {
4142 if (hw->phy_type != e1000_phy_gg82563) {
4143 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4144 if (ret_val) break;
4145 }
4146 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4147 if (ret_val) break;
4148 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4149 if (ret_val) break;
4150 ret_val = E1000_SUCCESS;
4151 } while (0);
4152
4153 return ret_val;
4154 }
4155
4156 /******************************************************************************
4157 * Get PHY information from various PHY registers for igp PHY only.
4158 *
4159 * hw - Struct containing variables accessed by shared code
4160 * phy_info - PHY information structure
4161 ******************************************************************************/
4162 static int32_t
e1000_phy_igp_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)4163 e1000_phy_igp_get_info(struct e1000_hw *hw,
4164 struct e1000_phy_info *phy_info)
4165 {
4166 int32_t ret_val;
4167 uint16_t phy_data, min_length, max_length, average;
4168 e1000_rev_polarity polarity;
4169
4170 DEBUGFUNC("e1000_phy_igp_get_info");
4171
4172 /* The downshift status is checked only once, after link is established,
4173 * and it stored in the hw->speed_downgraded parameter. */
4174 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4175
4176 /* IGP01E1000 does not need to support it. */
4177 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4178
4179 /* IGP01E1000 always correct polarity reversal */
4180 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4181
4182 /* Check polarity status */
4183 ret_val = e1000_check_polarity(hw, &polarity);
4184 if (ret_val)
4185 return ret_val;
4186
4187 phy_info->cable_polarity = polarity;
4188
4189 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4190 if (ret_val)
4191 return ret_val;
4192
4193 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4194 IGP01E1000_PSSR_MDIX_SHIFT);
4195
4196 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4197 IGP01E1000_PSSR_SPEED_1000MBPS) {
4198 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4199 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4200 if (ret_val)
4201 return ret_val;
4202
4203 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4204 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4205 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4206 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4207 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4208 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4209
4210 /* Get cable length */
4211 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4212 if (ret_val)
4213 return ret_val;
4214
4215 /* Translate to old method */
4216 average = (max_length + min_length) / 2;
4217
4218 if (average <= e1000_igp_cable_length_50)
4219 phy_info->cable_length = e1000_cable_length_50;
4220 else if (average <= e1000_igp_cable_length_80)
4221 phy_info->cable_length = e1000_cable_length_50_80;
4222 else if (average <= e1000_igp_cable_length_110)
4223 phy_info->cable_length = e1000_cable_length_80_110;
4224 else if (average <= e1000_igp_cable_length_140)
4225 phy_info->cable_length = e1000_cable_length_110_140;
4226 else
4227 phy_info->cable_length = e1000_cable_length_140;
4228 }
4229
4230 return E1000_SUCCESS;
4231 }
4232
4233 /******************************************************************************
4234 * Get PHY information from various PHY registers for ife PHY only.
4235 *
4236 * hw - Struct containing variables accessed by shared code
4237 * phy_info - PHY information structure
4238 ******************************************************************************/
4239 static int32_t
e1000_phy_ife_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)4240 e1000_phy_ife_get_info(struct e1000_hw *hw,
4241 struct e1000_phy_info *phy_info)
4242 {
4243 int32_t ret_val;
4244 uint16_t phy_data;
4245 e1000_rev_polarity polarity;
4246
4247 DEBUGFUNC("e1000_phy_ife_get_info");
4248
4249 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4250 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4251
4252 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4253 if (ret_val)
4254 return ret_val;
4255 phy_info->polarity_correction =
4256 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4257 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4258 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4259
4260 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4261 ret_val = e1000_check_polarity(hw, &polarity);
4262 if (ret_val)
4263 return ret_val;
4264 } else {
4265 /* Polarity is forced. */
4266 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4267 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4268 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4269 }
4270 phy_info->cable_polarity = polarity;
4271
4272 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4273 if (ret_val)
4274 return ret_val;
4275
4276 phy_info->mdix_mode = (e1000_auto_x_mode)
4277 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4278 IFE_PMC_MDIX_MODE_SHIFT);
4279
4280 return E1000_SUCCESS;
4281 }
4282
4283 /******************************************************************************
4284 * Get PHY information from various PHY registers fot m88 PHY only.
4285 *
4286 * hw - Struct containing variables accessed by shared code
4287 * phy_info - PHY information structure
4288 ******************************************************************************/
4289 static int32_t
e1000_phy_m88_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)4290 e1000_phy_m88_get_info(struct e1000_hw *hw,
4291 struct e1000_phy_info *phy_info)
4292 {
4293 int32_t ret_val;
4294 uint16_t phy_data;
4295 e1000_rev_polarity polarity;
4296
4297 DEBUGFUNC("e1000_phy_m88_get_info");
4298
4299 /* The downshift status is checked only once, after link is established,
4300 * and it stored in the hw->speed_downgraded parameter. */
4301 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4302
4303 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4304 if (ret_val)
4305 return ret_val;
4306
4307 phy_info->extended_10bt_distance =
4308 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4309 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4310 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4311
4312 phy_info->polarity_correction =
4313 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4314 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4315 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4316
4317 /* Check polarity status */
4318 ret_val = e1000_check_polarity(hw, &polarity);
4319 if (ret_val)
4320 return ret_val;
4321 phy_info->cable_polarity = polarity;
4322
4323 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4324 if (ret_val)
4325 return ret_val;
4326
4327 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4328 M88E1000_PSSR_MDIX_SHIFT);
4329
4330 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4331 /* Cable Length Estimation and Local/Remote Receiver Information
4332 * are only valid at 1000 Mbps.
4333 */
4334 if (hw->phy_type != e1000_phy_gg82563) {
4335 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4336 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4337 } else {
4338 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4339 &phy_data);
4340 if (ret_val)
4341 return ret_val;
4342
4343 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4344 }
4345
4346 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4347 if (ret_val)
4348 return ret_val;
4349
4350 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4351 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4352 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4353 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4354 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4355 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4356
4357 }
4358
4359 return E1000_SUCCESS;
4360 }
4361
4362 /******************************************************************************
4363 * Get PHY information from various PHY registers
4364 *
4365 * hw - Struct containing variables accessed by shared code
4366 * phy_info - PHY information structure
4367 ******************************************************************************/
4368 int32_t
e1000_phy_get_info(struct e1000_hw * hw,struct e1000_phy_info * phy_info)4369 e1000_phy_get_info(struct e1000_hw *hw,
4370 struct e1000_phy_info *phy_info)
4371 {
4372 int32_t ret_val;
4373 uint16_t phy_data;
4374
4375 DEBUGFUNC("e1000_phy_get_info");
4376
4377 phy_info->cable_length = e1000_cable_length_undefined;
4378 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4379 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4380 phy_info->downshift = e1000_downshift_undefined;
4381 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4382 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4383 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4384 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4385
4386 if (hw->media_type != e1000_media_type_copper) {
4387 DEBUGOUT("PHY info is only valid for copper media\n");
4388 return -E1000_ERR_CONFIG;
4389 }
4390
4391 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4392 if (ret_val)
4393 return ret_val;
4394
4395 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4396 if (ret_val)
4397 return ret_val;
4398
4399 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4400 DEBUGOUT("PHY info is only valid if link is up\n");
4401 return -E1000_ERR_CONFIG;
4402 }
4403
4404 if (hw->phy_type == e1000_phy_igp ||
4405 hw->phy_type == e1000_phy_igp_3 ||
4406 hw->phy_type == e1000_phy_igp_2)
4407 return e1000_phy_igp_get_info(hw, phy_info);
4408 else if (hw->phy_type == e1000_phy_ife)
4409 return e1000_phy_ife_get_info(hw, phy_info);
4410 else
4411 return e1000_phy_m88_get_info(hw, phy_info);
4412 }
4413
4414 int32_t
e1000_validate_mdi_setting(struct e1000_hw * hw)4415 e1000_validate_mdi_setting(struct e1000_hw *hw)
4416 {
4417 DEBUGFUNC("e1000_validate_mdi_settings");
4418
4419 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4420 DEBUGOUT("Invalid MDI setting detected\n");
4421 hw->mdix = 1;
4422 return -E1000_ERR_CONFIG;
4423 }
4424 return E1000_SUCCESS;
4425 }
4426
4427
4428 /******************************************************************************
4429 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4430 * is configured. Additionally, if this is ICH8, the flash controller GbE
4431 * registers must be mapped, or this will crash.
4432 *
4433 * hw - Struct containing variables accessed by shared code
4434 *****************************************************************************/
4435 int32_t
e1000_init_eeprom_params(struct e1000_hw * hw)4436 e1000_init_eeprom_params(struct e1000_hw *hw)
4437 {
4438 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4439 uint32_t eecd = E1000_READ_REG(hw, EECD);
4440 int32_t ret_val = E1000_SUCCESS;
4441 uint16_t eeprom_size;
4442
4443 DEBUGFUNC("e1000_init_eeprom_params");
4444
4445 switch (hw->mac_type) {
4446 case e1000_82542_rev2_0:
4447 case e1000_82542_rev2_1:
4448 case e1000_82543:
4449 case e1000_82544:
4450 eeprom->type = e1000_eeprom_microwire;
4451 eeprom->word_size = 64;
4452 eeprom->opcode_bits = 3;
4453 eeprom->address_bits = 6;
4454 eeprom->delay_usec = 50;
4455 eeprom->use_eerd = FALSE;
4456 eeprom->use_eewr = FALSE;
4457 break;
4458 case e1000_82540:
4459 case e1000_82545:
4460 case e1000_82545_rev_3:
4461 case e1000_82546:
4462 case e1000_82546_rev_3:
4463 eeprom->type = e1000_eeprom_microwire;
4464 eeprom->opcode_bits = 3;
4465 eeprom->delay_usec = 50;
4466 if (eecd & E1000_EECD_SIZE) {
4467 eeprom->word_size = 256;
4468 eeprom->address_bits = 8;
4469 } else {
4470 eeprom->word_size = 64;
4471 eeprom->address_bits = 6;
4472 }
4473 eeprom->use_eerd = FALSE;
4474 eeprom->use_eewr = FALSE;
4475 break;
4476 case e1000_82541:
4477 case e1000_82541_rev_2:
4478 case e1000_82547:
4479 case e1000_82547_rev_2:
4480 if (eecd & E1000_EECD_TYPE) {
4481 eeprom->type = e1000_eeprom_spi;
4482 eeprom->opcode_bits = 8;
4483 eeprom->delay_usec = 1;
4484 if (eecd & E1000_EECD_ADDR_BITS) {
4485 eeprom->page_size = 32;
4486 eeprom->address_bits = 16;
4487 } else {
4488 eeprom->page_size = 8;
4489 eeprom->address_bits = 8;
4490 }
4491 } else {
4492 eeprom->type = e1000_eeprom_microwire;
4493 eeprom->opcode_bits = 3;
4494 eeprom->delay_usec = 50;
4495 if (eecd & E1000_EECD_ADDR_BITS) {
4496 eeprom->word_size = 256;
4497 eeprom->address_bits = 8;
4498 } else {
4499 eeprom->word_size = 64;
4500 eeprom->address_bits = 6;
4501 }
4502 }
4503 eeprom->use_eerd = FALSE;
4504 eeprom->use_eewr = FALSE;
4505 break;
4506 case e1000_82571:
4507 case e1000_82572:
4508 eeprom->type = e1000_eeprom_spi;
4509 eeprom->opcode_bits = 8;
4510 eeprom->delay_usec = 1;
4511 if (eecd & E1000_EECD_ADDR_BITS) {
4512 eeprom->page_size = 32;
4513 eeprom->address_bits = 16;
4514 } else {
4515 eeprom->page_size = 8;
4516 eeprom->address_bits = 8;
4517 }
4518 eeprom->use_eerd = FALSE;
4519 eeprom->use_eewr = FALSE;
4520 break;
4521 case e1000_82573:
4522 eeprom->type = e1000_eeprom_spi;
4523 eeprom->opcode_bits = 8;
4524 eeprom->delay_usec = 1;
4525 if (eecd & E1000_EECD_ADDR_BITS) {
4526 eeprom->page_size = 32;
4527 eeprom->address_bits = 16;
4528 } else {
4529 eeprom->page_size = 8;
4530 eeprom->address_bits = 8;
4531 }
4532 eeprom->use_eerd = TRUE;
4533 eeprom->use_eewr = TRUE;
4534 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4535 eeprom->type = e1000_eeprom_flash;
4536 eeprom->word_size = 2048;
4537
4538 /* Ensure that the Autonomous FLASH update bit is cleared due to
4539 * Flash update issue on parts which use a FLASH for NVM. */
4540 eecd &= ~E1000_EECD_AUPDEN;
4541 E1000_WRITE_REG(hw, EECD, eecd);
4542 }
4543 break;
4544 case e1000_80003es2lan:
4545 eeprom->type = e1000_eeprom_spi;
4546 eeprom->opcode_bits = 8;
4547 eeprom->delay_usec = 1;
4548 if (eecd & E1000_EECD_ADDR_BITS) {
4549 eeprom->page_size = 32;
4550 eeprom->address_bits = 16;
4551 } else {
4552 eeprom->page_size = 8;
4553 eeprom->address_bits = 8;
4554 }
4555 eeprom->use_eerd = TRUE;
4556 eeprom->use_eewr = FALSE;
4557 break;
4558 case e1000_ich8lan:
4559 {
4560 int32_t i = 0;
4561 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4562
4563 eeprom->type = e1000_eeprom_ich8;
4564 eeprom->use_eerd = FALSE;
4565 eeprom->use_eewr = FALSE;
4566 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4567
4568 /* Zero the shadow RAM structure. But don't load it from NVM
4569 * so as to save time for driver init */
4570 if (hw->eeprom_shadow_ram != NULL) {
4571 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4572 hw->eeprom_shadow_ram[i].modified = FALSE;
4573 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4574 }
4575 }
4576
4577 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4578 ICH_FLASH_SECTOR_SIZE;
4579
4580 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4581 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4582
4583 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4584
4585 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4586 break;
4587 }
4588 default:
4589 break;
4590 }
4591
4592 if (eeprom->type == e1000_eeprom_spi) {
4593 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4594 * 32KB (incremented by powers of 2).
4595 */
4596 if (hw->mac_type <= e1000_82547_rev_2) {
4597 /* Set to default value for initial eeprom read. */
4598 eeprom->word_size = 64;
4599 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4600 if (ret_val)
4601 return ret_val;
4602 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4603 /* 256B eeprom size was not supported in earlier hardware, so we
4604 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4605 * is never the result used in the shifting logic below. */
4606 if (eeprom_size)
4607 eeprom_size++;
4608 } else {
4609 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4610 E1000_EECD_SIZE_EX_SHIFT);
4611 }
4612
4613 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4614 }
4615 return ret_val;
4616 }
4617
4618 /******************************************************************************
4619 * Raises the EEPROM's clock input.
4620 *
4621 * hw - Struct containing variables accessed by shared code
4622 * eecd - EECD's current value
4623 *****************************************************************************/
4624 static void
e1000_raise_ee_clk(struct e1000_hw * hw,uint32_t * eecd)4625 e1000_raise_ee_clk(struct e1000_hw *hw,
4626 uint32_t *eecd)
4627 {
4628 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4629 * wait <delay> microseconds.
4630 */
4631 *eecd = *eecd | E1000_EECD_SK;
4632 E1000_WRITE_REG(hw, EECD, *eecd);
4633 E1000_WRITE_FLUSH(hw);
4634 usec_delay(hw->eeprom.delay_usec);
4635 }
4636
4637 /******************************************************************************
4638 * Lowers the EEPROM's clock input.
4639 *
4640 * hw - Struct containing variables accessed by shared code
4641 * eecd - EECD's current value
4642 *****************************************************************************/
4643 static void
e1000_lower_ee_clk(struct e1000_hw * hw,uint32_t * eecd)4644 e1000_lower_ee_clk(struct e1000_hw *hw,
4645 uint32_t *eecd)
4646 {
4647 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4648 * wait 50 microseconds.
4649 */
4650 *eecd = *eecd & ~E1000_EECD_SK;
4651 E1000_WRITE_REG(hw, EECD, *eecd);
4652 E1000_WRITE_FLUSH(hw);
4653 usec_delay(hw->eeprom.delay_usec);
4654 }
4655
4656 /******************************************************************************
4657 * Shift data bits out to the EEPROM.
4658 *
4659 * hw - Struct containing variables accessed by shared code
4660 * data - data to send to the EEPROM
4661 * count - number of bits to shift out
4662 *****************************************************************************/
4663 static void
e1000_shift_out_ee_bits(struct e1000_hw * hw,uint16_t data,uint16_t count)4664 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4665 uint16_t data,
4666 uint16_t count)
4667 {
4668 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4669 uint32_t eecd;
4670 uint32_t mask;
4671
4672 /* We need to shift "count" bits out to the EEPROM. So, value in the
4673 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4674 * In order to do this, "data" must be broken down into bits.
4675 */
4676 mask = 0x01 << (count - 1);
4677 eecd = E1000_READ_REG(hw, EECD);
4678 if (eeprom->type == e1000_eeprom_microwire) {
4679 eecd &= ~E1000_EECD_DO;
4680 } else if (eeprom->type == e1000_eeprom_spi) {
4681 eecd |= E1000_EECD_DO;
4682 }
4683 do {
4684 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4685 * and then raising and then lowering the clock (the SK bit controls
4686 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4687 * by setting "DI" to "0" and then raising and then lowering the clock.
4688 */
4689 eecd &= ~E1000_EECD_DI;
4690
4691 if (data & mask)
4692 eecd |= E1000_EECD_DI;
4693
4694 E1000_WRITE_REG(hw, EECD, eecd);
4695 E1000_WRITE_FLUSH(hw);
4696
4697 usec_delay(eeprom->delay_usec);
4698
4699 e1000_raise_ee_clk(hw, &eecd);
4700 e1000_lower_ee_clk(hw, &eecd);
4701
4702 mask = mask >> 1;
4703
4704 } while (mask);
4705
4706 /* We leave the "DI" bit set to "0" when we leave this routine. */
4707 eecd &= ~E1000_EECD_DI;
4708 E1000_WRITE_REG(hw, EECD, eecd);
4709 }
4710
4711 /******************************************************************************
4712 * Shift data bits in from the EEPROM
4713 *
4714 * hw - Struct containing variables accessed by shared code
4715 *****************************************************************************/
4716 static uint16_t
e1000_shift_in_ee_bits(struct e1000_hw * hw,uint16_t count)4717 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4718 uint16_t count)
4719 {
4720 uint32_t eecd;
4721 uint32_t i;
4722 uint16_t data;
4723
4724 /* In order to read a register from the EEPROM, we need to shift 'count'
4725 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4726 * input to the EEPROM (setting the SK bit), and then reading the value of
4727 * the "DO" bit. During this "shifting in" process the "DI" bit should
4728 * always be clear.
4729 */
4730
4731 eecd = E1000_READ_REG(hw, EECD);
4732
4733 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4734 data = 0;
4735
4736 for (i = 0; i < count; i++) {
4737 data = data << 1;
4738 e1000_raise_ee_clk(hw, &eecd);
4739
4740 eecd = E1000_READ_REG(hw, EECD);
4741
4742 eecd &= ~(E1000_EECD_DI);
4743 if (eecd & E1000_EECD_DO)
4744 data |= 1;
4745
4746 e1000_lower_ee_clk(hw, &eecd);
4747 }
4748
4749 return data;
4750 }
4751
4752 /******************************************************************************
4753 * Prepares EEPROM for access
4754 *
4755 * hw - Struct containing variables accessed by shared code
4756 *
4757 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4758 * function should be called before issuing a command to the EEPROM.
4759 *****************************************************************************/
4760 static int32_t
e1000_acquire_eeprom(struct e1000_hw * hw)4761 e1000_acquire_eeprom(struct e1000_hw *hw)
4762 {
4763 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4764 uint32_t eecd, i=0;
4765
4766 DEBUGFUNC("e1000_acquire_eeprom");
4767
4768 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4769 return -E1000_ERR_SWFW_SYNC;
4770 eecd = E1000_READ_REG(hw, EECD);
4771
4772 if (hw->mac_type != e1000_82573) {
4773 /* Request EEPROM Access */
4774 if (hw->mac_type > e1000_82544) {
4775 eecd |= E1000_EECD_REQ;
4776 E1000_WRITE_REG(hw, EECD, eecd);
4777 eecd = E1000_READ_REG(hw, EECD);
4778 while ((!(eecd & E1000_EECD_GNT)) &&
4779 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4780 i++;
4781 usec_delay(5);
4782 eecd = E1000_READ_REG(hw, EECD);
4783 }
4784 if (!(eecd & E1000_EECD_GNT)) {
4785 eecd &= ~E1000_EECD_REQ;
4786 E1000_WRITE_REG(hw, EECD, eecd);
4787 DEBUGOUT("Could not acquire EEPROM grant\n");
4788 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4789 return -E1000_ERR_EEPROM;
4790 }
4791 }
4792 }
4793
4794 /* Setup EEPROM for Read/Write */
4795
4796 if (eeprom->type == e1000_eeprom_microwire) {
4797 /* Clear SK and DI */
4798 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4799 E1000_WRITE_REG(hw, EECD, eecd);
4800
4801 /* Set CS */
4802 eecd |= E1000_EECD_CS;
4803 E1000_WRITE_REG(hw, EECD, eecd);
4804 } else if (eeprom->type == e1000_eeprom_spi) {
4805 /* Clear SK and CS */
4806 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4807 E1000_WRITE_REG(hw, EECD, eecd);
4808 usec_delay(1);
4809 }
4810
4811 return E1000_SUCCESS;
4812 }
4813
4814 /******************************************************************************
4815 * Returns EEPROM to a "standby" state
4816 *
4817 * hw - Struct containing variables accessed by shared code
4818 *****************************************************************************/
4819 static void
e1000_standby_eeprom(struct e1000_hw * hw)4820 e1000_standby_eeprom(struct e1000_hw *hw)
4821 {
4822 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4823 uint32_t eecd;
4824
4825 eecd = E1000_READ_REG(hw, EECD);
4826
4827 if (eeprom->type == e1000_eeprom_microwire) {
4828 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4829 E1000_WRITE_REG(hw, EECD, eecd);
4830 E1000_WRITE_FLUSH(hw);
4831 usec_delay(eeprom->delay_usec);
4832
4833 /* Clock high */
4834 eecd |= E1000_EECD_SK;
4835 E1000_WRITE_REG(hw, EECD, eecd);
4836 E1000_WRITE_FLUSH(hw);
4837 usec_delay(eeprom->delay_usec);
4838
4839 /* Select EEPROM */
4840 eecd |= E1000_EECD_CS;
4841 E1000_WRITE_REG(hw, EECD, eecd);
4842 E1000_WRITE_FLUSH(hw);
4843 usec_delay(eeprom->delay_usec);
4844
4845 /* Clock low */
4846 eecd &= ~E1000_EECD_SK;
4847 E1000_WRITE_REG(hw, EECD, eecd);
4848 E1000_WRITE_FLUSH(hw);
4849 usec_delay(eeprom->delay_usec);
4850 } else if (eeprom->type == e1000_eeprom_spi) {
4851 /* Toggle CS to flush commands */
4852 eecd |= E1000_EECD_CS;
4853 E1000_WRITE_REG(hw, EECD, eecd);
4854 E1000_WRITE_FLUSH(hw);
4855 usec_delay(eeprom->delay_usec);
4856 eecd &= ~E1000_EECD_CS;
4857 E1000_WRITE_REG(hw, EECD, eecd);
4858 E1000_WRITE_FLUSH(hw);
4859 usec_delay(eeprom->delay_usec);
4860 }
4861 }
4862
4863 /******************************************************************************
4864 * Terminates a command by inverting the EEPROM's chip select pin
4865 *
4866 * hw - Struct containing variables accessed by shared code
4867 *****************************************************************************/
4868 static void
e1000_release_eeprom(struct e1000_hw * hw)4869 e1000_release_eeprom(struct e1000_hw *hw)
4870 {
4871 uint32_t eecd;
4872
4873 DEBUGFUNC("e1000_release_eeprom");
4874
4875 eecd = E1000_READ_REG(hw, EECD);
4876
4877 if (hw->eeprom.type == e1000_eeprom_spi) {
4878 eecd |= E1000_EECD_CS; /* Pull CS high */
4879 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4880
4881 E1000_WRITE_REG(hw, EECD, eecd);
4882
4883 usec_delay(hw->eeprom.delay_usec);
4884 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4885 /* cleanup eeprom */
4886
4887 /* CS on Microwire is active-high */
4888 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4889
4890 E1000_WRITE_REG(hw, EECD, eecd);
4891
4892 /* Rising edge of clock */
4893 eecd |= E1000_EECD_SK;
4894 E1000_WRITE_REG(hw, EECD, eecd);
4895 E1000_WRITE_FLUSH(hw);
4896 usec_delay(hw->eeprom.delay_usec);
4897
4898 /* Falling edge of clock */
4899 eecd &= ~E1000_EECD_SK;
4900 E1000_WRITE_REG(hw, EECD, eecd);
4901 E1000_WRITE_FLUSH(hw);
4902 usec_delay(hw->eeprom.delay_usec);
4903 }
4904
4905 /* Stop requesting EEPROM access */
4906 if (hw->mac_type > e1000_82544) {
4907 eecd &= ~E1000_EECD_REQ;
4908 E1000_WRITE_REG(hw, EECD, eecd);
4909 }
4910
4911 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4912 }
4913
4914 /******************************************************************************
4915 * Reads a 16 bit word from the EEPROM.
4916 *
4917 * hw - Struct containing variables accessed by shared code
4918 *****************************************************************************/
4919 static int32_t
e1000_spi_eeprom_ready(struct e1000_hw * hw)4920 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4921 {
4922 uint16_t retry_count = 0;
4923 uint8_t spi_stat_reg;
4924
4925 DEBUGFUNC("e1000_spi_eeprom_ready");
4926
4927 /* Read "Status Register" repeatedly until the LSB is cleared. The
4928 * EEPROM will signal that the command has been completed by clearing
4929 * bit 0 of the internal status register. If it's not cleared within
4930 * 5 milliseconds, then error out.
4931 */
4932 retry_count = 0;
4933 do {
4934 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4935 hw->eeprom.opcode_bits);
4936 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4937 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4938 break;
4939
4940 usec_delay(5);
4941 retry_count += 5;
4942
4943 e1000_standby_eeprom(hw);
4944 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4945
4946 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4947 * only 0-5mSec on 5V devices)
4948 */
4949 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4950 DEBUGOUT("SPI EEPROM Status error\n");
4951 return -E1000_ERR_EEPROM;
4952 }
4953
4954 return E1000_SUCCESS;
4955 }
4956
4957 /******************************************************************************
4958 * Reads a 16 bit word from the EEPROM.
4959 *
4960 * hw - Struct containing variables accessed by shared code
4961 * offset - offset of word in the EEPROM to read
4962 * data - word read from the EEPROM
4963 * words - number of words to read
4964 *****************************************************************************/
4965 int32_t
e1000_read_eeprom(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)4966 e1000_read_eeprom(struct e1000_hw *hw,
4967 uint16_t offset,
4968 uint16_t words,
4969 uint16_t *data)
4970 {
4971 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4972 uint32_t i = 0;
4973
4974 DEBUGFUNC("e1000_read_eeprom");
4975
4976 /* If eeprom is not yet detected, do so now */
4977 if (eeprom->word_size == 0)
4978 e1000_init_eeprom_params(hw);
4979
4980 /* A check for invalid values: offset too large, too many words, and not
4981 * enough words.
4982 */
4983 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4984 (words == 0)) {
4985 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4986 return -E1000_ERR_EEPROM;
4987 }
4988
4989 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4990 * directly. In this case, we need to acquire the EEPROM so that
4991 * FW or other port software does not interrupt.
4992 */
4993 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4994 hw->eeprom.use_eerd == FALSE) {
4995 /* Prepare the EEPROM for bit-bang reading */
4996 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4997 return -E1000_ERR_EEPROM;
4998 }
4999
5000 /* Eerd register EEPROM access requires no eeprom aquire/release */
5001 if (eeprom->use_eerd == TRUE)
5002 return e1000_read_eeprom_eerd(hw, offset, words, data);
5003
5004 /* ICH EEPROM access is done via the ICH flash controller */
5005 if (eeprom->type == e1000_eeprom_ich8)
5006 return e1000_read_eeprom_ich8(hw, offset, words, data);
5007
5008 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5009 * acquired the EEPROM at this point, so any returns should relase it */
5010 if (eeprom->type == e1000_eeprom_spi) {
5011 uint16_t word_in;
5012 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5013
5014 if (e1000_spi_eeprom_ready(hw)) {
5015 e1000_release_eeprom(hw);
5016 return -E1000_ERR_EEPROM;
5017 }
5018
5019 e1000_standby_eeprom(hw);
5020
5021 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5022 if ((eeprom->address_bits == 8) && (offset >= 128))
5023 read_opcode |= EEPROM_A8_OPCODE_SPI;
5024
5025 /* Send the READ command (opcode + addr) */
5026 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5027 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5028
5029 /* Read the data. The address of the eeprom internally increments with
5030 * each byte (spi) being read, saving on the overhead of eeprom setup
5031 * and tear-down. The address counter will roll over if reading beyond
5032 * the size of the eeprom, thus allowing the entire memory to be read
5033 * starting from any offset. */
5034 for (i = 0; i < words; i++) {
5035 word_in = e1000_shift_in_ee_bits(hw, 16);
5036 data[i] = (word_in >> 8) | (word_in << 8);
5037 }
5038 } else if (eeprom->type == e1000_eeprom_microwire) {
5039 for (i = 0; i < words; i++) {
5040 /* Send the READ command (opcode + addr) */
5041 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5042 eeprom->opcode_bits);
5043 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5044 eeprom->address_bits);
5045
5046 /* Read the data. For microwire, each word requires the overhead
5047 * of eeprom setup and tear-down. */
5048 data[i] = e1000_shift_in_ee_bits(hw, 16);
5049 e1000_standby_eeprom(hw);
5050 }
5051 }
5052
5053 /* End this read operation */
5054 e1000_release_eeprom(hw);
5055
5056 return E1000_SUCCESS;
5057 }
5058
5059 /******************************************************************************
5060 * Reads a 16 bit word from the EEPROM using the EERD register.
5061 *
5062 * hw - Struct containing variables accessed by shared code
5063 * offset - offset of word in the EEPROM to read
5064 * data - word read from the EEPROM
5065 * words - number of words to read
5066 *****************************************************************************/
5067 static int32_t
e1000_read_eeprom_eerd(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)5068 e1000_read_eeprom_eerd(struct e1000_hw *hw,
5069 uint16_t offset,
5070 uint16_t words,
5071 uint16_t *data)
5072 {
5073 uint32_t i, eerd = 0;
5074 int32_t error = 0;
5075
5076 for (i = 0; i < words; i++) {
5077 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5078 E1000_EEPROM_RW_REG_START;
5079
5080 E1000_WRITE_REG(hw, EERD, eerd);
5081 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5082
5083 if (error) {
5084 break;
5085 }
5086 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5087
5088 }
5089
5090 return error;
5091 }
5092
5093 /******************************************************************************
5094 * Writes a 16 bit word from the EEPROM using the EEWR register.
5095 *
5096 * hw - Struct containing variables accessed by shared code
5097 * offset - offset of word in the EEPROM to read
5098 * data - word read from the EEPROM
5099 * words - number of words to read
5100 *****************************************************************************/
5101 static int32_t
e1000_write_eeprom_eewr(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)5102 e1000_write_eeprom_eewr(struct e1000_hw *hw,
5103 uint16_t offset,
5104 uint16_t words,
5105 uint16_t *data)
5106 {
5107 uint32_t register_value = 0;
5108 uint32_t i = 0;
5109 int32_t error = 0;
5110
5111 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5112 return -E1000_ERR_SWFW_SYNC;
5113
5114 for (i = 0; i < words; i++) {
5115 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5116 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5117 E1000_EEPROM_RW_REG_START;
5118
5119 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5120 if (error) {
5121 break;
5122 }
5123
5124 E1000_WRITE_REG(hw, EEWR, register_value);
5125
5126 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5127
5128 if (error) {
5129 break;
5130 }
5131 }
5132
5133 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5134 return error;
5135 }
5136
5137 /******************************************************************************
5138 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5139 *
5140 * hw - Struct containing variables accessed by shared code
5141 *****************************************************************************/
5142 static int32_t
e1000_poll_eerd_eewr_done(struct e1000_hw * hw,int eerd)5143 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5144 {
5145 uint32_t attempts = 100000;
5146 uint32_t i, reg = 0;
5147 int32_t done = E1000_ERR_EEPROM;
5148
5149 for (i = 0; i < attempts; i++) {
5150 if (eerd == E1000_EEPROM_POLL_READ)
5151 reg = E1000_READ_REG(hw, EERD);
5152 else
5153 reg = E1000_READ_REG(hw, EEWR);
5154
5155 if (reg & E1000_EEPROM_RW_REG_DONE) {
5156 done = E1000_SUCCESS;
5157 break;
5158 }
5159 usec_delay(5);
5160 }
5161
5162 return done;
5163 }
5164
5165 /***************************************************************************
5166 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5167 *
5168 * hw - Struct containing variables accessed by shared code
5169 ****************************************************************************/
5170 static boolean_t
e1000_is_onboard_nvm_eeprom(struct e1000_hw * hw)5171 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5172 {
5173 uint32_t eecd = 0;
5174
5175 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5176
5177 if (hw->is_ich == TRUE)
5178 return FALSE;
5179
5180 if (hw->mac_type == e1000_82573) {
5181 eecd = E1000_READ_REG(hw, EECD);
5182
5183 /* Isolate bits 15 & 16 */
5184 eecd = ((eecd >> 15) & 0x03);
5185
5186 /* If both bits are set, device is Flash type */
5187 if (eecd == 0x03) {
5188 return FALSE;
5189 }
5190 }
5191 return TRUE;
5192 }
5193
5194 /******************************************************************************
5195 * Verifies that the EEPROM has a valid checksum
5196 *
5197 * hw - Struct containing variables accessed by shared code
5198 *
5199 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5200 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5201 * valid.
5202 *****************************************************************************/
5203 int32_t
e1000_validate_eeprom_checksum(struct e1000_hw * hw)5204 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5205 {
5206 uint16_t checksum = 0;
5207 uint16_t i, eeprom_data;
5208
5209 DEBUGFUNC("e1000_validate_eeprom_checksum");
5210
5211 if ((hw->mac_type == e1000_82573) &&
5212 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5213 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5214 * 10h-12h. Checksum may need to be fixed. */
5215 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5216 if ((eeprom_data & 0x10) == 0) {
5217 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5218 * has already been fixed. If the checksum is still wrong and this
5219 * bit is a 1, we need to return bad checksum. Otherwise, we need
5220 * to set this bit to a 1 and update the checksum. */
5221 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5222 if ((eeprom_data & 0x8000) == 0) {
5223 eeprom_data |= 0x8000;
5224 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5225 e1000_update_eeprom_checksum(hw);
5226 }
5227 }
5228 }
5229
5230 if (hw->is_ich == TRUE) {
5231
5232 /* Drivers must allocate the shadow ram structure for the
5233 * EEPROM checksum to be updated. Otherwise, this bit as well
5234 * as the checksum must both be set correctly for this
5235 * validation to pass.
5236 */
5237 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5238 if ((eeprom_data & 0x40) == 0) {
5239 eeprom_data |= 0x40;
5240 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5241 e1000_update_eeprom_checksum(hw);
5242 }
5243 }
5244
5245 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5246 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5247 DEBUGOUT("EEPROM Read Error\n");
5248 return -E1000_ERR_EEPROM;
5249 }
5250 checksum += eeprom_data;
5251 }
5252
5253 if (checksum == (uint16_t) EEPROM_SUM)
5254 return E1000_SUCCESS;
5255 else {
5256 DEBUGOUT("EEPROM Checksum Invalid\n");
5257 return -E1000_ERR_EEPROM;
5258 }
5259 }
5260
5261 /******************************************************************************
5262 * Calculates the EEPROM checksum and writes it to the EEPROM
5263 *
5264 * hw - Struct containing variables accessed by shared code
5265 *
5266 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5267 * Writes the difference to word offset 63 of the EEPROM.
5268 *****************************************************************************/
5269 int32_t
e1000_update_eeprom_checksum(struct e1000_hw * hw)5270 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5271 {
5272 uint32_t ctrl_ext;
5273 uint16_t checksum = 0;
5274 uint16_t i, eeprom_data;
5275
5276 DEBUGFUNC("e1000_update_eeprom_checksum");
5277
5278 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5279 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5280 DEBUGOUT("EEPROM Read Error\n");
5281 return -E1000_ERR_EEPROM;
5282 }
5283 checksum += eeprom_data;
5284 }
5285 checksum = (uint16_t) EEPROM_SUM - checksum;
5286 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5287 DEBUGOUT("EEPROM Write Error\n");
5288 return -E1000_ERR_EEPROM;
5289 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5290 e1000_commit_shadow_ram(hw);
5291 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5292 e1000_commit_shadow_ram(hw);
5293 /* Reload the EEPROM, or else modifications will not appear
5294 * until after next adapter reset. */
5295 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5296 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5297 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5298 msec_delay(10);
5299 }
5300 return E1000_SUCCESS;
5301 }
5302
5303 /******************************************************************************
5304 * Parent function for writing words to the different EEPROM types.
5305 *
5306 * hw - Struct containing variables accessed by shared code
5307 * offset - offset within the EEPROM to be written to
5308 * words - number of words to write
5309 * data - 16 bit word to be written to the EEPROM
5310 *
5311 * If e1000_update_eeprom_checksum is not called after this function, the
5312 * EEPROM will most likely contain an invalid checksum.
5313 *****************************************************************************/
5314 int32_t
e1000_write_eeprom(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)5315 e1000_write_eeprom(struct e1000_hw *hw,
5316 uint16_t offset,
5317 uint16_t words,
5318 uint16_t *data)
5319 {
5320 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5321 int32_t status = 0;
5322
5323 DEBUGFUNC("e1000_write_eeprom");
5324
5325 /* If eeprom is not yet detected, do so now */
5326 if (eeprom->word_size == 0)
5327 e1000_init_eeprom_params(hw);
5328
5329 /* A check for invalid values: offset too large, too many words, and not
5330 * enough words.
5331 */
5332 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5333 (words == 0)) {
5334 DEBUGOUT("\"words\" parameter out of bounds\n");
5335 return -E1000_ERR_EEPROM;
5336 }
5337
5338 /* 82573 writes only through eewr */
5339 if (eeprom->use_eewr == TRUE)
5340 return e1000_write_eeprom_eewr(hw, offset, words, data);
5341
5342 if (eeprom->type == e1000_eeprom_ich8)
5343 return e1000_write_eeprom_ich8(hw, offset, words, data);
5344
5345 /* Prepare the EEPROM for writing */
5346 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5347 return -E1000_ERR_EEPROM;
5348
5349 if (eeprom->type == e1000_eeprom_microwire) {
5350 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5351 } else {
5352 status = e1000_write_eeprom_spi(hw, offset, words, data);
5353 msec_delay(10);
5354 }
5355
5356 /* Done with writing */
5357 e1000_release_eeprom(hw);
5358
5359 return status;
5360 }
5361
5362 /******************************************************************************
5363 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5364 *
5365 * hw - Struct containing variables accessed by shared code
5366 * offset - offset within the EEPROM to be written to
5367 * words - number of words to write
5368 * data - pointer to array of 8 bit words to be written to the EEPROM
5369 *
5370 *****************************************************************************/
5371 static int32_t
e1000_write_eeprom_spi(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)5372 e1000_write_eeprom_spi(struct e1000_hw *hw,
5373 uint16_t offset,
5374 uint16_t words,
5375 uint16_t *data)
5376 {
5377 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5378 uint16_t widx = 0;
5379
5380 DEBUGFUNC("e1000_write_eeprom_spi");
5381
5382 while (widx < words) {
5383 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5384
5385 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5386
5387 e1000_standby_eeprom(hw);
5388
5389 /* Send the WRITE ENABLE command (8 bit opcode ) */
5390 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5391 eeprom->opcode_bits);
5392
5393 e1000_standby_eeprom(hw);
5394
5395 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5396 if ((eeprom->address_bits == 8) && (offset >= 128))
5397 write_opcode |= EEPROM_A8_OPCODE_SPI;
5398
5399 /* Send the Write command (8-bit opcode + addr) */
5400 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5401
5402 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5403 eeprom->address_bits);
5404
5405 /* Send the data */
5406
5407 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5408 while (widx < words) {
5409 uint16_t word_out = data[widx];
5410 word_out = (word_out >> 8) | (word_out << 8);
5411 e1000_shift_out_ee_bits(hw, word_out, 16);
5412 widx++;
5413
5414 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5415 * operation, while the smaller eeproms are capable of an 8-byte
5416 * PAGE WRITE operation. Break the inner loop to pass new address
5417 */
5418 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5419 e1000_standby_eeprom(hw);
5420 break;
5421 }
5422 }
5423 }
5424
5425 return E1000_SUCCESS;
5426 }
5427
5428 /******************************************************************************
5429 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5430 *
5431 * hw - Struct containing variables accessed by shared code
5432 * offset - offset within the EEPROM to be written to
5433 * words - number of words to write
5434 * data - pointer to array of 16 bit words to be written to the EEPROM
5435 *
5436 *****************************************************************************/
5437 static int32_t
e1000_write_eeprom_microwire(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)5438 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5439 uint16_t offset,
5440 uint16_t words,
5441 uint16_t *data)
5442 {
5443 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5444 uint32_t eecd;
5445 uint16_t words_written = 0;
5446 uint16_t i = 0;
5447
5448 DEBUGFUNC("e1000_write_eeprom_microwire");
5449
5450 /* Send the write enable command to the EEPROM (3-bit opcode plus
5451 * 6/8-bit dummy address beginning with 11). It's less work to include
5452 * the 11 of the dummy address as part of the opcode than it is to shift
5453 * it over the correct number of bits for the address. This puts the
5454 * EEPROM into write/erase mode.
5455 */
5456 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5457 (uint16_t)(eeprom->opcode_bits + 2));
5458
5459 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5460
5461 /* Prepare the EEPROM */
5462 e1000_standby_eeprom(hw);
5463
5464 while (words_written < words) {
5465 /* Send the Write command (3-bit opcode + addr) */
5466 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5467 eeprom->opcode_bits);
5468
5469 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5470 eeprom->address_bits);
5471
5472 /* Send the data */
5473 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5474
5475 /* Toggle the CS line. This in effect tells the EEPROM to execute
5476 * the previous command.
5477 */
5478 e1000_standby_eeprom(hw);
5479
5480 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5481 * signal that the command has been completed by raising the DO signal.
5482 * If DO does not go high in 10 milliseconds, then error out.
5483 */
5484 for (i = 0; i < 200; i++) {
5485 eecd = E1000_READ_REG(hw, EECD);
5486 if (eecd & E1000_EECD_DO) break;
5487 usec_delay(50);
5488 }
5489 if (i == 200) {
5490 DEBUGOUT("EEPROM Write did not complete\n");
5491 return -E1000_ERR_EEPROM;
5492 }
5493
5494 /* Recover from write */
5495 e1000_standby_eeprom(hw);
5496
5497 words_written++;
5498 }
5499
5500 /* Send the write disable command to the EEPROM (3-bit opcode plus
5501 * 6/8-bit dummy address beginning with 10). It's less work to include
5502 * the 10 of the dummy address as part of the opcode than it is to shift
5503 * it over the correct number of bits for the address. This takes the
5504 * EEPROM out of write/erase mode.
5505 */
5506 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5507 (uint16_t)(eeprom->opcode_bits + 2));
5508
5509 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5510
5511 return E1000_SUCCESS;
5512 }
5513
5514 /******************************************************************************
5515 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5516 * in the eeprom cache and the non modified values in the currently active bank
5517 * to the new bank.
5518 *
5519 * hw - Struct containing variables accessed by shared code
5520 * offset - offset of word in the EEPROM to read
5521 * data - word read from the EEPROM
5522 * words - number of words to read
5523 *****************************************************************************/
5524 static int32_t
e1000_commit_shadow_ram(struct e1000_hw * hw)5525 e1000_commit_shadow_ram(struct e1000_hw *hw)
5526 {
5527 uint32_t attempts = 100000;
5528 uint32_t eecd = 0;
5529 uint32_t flop = 0;
5530 uint32_t i = 0;
5531 int32_t error = E1000_SUCCESS;
5532 uint32_t old_bank_offset = 0;
5533 uint32_t new_bank_offset = 0;
5534 uint8_t low_byte = 0;
5535 uint8_t high_byte = 0;
5536 boolean_t sector_write_failed = FALSE;
5537
5538 if (hw->mac_type == e1000_82573) {
5539 /* The flop register will be used to determine if flash type is STM */
5540 flop = E1000_READ_REG(hw, FLOP);
5541 for (i=0; i < attempts; i++) {
5542 eecd = E1000_READ_REG(hw, EECD);
5543 if ((eecd & E1000_EECD_FLUPD) == 0) {
5544 break;
5545 }
5546 usec_delay(5);
5547 }
5548
5549 if (i == attempts) {
5550 return -E1000_ERR_EEPROM;
5551 }
5552
5553 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5554 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5555 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5556 }
5557
5558 /* Perform the flash update */
5559 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5560
5561 for (i=0; i < attempts; i++) {
5562 eecd = E1000_READ_REG(hw, EECD);
5563 if ((eecd & E1000_EECD_FLUPD) == 0) {
5564 break;
5565 }
5566 usec_delay(5);
5567 }
5568
5569 if (i == attempts) {
5570 return -E1000_ERR_EEPROM;
5571 }
5572 }
5573
5574 if ((hw->is_ich == TRUE) && hw->eeprom_shadow_ram != NULL) {
5575 /* We're writing to the opposite bank so if we're on bank 1,
5576 * write to bank 0 etc. We also need to erase the segment that
5577 * is going to be written */
5578 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5579 new_bank_offset = hw->flash_bank_size * 2;
5580 old_bank_offset = 0;
5581 e1000_erase_ich8_4k_segment(hw, 1);
5582 } else {
5583 old_bank_offset = hw->flash_bank_size * 2;
5584 new_bank_offset = 0;
5585 e1000_erase_ich8_4k_segment(hw, 0);
5586 }
5587
5588 sector_write_failed = FALSE;
5589 /* Loop for every byte in the shadow RAM,
5590 * which is in units of words. */
5591 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5592 /* Determine whether to write the value stored
5593 * in the other NVM bank or a modified value stored
5594 * in the shadow RAM */
5595 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5596 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5597 usec_delay(100);
5598 error = e1000_verify_write_ich8_byte(hw,
5599 (i << 1) + new_bank_offset, low_byte);
5600
5601 if (error != E1000_SUCCESS)
5602 sector_write_failed = TRUE;
5603 else {
5604 high_byte =
5605 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5606 usec_delay(100);
5607 }
5608 } else {
5609 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5610 &low_byte);
5611 usec_delay(100);
5612 error = e1000_verify_write_ich8_byte(hw,
5613 (i << 1) + new_bank_offset, low_byte);
5614
5615 if (error != E1000_SUCCESS)
5616 sector_write_failed = TRUE;
5617 else {
5618 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5619 &high_byte);
5620 usec_delay(100);
5621 }
5622 }
5623
5624 /* If the write of the low byte was successful, go ahread and
5625 * write the high byte while checking to make sure that if it
5626 * is the signature byte, then it is handled properly */
5627 if (sector_write_failed == FALSE) {
5628 /* If the word is 0x13, then make sure the signature bits
5629 * (15:14) are 11b until the commit has completed.
5630 * This will allow us to write 10b which indicates the
5631 * signature is valid. We want to do this after the write
5632 * has completed so that we don't mark the segment valid
5633 * while the write is still in progress */
5634 if (i == E1000_ICH_NVM_SIG_WORD)
5635 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5636
5637 error = e1000_verify_write_ich8_byte(hw,
5638 (i << 1) + new_bank_offset + 1, high_byte);
5639 if (error != E1000_SUCCESS)
5640 sector_write_failed = TRUE;
5641
5642 } else {
5643 /* If the write failed then break from the loop and
5644 * return an error */
5645 break;
5646 }
5647 }
5648
5649 /* Don't bother writing the segment valid bits if sector
5650 * programming failed. */
5651 if (sector_write_failed == FALSE) {
5652 /* Finally validate the new segment by setting bit 15:14
5653 * to 10b in word 0x13 , this can be done without an
5654 * erase as well since these bits are 11 to start with
5655 * and we need to change bit 14 to 0b */
5656 e1000_read_ich8_byte(hw,
5657 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5658 &high_byte);
5659 high_byte &= 0xBF;
5660 error = e1000_verify_write_ich8_byte(hw,
5661 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5662 /* And invalidate the previously valid segment by setting
5663 * its signature word (0x13) high_byte to 0b. This can be
5664 * done without an erase because flash erase sets all bits
5665 * to 1's. We can write 1's to 0's without an erase */
5666 if (error == E1000_SUCCESS) {
5667 error = e1000_verify_write_ich8_byte(hw,
5668 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5669 }
5670
5671 /* Clear the now not used entry in the cache */
5672 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5673 hw->eeprom_shadow_ram[i].modified = FALSE;
5674 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5675 }
5676 }
5677 }
5678
5679 return error;
5680 }
5681
5682 /******************************************************************************
5683 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5684 * second function of dual function devices
5685 *
5686 * hw - Struct containing variables accessed by shared code
5687 *****************************************************************************/
5688 int32_t
e1000_read_mac_addr(struct e1000_hw * hw)5689 e1000_read_mac_addr(struct e1000_hw * hw)
5690 {
5691 uint16_t offset;
5692 uint16_t eeprom_data, i;
5693
5694 DEBUGFUNC("e1000_read_mac_addr");
5695
5696 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5697 offset = i >> 1;
5698 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5699 DEBUGOUT("EEPROM Read Error\n");
5700 return -E1000_ERR_EEPROM;
5701 }
5702 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5703 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5704 }
5705
5706 switch (hw->mac_type) {
5707 default:
5708 break;
5709 case e1000_82546:
5710 case e1000_82546_rev_3:
5711 case e1000_82571:
5712 case e1000_80003es2lan:
5713 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5714 hw->perm_mac_addr[5] ^= 0x01;
5715 break;
5716 }
5717
5718 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5719 hw->mac_addr[i] = hw->perm_mac_addr[i];
5720 return E1000_SUCCESS;
5721 }
5722
5723 /******************************************************************************
5724 * Initializes receive address filters.
5725 *
5726 * hw - Struct containing variables accessed by shared code
5727 *
5728 * Places the MAC address in receive address register 0 and clears the rest
5729 * of the receive addresss registers. Clears the multicast table. Assumes
5730 * the receiver is in reset when the routine is called.
5731 *****************************************************************************/
5732 static void
e1000_init_rx_addrs(struct e1000_hw * hw)5733 e1000_init_rx_addrs(struct e1000_hw *hw)
5734 {
5735 uint32_t i;
5736 uint32_t rar_num;
5737
5738 DEBUGFUNC("e1000_init_rx_addrs");
5739
5740 /* Setup the receive address. */
5741 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5742
5743 e1000_rar_set(hw, hw->mac_addr, 0);
5744
5745 rar_num = E1000_RAR_ENTRIES;
5746
5747 /* Reserve a spot for the Locally Administered Address to work around
5748 * an 82571 issue in which a reset on one port will reload the MAC on
5749 * the other port. */
5750 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5751 rar_num -= 1;
5752 if (hw->mac_type == e1000_ich8lan)
5753 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5754
5755 /* Zero out the other 15 receive addresses. */
5756 DEBUGOUT("Clearing RAR[1-15]\n");
5757 for (i = 1; i < rar_num; i++) {
5758 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5759 E1000_WRITE_FLUSH(hw);
5760 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5761 E1000_WRITE_FLUSH(hw);
5762 }
5763 }
5764
5765 /******************************************************************************
5766 * Hashes an address to determine its location in the multicast table
5767 *
5768 * hw - Struct containing variables accessed by shared code
5769 * mc_addr - the multicast address to hash
5770 *****************************************************************************/
5771 uint32_t
e1000_hash_mc_addr(struct e1000_hw * hw,uint8_t * mc_addr)5772 e1000_hash_mc_addr(struct e1000_hw *hw,
5773 uint8_t *mc_addr)
5774 {
5775 uint32_t hash_value = 0;
5776
5777 /* The portion of the address that is used for the hash table is
5778 * determined by the mc_filter_type setting.
5779 */
5780 switch (hw->mc_filter_type) {
5781 /* [0] [1] [2] [3] [4] [5]
5782 * 01 AA 00 12 34 56
5783 * LSB MSB
5784 */
5785 case 0:
5786 if (hw->is_ich == TRUE) {
5787 /* [47:38] i.e. 0x158 for above example address */
5788 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5789 } else {
5790 /* [47:36] i.e. 0x563 for above example address */
5791 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5792 }
5793 break;
5794 case 1:
5795 if (hw->is_ich == TRUE) {
5796 /* [46:37] i.e. 0x2B1 for above example address */
5797 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5798 } else {
5799 /* [46:35] i.e. 0xAC6 for above example address */
5800 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5801 }
5802 break;
5803 case 2:
5804 if (hw->is_ich == TRUE) {
5805 /*[45:36] i.e. 0x163 for above example address */
5806 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5807 } else {
5808 /* [45:34] i.e. 0x5D8 for above example address */
5809 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5810 }
5811 break;
5812 case 3:
5813 if (hw->is_ich == TRUE) {
5814 /* [43:34] i.e. 0x18D for above example address */
5815 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5816 } else {
5817 /* [43:32] i.e. 0x634 for above example address */
5818 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5819 }
5820 break;
5821 }
5822
5823 hash_value &= 0xFFF;
5824 if (hw->is_ich == TRUE)
5825 hash_value &= 0x3FF;
5826
5827 return hash_value;
5828 }
5829
5830 /******************************************************************************
5831 * Sets the bit in the multicast table corresponding to the hash value.
5832 *
5833 * hw - Struct containing variables accessed by shared code
5834 * hash_value - Multicast address hash value
5835 *****************************************************************************/
5836 void
e1000_mta_set(struct e1000_hw * hw,uint32_t hash_value)5837 e1000_mta_set(struct e1000_hw *hw,
5838 uint32_t hash_value)
5839 {
5840 uint32_t hash_bit, hash_reg;
5841 uint32_t mta;
5842 uint32_t temp;
5843
5844 /* The MTA is a register array of 128 32-bit registers.
5845 * It is treated like an array of 4096 bits. We want to set
5846 * bit BitArray[hash_value]. So we figure out what register
5847 * the bit is in, read it, OR in the new bit, then write
5848 * back the new value. The register is determined by the
5849 * upper 7 bits of the hash value and the bit within that
5850 * register are determined by the lower 5 bits of the value.
5851 */
5852 hash_reg = (hash_value >> 5) & 0x7F;
5853 if (hw->is_ich == TRUE)
5854 hash_reg &= 0x1F;
5855
5856 hash_bit = hash_value & 0x1F;
5857
5858 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5859
5860 mta |= (1 << hash_bit);
5861
5862 /* If we are on an 82544 and we are trying to write an odd offset
5863 * in the MTA, save off the previous entry before writing and
5864 * restore the old value after writing.
5865 */
5866 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5867 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5868 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5869 E1000_WRITE_FLUSH(hw);
5870 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5871 E1000_WRITE_FLUSH(hw);
5872 } else {
5873 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5874 E1000_WRITE_FLUSH(hw);
5875 }
5876 }
5877
5878 /******************************************************************************
5879 * Puts an ethernet address into a receive address register.
5880 *
5881 * hw - Struct containing variables accessed by shared code
5882 * addr - Address to put into receive address register
5883 * index - Receive address register to write
5884 *****************************************************************************/
5885 void
e1000_rar_set(struct e1000_hw * hw,uint8_t * addr,uint32_t index)5886 e1000_rar_set(struct e1000_hw *hw,
5887 uint8_t *addr,
5888 uint32_t index)
5889 {
5890 uint32_t rar_low, rar_high;
5891
5892 /* HW expects these in little endian so we reverse the byte order
5893 * from network order (big endian) to little endian
5894 */
5895 rar_low = ((uint32_t) addr[0] |
5896 ((uint32_t) addr[1] << 8) |
5897 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5898 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5899
5900 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5901 * unit hang.
5902 *
5903 * Description:
5904 * If there are any Rx frames queued up or otherwise present in the HW
5905 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5906 * hang. To work around this issue, we have to disable receives and
5907 * flush out all Rx frames before we enable RSS. To do so, we modify we
5908 * redirect all Rx traffic to manageability and then reset the HW.
5909 * This flushes away Rx frames, and (since the redirections to
5910 * manageability persists across resets) keeps new ones from coming in
5911 * while we work. Then, we clear the Address Valid AV bit for all MAC
5912 * addresses and undo the re-direction to manageability.
5913 * Now, frames are coming in again, but the MAC won't accept them, so
5914 * far so good. We now proceed to initialize RSS (if necessary) and
5915 * configure the Rx unit. Last, we re-enable the AV bits and continue
5916 * on our merry way.
5917 */
5918 switch (hw->mac_type) {
5919 case e1000_82571:
5920 case e1000_82572:
5921 case e1000_80003es2lan:
5922 if (hw->leave_av_bit_off == TRUE)
5923 break;
5924 default:
5925 /* Indicate to hardware the Address is Valid. */
5926 rar_high |= E1000_RAH_AV;
5927 break;
5928 }
5929
5930 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5931 E1000_WRITE_FLUSH(hw);
5932 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5933 E1000_WRITE_FLUSH(hw);
5934 }
5935
5936 /******************************************************************************
5937 * Writes a value to the specified offset in the VLAN filter table.
5938 *
5939 * hw - Struct containing variables accessed by shared code
5940 * offset - Offset in VLAN filer table to write
5941 * value - Value to write into VLAN filter table
5942 *****************************************************************************/
5943 void
e1000_write_vfta(struct e1000_hw * hw,uint32_t offset,uint32_t value)5944 e1000_write_vfta(struct e1000_hw *hw,
5945 uint32_t offset,
5946 uint32_t value)
5947 {
5948 uint32_t temp;
5949
5950 if (hw->is_ich == TRUE)
5951 return;
5952
5953 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5954 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5955 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5956 E1000_WRITE_FLUSH(hw);
5957 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5958 E1000_WRITE_FLUSH(hw);
5959 } else {
5960 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5961 E1000_WRITE_FLUSH(hw);
5962 }
5963 }
5964
5965 /******************************************************************************
5966 * Clears the VLAN filer table
5967 *
5968 * hw - Struct containing variables accessed by shared code
5969 *****************************************************************************/
5970 static void
e1000_clear_vfta(struct e1000_hw * hw)5971 e1000_clear_vfta(struct e1000_hw *hw)
5972 {
5973 uint32_t offset;
5974 uint32_t vfta_value = 0;
5975 uint32_t vfta_offset = 0;
5976 uint32_t vfta_bit_in_reg = 0;
5977
5978 if (hw->is_ich == TRUE)
5979 return;
5980
5981 if (hw->mac_type == e1000_82573) {
5982 if (hw->mng_cookie.vlan_id != 0) {
5983 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5984 * ID. The following operations determine which 32b entry
5985 * (i.e. offset) into the array we want to set the VLAN ID
5986 * (i.e. bit) of the manageability unit. */
5987 vfta_offset = (hw->mng_cookie.vlan_id >>
5988 E1000_VFTA_ENTRY_SHIFT) &
5989 E1000_VFTA_ENTRY_MASK;
5990 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5991 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5992 }
5993 }
5994 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5995 /* If the offset we want to clear is the same offset of the
5996 * manageability VLAN ID, then clear all bits except that of the
5997 * manageability unit */
5998 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5999 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6000 E1000_WRITE_FLUSH(hw);
6001 }
6002 }
6003
6004 static int32_t
e1000_id_led_init(struct e1000_hw * hw)6005 e1000_id_led_init(struct e1000_hw * hw)
6006 {
6007 uint32_t ledctl;
6008 const uint32_t ledctl_mask = 0x000000FF;
6009 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6010 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6011 uint16_t eeprom_data, i, temp;
6012 const uint16_t led_mask = 0x0F;
6013
6014 DEBUGFUNC("e1000_id_led_init");
6015
6016 if (hw->mac_type < e1000_82540) {
6017 /* Nothing to do */
6018 return E1000_SUCCESS;
6019 }
6020
6021 ledctl = E1000_READ_REG(hw, LEDCTL);
6022 hw->ledctl_default = ledctl;
6023 hw->ledctl_mode1 = hw->ledctl_default;
6024 hw->ledctl_mode2 = hw->ledctl_default;
6025
6026 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6027 DEBUGOUT("EEPROM Read Error\n");
6028 return -E1000_ERR_EEPROM;
6029 }
6030
6031 if ((hw->mac_type == e1000_82573) &&
6032 (eeprom_data == ID_LED_RESERVED_82573))
6033 eeprom_data = ID_LED_DEFAULT_82573;
6034 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6035 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6036 if (hw->is_ich == TRUE)
6037 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6038 else
6039 eeprom_data = ID_LED_DEFAULT;
6040 }
6041
6042 for (i = 0; i < 4; i++) {
6043 temp = (eeprom_data >> (i << 2)) & led_mask;
6044 switch (temp) {
6045 case ID_LED_ON1_DEF2:
6046 case ID_LED_ON1_ON2:
6047 case ID_LED_ON1_OFF2:
6048 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6049 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6050 break;
6051 case ID_LED_OFF1_DEF2:
6052 case ID_LED_OFF1_ON2:
6053 case ID_LED_OFF1_OFF2:
6054 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6055 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6056 break;
6057 default:
6058 /* Do nothing */
6059 break;
6060 }
6061 switch (temp) {
6062 case ID_LED_DEF1_ON2:
6063 case ID_LED_ON1_ON2:
6064 case ID_LED_OFF1_ON2:
6065 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6066 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6067 break;
6068 case ID_LED_DEF1_OFF2:
6069 case ID_LED_ON1_OFF2:
6070 case ID_LED_OFF1_OFF2:
6071 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6072 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6073 break;
6074 default:
6075 /* Do nothing */
6076 break;
6077 }
6078 }
6079 return E1000_SUCCESS;
6080 }
6081
6082 /******************************************************************************
6083 * Prepares SW controlable LED for use and saves the current state of the LED.
6084 *
6085 * hw - Struct containing variables accessed by shared code
6086 *****************************************************************************/
6087 int32_t
e1000_setup_led(struct e1000_hw * hw)6088 e1000_setup_led(struct e1000_hw *hw)
6089 {
6090 uint32_t ledctl;
6091 int32_t ret_val = E1000_SUCCESS;
6092
6093 DEBUGFUNC("e1000_setup_led");
6094
6095 switch (hw->mac_type) {
6096 case e1000_82542_rev2_0:
6097 case e1000_82542_rev2_1:
6098 case e1000_82543:
6099 case e1000_82544:
6100 /* No setup necessary */
6101 break;
6102 case e1000_82541:
6103 case e1000_82547:
6104 case e1000_82541_rev_2:
6105 case e1000_82547_rev_2:
6106 /* Turn off PHY Smart Power Down (if enabled) */
6107 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6108 &hw->phy_spd_default);
6109 if (ret_val)
6110 return ret_val;
6111 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6112 (uint16_t)(hw->phy_spd_default &
6113 ~IGP01E1000_GMII_SPD));
6114 if (ret_val)
6115 return ret_val;
6116 /* Fall Through */
6117 default:
6118 if (hw->media_type == e1000_media_type_fiber) {
6119 ledctl = E1000_READ_REG(hw, LEDCTL);
6120 /* Save current LEDCTL settings */
6121 hw->ledctl_default = ledctl;
6122 /* Turn off LED0 */
6123 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6124 E1000_LEDCTL_LED0_BLINK |
6125 E1000_LEDCTL_LED0_MODE_MASK);
6126 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6127 E1000_LEDCTL_LED0_MODE_SHIFT);
6128 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6129 } else if (hw->media_type == e1000_media_type_copper)
6130 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6131 break;
6132 }
6133
6134 return E1000_SUCCESS;
6135 }
6136
6137
6138 /******************************************************************************
6139 * Used on 82571 and later Si that has LED blink bits.
6140 * Callers must use their own timer and should have already called
6141 * e1000_id_led_init()
6142 * Call e1000_cleanup led() to stop blinking
6143 *
6144 * hw - Struct containing variables accessed by shared code
6145 *****************************************************************************/
6146 int32_t
e1000_blink_led_start(struct e1000_hw * hw)6147 e1000_blink_led_start(struct e1000_hw *hw)
6148 {
6149 int16_t i;
6150 uint32_t ledctl_blink = 0;
6151
6152 DEBUGFUNC("e1000_id_led_blink_on");
6153
6154 if (hw->mac_type < e1000_82571) {
6155 /* Nothing to do */
6156 return E1000_SUCCESS;
6157 }
6158 if (hw->media_type == e1000_media_type_fiber) {
6159 /* always blink LED0 for PCI-E fiber */
6160 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6161 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6162 } else {
6163 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6164 ledctl_blink = hw->ledctl_mode2;
6165 for (i=0; i < 4; i++)
6166 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6167 E1000_LEDCTL_MODE_LED_ON)
6168 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6169 }
6170
6171 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6172
6173 return E1000_SUCCESS;
6174 }
6175
6176 /******************************************************************************
6177 * Restores the saved state of the SW controlable LED.
6178 *
6179 * hw - Struct containing variables accessed by shared code
6180 *****************************************************************************/
6181 int32_t
e1000_cleanup_led(struct e1000_hw * hw)6182 e1000_cleanup_led(struct e1000_hw *hw)
6183 {
6184 int32_t ret_val = E1000_SUCCESS;
6185
6186 DEBUGFUNC("e1000_cleanup_led");
6187
6188 switch (hw->mac_type) {
6189 case e1000_82542_rev2_0:
6190 case e1000_82542_rev2_1:
6191 case e1000_82543:
6192 case e1000_82544:
6193 /* No cleanup necessary */
6194 break;
6195 case e1000_82541:
6196 case e1000_82547:
6197 case e1000_82541_rev_2:
6198 case e1000_82547_rev_2:
6199 /* Turn on PHY Smart Power Down (if previously enabled) */
6200 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6201 hw->phy_spd_default);
6202 if (ret_val)
6203 return ret_val;
6204 /* Fall Through */
6205 default:
6206 if (hw->phy_type == e1000_phy_ife) {
6207 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6208 break;
6209 }
6210 /* Restore LEDCTL settings */
6211 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6212 break;
6213 }
6214
6215 return E1000_SUCCESS;
6216 }
6217
6218 /******************************************************************************
6219 * Turns on the software controllable LED
6220 *
6221 * hw - Struct containing variables accessed by shared code
6222 *****************************************************************************/
6223 int32_t
e1000_led_on(struct e1000_hw * hw)6224 e1000_led_on(struct e1000_hw *hw)
6225 {
6226 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6227
6228 DEBUGFUNC("e1000_led_on");
6229
6230 switch (hw->mac_type) {
6231 case e1000_82542_rev2_0:
6232 case e1000_82542_rev2_1:
6233 case e1000_82543:
6234 /* Set SW Defineable Pin 0 to turn on the LED */
6235 ctrl |= E1000_CTRL_SWDPIN0;
6236 ctrl |= E1000_CTRL_SWDPIO0;
6237 break;
6238 case e1000_82544:
6239 if (hw->media_type == e1000_media_type_fiber) {
6240 /* Set SW Defineable Pin 0 to turn on the LED */
6241 ctrl |= E1000_CTRL_SWDPIN0;
6242 ctrl |= E1000_CTRL_SWDPIO0;
6243 } else {
6244 /* Clear SW Defineable Pin 0 to turn on the LED */
6245 ctrl &= ~E1000_CTRL_SWDPIN0;
6246 ctrl |= E1000_CTRL_SWDPIO0;
6247 }
6248 break;
6249 default:
6250 if (hw->media_type == e1000_media_type_fiber) {
6251 /* Clear SW Defineable Pin 0 to turn on the LED */
6252 ctrl &= ~E1000_CTRL_SWDPIN0;
6253 ctrl |= E1000_CTRL_SWDPIO0;
6254 } else if (hw->phy_type == e1000_phy_ife) {
6255 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6256 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6257 } else if (hw->media_type == e1000_media_type_copper) {
6258 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6259 return E1000_SUCCESS;
6260 }
6261 break;
6262 }
6263
6264 E1000_WRITE_REG(hw, CTRL, ctrl);
6265
6266 return E1000_SUCCESS;
6267 }
6268
6269 /******************************************************************************
6270 * Turns off the software controllable LED
6271 *
6272 * hw - Struct containing variables accessed by shared code
6273 *****************************************************************************/
6274 int32_t
e1000_led_off(struct e1000_hw * hw)6275 e1000_led_off(struct e1000_hw *hw)
6276 {
6277 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6278
6279 DEBUGFUNC("e1000_led_off");
6280
6281 switch (hw->mac_type) {
6282 case e1000_82542_rev2_0:
6283 case e1000_82542_rev2_1:
6284 case e1000_82543:
6285 /* Clear SW Defineable Pin 0 to turn off the LED */
6286 ctrl &= ~E1000_CTRL_SWDPIN0;
6287 ctrl |= E1000_CTRL_SWDPIO0;
6288 break;
6289 case e1000_82544:
6290 if (hw->media_type == e1000_media_type_fiber) {
6291 /* Clear SW Defineable Pin 0 to turn off the LED */
6292 ctrl &= ~E1000_CTRL_SWDPIN0;
6293 ctrl |= E1000_CTRL_SWDPIO0;
6294 } else {
6295 /* Set SW Defineable Pin 0 to turn off the LED */
6296 ctrl |= E1000_CTRL_SWDPIN0;
6297 ctrl |= E1000_CTRL_SWDPIO0;
6298 }
6299 break;
6300 default:
6301 if (hw->media_type == e1000_media_type_fiber) {
6302 /* Set SW Defineable Pin 0 to turn off the LED */
6303 ctrl |= E1000_CTRL_SWDPIN0;
6304 ctrl |= E1000_CTRL_SWDPIO0;
6305 } else if (hw->phy_type == e1000_phy_ife) {
6306 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6307 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6308 } else if (hw->media_type == e1000_media_type_copper) {
6309 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6310 return E1000_SUCCESS;
6311 }
6312 break;
6313 }
6314
6315 E1000_WRITE_REG(hw, CTRL, ctrl);
6316
6317 return E1000_SUCCESS;
6318 }
6319
6320 /******************************************************************************
6321 * Clears all hardware statistics counters.
6322 *
6323 * hw - Struct containing variables accessed by shared code
6324 *****************************************************************************/
6325 static void
e1000_clear_hw_cntrs(struct e1000_hw * hw)6326 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6327 {
6328 volatile uint32_t temp;
6329
6330 temp = E1000_READ_REG(hw, CRCERRS);
6331 temp = E1000_READ_REG(hw, SYMERRS);
6332 temp = E1000_READ_REG(hw, MPC);
6333 temp = E1000_READ_REG(hw, SCC);
6334 temp = E1000_READ_REG(hw, ECOL);
6335 temp = E1000_READ_REG(hw, MCC);
6336 temp = E1000_READ_REG(hw, LATECOL);
6337 temp = E1000_READ_REG(hw, COLC);
6338 temp = E1000_READ_REG(hw, DC);
6339 temp = E1000_READ_REG(hw, SEC);
6340 temp = E1000_READ_REG(hw, RLEC);
6341 temp = E1000_READ_REG(hw, XONRXC);
6342 temp = E1000_READ_REG(hw, XONTXC);
6343 temp = E1000_READ_REG(hw, XOFFRXC);
6344 temp = E1000_READ_REG(hw, XOFFTXC);
6345 temp = E1000_READ_REG(hw, FCRUC);
6346
6347 if (hw->is_ich == FALSE) {
6348 temp = E1000_READ_REG(hw, PRC64);
6349 temp = E1000_READ_REG(hw, PRC127);
6350 temp = E1000_READ_REG(hw, PRC255);
6351 temp = E1000_READ_REG(hw, PRC511);
6352 temp = E1000_READ_REG(hw, PRC1023);
6353 temp = E1000_READ_REG(hw, PRC1522);
6354 }
6355
6356 temp = E1000_READ_REG(hw, GPRC);
6357 temp = E1000_READ_REG(hw, BPRC);
6358 temp = E1000_READ_REG(hw, MPRC);
6359 temp = E1000_READ_REG(hw, GPTC);
6360 temp = E1000_READ_REG(hw, GORCL);
6361 temp = E1000_READ_REG(hw, GORCH);
6362 temp = E1000_READ_REG(hw, GOTCL);
6363 temp = E1000_READ_REG(hw, GOTCH);
6364 temp = E1000_READ_REG(hw, RNBC);
6365 temp = E1000_READ_REG(hw, RUC);
6366 temp = E1000_READ_REG(hw, RFC);
6367 temp = E1000_READ_REG(hw, ROC);
6368 temp = E1000_READ_REG(hw, RJC);
6369 temp = E1000_READ_REG(hw, TORL);
6370 temp = E1000_READ_REG(hw, TORH);
6371 temp = E1000_READ_REG(hw, TOTL);
6372 temp = E1000_READ_REG(hw, TOTH);
6373 temp = E1000_READ_REG(hw, TPR);
6374 temp = E1000_READ_REG(hw, TPT);
6375
6376 if (hw->is_ich == FALSE) {
6377 temp = E1000_READ_REG(hw, PTC64);
6378 temp = E1000_READ_REG(hw, PTC127);
6379 temp = E1000_READ_REG(hw, PTC255);
6380 temp = E1000_READ_REG(hw, PTC511);
6381 temp = E1000_READ_REG(hw, PTC1023);
6382 temp = E1000_READ_REG(hw, PTC1522);
6383 }
6384
6385 temp = E1000_READ_REG(hw, MPTC);
6386 temp = E1000_READ_REG(hw, BPTC);
6387
6388 if (hw->mac_type < e1000_82543) return;
6389
6390 temp = E1000_READ_REG(hw, ALGNERRC);
6391 temp = E1000_READ_REG(hw, RXERRC);
6392 temp = E1000_READ_REG(hw, TNCRS);
6393 temp = E1000_READ_REG(hw, CEXTERR);
6394 temp = E1000_READ_REG(hw, TSCTC);
6395 temp = E1000_READ_REG(hw, TSCTFC);
6396
6397 if (hw->mac_type <= e1000_82544) return;
6398
6399 temp = E1000_READ_REG(hw, MGTPRC);
6400 temp = E1000_READ_REG(hw, MGTPDC);
6401 temp = E1000_READ_REG(hw, MGTPTC);
6402
6403 if (hw->mac_type <= e1000_82547_rev_2) return;
6404
6405 temp = E1000_READ_REG(hw, IAC);
6406 temp = E1000_READ_REG(hw, ICRXOC);
6407
6408 if (hw->is_ich == TRUE) return;
6409
6410 temp = E1000_READ_REG(hw, ICRXPTC);
6411 temp = E1000_READ_REG(hw, ICRXATC);
6412 temp = E1000_READ_REG(hw, ICTXPTC);
6413 temp = E1000_READ_REG(hw, ICTXATC);
6414 temp = E1000_READ_REG(hw, ICTXQEC);
6415 temp = E1000_READ_REG(hw, ICTXQMTC);
6416 temp = E1000_READ_REG(hw, ICRXDMTC);
6417
6418 }
6419
6420 /******************************************************************************
6421 * Resets Adaptive IFS to its default state.
6422 *
6423 * hw - Struct containing variables accessed by shared code
6424 *
6425 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6426 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6427 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6428 * before calling this function.
6429 *****************************************************************************/
6430 void
e1000_reset_adaptive(struct e1000_hw * hw)6431 e1000_reset_adaptive(struct e1000_hw *hw)
6432 {
6433 DEBUGFUNC("e1000_reset_adaptive");
6434
6435 if (hw->adaptive_ifs) {
6436 if (!hw->ifs_params_forced) {
6437 hw->current_ifs_val = 0;
6438 hw->ifs_min_val = IFS_MIN;
6439 hw->ifs_max_val = IFS_MAX;
6440 hw->ifs_step_size = IFS_STEP;
6441 hw->ifs_ratio = IFS_RATIO;
6442 }
6443 hw->in_ifs_mode = FALSE;
6444 E1000_WRITE_REG(hw, AIT, 0);
6445 } else {
6446 DEBUGOUT("Not in Adaptive IFS mode!\n");
6447 }
6448 }
6449
6450 /******************************************************************************
6451 * Called during the callback/watchdog routine to update IFS value based on
6452 * the ratio of transmits to collisions.
6453 *
6454 * hw - Struct containing variables accessed by shared code
6455 * tx_packets - Number of transmits since last callback
6456 * total_collisions - Number of collisions since last callback
6457 *****************************************************************************/
6458 void
e1000_update_adaptive(struct e1000_hw * hw)6459 e1000_update_adaptive(struct e1000_hw *hw)
6460 {
6461 DEBUGFUNC("e1000_update_adaptive");
6462
6463 if (hw->adaptive_ifs) {
6464 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6465 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6466 hw->in_ifs_mode = TRUE;
6467 if (hw->current_ifs_val < hw->ifs_max_val) {
6468 if (hw->current_ifs_val == 0)
6469 hw->current_ifs_val = hw->ifs_min_val;
6470 else
6471 hw->current_ifs_val += hw->ifs_step_size;
6472 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6473 }
6474 }
6475 } else {
6476 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6477 hw->current_ifs_val = 0;
6478 hw->in_ifs_mode = FALSE;
6479 E1000_WRITE_REG(hw, AIT, 0);
6480 }
6481 }
6482 } else {
6483 DEBUGOUT("Not in Adaptive IFS mode!\n");
6484 }
6485 }
6486
6487 /******************************************************************************
6488 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6489 *
6490 * hw - Struct containing variables accessed by shared code
6491 * frame_len - The length of the frame in question
6492 * mac_addr - The Ethernet destination address of the frame in question
6493 *****************************************************************************/
6494 void
e1000_tbi_adjust_stats(struct e1000_hw * hw,struct e1000_hw_stats * stats,uint32_t frame_len,uint8_t * mac_addr)6495 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6496 struct e1000_hw_stats *stats,
6497 uint32_t frame_len,
6498 uint8_t *mac_addr)
6499 {
6500 uint64_t carry_bit;
6501
6502 /* First adjust the frame length. */
6503 frame_len--;
6504 /* We need to adjust the statistics counters, since the hardware
6505 * counters overcount this packet as a CRC error and undercount
6506 * the packet as a good packet
6507 */
6508 /* This packet should not be counted as a CRC error. */
6509 stats->crcerrs--;
6510 /* This packet does count as a Good Packet Received. */
6511 stats->gprc++;
6512
6513 /* Adjust the Good Octets received counters */
6514 carry_bit = 0x80000000 & stats->gorcl;
6515 stats->gorcl += frame_len;
6516 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6517 * Received Count) was one before the addition,
6518 * AND it is zero after, then we lost the carry out,
6519 * need to add one to Gorch (Good Octets Received Count High).
6520 * This could be simplified if all environments supported
6521 * 64-bit integers.
6522 */
6523 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6524 stats->gorch++;
6525 /* Is this a broadcast or multicast? Check broadcast first,
6526 * since the test for a multicast frame will test positive on
6527 * a broadcast frame.
6528 */
6529 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6530 /* Broadcast packet */
6531 stats->bprc++;
6532 else if (*mac_addr & 0x01)
6533 /* Multicast packet */
6534 stats->mprc++;
6535
6536 if (frame_len == hw->max_frame_size) {
6537 /* In this case, the hardware has overcounted the number of
6538 * oversize frames.
6539 */
6540 if (stats->roc > 0)
6541 stats->roc--;
6542 }
6543
6544 /* Adjust the bin counters when the extra byte put the frame in the
6545 * wrong bin. Remember that the frame_len was adjusted above.
6546 */
6547 if (frame_len == 64) {
6548 stats->prc64++;
6549 stats->prc127--;
6550 } else if (frame_len == 127) {
6551 stats->prc127++;
6552 stats->prc255--;
6553 } else if (frame_len == 255) {
6554 stats->prc255++;
6555 stats->prc511--;
6556 } else if (frame_len == 511) {
6557 stats->prc511++;
6558 stats->prc1023--;
6559 } else if (frame_len == 1023) {
6560 stats->prc1023++;
6561 stats->prc1522--;
6562 } else if (frame_len == 1522) {
6563 stats->prc1522++;
6564 }
6565 }
6566
6567 /******************************************************************************
6568 * Gets the current PCI bus type, speed, and width of the hardware
6569 *
6570 * hw - Struct containing variables accessed by shared code
6571 *****************************************************************************/
6572 void
e1000_get_bus_info(struct e1000_hw * hw)6573 e1000_get_bus_info(struct e1000_hw *hw)
6574 {
6575 int32_t ret_val;
6576 uint16_t pci_ex_link_status;
6577 uint32_t status;
6578
6579 switch (hw->mac_type) {
6580 case e1000_82542_rev2_0:
6581 case e1000_82542_rev2_1:
6582 hw->bus_type = e1000_bus_type_pci;
6583 hw->bus_speed = e1000_bus_speed_unknown;
6584 hw->bus_width = e1000_bus_width_unknown;
6585 break;
6586 case e1000_82571:
6587 case e1000_82572:
6588 case e1000_82573:
6589 case e1000_80003es2lan:
6590 hw->bus_type = e1000_bus_type_pci_express;
6591 hw->bus_speed = e1000_bus_speed_2500;
6592 ret_val = e1000_read_pcie_cap_reg(hw,
6593 PCI_EX_LINK_STATUS,
6594 &pci_ex_link_status);
6595 if (ret_val)
6596 hw->bus_width = e1000_bus_width_unknown;
6597 else
6598 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6599 PCI_EX_LINK_WIDTH_SHIFT;
6600 break;
6601 case e1000_ich8lan:
6602
6603 hw->bus_type = e1000_bus_type_pci_express;
6604 hw->bus_speed = e1000_bus_speed_2500;
6605 hw->bus_width = e1000_bus_width_pciex_1;
6606 break;
6607 default:
6608 status = E1000_READ_REG(hw, STATUS);
6609 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6610 e1000_bus_type_pcix : e1000_bus_type_pci;
6611
6612 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6613 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6614 e1000_bus_speed_66 : e1000_bus_speed_120;
6615 } else if (hw->bus_type == e1000_bus_type_pci) {
6616 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6617 e1000_bus_speed_66 : e1000_bus_speed_33;
6618 } else {
6619 switch (status & E1000_STATUS_PCIX_SPEED) {
6620 case E1000_STATUS_PCIX_SPEED_66:
6621 hw->bus_speed = e1000_bus_speed_66;
6622 break;
6623 case E1000_STATUS_PCIX_SPEED_100:
6624 hw->bus_speed = e1000_bus_speed_100;
6625 break;
6626 case E1000_STATUS_PCIX_SPEED_133:
6627 hw->bus_speed = e1000_bus_speed_133;
6628 break;
6629 default:
6630 hw->bus_speed = e1000_bus_speed_reserved;
6631 break;
6632 }
6633 }
6634 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6635 e1000_bus_width_64 : e1000_bus_width_32;
6636 break;
6637 }
6638 }
6639
6640 /******************************************************************************
6641 * Writes a value to one of the devices registers using port I/O (as opposed to
6642 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6643 *
6644 * hw - Struct containing variables accessed by shared code
6645 * offset - offset to write to
6646 * value - value to write
6647 *****************************************************************************/
6648 static void
e1000_write_reg_io(struct e1000_hw * hw,uint32_t offset,uint32_t value)6649 e1000_write_reg_io(struct e1000_hw *hw,
6650 uint32_t offset,
6651 uint32_t value)
6652 {
6653 unsigned long io_addr = hw->io_base;
6654 unsigned long io_data = hw->io_base + 4;
6655
6656 e1000_io_write(hw, io_addr, offset);
6657 e1000_io_write(hw, io_data, value);
6658 }
6659
6660 /******************************************************************************
6661 * Estimates the cable length.
6662 *
6663 * hw - Struct containing variables accessed by shared code
6664 * min_length - The estimated minimum length
6665 * max_length - The estimated maximum length
6666 *
6667 * returns: - E1000_ERR_XXX
6668 * E1000_SUCCESS
6669 *
6670 * This function always returns a ranged length (minimum & maximum).
6671 * So for M88 phy's, this function interprets the one value returned from the
6672 * register to the minimum and maximum range.
6673 * For IGP phy's, the function calculates the range by the AGC registers.
6674 *****************************************************************************/
6675 static int32_t
e1000_get_cable_length(struct e1000_hw * hw,uint16_t * min_length,uint16_t * max_length)6676 e1000_get_cable_length(struct e1000_hw *hw,
6677 uint16_t *min_length,
6678 uint16_t *max_length)
6679 {
6680 int32_t ret_val;
6681 uint16_t agc_value = 0;
6682 uint16_t i, phy_data;
6683 uint16_t cable_length;
6684
6685 DEBUGFUNC("e1000_get_cable_length");
6686
6687 *min_length = *max_length = 0;
6688
6689 /* Use old method for Phy older than IGP */
6690 if (hw->phy_type == e1000_phy_m88) {
6691
6692 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6693 &phy_data);
6694 if (ret_val)
6695 return ret_val;
6696 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6697 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6698
6699 /* Convert the enum value to ranged values */
6700 switch (cable_length) {
6701 case e1000_cable_length_50:
6702 *min_length = 0;
6703 *max_length = e1000_igp_cable_length_50;
6704 break;
6705 case e1000_cable_length_50_80:
6706 *min_length = e1000_igp_cable_length_50;
6707 *max_length = e1000_igp_cable_length_80;
6708 break;
6709 case e1000_cable_length_80_110:
6710 *min_length = e1000_igp_cable_length_80;
6711 *max_length = e1000_igp_cable_length_110;
6712 break;
6713 case e1000_cable_length_110_140:
6714 *min_length = e1000_igp_cable_length_110;
6715 *max_length = e1000_igp_cable_length_140;
6716 break;
6717 case e1000_cable_length_140:
6718 *min_length = e1000_igp_cable_length_140;
6719 *max_length = e1000_igp_cable_length_170;
6720 break;
6721 default:
6722 return -E1000_ERR_PHY;
6723 break;
6724 }
6725 } else if (hw->phy_type == e1000_phy_gg82563) {
6726 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6727 &phy_data);
6728 if (ret_val)
6729 return ret_val;
6730 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6731
6732 switch (cable_length) {
6733 case e1000_gg_cable_length_60:
6734 *min_length = 0;
6735 *max_length = e1000_igp_cable_length_60;
6736 break;
6737 case e1000_gg_cable_length_60_115:
6738 *min_length = e1000_igp_cable_length_60;
6739 *max_length = e1000_igp_cable_length_115;
6740 break;
6741 case e1000_gg_cable_length_115_150:
6742 *min_length = e1000_igp_cable_length_115;
6743 *max_length = e1000_igp_cable_length_150;
6744 break;
6745 case e1000_gg_cable_length_150:
6746 *min_length = e1000_igp_cable_length_150;
6747 *max_length = e1000_igp_cable_length_180;
6748 break;
6749 default:
6750 return -E1000_ERR_PHY;
6751 break;
6752 }
6753 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6754 uint16_t cur_agc_value;
6755 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6756 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6757 {IGP01E1000_PHY_AGC_A,
6758 IGP01E1000_PHY_AGC_B,
6759 IGP01E1000_PHY_AGC_C,
6760 IGP01E1000_PHY_AGC_D};
6761 /* Read the AGC registers for all channels */
6762 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6763
6764 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6765 if (ret_val)
6766 return ret_val;
6767
6768 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6769
6770 /* Value bound check. */
6771 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6772 (cur_agc_value == 0))
6773 return -E1000_ERR_PHY;
6774
6775 agc_value += cur_agc_value;
6776
6777 /* Update minimal AGC value. */
6778 if (min_agc_value > cur_agc_value)
6779 min_agc_value = cur_agc_value;
6780 }
6781
6782 /* Remove the minimal AGC result for length < 50m */
6783 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6784 agc_value -= min_agc_value;
6785
6786 /* Get the average length of the remaining 3 channels */
6787 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6788 } else {
6789 /* Get the average length of all the 4 channels. */
6790 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6791 }
6792
6793 /* Set the range of the calculated length. */
6794 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6795 IGP01E1000_AGC_RANGE) > 0) ?
6796 (e1000_igp_cable_length_table[agc_value] -
6797 IGP01E1000_AGC_RANGE) : 0;
6798 *max_length = e1000_igp_cable_length_table[agc_value] +
6799 IGP01E1000_AGC_RANGE;
6800 } else if (hw->phy_type == e1000_phy_igp_2 ||
6801 hw->phy_type == e1000_phy_igp_3) {
6802 uint16_t cur_agc_index, max_agc_index = 0;
6803 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6804 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6805 {IGP02E1000_PHY_AGC_A,
6806 IGP02E1000_PHY_AGC_B,
6807 IGP02E1000_PHY_AGC_C,
6808 IGP02E1000_PHY_AGC_D};
6809 /* Read the AGC registers for all channels */
6810 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6811 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6812 if (ret_val)
6813 return ret_val;
6814
6815 /* Getting bits 15:9, which represent the combination of course and
6816 * fine gain values. The result is a number that can be put into
6817 * the lookup table to obtain the approximate cable length. */
6818 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6819 IGP02E1000_AGC_LENGTH_MASK;
6820
6821 /* Array index bound check. */
6822 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6823 (cur_agc_index == 0))
6824 return -E1000_ERR_PHY;
6825
6826 /* Remove min & max AGC values from calculation. */
6827 if (e1000_igp_2_cable_length_table[min_agc_index] >
6828 e1000_igp_2_cable_length_table[cur_agc_index])
6829 min_agc_index = cur_agc_index;
6830 if (e1000_igp_2_cable_length_table[max_agc_index] <
6831 e1000_igp_2_cable_length_table[cur_agc_index])
6832 max_agc_index = cur_agc_index;
6833
6834 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6835 }
6836
6837 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6838 e1000_igp_2_cable_length_table[max_agc_index]);
6839 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6840
6841 /* Calculate cable length with the error range of +/- 10 meters. */
6842 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6843 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6844 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6845 }
6846
6847 return E1000_SUCCESS;
6848 }
6849
6850 /******************************************************************************
6851 * Check the cable polarity
6852 *
6853 * hw - Struct containing variables accessed by shared code
6854 * polarity - output parameter : 0 - Polarity is not reversed
6855 * 1 - Polarity is reversed.
6856 *
6857 * returns: - E1000_ERR_XXX
6858 * E1000_SUCCESS
6859 *
6860 * For phy's older then IGP, this function simply reads the polarity bit in the
6861 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6862 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6864 * IGP01E1000_PHY_PCS_INIT_REG.
6865 *****************************************************************************/
6866 static int32_t
e1000_check_polarity(struct e1000_hw * hw,e1000_rev_polarity * polarity)6867 e1000_check_polarity(struct e1000_hw *hw,
6868 e1000_rev_polarity *polarity)
6869 {
6870 int32_t ret_val;
6871 uint16_t phy_data;
6872
6873 DEBUGFUNC("e1000_check_polarity");
6874
6875 if ((hw->phy_type == e1000_phy_m88) ||
6876 (hw->phy_type == e1000_phy_gg82563)) {
6877 /* return the Polarity bit in the Status register. */
6878 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6879 &phy_data);
6880 if (ret_val)
6881 return ret_val;
6882 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6883 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6884 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6885
6886 } else if (hw->phy_type == e1000_phy_igp ||
6887 hw->phy_type == e1000_phy_igp_3 ||
6888 hw->phy_type == e1000_phy_igp_2) {
6889 /* Read the Status register to check the speed */
6890 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6891 &phy_data);
6892 if (ret_val)
6893 return ret_val;
6894
6895 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6896 * find the polarity status */
6897 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6898 IGP01E1000_PSSR_SPEED_1000MBPS) {
6899
6900 /* Read the GIG initialization PCS register (0x00B4) */
6901 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6902 &phy_data);
6903 if (ret_val)
6904 return ret_val;
6905
6906 /* Check the polarity bits */
6907 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6908 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6909 } else {
6910 /* For 10 Mbps, read the polarity bit in the status register. (for
6911 * 100 Mbps this bit is always 0) */
6912 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6913 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6914 }
6915 } else if (hw->phy_type == e1000_phy_ife) {
6916 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6917 &phy_data);
6918 if (ret_val)
6919 return ret_val;
6920 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6921 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6922 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6923 }
6924 return E1000_SUCCESS;
6925 }
6926
6927 /******************************************************************************
6928 * Check if Downshift occured
6929 *
6930 * hw - Struct containing variables accessed by shared code
6931 * downshift - output parameter : 0 - No Downshift ocured.
6932 * 1 - Downshift ocured.
6933 *
6934 * returns: - E1000_ERR_XXX
6935 * E1000_SUCCESS
6936 *
6937 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6938 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6939 * Link Health register. In IGP this bit is latched high, so the driver must
6940 * read it immediately after link is established.
6941 *****************************************************************************/
6942 static int32_t
e1000_check_downshift(struct e1000_hw * hw)6943 e1000_check_downshift(struct e1000_hw *hw)
6944 {
6945 int32_t ret_val;
6946 uint16_t phy_data;
6947
6948 DEBUGFUNC("e1000_check_downshift");
6949
6950 if (hw->phy_type == e1000_phy_igp ||
6951 hw->phy_type == e1000_phy_igp_3 ||
6952 hw->phy_type == e1000_phy_igp_2) {
6953 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6954 &phy_data);
6955 if (ret_val)
6956 return ret_val;
6957
6958 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6959 } else if ((hw->phy_type == e1000_phy_m88) ||
6960 (hw->phy_type == e1000_phy_gg82563)) {
6961 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6962 &phy_data);
6963 if (ret_val)
6964 return ret_val;
6965
6966 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6967 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6968 } else if (hw->phy_type == e1000_phy_ife) {
6969 /* e1000_phy_ife supports 10/100 speed only */
6970 hw->speed_downgraded = FALSE;
6971 }
6972
6973 return E1000_SUCCESS;
6974 }
6975
6976 /*****************************************************************************
6977 *
6978 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6979 * gigabit link is achieved to improve link quality.
6980 *
6981 * hw: Struct containing variables accessed by shared code
6982 *
6983 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6984 * E1000_SUCCESS at any other case.
6985 *
6986 ****************************************************************************/
6987
6988 static int32_t
e1000_config_dsp_after_link_change(struct e1000_hw * hw,boolean_t link_up)6989 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6990 boolean_t link_up)
6991 {
6992 int32_t ret_val;
6993 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6994 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6995 {IGP01E1000_PHY_AGC_PARAM_A,
6996 IGP01E1000_PHY_AGC_PARAM_B,
6997 IGP01E1000_PHY_AGC_PARAM_C,
6998 IGP01E1000_PHY_AGC_PARAM_D};
6999 uint16_t min_length, max_length;
7000
7001 DEBUGFUNC("e1000_config_dsp_after_link_change");
7002
7003 if (hw->phy_type != e1000_phy_igp)
7004 return E1000_SUCCESS;
7005
7006 if (link_up) {
7007 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7008 if (ret_val) {
7009 DEBUGOUT("Error getting link speed and duplex\n");
7010 return ret_val;
7011 }
7012
7013 if (speed == SPEED_1000) {
7014
7015 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7016 if (ret_val)
7017 return ret_val;
7018
7019 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7020 min_length >= e1000_igp_cable_length_50) {
7021
7022 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7023 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7024 &phy_data);
7025 if (ret_val)
7026 return ret_val;
7027
7028 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7029
7030 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7031 phy_data);
7032 if (ret_val)
7033 return ret_val;
7034 }
7035 hw->dsp_config_state = e1000_dsp_config_activated;
7036 }
7037
7038 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7039 (min_length < e1000_igp_cable_length_50)) {
7040
7041 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7042 uint32_t idle_errs = 0;
7043
7044 /* clear previous idle error counts */
7045 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7046 &phy_data);
7047 if (ret_val)
7048 return ret_val;
7049
7050 for (i = 0; i < ffe_idle_err_timeout; i++) {
7051 usec_delay(1000);
7052 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7053 &phy_data);
7054 if (ret_val)
7055 return ret_val;
7056
7057 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7058 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7059 hw->ffe_config_state = e1000_ffe_config_active;
7060
7061 ret_val = e1000_write_phy_reg(hw,
7062 IGP01E1000_PHY_DSP_FFE,
7063 IGP01E1000_PHY_DSP_FFE_CM_CP);
7064 if (ret_val)
7065 return ret_val;
7066 break;
7067 }
7068
7069 if (idle_errs)
7070 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7071 }
7072 }
7073 }
7074 } else {
7075 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7076 /* Save off the current value of register 0x2F5B to be restored at
7077 * the end of the routines. */
7078 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7079
7080 if (ret_val)
7081 return ret_val;
7082
7083 /* Disable the PHY transmitter */
7084 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7085
7086 if (ret_val)
7087 return ret_val;
7088
7089 msec_delay_irq(20);
7090
7091 ret_val = e1000_write_phy_reg(hw, 0x0000,
7092 IGP01E1000_IEEE_FORCE_GIGA);
7093 if (ret_val)
7094 return ret_val;
7095 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7096 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7097 if (ret_val)
7098 return ret_val;
7099
7100 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7101 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7102
7103 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7104 if (ret_val)
7105 return ret_val;
7106 }
7107
7108 ret_val = e1000_write_phy_reg(hw, 0x0000,
7109 IGP01E1000_IEEE_RESTART_AUTONEG);
7110 if (ret_val)
7111 return ret_val;
7112
7113 msec_delay_irq(20);
7114
7115 /* Now enable the transmitter */
7116 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7117
7118 if (ret_val)
7119 return ret_val;
7120
7121 hw->dsp_config_state = e1000_dsp_config_enabled;
7122 }
7123
7124 if (hw->ffe_config_state == e1000_ffe_config_active) {
7125 /* Save off the current value of register 0x2F5B to be restored at
7126 * the end of the routines. */
7127 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7128
7129 if (ret_val)
7130 return ret_val;
7131
7132 /* Disable the PHY transmitter */
7133 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7134
7135 if (ret_val)
7136 return ret_val;
7137
7138 msec_delay_irq(20);
7139
7140 ret_val = e1000_write_phy_reg(hw, 0x0000,
7141 IGP01E1000_IEEE_FORCE_GIGA);
7142 if (ret_val)
7143 return ret_val;
7144 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7145 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7146 if (ret_val)
7147 return ret_val;
7148
7149 ret_val = e1000_write_phy_reg(hw, 0x0000,
7150 IGP01E1000_IEEE_RESTART_AUTONEG);
7151 if (ret_val)
7152 return ret_val;
7153
7154 msec_delay_irq(20);
7155
7156 /* Now enable the transmitter */
7157 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7158
7159 if (ret_val)
7160 return ret_val;
7161
7162 hw->ffe_config_state = e1000_ffe_config_enabled;
7163 }
7164 }
7165 return E1000_SUCCESS;
7166 }
7167
7168 /*****************************************************************************
7169 * Set PHY to class A mode
7170 * Assumes the following operations will follow to enable the new class mode.
7171 * 1. Do a PHY soft reset
7172 * 2. Restart auto-negotiation or force link.
7173 *
7174 * hw - Struct containing variables accessed by shared code
7175 ****************************************************************************/
7176 static int32_t
e1000_set_phy_mode(struct e1000_hw * hw)7177 e1000_set_phy_mode(struct e1000_hw *hw)
7178 {
7179 int32_t ret_val;
7180 uint16_t eeprom_data;
7181
7182 DEBUGFUNC("e1000_set_phy_mode");
7183
7184 if ((hw->mac_type == e1000_82545_rev_3) &&
7185 (hw->media_type == e1000_media_type_copper)) {
7186 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7187 if (ret_val) {
7188 return ret_val;
7189 }
7190
7191 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7192 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7193 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7194 if (ret_val)
7195 return ret_val;
7196 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7197 if (ret_val)
7198 return ret_val;
7199
7200 hw->phy_reset_disable = FALSE;
7201 }
7202 }
7203
7204 return E1000_SUCCESS;
7205 }
7206
7207 /*****************************************************************************
7208 *
7209 * This function sets the lplu state according to the active flag. When
7210 * activating lplu this function also disables smart speed and vise versa.
7211 * lplu will not be activated unless the device autonegotiation advertisment
7212 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7213 * hw: Struct containing variables accessed by shared code
7214 * active - true to enable lplu false to disable lplu.
7215 *
7216 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7217 * E1000_SUCCESS at any other case.
7218 *
7219 ****************************************************************************/
7220
7221 static int32_t
e1000_set_d3_lplu_state(struct e1000_hw * hw,boolean_t active)7222 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7223 boolean_t active)
7224 {
7225 uint32_t phy_ctrl = 0;
7226 int32_t ret_val;
7227 uint16_t phy_data;
7228 DEBUGFUNC("e1000_set_d3_lplu_state");
7229
7230 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7231 && hw->phy_type != e1000_phy_igp_3)
7232 return E1000_SUCCESS;
7233
7234 /* During driver activity LPLU should not be used or it will attain link
7235 * from the lowest speeds starting from 10Mbps. The capability is used for
7236 * Dx transitions and states */
7237 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7238 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7239 if (ret_val)
7240 return ret_val;
7241 } else if (hw->is_ich == TRUE) {
7242 /* MAC writes into PHY register based on the state transition
7243 * and start auto-negotiation. SW driver can overwrite the settings
7244 * in CSR PHY power control E1000_PHY_CTRL register. */
7245 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7246 } else {
7247 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7248 if (ret_val)
7249 return ret_val;
7250 }
7251
7252 if (!active) {
7253 if (hw->mac_type == e1000_82541_rev_2 ||
7254 hw->mac_type == e1000_82547_rev_2) {
7255 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7256 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7257 if (ret_val)
7258 return ret_val;
7259 } else {
7260 if (hw->is_ich == TRUE) {
7261 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7262 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7263 } else {
7264 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7265 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7266 phy_data);
7267 if (ret_val)
7268 return ret_val;
7269 }
7270 }
7271
7272 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7273 * Dx states where the power conservation is most important. During
7274 * driver activity we should enable SmartSpeed, so performance is
7275 * maintained. */
7276 if (hw->smart_speed == e1000_smart_speed_on) {
7277 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7278 &phy_data);
7279 if (ret_val)
7280 return ret_val;
7281
7282 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7283 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7284 phy_data);
7285 if (ret_val)
7286 return ret_val;
7287 } else if (hw->smart_speed == e1000_smart_speed_off) {
7288 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7289 &phy_data);
7290 if (ret_val)
7291 return ret_val;
7292
7293 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7294 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7295 phy_data);
7296 if (ret_val)
7297 return ret_val;
7298 }
7299
7300 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7301 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7302 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7303
7304 if (hw->mac_type == e1000_82541_rev_2 ||
7305 hw->mac_type == e1000_82547_rev_2) {
7306 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7307 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7308 if (ret_val)
7309 return ret_val;
7310 } else {
7311 if (hw->is_ich == TRUE) {
7312 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7313 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7314 } else {
7315 phy_data |= IGP02E1000_PM_D3_LPLU;
7316 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7317 phy_data);
7318 if (ret_val)
7319 return ret_val;
7320 }
7321 }
7322
7323 /* When LPLU is enabled we should disable SmartSpeed */
7324 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7325 if (ret_val)
7326 return ret_val;
7327
7328 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7329 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7330 if (ret_val)
7331 return ret_val;
7332
7333 }
7334 return E1000_SUCCESS;
7335 }
7336
7337 /*****************************************************************************
7338 *
7339 * This function sets the lplu d0 state according to the active flag. When
7340 * activating lplu this function also disables smart speed and vise versa.
7341 * lplu will not be activated unless the device autonegotiation advertisment
7342 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7343 * hw: Struct containing variables accessed by shared code
7344 * active - true to enable lplu false to disable lplu.
7345 *
7346 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7347 * E1000_SUCCESS at any other case.
7348 *
7349 ****************************************************************************/
7350
7351 static int32_t
e1000_set_d0_lplu_state(struct e1000_hw * hw,boolean_t active)7352 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7353 boolean_t active)
7354 {
7355 uint32_t phy_ctrl = 0;
7356 int32_t ret_val;
7357 uint16_t phy_data;
7358 DEBUGFUNC("e1000_set_d0_lplu_state");
7359
7360 if (hw->mac_type <= e1000_82547_rev_2)
7361 return E1000_SUCCESS;
7362
7363 if (hw->is_ich == TRUE) {
7364 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7365 } else {
7366 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7367 if (ret_val)
7368 return ret_val;
7369 }
7370
7371 if (!active) {
7372 if (hw->is_ich == TRUE) {
7373 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7374 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7375 } else {
7376 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7377 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7378 if (ret_val)
7379 return ret_val;
7380 }
7381
7382 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7383 * Dx states where the power conservation is most important. During
7384 * driver activity we should enable SmartSpeed, so performance is
7385 * maintained. */
7386 if (hw->smart_speed == e1000_smart_speed_on) {
7387 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7388 &phy_data);
7389 if (ret_val)
7390 return ret_val;
7391
7392 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7393 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7394 phy_data);
7395 if (ret_val)
7396 return ret_val;
7397 } else if (hw->smart_speed == e1000_smart_speed_off) {
7398 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7399 &phy_data);
7400 if (ret_val)
7401 return ret_val;
7402
7403 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7404 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7405 phy_data);
7406 if (ret_val)
7407 return ret_val;
7408 }
7409
7410
7411 } else {
7412
7413 if (hw->is_ich == TRUE) {
7414 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7415 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7416 } else {
7417 phy_data |= IGP02E1000_PM_D0_LPLU;
7418 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7419 if (ret_val)
7420 return ret_val;
7421 }
7422
7423 /* When LPLU is enabled we should disable SmartSpeed */
7424 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7425 if (ret_val)
7426 return ret_val;
7427
7428 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7429 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7430 if (ret_val)
7431 return ret_val;
7432
7433 }
7434 return E1000_SUCCESS;
7435 }
7436
7437 /******************************************************************************
7438 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7439 *
7440 * hw - Struct containing variables accessed by shared code
7441 *****************************************************************************/
7442 static int32_t
e1000_set_vco_speed(struct e1000_hw * hw)7443 e1000_set_vco_speed(struct e1000_hw *hw)
7444 {
7445 int32_t ret_val;
7446 uint16_t default_page = 0;
7447 uint16_t phy_data;
7448
7449 DEBUGFUNC("e1000_set_vco_speed");
7450
7451 switch (hw->mac_type) {
7452 case e1000_82545_rev_3:
7453 case e1000_82546_rev_3:
7454 break;
7455 default:
7456 return E1000_SUCCESS;
7457 }
7458
7459 /* Set PHY register 30, page 5, bit 8 to 0 */
7460
7461 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7462 if (ret_val)
7463 return ret_val;
7464
7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7466 if (ret_val)
7467 return ret_val;
7468
7469 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7470 if (ret_val)
7471 return ret_val;
7472
7473 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7474 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7475 if (ret_val)
7476 return ret_val;
7477
7478 /* Set PHY register 30, page 4, bit 11 to 1 */
7479
7480 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7481 if (ret_val)
7482 return ret_val;
7483
7484 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7485 if (ret_val)
7486 return ret_val;
7487
7488 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7489 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7490 if (ret_val)
7491 return ret_val;
7492
7493 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7494 if (ret_val)
7495 return ret_val;
7496
7497 return E1000_SUCCESS;
7498 }
7499
7500
7501 /*****************************************************************************
7502 * This function reads the cookie from ARC ram.
7503 *
7504 * returns: - E1000_SUCCESS .
7505 ****************************************************************************/
7506 static int32_t
e1000_host_if_read_cookie(struct e1000_hw * hw,uint8_t * buffer)7507 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7508 {
7509 uint8_t i;
7510 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7511 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7512
7513 length = (length >> 2);
7514 offset = (offset >> 2);
7515
7516 for (i = 0; i < length; i++) {
7517 *((uint32_t *) buffer + i) =
7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7519 }
7520 return E1000_SUCCESS;
7521 }
7522
7523
7524 /*****************************************************************************
7525 * This function checks whether the HOST IF is enabled for command operaton
7526 * and also checks whether the previous command is completed.
7527 * It busy waits in case of previous command is not completed.
7528 *
7529 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7530 * timeout
7531 * - E1000_SUCCESS for success.
7532 ****************************************************************************/
7533 static int32_t
e1000_mng_enable_host_if(struct e1000_hw * hw)7534 e1000_mng_enable_host_if(struct e1000_hw * hw)
7535 {
7536 uint32_t hicr;
7537 uint8_t i;
7538
7539 /* Check that the host interface is enabled. */
7540 hicr = E1000_READ_REG(hw, HICR);
7541 if ((hicr & E1000_HICR_EN) == 0) {
7542 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7543 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7544 }
7545 /* check the previous command is completed */
7546 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7547 hicr = E1000_READ_REG(hw, HICR);
7548 if (!(hicr & E1000_HICR_C))
7549 break;
7550 msec_delay_irq(1);
7551 }
7552
7553 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7554 DEBUGOUT("Previous command timeout failed .\n");
7555 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7556 }
7557 return E1000_SUCCESS;
7558 }
7559
7560 /*****************************************************************************
7561 * This function writes the buffer content at the offset given on the host if.
7562 * It also does alignment considerations to do the writes in most efficient way.
7563 * Also fills up the sum of the buffer in *buffer parameter.
7564 *
7565 * returns - E1000_SUCCESS for success.
7566 ****************************************************************************/
7567 static int32_t
e1000_mng_host_if_write(struct e1000_hw * hw,uint8_t * buffer,uint16_t length,uint16_t offset,uint8_t * sum)7568 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7569 uint16_t length, uint16_t offset, uint8_t *sum)
7570 {
7571 uint8_t *tmp;
7572 uint8_t *bufptr = buffer;
7573 uint32_t data = 0;
7574 uint16_t remaining, i, j, prev_bytes;
7575
7576 /* sum = only sum of the data and it is not checksum */
7577
7578 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7579 return -E1000_ERR_PARAM;
7580 }
7581
7582 tmp = (uint8_t *)&data;
7583 prev_bytes = offset & 0x3;
7584 offset &= 0xFFFC;
7585 offset >>= 2;
7586
7587 if (prev_bytes) {
7588 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7589 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7590 *(tmp + j) = *bufptr++;
7591 *sum += *(tmp + j);
7592 }
7593 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7594 length -= j - prev_bytes;
7595 offset++;
7596 }
7597
7598 remaining = length & 0x3;
7599 length -= remaining;
7600
7601 /* Calculate length in DWORDs */
7602 length >>= 2;
7603
7604 /* The device driver writes the relevant command block into the
7605 * ram area. */
7606 for (i = 0; i < length; i++) {
7607 for (j = 0; j < sizeof(uint32_t); j++) {
7608 *(tmp + j) = *bufptr++;
7609 *sum += *(tmp + j);
7610 }
7611
7612 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7613 }
7614 if (remaining) {
7615 for (j = 0; j < sizeof(uint32_t); j++) {
7616 if (j < remaining)
7617 *(tmp + j) = *bufptr++;
7618 else
7619 *(tmp + j) = 0;
7620
7621 *sum += *(tmp + j);
7622 }
7623 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7624 }
7625
7626 return E1000_SUCCESS;
7627 }
7628
7629
7630 /*****************************************************************************
7631 * This function writes the command header after does the checksum calculation.
7632 *
7633 * returns - E1000_SUCCESS for success.
7634 ****************************************************************************/
7635 static int32_t
e1000_mng_write_cmd_header(struct e1000_hw * hw,struct e1000_host_mng_command_header * hdr)7636 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7637 struct e1000_host_mng_command_header * hdr)
7638 {
7639 uint16_t i;
7640 uint8_t sum;
7641 uint8_t *buffer;
7642
7643 /* Write the whole command header structure which includes sum of
7644 * the buffer */
7645
7646 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7647
7648 sum = hdr->checksum;
7649 hdr->checksum = 0;
7650
7651 buffer = (uint8_t *) hdr;
7652 i = length;
7653 while (i--)
7654 sum += buffer[i];
7655
7656 hdr->checksum = 0 - sum;
7657
7658 length >>= 2;
7659 /* The device driver writes the relevant command block into the ram area. */
7660 for (i = 0; i < length; i++) {
7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7662 E1000_WRITE_FLUSH(hw);
7663 }
7664
7665 return E1000_SUCCESS;
7666 }
7667
7668
7669 /*****************************************************************************
7670 * This function indicates to ARC that a new command is pending which completes
7671 * one write operation by the driver.
7672 *
7673 * returns - E1000_SUCCESS for success.
7674 ****************************************************************************/
7675 static int32_t
e1000_mng_write_commit(struct e1000_hw * hw)7676 e1000_mng_write_commit(struct e1000_hw * hw)
7677 {
7678 uint32_t hicr;
7679
7680 hicr = E1000_READ_REG(hw, HICR);
7681 /* Setting this bit tells the ARC that a new command is pending. */
7682 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7683
7684 return E1000_SUCCESS;
7685 }
7686
7687
7688 /*****************************************************************************
7689 * This function checks the mode of the firmware.
7690 *
7691 * returns - TRUE when the mode is IAMT or FALSE.
7692 ****************************************************************************/
7693 boolean_t
e1000_check_mng_mode(struct e1000_hw * hw)7694 e1000_check_mng_mode(struct e1000_hw *hw)
7695 {
7696 uint32_t fwsm;
7697
7698 fwsm = E1000_READ_REG(hw, FWSM);
7699
7700 if (hw->is_ich == TRUE) {
7701 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7702 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7703 return TRUE;
7704 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7705 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7706 return TRUE;
7707
7708 return FALSE;
7709 }
7710
7711
7712 /*****************************************************************************
7713 * This function writes the dhcp info .
7714 ****************************************************************************/
7715 int32_t
e1000_mng_write_dhcp_info(struct e1000_hw * hw,uint8_t * buffer,uint16_t length)7716 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7717 uint16_t length)
7718 {
7719 int32_t ret_val;
7720 struct e1000_host_mng_command_header hdr;
7721
7722 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7723 hdr.command_length = length;
7724 hdr.reserved1 = 0;
7725 hdr.reserved2 = 0;
7726 hdr.checksum = 0;
7727
7728 ret_val = e1000_mng_enable_host_if(hw);
7729 if (ret_val == E1000_SUCCESS) {
7730 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7731 &(hdr.checksum));
7732 if (ret_val == E1000_SUCCESS) {
7733 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7734 if (ret_val == E1000_SUCCESS)
7735 ret_val = e1000_mng_write_commit(hw);
7736 }
7737 }
7738 return ret_val;
7739 }
7740
7741
7742 /*****************************************************************************
7743 * This function calculates the checksum.
7744 *
7745 * returns - checksum of buffer contents.
7746 ****************************************************************************/
7747 static uint8_t
e1000_calculate_mng_checksum(char * buffer,uint32_t length)7748 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7749 {
7750 uint8_t sum = 0;
7751 uint32_t i;
7752
7753 if (!buffer)
7754 return 0;
7755
7756 for (i=0; i < length; i++)
7757 sum += buffer[i];
7758
7759 return (uint8_t) (0 - sum);
7760 }
7761
7762 /*****************************************************************************
7763 * This function checks whether tx pkt filtering needs to be enabled or not.
7764 *
7765 * returns - TRUE for packet filtering or FALSE.
7766 ****************************************************************************/
7767 boolean_t
e1000_enable_tx_pkt_filtering(struct e1000_hw * hw)7768 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7769 {
7770 /* called in init as well as watchdog timer functions */
7771
7772 int32_t ret_val, checksum;
7773 boolean_t tx_filter = FALSE;
7774 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7775 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7776
7777 if (e1000_check_mng_mode(hw)) {
7778 ret_val = e1000_mng_enable_host_if(hw);
7779 if (ret_val == E1000_SUCCESS) {
7780 ret_val = e1000_host_if_read_cookie(hw, buffer);
7781 if (ret_val == E1000_SUCCESS) {
7782 checksum = hdr->checksum;
7783 hdr->checksum = 0;
7784 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7785 checksum == e1000_calculate_mng_checksum((char *)buffer,
7786 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7787 if (hdr->status &
7788 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7789 tx_filter = TRUE;
7790 } else
7791 tx_filter = TRUE;
7792 } else
7793 tx_filter = TRUE;
7794 }
7795 }
7796
7797 hw->tx_pkt_filtering = tx_filter;
7798 return tx_filter;
7799 }
7800
7801 /******************************************************************************
7802 * Verifies the hardware needs to allow ARPs to be processed by the host
7803 *
7804 * hw - Struct containing variables accessed by shared code
7805 *
7806 * returns: - TRUE/FALSE
7807 *
7808 *****************************************************************************/
7809 uint32_t
e1000_enable_mng_pass_thru(struct e1000_hw * hw)7810 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7811 {
7812 uint32_t manc;
7813 uint32_t fwsm, factps;
7814
7815 if (hw->asf_firmware_present) {
7816 manc = E1000_READ_REG(hw, MANC);
7817
7818 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7819 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7820 return FALSE;
7821 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7822 fwsm = E1000_READ_REG(hw, FWSM);
7823 factps = E1000_READ_REG(hw, FACTPS);
7824
7825 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7826 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7827 return TRUE;
7828 } else
7829 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7830 return TRUE;
7831 }
7832 return FALSE;
7833 }
7834
7835 static int32_t
e1000_polarity_reversal_workaround(struct e1000_hw * hw)7836 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7837 {
7838 int32_t ret_val;
7839 uint16_t mii_status_reg;
7840 uint16_t i;
7841
7842 /* Polarity reversal workaround for forced 10F/10H links. */
7843
7844 /* Disable the transmitter on the PHY */
7845
7846 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7847 if (ret_val)
7848 return ret_val;
7849 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7850 if (ret_val)
7851 return ret_val;
7852
7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7854 if (ret_val)
7855 return ret_val;
7856
7857 /* This loop will early-out if the NO link condition has been met. */
7858 for (i = PHY_FORCE_TIME; i > 0; i--) {
7859 /* Read the MII Status Register and wait for Link Status bit
7860 * to be clear.
7861 */
7862
7863 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7864 if (ret_val)
7865 return ret_val;
7866
7867 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7868 if (ret_val)
7869 return ret_val;
7870
7871 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7872 msec_delay_irq(100);
7873 }
7874
7875 /* Recommended delay time after link has been lost */
7876 msec_delay_irq(1000);
7877
7878 /* Now we will re-enable th transmitter on the PHY */
7879
7880 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7881 if (ret_val)
7882 return ret_val;
7883 msec_delay_irq(50);
7884 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7885 if (ret_val)
7886 return ret_val;
7887 msec_delay_irq(50);
7888 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7889 if (ret_val)
7890 return ret_val;
7891 msec_delay_irq(50);
7892 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7893 if (ret_val)
7894 return ret_val;
7895
7896 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7897 if (ret_val)
7898 return ret_val;
7899
7900 /* This loop will early-out if the link condition has been met. */
7901 for (i = PHY_FORCE_TIME; i > 0; i--) {
7902 /* Read the MII Status Register and wait for Link Status bit
7903 * to be set.
7904 */
7905
7906 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7907 if (ret_val)
7908 return ret_val;
7909
7910 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7911 if (ret_val)
7912 return ret_val;
7913
7914 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7915 msec_delay_irq(100);
7916 }
7917 return E1000_SUCCESS;
7918 }
7919
7920 /***************************************************************************
7921 *
7922 * Disables PCI-Express master access.
7923 *
7924 * hw: Struct containing variables accessed by shared code
7925 *
7926 * returns: - none.
7927 *
7928 ***************************************************************************/
7929 static void
e1000_set_pci_express_master_disable(struct e1000_hw * hw)7930 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7931 {
7932 uint32_t ctrl;
7933
7934 DEBUGFUNC("e1000_set_pci_express_master_disable");
7935
7936 if (hw->bus_type != e1000_bus_type_pci_express)
7937 return;
7938
7939 ctrl = E1000_READ_REG(hw, CTRL);
7940 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7941 E1000_WRITE_REG(hw, CTRL, ctrl);
7942 }
7943
7944 /*******************************************************************************
7945 *
7946 * Disables PCI-Express master access and verifies there are no pending requests
7947 *
7948 * hw: Struct containing variables accessed by shared code
7949 *
7950 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7951 * caused the master requests to be disabled.
7952 * E1000_SUCCESS master requests disabled.
7953 *
7954 ******************************************************************************/
7955 int32_t
e1000_disable_pciex_master(struct e1000_hw * hw)7956 e1000_disable_pciex_master(struct e1000_hw *hw)
7957 {
7958 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7959
7960 DEBUGFUNC("e1000_disable_pciex_master");
7961
7962 if (hw->bus_type != e1000_bus_type_pci_express)
7963 return E1000_SUCCESS;
7964
7965 e1000_set_pci_express_master_disable(hw);
7966
7967 while (timeout) {
7968 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7969 break;
7970 else
7971 usec_delay(100);
7972 timeout--;
7973 }
7974
7975 if (!timeout) {
7976 DEBUGOUT("Master requests are pending.\n");
7977 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7978 }
7979
7980 return E1000_SUCCESS;
7981 }
7982
7983 /*******************************************************************************
7984 *
7985 * Check for EEPROM Auto Read bit done.
7986 *
7987 * hw: Struct containing variables accessed by shared code
7988 *
7989 * returns: - E1000_ERR_RESET if fail to reset MAC
7990 * E1000_SUCCESS at any other case.
7991 *
7992 ******************************************************************************/
7993 static int32_t
e1000_get_auto_rd_done(struct e1000_hw * hw)7994 e1000_get_auto_rd_done(struct e1000_hw *hw)
7995 {
7996 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7997
7998 DEBUGFUNC("e1000_get_auto_rd_done");
7999
8000 switch (hw->mac_type) {
8001 default:
8002 msec_delay(5);
8003 break;
8004 case e1000_82571:
8005 case e1000_82572:
8006 case e1000_82573:
8007 case e1000_80003es2lan:
8008 case e1000_ich8lan:
8009 while (timeout) {
8010 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8011 break;
8012 else msec_delay(1);
8013 timeout--;
8014 }
8015
8016 if (!timeout) {
8017 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8018 return -E1000_ERR_RESET;
8019 }
8020 break;
8021 }
8022
8023 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8024 * Need to wait for PHY configuration completion before accessing NVM
8025 * and PHY. */
8026 if (hw->mac_type == e1000_82573)
8027 msec_delay(25);
8028
8029 return E1000_SUCCESS;
8030 }
8031
8032 /***************************************************************************
8033 * Checks if the PHY configuration is done
8034 *
8035 * hw: Struct containing variables accessed by shared code
8036 *
8037 * returns: - E1000_ERR_RESET if fail to reset MAC
8038 * E1000_SUCCESS at any other case.
8039 *
8040 ***************************************************************************/
8041 static int32_t
e1000_get_phy_cfg_done(struct e1000_hw * hw)8042 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8043 {
8044 int32_t timeout = PHY_CFG_TIMEOUT;
8045 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8046
8047 DEBUGFUNC("e1000_get_phy_cfg_done");
8048
8049 switch (hw->mac_type) {
8050 default:
8051 msec_delay_irq(10);
8052 break;
8053 case e1000_80003es2lan:
8054 /* Separate *_CFG_DONE_* bit for each port */
8055 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8056 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8057 /* Fall Through */
8058 case e1000_82571:
8059 case e1000_82572:
8060 while (timeout) {
8061 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8062 break;
8063 else
8064 msec_delay(1);
8065 timeout--;
8066 }
8067 if (!timeout) {
8068 DEBUGOUT("MNG configuration cycle has not completed.\n");
8069 return -E1000_ERR_RESET;
8070 }
8071 break;
8072 }
8073
8074 return E1000_SUCCESS;
8075 }
8076
8077 /***************************************************************************
8078 *
8079 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8080 * adapter or Eeprom access.
8081 *
8082 * hw: Struct containing variables accessed by shared code
8083 *
8084 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8085 * E1000_SUCCESS at any other case.
8086 *
8087 ***************************************************************************/
8088 static int32_t
e1000_get_hw_eeprom_semaphore(struct e1000_hw * hw)8089 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090 {
8091 int32_t timeout;
8092 uint32_t swsm;
8093
8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8095
8096 if (!hw->eeprom_semaphore_present)
8097 return E1000_SUCCESS;
8098
8099 if (hw->mac_type == e1000_80003es2lan) {
8100 /* Get the SW semaphore. */
8101 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8102 return -E1000_ERR_EEPROM;
8103 }
8104
8105 /* Get the FW semaphore. */
8106 timeout = hw->eeprom.word_size + 1;
8107 while (timeout) {
8108 swsm = E1000_READ_REG(hw, SWSM);
8109 swsm |= E1000_SWSM_SWESMBI;
8110 E1000_WRITE_REG(hw, SWSM, swsm);
8111 /* if we managed to set the bit we got the semaphore. */
8112 swsm = E1000_READ_REG(hw, SWSM);
8113 if (swsm & E1000_SWSM_SWESMBI)
8114 break;
8115
8116 usec_delay(50);
8117 timeout--;
8118 }
8119
8120 if (!timeout) {
8121 /* Release semaphores */
8122 e1000_put_hw_eeprom_semaphore(hw);
8123 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8124 return -E1000_ERR_EEPROM;
8125 }
8126
8127 return E1000_SUCCESS;
8128 }
8129
8130 /***************************************************************************
8131 * This function clears HW semaphore bits.
8132 *
8133 * hw: Struct containing variables accessed by shared code
8134 *
8135 * returns: - None.
8136 *
8137 ***************************************************************************/
8138 static void
e1000_put_hw_eeprom_semaphore(struct e1000_hw * hw)8139 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8140 {
8141 uint32_t swsm;
8142
8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8144
8145 if (!hw->eeprom_semaphore_present)
8146 return;
8147
8148 swsm = E1000_READ_REG(hw, SWSM);
8149 if (hw->mac_type == e1000_80003es2lan) {
8150 /* Release both semaphores. */
8151 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8152 } else
8153 swsm &= ~(E1000_SWSM_SWESMBI);
8154 E1000_WRITE_REG(hw, SWSM, swsm);
8155 }
8156
8157 /***************************************************************************
8158 *
8159 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8160 *
8161 * hw: Struct containing variables accessed by shared code
8162 *
8163 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8164 * E1000_SUCCESS at any other case.
8165 *
8166 ***************************************************************************/
8167 static int32_t
e1000_get_software_semaphore(struct e1000_hw * hw)8168 e1000_get_software_semaphore(struct e1000_hw *hw)
8169 {
8170 int32_t timeout = hw->eeprom.word_size + 1;
8171 uint32_t swsm;
8172
8173 DEBUGFUNC("e1000_get_software_semaphore");
8174
8175 if (hw->mac_type != e1000_80003es2lan) {
8176 return E1000_SUCCESS;
8177 }
8178
8179 while (timeout) {
8180 swsm = E1000_READ_REG(hw, SWSM);
8181 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8182 if (!(swsm & E1000_SWSM_SMBI))
8183 break;
8184 msec_delay_irq(1);
8185 timeout--;
8186 }
8187
8188 if (!timeout) {
8189 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8190 return -E1000_ERR_RESET;
8191 }
8192
8193 return E1000_SUCCESS;
8194 }
8195
8196 /***************************************************************************
8197 *
8198 * Release semaphore bit (SMBI).
8199 *
8200 * hw: Struct containing variables accessed by shared code
8201 *
8202 ***************************************************************************/
8203 static void
e1000_release_software_semaphore(struct e1000_hw * hw)8204 e1000_release_software_semaphore(struct e1000_hw *hw)
8205 {
8206 uint32_t swsm;
8207
8208 DEBUGFUNC("e1000_release_software_semaphore");
8209
8210 if (hw->mac_type != e1000_80003es2lan) {
8211 return;
8212 }
8213
8214 swsm = E1000_READ_REG(hw, SWSM);
8215 /* Release the SW semaphores.*/
8216 swsm &= ~E1000_SWSM_SMBI;
8217 E1000_WRITE_REG(hw, SWSM, swsm);
8218 }
8219
8220 /******************************************************************************
8221 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8222 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8223 * the caller to figure out how to deal with it.
8224 *
8225 * hw - Struct containing variables accessed by shared code
8226 *
8227 * returns: - E1000_BLK_PHY_RESET
8228 * E1000_SUCCESS
8229 *
8230 *****************************************************************************/
8231 int32_t
e1000_check_phy_reset_block(struct e1000_hw * hw)8232 e1000_check_phy_reset_block(struct e1000_hw *hw)
8233 {
8234 uint32_t manc = 0;
8235 uint32_t fwsm = 0;
8236
8237 if (hw->is_ich == TRUE) {
8238 fwsm = E1000_READ_REG(hw, FWSM);
8239 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8240 : E1000_BLK_PHY_RESET;
8241 }
8242
8243 if (hw->mac_type > e1000_82547_rev_2)
8244 manc = E1000_READ_REG(hw, MANC);
8245 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8246 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8247 }
8248
8249 static uint8_t
e1000_arc_subsystem_valid(struct e1000_hw * hw)8250 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8251 {
8252 uint32_t fwsm;
8253
8254 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8255 * may not be provided a DMA clock when no manageability features are
8256 * enabled. We do not want to perform any reads/writes to these registers
8257 * if this is the case. We read FWSM to determine the manageability mode.
8258 */
8259 switch (hw->mac_type) {
8260 case e1000_82571:
8261 case e1000_82572:
8262 case e1000_82573:
8263 case e1000_80003es2lan:
8264 fwsm = E1000_READ_REG(hw, FWSM);
8265 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8266 return TRUE;
8267 break;
8268 case e1000_ich8lan:
8269 return TRUE;
8270 default:
8271 break;
8272 }
8273 return FALSE;
8274 }
8275
8276
8277 /******************************************************************************
8278 * Configure PCI-Ex no-snoop
8279 *
8280 * hw - Struct containing variables accessed by shared code.
8281 * no_snoop - Bitmap of no-snoop events.
8282 *
8283 * returns: E1000_SUCCESS
8284 *
8285 *****************************************************************************/
8286 static int32_t
e1000_set_pci_ex_no_snoop(struct e1000_hw * hw,uint32_t no_snoop)8287 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8288 {
8289 uint32_t gcr_reg = 0;
8290
8291 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8292
8293 if (hw->bus_type == e1000_bus_type_unknown)
8294 e1000_get_bus_info(hw);
8295
8296 if (hw->bus_type != e1000_bus_type_pci_express)
8297 return E1000_SUCCESS;
8298
8299 if (no_snoop) {
8300 gcr_reg = E1000_READ_REG(hw, GCR);
8301 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8302 gcr_reg |= no_snoop;
8303 E1000_WRITE_REG(hw, GCR, gcr_reg);
8304 }
8305 if (hw->is_ich == TRUE) {
8306 uint32_t ctrl_ext;
8307
8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8309
8310 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8311 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8312 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8313 }
8314
8315 return E1000_SUCCESS;
8316 }
8317
8318 /***************************************************************************
8319 *
8320 * Get software semaphore FLAG bit (SWFLAG).
8321 * SWFLAG is used to synchronize the access to all shared resource between
8322 * SW, FW and HW.
8323 *
8324 * hw: Struct containing variables accessed by shared code
8325 *
8326 ***************************************************************************/
8327 static int32_t
e1000_get_software_flag(struct e1000_hw * hw)8328 e1000_get_software_flag(struct e1000_hw *hw)
8329 {
8330 int32_t timeout = PHY_CFG_TIMEOUT;
8331 uint32_t extcnf_ctrl;
8332
8333 DEBUGFUNC("e1000_get_software_flag");
8334
8335 if (hw->is_ich == TRUE) {
8336 while (timeout) {
8337 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8338 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8339 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8340
8341 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8342 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8343 break;
8344 msec_delay_irq(1);
8345 timeout--;
8346 }
8347
8348 if (!timeout) {
8349 DEBUGOUT("FW or HW locks the resource too long.\n");
8350 return -E1000_ERR_CONFIG;
8351 }
8352 }
8353
8354 return E1000_SUCCESS;
8355 }
8356
8357 /***************************************************************************
8358 *
8359 * Release software semaphore FLAG bit (SWFLAG).
8360 * SWFLAG is used to synchronize the access to all shared resource between
8361 * SW, FW and HW.
8362 *
8363 * hw: Struct containing variables accessed by shared code
8364 *
8365 ***************************************************************************/
8366 static void
e1000_release_software_flag(struct e1000_hw * hw)8367 e1000_release_software_flag(struct e1000_hw *hw)
8368 {
8369 uint32_t extcnf_ctrl;
8370
8371 DEBUGFUNC("e1000_release_software_flag");
8372
8373 if (hw->is_ich == TRUE) {
8374 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8375 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8376 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8377 }
8378
8379 return;
8380 }
8381
8382
8383 /******************************************************************************
8384 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8385 * register.
8386 *
8387 * hw - Struct containing variables accessed by shared code
8388 * offset - offset of word in the EEPROM to read
8389 * data - word read from the EEPROM
8390 * words - number of words to read
8391 *****************************************************************************/
8392 static int32_t
e1000_read_eeprom_ich8(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)8393 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8394 uint16_t *data)
8395 {
8396 int32_t error = E1000_SUCCESS;
8397 uint32_t flash_bank = 0;
8398 uint32_t act_offset = 0;
8399 uint32_t bank_offset = 0;
8400 uint16_t word = 0;
8401 uint16_t i = 0;
8402
8403 /* We need to know which is the valid flash bank. In the event
8404 * that we didn't allocate eeprom_shadow_ram, we may not be
8405 * managing flash_bank. So it cannot be trusted and needs
8406 * to be updated with each read.
8407 */
8408 /* Value of bit 22 corresponds to the flash bank we're on. */
8409 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8410
8411 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8412 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8413
8414 error = e1000_get_software_flag(hw);
8415 if (error != E1000_SUCCESS)
8416 return error;
8417
8418 for (i = 0; i < words; i++) {
8419 if (hw->eeprom_shadow_ram != NULL &&
8420 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8421 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8422 } else {
8423 /* The NVM part needs a byte offset, hence * 2 */
8424 act_offset = bank_offset + ((offset + i) * 2);
8425 error = e1000_read_ich8_word(hw, act_offset, &word);
8426 if (error != E1000_SUCCESS)
8427 break;
8428 data[i] = word;
8429 }
8430 }
8431
8432 e1000_release_software_flag(hw);
8433
8434 return error;
8435 }
8436
8437 /******************************************************************************
8438 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8439 * register. Actually, writes are written to the shadow ram cache in the hw
8440 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8441 * the NVM, which occurs when the NVM checksum is updated.
8442 *
8443 * hw - Struct containing variables accessed by shared code
8444 * offset - offset of word in the EEPROM to write
8445 * words - number of words to write
8446 * data - words to write to the EEPROM
8447 *****************************************************************************/
8448 static int32_t
e1000_write_eeprom_ich8(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)8449 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8450 uint16_t *data)
8451 {
8452 uint32_t i = 0;
8453 int32_t error = E1000_SUCCESS;
8454
8455 error = e1000_get_software_flag(hw);
8456 if (error != E1000_SUCCESS)
8457 return error;
8458
8459 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8460 * allocated. Subsequent reads to the modified words are read from
8461 * this cached structure as well. Writes will only go into this
8462 * cached structure unless it's followed by a call to
8463 * e1000_update_eeprom_checksum() where it will commit the changes
8464 * and clear the "modified" field.
8465 */
8466 if (hw->eeprom_shadow_ram != NULL) {
8467 for (i = 0; i < words; i++) {
8468 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8469 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8470 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8471 } else {
8472 error = -E1000_ERR_EEPROM;
8473 break;
8474 }
8475 }
8476 } else {
8477 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8478 * as they don't perform any NVM writes. An attempt in doing so
8479 * will result in this error.
8480 */
8481 error = -E1000_ERR_EEPROM;
8482 }
8483
8484 e1000_release_software_flag(hw);
8485
8486 return error;
8487 }
8488
8489 /******************************************************************************
8490 * This function does initial flash setup so that a new read/write/erase cycle
8491 * can be started.
8492 *
8493 * hw - The pointer to the hw structure
8494 ****************************************************************************/
8495 static int32_t
e1000_ich8_cycle_init(struct e1000_hw * hw)8496 e1000_ich8_cycle_init(struct e1000_hw *hw)
8497 {
8498 union ich8_hws_flash_status hsfsts;
8499 int32_t error = E1000_ERR_EEPROM;
8500 int32_t i = 0;
8501
8502 DEBUGFUNC("e1000_ich8_cycle_init");
8503
8504 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8505
8506 /* May be check the Flash Des Valid bit in Hw status */
8507 if (hsfsts.hsf_status.fldesvalid == 0) {
8508 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8509 return error;
8510 }
8511
8512 /* Clear FCERR in Hw status by writing 1 */
8513 /* Clear DAEL in Hw status by writing a 1 */
8514 hsfsts.hsf_status.flcerr = 1;
8515 hsfsts.hsf_status.dael = 1;
8516
8517 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8518
8519 /* Either we should have a hardware SPI cycle in progress bit to check
8520 * against, in order to start a new cycle or FDONE bit should be changed
8521 * in the hardware so that it is 1 after harware reset, which can then be
8522 * used as an indication whether a cycle is in progress or has been
8523 * completed .. we should also have some software semaphore mechanism to
8524 * guard FDONE or the cycle in progress bit so that two threads access to
8525 * those bits can be sequentiallized or a way so that 2 threads dont
8526 * start the cycle at the same time */
8527
8528 if (hsfsts.hsf_status.flcinprog == 0) {
8529 /* There is no cycle running at present, so we can start a cycle */
8530 /* Begin by setting Flash Cycle Done. */
8531 hsfsts.hsf_status.flcdone = 1;
8532 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8533 error = E1000_SUCCESS;
8534 } else {
8535 /* otherwise poll for sometime so the current cycle has a chance
8536 * to end before giving up. */
8537 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8538 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8539 if (hsfsts.hsf_status.flcinprog == 0) {
8540 error = E1000_SUCCESS;
8541 break;
8542 }
8543 usec_delay(1);
8544 }
8545 if (error == E1000_SUCCESS) {
8546 /* Successful in waiting for previous cycle to timeout,
8547 * now set the Flash Cycle Done. */
8548 hsfsts.hsf_status.flcdone = 1;
8549 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8550 } else {
8551 DEBUGOUT("Flash controller busy, cannot get access");
8552 }
8553 }
8554 return error;
8555 }
8556
8557 /******************************************************************************
8558 * This function starts a flash cycle and waits for its completion
8559 *
8560 * hw - The pointer to the hw structure
8561 ****************************************************************************/
8562 static int32_t
e1000_ich8_flash_cycle(struct e1000_hw * hw,uint32_t timeout)8563 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8564 {
8565 union ich8_hws_flash_ctrl hsflctl;
8566 union ich8_hws_flash_status hsfsts;
8567 int32_t error = E1000_ERR_EEPROM;
8568 uint32_t i = 0;
8569
8570 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8571 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8572 hsflctl.hsf_ctrl.flcgo = 1;
8573 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8574
8575 /* wait till FDONE bit is set to 1 */
8576 do {
8577 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8578 if (hsfsts.hsf_status.flcdone == 1)
8579 break;
8580 usec_delay(1);
8581 i++;
8582 } while (i < timeout);
8583 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8584 error = E1000_SUCCESS;
8585 }
8586 return error;
8587 }
8588
8589 /******************************************************************************
8590 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8591 *
8592 * hw - The pointer to the hw structure
8593 * index - The index of the byte or word to read.
8594 * size - Size of data to read, 1=byte 2=word
8595 * data - Pointer to the word to store the value read.
8596 *****************************************************************************/
8597 static int32_t
e1000_read_ich8_data(struct e1000_hw * hw,uint32_t index,uint32_t size,uint16_t * data)8598 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8599 uint32_t size, uint16_t* data)
8600 {
8601 union ich8_hws_flash_status hsfsts;
8602 union ich8_hws_flash_ctrl hsflctl;
8603 uint32_t flash_linear_address;
8604 uint32_t flash_data = 0;
8605 int32_t error = -E1000_ERR_EEPROM;
8606 int32_t count = 0;
8607
8608 DEBUGFUNC("e1000_read_ich8_data");
8609
8610 if (size < 1 || size > 2 || data == 0x0 ||
8611 index > ICH_FLASH_LINEAR_ADDR_MASK)
8612 return error;
8613
8614 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8615 hw->flash_base_addr;
8616
8617 do {
8618 usec_delay(1);
8619 /* Steps */
8620 error = e1000_ich8_cycle_init(hw);
8621 if (error != E1000_SUCCESS)
8622 break;
8623
8624 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8625 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8626 hsflctl.hsf_ctrl.fldbcount = size - 1;
8627 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8628 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8629
8630 /* Write the last 24 bits of index into Flash Linear address field in
8631 * Flash Address */
8632 /* TODO: TBD maybe check the index against the size of flash */
8633
8634 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8635
8636 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8637
8638 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8639 * sequence a few more times, else read in (shift in) the Flash Data0,
8640 * the order is least significant byte first msb to lsb */
8641 if (error == E1000_SUCCESS) {
8642 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8643 if (size == 1) {
8644 *data = (uint8_t)(flash_data & 0x000000FF);
8645 } else if (size == 2) {
8646 *data = (uint16_t)(flash_data & 0x0000FFFF);
8647 }
8648 break;
8649 } else {
8650 /* If we've gotten here, then things are probably completely hosed,
8651 * but if the error condition is detected, it won't hurt to give
8652 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8653 */
8654 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8655 if (hsfsts.hsf_status.flcerr == 1) {
8656 /* Repeat for some time before giving up. */
8657 continue;
8658 } else if (hsfsts.hsf_status.flcdone == 0) {
8659 DEBUGOUT("Timeout error - flash cycle did not complete.");
8660 break;
8661 }
8662 }
8663 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8664
8665 return error;
8666 }
8667
8668 /******************************************************************************
8669 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8670 *
8671 * hw - The pointer to the hw structure
8672 * index - The index of the byte/word to read.
8673 * size - Size of data to read, 1=byte 2=word
8674 * data - The byte(s) to write to the NVM.
8675 *****************************************************************************/
8676 static int32_t
e1000_write_ich8_data(struct e1000_hw * hw,uint32_t index,uint32_t size,uint16_t data)8677 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8678 uint16_t data)
8679 {
8680 union ich8_hws_flash_status hsfsts;
8681 union ich8_hws_flash_ctrl hsflctl;
8682 uint32_t flash_linear_address;
8683 uint32_t flash_data = 0;
8684 int32_t error = -E1000_ERR_EEPROM;
8685 int32_t count = 0;
8686
8687 DEBUGFUNC("e1000_write_ich8_data");
8688
8689 if (size < 1 || size > 2 || data > size * 0xff ||
8690 index > ICH_FLASH_LINEAR_ADDR_MASK)
8691 return error;
8692
8693 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8694 hw->flash_base_addr;
8695
8696 do {
8697 usec_delay(1);
8698 /* Steps */
8699 error = e1000_ich8_cycle_init(hw);
8700 if (error != E1000_SUCCESS)
8701 break;
8702
8703 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8704 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8705 hsflctl.hsf_ctrl.fldbcount = size -1;
8706 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8707 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8708
8709 /* Write the last 24 bits of index into Flash Linear address field in
8710 * Flash Address */
8711 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8712
8713 if (size == 1)
8714 flash_data = (uint32_t)data & 0x00FF;
8715 else
8716 flash_data = (uint32_t)data;
8717
8718 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8719
8720 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8721 * sequence a few more times else done */
8722 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8723 if (error == E1000_SUCCESS) {
8724 break;
8725 } else {
8726 /* If we're here, then things are most likely completely hosed,
8727 * but if the error condition is detected, it won't hurt to give
8728 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8729 */
8730 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8731 if (hsfsts.hsf_status.flcerr == 1) {
8732 /* Repeat for some time before giving up. */
8733 continue;
8734 } else if (hsfsts.hsf_status.flcdone == 0) {
8735 DEBUGOUT("Timeout error - flash cycle did not complete.");
8736 break;
8737 }
8738 }
8739 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8740
8741 return error;
8742 }
8743
8744 /******************************************************************************
8745 * Reads a single byte from the NVM using the ICH8 flash access registers.
8746 *
8747 * hw - pointer to e1000_hw structure
8748 * index - The index of the byte to read.
8749 * data - Pointer to a byte to store the value read.
8750 *****************************************************************************/
8751 static int32_t
e1000_read_ich8_byte(struct e1000_hw * hw,uint32_t index,uint8_t * data)8752 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8753 {
8754 int32_t status = E1000_SUCCESS;
8755 uint16_t word = 0;
8756
8757 status = e1000_read_ich8_data(hw, index, 1, &word);
8758 if (status == E1000_SUCCESS) {
8759 *data = (uint8_t)word;
8760 }
8761
8762 return status;
8763 }
8764
8765 /******************************************************************************
8766 * Writes a single byte to the NVM using the ICH8 flash access registers.
8767 * Performs verification by reading back the value and then going through
8768 * a retry algorithm before giving up.
8769 *
8770 * hw - pointer to e1000_hw structure
8771 * index - The index of the byte to write.
8772 * byte - The byte to write to the NVM.
8773 *****************************************************************************/
8774 static int32_t
e1000_verify_write_ich8_byte(struct e1000_hw * hw,uint32_t index,uint8_t byte)8775 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8776 {
8777 int32_t error = E1000_SUCCESS;
8778 int32_t program_retries = 0;
8779
8780 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8781
8782 error = e1000_write_ich8_byte(hw, index, byte);
8783
8784 if (error != E1000_SUCCESS) {
8785 for (program_retries = 0; program_retries < 100; program_retries++) {
8786 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8787 error = e1000_write_ich8_byte(hw, index, byte);
8788 usec_delay(100);
8789 if (error == E1000_SUCCESS)
8790 break;
8791 }
8792 }
8793
8794 if (program_retries == 100)
8795 error = E1000_ERR_EEPROM;
8796
8797 return error;
8798 }
8799
8800 /******************************************************************************
8801 * Writes a single byte to the NVM using the ICH8 flash access registers.
8802 *
8803 * hw - pointer to e1000_hw structure
8804 * index - The index of the byte to read.
8805 * data - The byte to write to the NVM.
8806 *****************************************************************************/
8807 static int32_t
e1000_write_ich8_byte(struct e1000_hw * hw,uint32_t index,uint8_t data)8808 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8809 {
8810 int32_t status = E1000_SUCCESS;
8811 uint16_t word = (uint16_t)data;
8812
8813 status = e1000_write_ich8_data(hw, index, 1, word);
8814
8815 return status;
8816 }
8817
8818 /******************************************************************************
8819 * Reads a word from the NVM using the ICH8 flash access registers.
8820 *
8821 * hw - pointer to e1000_hw structure
8822 * index - The starting byte index of the word to read.
8823 * data - Pointer to a word to store the value read.
8824 *****************************************************************************/
8825 static int32_t
e1000_read_ich8_word(struct e1000_hw * hw,uint32_t index,uint16_t * data)8826 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8827 {
8828 int32_t status = E1000_SUCCESS;
8829 status = e1000_read_ich8_data(hw, index, 2, data);
8830 return status;
8831 }
8832
8833
8834 /******************************************************************************
8835 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8836 * based.
8837 *
8838 * hw - pointer to e1000_hw structure
8839 * bank - 0 for first bank, 1 for second bank
8840 *
8841 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8842 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8843 * bank size may be 4, 8 or 64 KBytes
8844 *****************************************************************************/
8845 int32_t
e1000_erase_ich8_4k_segment(struct e1000_hw * hw,uint32_t bank)8846 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8847 {
8848 union ich8_hws_flash_status hsfsts;
8849 union ich8_hws_flash_ctrl hsflctl;
8850 uint32_t flash_linear_address;
8851 int32_t count = 0;
8852 int32_t error = E1000_ERR_EEPROM;
8853 int32_t iteration;
8854 int32_t sub_sector_size = 0;
8855 int32_t bank_size;
8856 int32_t j = 0;
8857 int32_t error_flag = 0;
8858
8859 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8860
8861 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8862 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8863 * consecutive sectors. The start index for the nth Hw sector can be
8864 * calculated as bank * 4096 + n * 256
8865 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8866 * The start index for the nth Hw sector can be calculated
8867 * as bank * 4096
8868 * 10: The HW sector is 8K bytes
8869 * 11: The Hw sector size is 64K bytes */
8870 if (hsfsts.hsf_status.berasesz == 0x0) {
8871 /* Hw sector size 256 */
8872 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8873 bank_size = ICH_FLASH_SECTOR_SIZE;
8874 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8875 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8876 bank_size = ICH_FLASH_SEG_SIZE_4K;
8877 iteration = 1;
8878 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8879 bank_size = ICH_FLASH_SEG_SIZE_64K;
8880 iteration = 1;
8881 } else {
8882 return error;
8883 }
8884
8885 for (j = 0; j < iteration ; j++) {
8886 do {
8887 count++;
8888 /* Steps */
8889 error = e1000_ich8_cycle_init(hw);
8890 if (error != E1000_SUCCESS) {
8891 error_flag = 1;
8892 break;
8893 }
8894
8895 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8896 * Control */
8897 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8898 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8899 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8900
8901 /* Write the last 24 bits of an index within the block into Flash
8902 * Linear address field in Flash Address. This probably needs to
8903 * be calculated here based off the on-chip erase sector size and
8904 * the software bank size (4, 8 or 64 KBytes) */
8905 flash_linear_address = bank * bank_size + j * sub_sector_size;
8906 flash_linear_address += hw->flash_base_addr;
8907 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8908
8909 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8910
8911 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8912 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8913 * sequence a few more times else Done */
8914 if (error == E1000_SUCCESS) {
8915 break;
8916 } else {
8917 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8918 if (hsfsts.hsf_status.flcerr == 1) {
8919 /* repeat for some time before giving up */
8920 continue;
8921 } else if (hsfsts.hsf_status.flcdone == 0) {
8922 error_flag = 1;
8923 break;
8924 }
8925 }
8926 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8927 if (error_flag == 1)
8928 break;
8929 }
8930 if (error_flag != 1)
8931 error = E1000_SUCCESS;
8932 return error;
8933 }
8934
8935
8936 static int32_t
e1000_init_lcd_from_nvm_config_region(struct e1000_hw * hw,uint32_t cnf_base_addr,uint32_t cnf_size)8937 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8938 uint32_t cnf_base_addr, uint32_t cnf_size)
8939 {
8940 uint32_t ret_val = E1000_SUCCESS;
8941 uint16_t word_addr, reg_data, reg_addr;
8942 uint16_t i;
8943
8944 /* cnf_base_addr is in DWORD */
8945 word_addr = (uint16_t)(cnf_base_addr << 1);
8946
8947 /* cnf_size is returned in size of dwords */
8948 for (i = 0; i < cnf_size; i++) {
8949 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
8950 if (ret_val)
8951 return ret_val;
8952
8953 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
8954 if (ret_val)
8955 return ret_val;
8956
8957 ret_val = e1000_get_software_flag(hw);
8958 if (ret_val != E1000_SUCCESS)
8959 return ret_val;
8960
8961 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8962
8963 e1000_release_software_flag(hw);
8964 }
8965
8966 return ret_val;
8967 }
8968
8969
8970 /******************************************************************************
8971 * This function initializes the PHY from the NVM on ICH8 platforms. This
8972 * is needed due to an issue where the NVM configuration is not properly
8973 * autoloaded after power transitions. Therefore, after each PHY reset, we
8974 * will load the configuration data out of the NVM manually.
8975 *
8976 * hw: Struct containing variables accessed by shared code
8977 *****************************************************************************/
8978 static int32_t
e1000_init_lcd_from_nvm(struct e1000_hw * hw)8979 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8980 {
8981 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8982
8983 if (hw->phy_type != e1000_phy_igp_3)
8984 return E1000_SUCCESS;
8985
8986 /* Check if SW needs configure the PHY */
8987 reg_data = E1000_READ_REG(hw, FEXTNVM);
8988 if (!(reg_data & FEXTNVM_SW_CONFIG))
8989 return E1000_SUCCESS;
8990
8991 /* Wait for basic configuration completes before proceeding*/
8992 loop = 0;
8993 do {
8994 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8995 usec_delay(100);
8996 loop++;
8997 } while ((!reg_data) && (loop < 50));
8998
8999 /* Clear the Init Done bit for the next init event */
9000 reg_data = E1000_READ_REG(hw, STATUS);
9001 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9002 E1000_WRITE_REG(hw, STATUS, reg_data);
9003
9004 /* Make sure HW does not configure LCD from PHY extended configuration
9005 before SW configuration */
9006 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9007 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9008 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9009 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9010 cnf_size >>= 16;
9011 if (cnf_size) {
9012 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9013 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9014 /* cnf_base_addr is in DWORD */
9015 cnf_base_addr >>= 16;
9016
9017 /* Configure LCD from extended configuration region. */
9018 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9019 cnf_size);
9020 if (ret_val)
9021 return ret_val;
9022 }
9023 }
9024
9025 return E1000_SUCCESS;
9026 }
9027
9028