1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
5 *
6 * This only implements the mac core functions for this chip.
7 *
8 * Copyright (C) 2015 STMicroelectronics Ltd
9 *
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
11 */
12
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
16 #include <linux/io.h>
17 #include "stmmac.h"
18 #include "stmmac_pcs.h"
19 #include "dwmac4.h"
20 #include "dwmac5.h"
21
dwmac4_core_init(struct mac_device_info * hw,struct net_device * dev)22 static void dwmac4_core_init(struct mac_device_info *hw,
23 struct net_device *dev)
24 {
25 struct stmmac_priv *priv = netdev_priv(dev);
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONFIG);
28 u32 clk_rate;
29
30 value |= GMAC_CORE_INIT;
31
32 if (hw->ps) {
33 value |= GMAC_CONFIG_TE;
34
35 value &= hw->link.speed_mask;
36 switch (hw->ps) {
37 case SPEED_1000:
38 value |= hw->link.speed1000;
39 break;
40 case SPEED_100:
41 value |= hw->link.speed100;
42 break;
43 case SPEED_10:
44 value |= hw->link.speed10;
45 break;
46 }
47 }
48
49 writel(value, ioaddr + GMAC_CONFIG);
50
51 /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
52 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
53 writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
54
55 /* Enable GMAC interrupts */
56 value = GMAC_INT_DEFAULT_ENABLE;
57
58 if (hw->pcs)
59 value |= GMAC_PCS_IRQ_DEFAULT;
60
61 /* Enable FPE interrupt */
62 if ((GMAC_HW_FEAT_FPESEL & readl(ioaddr + GMAC_HW_FEATURE3)) >> 26)
63 value |= GMAC_INT_FPE_EN;
64
65 writel(value, ioaddr + GMAC_INT_EN);
66
67 if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
68 init_waitqueue_head(&priv->tstamp_busy_wait);
69 }
70
dwmac4_phylink_get_caps(struct stmmac_priv * priv)71 static void dwmac4_phylink_get_caps(struct stmmac_priv *priv)
72 {
73 priv->phylink_config.mac_capabilities |= MAC_2500FD;
74 }
75
dwmac4_rx_queue_enable(struct mac_device_info * hw,u8 mode,u32 queue)76 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
77 u8 mode, u32 queue)
78 {
79 void __iomem *ioaddr = hw->pcsr;
80 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
81
82 value &= GMAC_RX_QUEUE_CLEAR(queue);
83 if (mode == MTL_QUEUE_AVB)
84 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
85 else if (mode == MTL_QUEUE_DCB)
86 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
87
88 writel(value, ioaddr + GMAC_RXQ_CTRL0);
89 }
90
dwmac4_rx_queue_priority(struct mac_device_info * hw,u32 prio,u32 queue)91 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
92 u32 prio, u32 queue)
93 {
94 void __iomem *ioaddr = hw->pcsr;
95 u32 base_register;
96 u32 value;
97
98 base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
99 if (queue >= 4)
100 queue -= 4;
101
102 value = readl(ioaddr + base_register);
103
104 value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
105 value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
106 GMAC_RXQCTRL_PSRQX_MASK(queue);
107 writel(value, ioaddr + base_register);
108 }
109
dwmac4_tx_queue_priority(struct mac_device_info * hw,u32 prio,u32 queue)110 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
111 u32 prio, u32 queue)
112 {
113 void __iomem *ioaddr = hw->pcsr;
114 u32 base_register;
115 u32 value;
116
117 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
118 if (queue >= 4)
119 queue -= 4;
120
121 value = readl(ioaddr + base_register);
122
123 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
124 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
125 GMAC_TXQCTRL_PSTQX_MASK(queue);
126
127 writel(value, ioaddr + base_register);
128 }
129
dwmac4_rx_queue_routing(struct mac_device_info * hw,u8 packet,u32 queue)130 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
131 u8 packet, u32 queue)
132 {
133 void __iomem *ioaddr = hw->pcsr;
134 u32 value;
135
136 static const struct stmmac_rx_routing route_possibilities[] = {
137 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
138 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
139 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
140 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
141 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
142 };
143
144 value = readl(ioaddr + GMAC_RXQ_CTRL1);
145
146 /* routing configuration */
147 value &= ~route_possibilities[packet - 1].reg_mask;
148 value |= (queue << route_possibilities[packet-1].reg_shift) &
149 route_possibilities[packet - 1].reg_mask;
150
151 /* some packets require extra ops */
152 if (packet == PACKET_AVCPQ) {
153 value &= ~GMAC_RXQCTRL_TACPQE;
154 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
155 } else if (packet == PACKET_MCBCQ) {
156 value &= ~GMAC_RXQCTRL_MCBCQEN;
157 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
158 }
159
160 writel(value, ioaddr + GMAC_RXQ_CTRL1);
161 }
162
dwmac4_prog_mtl_rx_algorithms(struct mac_device_info * hw,u32 rx_alg)163 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
164 u32 rx_alg)
165 {
166 void __iomem *ioaddr = hw->pcsr;
167 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
168
169 value &= ~MTL_OPERATION_RAA;
170 switch (rx_alg) {
171 case MTL_RX_ALGORITHM_SP:
172 value |= MTL_OPERATION_RAA_SP;
173 break;
174 case MTL_RX_ALGORITHM_WSP:
175 value |= MTL_OPERATION_RAA_WSP;
176 break;
177 default:
178 break;
179 }
180
181 writel(value, ioaddr + MTL_OPERATION_MODE);
182 }
183
dwmac4_prog_mtl_tx_algorithms(struct mac_device_info * hw,u32 tx_alg)184 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
185 u32 tx_alg)
186 {
187 void __iomem *ioaddr = hw->pcsr;
188 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
189
190 value &= ~MTL_OPERATION_SCHALG_MASK;
191 switch (tx_alg) {
192 case MTL_TX_ALGORITHM_WRR:
193 value |= MTL_OPERATION_SCHALG_WRR;
194 break;
195 case MTL_TX_ALGORITHM_WFQ:
196 value |= MTL_OPERATION_SCHALG_WFQ;
197 break;
198 case MTL_TX_ALGORITHM_DWRR:
199 value |= MTL_OPERATION_SCHALG_DWRR;
200 break;
201 case MTL_TX_ALGORITHM_SP:
202 value |= MTL_OPERATION_SCHALG_SP;
203 break;
204 default:
205 break;
206 }
207
208 writel(value, ioaddr + MTL_OPERATION_MODE);
209 }
210
dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv * priv,struct mac_device_info * hw,u32 weight,u32 queue)211 static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv *priv,
212 struct mac_device_info *hw,
213 u32 weight, u32 queue)
214 {
215 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
216 void __iomem *ioaddr = hw->pcsr;
217 u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs,
218 queue));
219
220 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
221 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
222 writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue));
223 }
224
dwmac4_map_mtl_dma(struct mac_device_info * hw,u32 queue,u32 chan)225 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
226 {
227 void __iomem *ioaddr = hw->pcsr;
228 u32 value;
229
230 if (queue < 4) {
231 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
232 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
233 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
234 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
235 } else {
236 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
237 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
238 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
239 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
240 }
241 }
242
dwmac4_config_cbs(struct stmmac_priv * priv,struct mac_device_info * hw,u32 send_slope,u32 idle_slope,u32 high_credit,u32 low_credit,u32 queue)243 static void dwmac4_config_cbs(struct stmmac_priv *priv,
244 struct mac_device_info *hw,
245 u32 send_slope, u32 idle_slope,
246 u32 high_credit, u32 low_credit, u32 queue)
247 {
248 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
249 void __iomem *ioaddr = hw->pcsr;
250 u32 value;
251
252 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
253 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
254 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
255 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
256 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
257
258 /* enable AV algorithm */
259 value = readl(ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
260 value |= MTL_ETS_CTRL_AVALG;
261 value |= MTL_ETS_CTRL_CC;
262 writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
263
264 /* configure send slope */
265 value = readl(ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
266 queue));
267 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
268 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
269 writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
270 queue));
271
272 /* configure idle slope (same register as tx weight) */
273 dwmac4_set_mtl_tx_queue_weight(priv, hw, idle_slope, queue);
274
275 /* configure high credit */
276 value = readl(ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
277 value &= ~MTL_HIGH_CRED_HC_MASK;
278 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
279 writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
280
281 /* configure high credit */
282 value = readl(ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
283 value &= ~MTL_HIGH_CRED_LC_MASK;
284 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
285 writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
286 }
287
dwmac4_dump_regs(struct mac_device_info * hw,u32 * reg_space)288 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
289 {
290 void __iomem *ioaddr = hw->pcsr;
291 int i;
292
293 for (i = 0; i < GMAC_REG_NUM; i++)
294 reg_space[i] = readl(ioaddr + i * 4);
295 }
296
dwmac4_rx_ipc_enable(struct mac_device_info * hw)297 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
298 {
299 void __iomem *ioaddr = hw->pcsr;
300 u32 value = readl(ioaddr + GMAC_CONFIG);
301
302 if (hw->rx_csum)
303 value |= GMAC_CONFIG_IPC;
304 else
305 value &= ~GMAC_CONFIG_IPC;
306
307 writel(value, ioaddr + GMAC_CONFIG);
308
309 value = readl(ioaddr + GMAC_CONFIG);
310
311 return !!(value & GMAC_CONFIG_IPC);
312 }
313
dwmac4_pmt(struct mac_device_info * hw,unsigned long mode)314 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
315 {
316 void __iomem *ioaddr = hw->pcsr;
317 unsigned int pmt = 0;
318 u32 config;
319
320 if (mode & WAKE_MAGIC) {
321 pr_debug("GMAC: WOL Magic frame\n");
322 pmt |= power_down | magic_pkt_en;
323 }
324 if (mode & WAKE_UCAST) {
325 pr_debug("GMAC: WOL on global unicast\n");
326 pmt |= power_down | global_unicast | wake_up_frame_en;
327 }
328
329 if (pmt) {
330 /* The receiver must be enabled for WOL before powering down */
331 config = readl(ioaddr + GMAC_CONFIG);
332 config |= GMAC_CONFIG_RE;
333 writel(config, ioaddr + GMAC_CONFIG);
334 }
335 writel(pmt, ioaddr + GMAC_PMT);
336 }
337
dwmac4_set_umac_addr(struct mac_device_info * hw,const unsigned char * addr,unsigned int reg_n)338 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
339 const unsigned char *addr, unsigned int reg_n)
340 {
341 void __iomem *ioaddr = hw->pcsr;
342
343 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
344 GMAC_ADDR_LOW(reg_n));
345 }
346
dwmac4_get_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)347 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
348 unsigned char *addr, unsigned int reg_n)
349 {
350 void __iomem *ioaddr = hw->pcsr;
351
352 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
353 GMAC_ADDR_LOW(reg_n));
354 }
355
dwmac4_set_eee_mode(struct mac_device_info * hw,bool en_tx_lpi_clockgating)356 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
357 bool en_tx_lpi_clockgating)
358 {
359 void __iomem *ioaddr = hw->pcsr;
360 u32 value;
361
362 /* Enable the link status receive on RGMII, SGMII ore SMII
363 * receive path and instruct the transmit to enter in LPI
364 * state.
365 */
366 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
367 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
368
369 if (en_tx_lpi_clockgating)
370 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
371
372 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
373 }
374
dwmac4_reset_eee_mode(struct mac_device_info * hw)375 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
376 {
377 void __iomem *ioaddr = hw->pcsr;
378 u32 value;
379
380 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
381 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
382 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
383 }
384
dwmac4_set_eee_pls(struct mac_device_info * hw,int link)385 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
386 {
387 void __iomem *ioaddr = hw->pcsr;
388 u32 value;
389
390 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
391
392 if (link)
393 value |= GMAC4_LPI_CTRL_STATUS_PLS;
394 else
395 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
396
397 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
398 }
399
dwmac4_set_eee_lpi_entry_timer(struct mac_device_info * hw,int et)400 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, int et)
401 {
402 void __iomem *ioaddr = hw->pcsr;
403 int value = et & STMMAC_ET_MAX;
404 int regval;
405
406 /* Program LPI entry timer value into register */
407 writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
408
409 /* Enable/disable LPI entry timer */
410 regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
411 regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
412
413 if (et)
414 regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
415 else
416 regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
417
418 writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
419 }
420
dwmac4_set_eee_timer(struct mac_device_info * hw,int ls,int tw)421 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
422 {
423 void __iomem *ioaddr = hw->pcsr;
424 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
425
426 /* Program the timers in the LPI timer control register:
427 * LS: minimum time (ms) for which the link
428 * status from PHY should be ok before transmitting
429 * the LPI pattern.
430 * TW: minimum time (us) for which the core waits
431 * after it has stopped transmitting the LPI pattern.
432 */
433 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
434 }
435
dwmac4_write_single_vlan(struct net_device * dev,u16 vid)436 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
437 {
438 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
439 u32 val;
440
441 val = readl(ioaddr + GMAC_VLAN_TAG);
442 val &= ~GMAC_VLAN_TAG_VID;
443 val |= GMAC_VLAN_TAG_ETV | vid;
444
445 writel(val, ioaddr + GMAC_VLAN_TAG);
446 }
447
dwmac4_write_vlan_filter(struct net_device * dev,struct mac_device_info * hw,u8 index,u32 data)448 static int dwmac4_write_vlan_filter(struct net_device *dev,
449 struct mac_device_info *hw,
450 u8 index, u32 data)
451 {
452 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
453 int i, timeout = 10;
454 u32 val;
455
456 if (index >= hw->num_vlan)
457 return -EINVAL;
458
459 writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
460
461 val = readl(ioaddr + GMAC_VLAN_TAG);
462 val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
463 GMAC_VLAN_TAG_CTRL_CT |
464 GMAC_VLAN_TAG_CTRL_OB);
465 val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
466
467 writel(val, ioaddr + GMAC_VLAN_TAG);
468
469 for (i = 0; i < timeout; i++) {
470 val = readl(ioaddr + GMAC_VLAN_TAG);
471 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
472 return 0;
473 udelay(1);
474 }
475
476 netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
477
478 return -EBUSY;
479 }
480
dwmac4_add_hw_vlan_rx_fltr(struct net_device * dev,struct mac_device_info * hw,__be16 proto,u16 vid)481 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
482 struct mac_device_info *hw,
483 __be16 proto, u16 vid)
484 {
485 int index = -1;
486 u32 val = 0;
487 int i, ret;
488
489 if (vid > 4095)
490 return -EINVAL;
491
492 /* Single Rx VLAN Filter */
493 if (hw->num_vlan == 1) {
494 /* For single VLAN filter, VID 0 means VLAN promiscuous */
495 if (vid == 0) {
496 netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
497 return -EPERM;
498 }
499
500 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
501 netdev_err(dev, "Only single VLAN ID supported\n");
502 return -EPERM;
503 }
504
505 hw->vlan_filter[0] = vid;
506 dwmac4_write_single_vlan(dev, vid);
507
508 return 0;
509 }
510
511 /* Extended Rx VLAN Filter Enable */
512 val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
513
514 for (i = 0; i < hw->num_vlan; i++) {
515 if (hw->vlan_filter[i] == val)
516 return 0;
517 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
518 index = i;
519 }
520
521 if (index == -1) {
522 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
523 hw->num_vlan);
524 return -EPERM;
525 }
526
527 ret = dwmac4_write_vlan_filter(dev, hw, index, val);
528
529 if (!ret)
530 hw->vlan_filter[index] = val;
531
532 return ret;
533 }
534
dwmac4_del_hw_vlan_rx_fltr(struct net_device * dev,struct mac_device_info * hw,__be16 proto,u16 vid)535 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
536 struct mac_device_info *hw,
537 __be16 proto, u16 vid)
538 {
539 int i, ret = 0;
540
541 /* Single Rx VLAN Filter */
542 if (hw->num_vlan == 1) {
543 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
544 hw->vlan_filter[0] = 0;
545 dwmac4_write_single_vlan(dev, 0);
546 }
547 return 0;
548 }
549
550 /* Extended Rx VLAN Filter Enable */
551 for (i = 0; i < hw->num_vlan; i++) {
552 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
553 ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
554
555 if (!ret)
556 hw->vlan_filter[i] = 0;
557 else
558 return ret;
559 }
560 }
561
562 return ret;
563 }
564
dwmac4_restore_hw_vlan_rx_fltr(struct net_device * dev,struct mac_device_info * hw)565 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
566 struct mac_device_info *hw)
567 {
568 void __iomem *ioaddr = hw->pcsr;
569 u32 value;
570 u32 hash;
571 u32 val;
572 int i;
573
574 /* Single Rx VLAN Filter */
575 if (hw->num_vlan == 1) {
576 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
577 return;
578 }
579
580 /* Extended Rx VLAN Filter Enable */
581 for (i = 0; i < hw->num_vlan; i++) {
582 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
583 val = hw->vlan_filter[i];
584 dwmac4_write_vlan_filter(dev, hw, i, val);
585 }
586 }
587
588 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
589 if (hash & GMAC_VLAN_VLHT) {
590 value = readl(ioaddr + GMAC_VLAN_TAG);
591 value |= GMAC_VLAN_VTHM;
592 writel(value, ioaddr + GMAC_VLAN_TAG);
593 }
594 }
595
dwmac4_set_filter(struct mac_device_info * hw,struct net_device * dev)596 static void dwmac4_set_filter(struct mac_device_info *hw,
597 struct net_device *dev)
598 {
599 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
600 int numhashregs = (hw->multicast_filter_bins >> 5);
601 int mcbitslog2 = hw->mcast_bits_log2;
602 unsigned int value;
603 u32 mc_filter[8];
604 int i;
605
606 memset(mc_filter, 0, sizeof(mc_filter));
607
608 value = readl(ioaddr + GMAC_PACKET_FILTER);
609 value &= ~GMAC_PACKET_FILTER_HMC;
610 value &= ~GMAC_PACKET_FILTER_HPF;
611 value &= ~GMAC_PACKET_FILTER_PCF;
612 value &= ~GMAC_PACKET_FILTER_PM;
613 value &= ~GMAC_PACKET_FILTER_PR;
614 value &= ~GMAC_PACKET_FILTER_RA;
615 if (dev->flags & IFF_PROMISC) {
616 /* VLAN Tag Filter Fail Packets Queuing */
617 if (hw->vlan_fail_q_en) {
618 value = readl(ioaddr + GMAC_RXQ_CTRL4);
619 value &= ~GMAC_RXQCTRL_VFFQ_MASK;
620 value |= GMAC_RXQCTRL_VFFQE |
621 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
622 writel(value, ioaddr + GMAC_RXQ_CTRL4);
623 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
624 } else {
625 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
626 }
627
628 } else if ((dev->flags & IFF_ALLMULTI) ||
629 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
630 /* Pass all multi */
631 value |= GMAC_PACKET_FILTER_PM;
632 /* Set all the bits of the HASH tab */
633 memset(mc_filter, 0xff, sizeof(mc_filter));
634 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
635 struct netdev_hw_addr *ha;
636
637 /* Hash filter for multicast */
638 value |= GMAC_PACKET_FILTER_HMC;
639
640 netdev_for_each_mc_addr(ha, dev) {
641 /* The upper n bits of the calculated CRC are used to
642 * index the contents of the hash table. The number of
643 * bits used depends on the hardware configuration
644 * selected at core configuration time.
645 */
646 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
647 ETH_ALEN)) >> (32 - mcbitslog2);
648 /* The most significant bit determines the register to
649 * use (H/L) while the other 5 bits determine the bit
650 * within the register.
651 */
652 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
653 }
654 }
655
656 for (i = 0; i < numhashregs; i++)
657 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
658
659 value |= GMAC_PACKET_FILTER_HPF;
660
661 /* Handle multiple unicast addresses */
662 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
663 /* Switch to promiscuous mode if more than 128 addrs
664 * are required
665 */
666 value |= GMAC_PACKET_FILTER_PR;
667 } else {
668 struct netdev_hw_addr *ha;
669 int reg = 1;
670
671 netdev_for_each_uc_addr(ha, dev) {
672 dwmac4_set_umac_addr(hw, ha->addr, reg);
673 reg++;
674 }
675
676 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
677 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
678 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
679 reg++;
680 }
681 }
682
683 /* VLAN filtering */
684 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en)
685 value &= ~GMAC_PACKET_FILTER_VTFE;
686 else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
687 value |= GMAC_PACKET_FILTER_VTFE;
688
689 writel(value, ioaddr + GMAC_PACKET_FILTER);
690 }
691
dwmac4_flow_ctrl(struct mac_device_info * hw,unsigned int duplex,unsigned int fc,unsigned int pause_time,u32 tx_cnt)692 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
693 unsigned int fc, unsigned int pause_time,
694 u32 tx_cnt)
695 {
696 void __iomem *ioaddr = hw->pcsr;
697 unsigned int flow = 0;
698 u32 queue = 0;
699
700 pr_debug("GMAC Flow-Control:\n");
701 if (fc & FLOW_RX) {
702 pr_debug("\tReceive Flow-Control ON\n");
703 flow |= GMAC_RX_FLOW_CTRL_RFE;
704 } else {
705 pr_debug("\tReceive Flow-Control OFF\n");
706 }
707 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
708
709 if (fc & FLOW_TX) {
710 pr_debug("\tTransmit Flow-Control ON\n");
711
712 if (duplex)
713 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
714
715 for (queue = 0; queue < tx_cnt; queue++) {
716 flow = GMAC_TX_FLOW_CTRL_TFE;
717
718 if (duplex)
719 flow |=
720 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
721
722 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
723 }
724 } else {
725 for (queue = 0; queue < tx_cnt; queue++)
726 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
727 }
728 }
729
dwmac4_ctrl_ane(void __iomem * ioaddr,bool ane,bool srgmi_ral,bool loopback)730 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
731 bool loopback)
732 {
733 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
734 }
735
dwmac4_rane(void __iomem * ioaddr,bool restart)736 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
737 {
738 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
739 }
740
dwmac4_get_adv_lp(void __iomem * ioaddr,struct rgmii_adv * adv)741 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
742 {
743 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
744 }
745
746 /* RGMII or SMII interface */
dwmac4_phystatus(void __iomem * ioaddr,struct stmmac_extra_stats * x)747 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
748 {
749 u32 status;
750
751 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
752 x->irq_rgmii_n++;
753
754 /* Check the link status */
755 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
756 int speed_value;
757
758 x->pcs_link = 1;
759
760 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
761 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
762 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
763 x->pcs_speed = SPEED_1000;
764 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
765 x->pcs_speed = SPEED_100;
766 else
767 x->pcs_speed = SPEED_10;
768
769 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
770
771 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
772 x->pcs_duplex ? "Full" : "Half");
773 } else {
774 x->pcs_link = 0;
775 pr_info("Link is Down\n");
776 }
777 }
778
dwmac4_irq_mtl_status(struct stmmac_priv * priv,struct mac_device_info * hw,u32 chan)779 static int dwmac4_irq_mtl_status(struct stmmac_priv *priv,
780 struct mac_device_info *hw, u32 chan)
781 {
782 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
783 void __iomem *ioaddr = hw->pcsr;
784 u32 mtl_int_qx_status;
785 int ret = 0;
786
787 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
788
789 /* Check MTL Interrupt */
790 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
791 /* read Queue x Interrupt status */
792 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs,
793 chan));
794
795 if (status & MTL_RX_OVERFLOW_INT) {
796 /* clear Interrupt */
797 writel(status | MTL_RX_OVERFLOW_INT,
798 ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, chan));
799 ret = CORE_IRQ_MTL_RX_OVERFLOW;
800 }
801 }
802
803 return ret;
804 }
805
dwmac4_irq_status(struct mac_device_info * hw,struct stmmac_extra_stats * x)806 static int dwmac4_irq_status(struct mac_device_info *hw,
807 struct stmmac_extra_stats *x)
808 {
809 void __iomem *ioaddr = hw->pcsr;
810 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
811 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
812 int ret = 0;
813
814 /* Discard disabled bits */
815 intr_status &= intr_enable;
816
817 /* Not used events (e.g. MMC interrupts) are not handled. */
818 if ((intr_status & mmc_tx_irq))
819 x->mmc_tx_irq_n++;
820 if (unlikely(intr_status & mmc_rx_irq))
821 x->mmc_rx_irq_n++;
822 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
823 x->mmc_rx_csum_offload_irq_n++;
824 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
825 if (unlikely(intr_status & pmt_irq)) {
826 readl(ioaddr + GMAC_PMT);
827 x->irq_receive_pmt_irq_n++;
828 }
829
830 /* MAC tx/rx EEE LPI entry/exit interrupts */
831 if (intr_status & lpi_irq) {
832 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
833 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
834
835 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
836 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
837 x->irq_tx_path_in_lpi_mode_n++;
838 }
839 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
840 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
841 x->irq_tx_path_exit_lpi_mode_n++;
842 }
843 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
844 x->irq_rx_path_in_lpi_mode_n++;
845 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
846 x->irq_rx_path_exit_lpi_mode_n++;
847 }
848
849 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
850 if (intr_status & PCS_RGSMIIIS_IRQ)
851 dwmac4_phystatus(ioaddr, x);
852
853 return ret;
854 }
855
dwmac4_debug(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 rx_queues,u32 tx_queues)856 static void dwmac4_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
857 struct stmmac_extra_stats *x,
858 u32 rx_queues, u32 tx_queues)
859 {
860 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
861 u32 value;
862 u32 queue;
863
864 for (queue = 0; queue < tx_queues; queue++) {
865 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(dwmac4_addrs, queue));
866
867 if (value & MTL_DEBUG_TXSTSFSTS)
868 x->mtl_tx_status_fifo_full++;
869 if (value & MTL_DEBUG_TXFSTS)
870 x->mtl_tx_fifo_not_empty++;
871 if (value & MTL_DEBUG_TWCSTS)
872 x->mmtl_fifo_ctrl++;
873 if (value & MTL_DEBUG_TRCSTS_MASK) {
874 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
875 >> MTL_DEBUG_TRCSTS_SHIFT;
876 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
877 x->mtl_tx_fifo_read_ctrl_write++;
878 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
879 x->mtl_tx_fifo_read_ctrl_wait++;
880 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
881 x->mtl_tx_fifo_read_ctrl_read++;
882 else
883 x->mtl_tx_fifo_read_ctrl_idle++;
884 }
885 if (value & MTL_DEBUG_TXPAUSED)
886 x->mac_tx_in_pause++;
887 }
888
889 for (queue = 0; queue < rx_queues; queue++) {
890 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue));
891
892 if (value & MTL_DEBUG_RXFSTS_MASK) {
893 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
894 >> MTL_DEBUG_RRCSTS_SHIFT;
895
896 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
897 x->mtl_rx_fifo_fill_level_full++;
898 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
899 x->mtl_rx_fifo_fill_above_thresh++;
900 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
901 x->mtl_rx_fifo_fill_below_thresh++;
902 else
903 x->mtl_rx_fifo_fill_level_empty++;
904 }
905 if (value & MTL_DEBUG_RRCSTS_MASK) {
906 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
907 MTL_DEBUG_RRCSTS_SHIFT;
908
909 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
910 x->mtl_rx_fifo_read_ctrl_flush++;
911 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
912 x->mtl_rx_fifo_read_ctrl_read_data++;
913 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
914 x->mtl_rx_fifo_read_ctrl_status++;
915 else
916 x->mtl_rx_fifo_read_ctrl_idle++;
917 }
918 if (value & MTL_DEBUG_RWCSTS)
919 x->mtl_rx_fifo_ctrl_active++;
920 }
921
922 /* GMAC debug */
923 value = readl(ioaddr + GMAC_DEBUG);
924
925 if (value & GMAC_DEBUG_TFCSTS_MASK) {
926 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
927 >> GMAC_DEBUG_TFCSTS_SHIFT;
928
929 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
930 x->mac_tx_frame_ctrl_xfer++;
931 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
932 x->mac_tx_frame_ctrl_pause++;
933 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
934 x->mac_tx_frame_ctrl_wait++;
935 else
936 x->mac_tx_frame_ctrl_idle++;
937 }
938 if (value & GMAC_DEBUG_TPESTS)
939 x->mac_gmii_tx_proto_engine++;
940 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
941 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
942 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
943 if (value & GMAC_DEBUG_RPESTS)
944 x->mac_gmii_rx_proto_engine++;
945 }
946
dwmac4_set_mac_loopback(void __iomem * ioaddr,bool enable)947 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
948 {
949 u32 value = readl(ioaddr + GMAC_CONFIG);
950
951 if (enable)
952 value |= GMAC_CONFIG_LM;
953 else
954 value &= ~GMAC_CONFIG_LM;
955
956 writel(value, ioaddr + GMAC_CONFIG);
957 }
958
dwmac4_update_vlan_hash(struct mac_device_info * hw,u32 hash,__le16 perfect_match,bool is_double)959 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
960 __le16 perfect_match, bool is_double)
961 {
962 void __iomem *ioaddr = hw->pcsr;
963 u32 value;
964
965 writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
966
967 value = readl(ioaddr + GMAC_VLAN_TAG);
968
969 if (hash) {
970 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
971 if (is_double) {
972 value |= GMAC_VLAN_EDVLP;
973 value |= GMAC_VLAN_ESVL;
974 value |= GMAC_VLAN_DOVLTC;
975 }
976
977 writel(value, ioaddr + GMAC_VLAN_TAG);
978 } else if (perfect_match) {
979 u32 value = GMAC_VLAN_ETV;
980
981 if (is_double) {
982 value |= GMAC_VLAN_EDVLP;
983 value |= GMAC_VLAN_ESVL;
984 value |= GMAC_VLAN_DOVLTC;
985 }
986
987 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
988 } else {
989 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
990 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
991 value &= ~GMAC_VLAN_DOVLTC;
992 value &= ~GMAC_VLAN_VID;
993
994 writel(value, ioaddr + GMAC_VLAN_TAG);
995 }
996 }
997
dwmac4_sarc_configure(void __iomem * ioaddr,int val)998 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
999 {
1000 u32 value = readl(ioaddr + GMAC_CONFIG);
1001
1002 value &= ~GMAC_CONFIG_SARC;
1003 value |= val << GMAC_CONFIG_SARC_SHIFT;
1004
1005 writel(value, ioaddr + GMAC_CONFIG);
1006 }
1007
dwmac4_enable_vlan(struct mac_device_info * hw,u32 type)1008 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1009 {
1010 void __iomem *ioaddr = hw->pcsr;
1011 u32 value;
1012
1013 value = readl(ioaddr + GMAC_VLAN_INCL);
1014 value |= GMAC_VLAN_VLTI;
1015 value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
1016 value &= ~GMAC_VLAN_VLC;
1017 value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1018 writel(value, ioaddr + GMAC_VLAN_INCL);
1019 }
1020
dwmac4_set_arp_offload(struct mac_device_info * hw,bool en,u32 addr)1021 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1022 u32 addr)
1023 {
1024 void __iomem *ioaddr = hw->pcsr;
1025 u32 value;
1026
1027 writel(addr, ioaddr + GMAC_ARP_ADDR);
1028
1029 value = readl(ioaddr + GMAC_CONFIG);
1030 if (en)
1031 value |= GMAC_CONFIG_ARPEN;
1032 else
1033 value &= ~GMAC_CONFIG_ARPEN;
1034 writel(value, ioaddr + GMAC_CONFIG);
1035 }
1036
dwmac4_config_l3_filter(struct mac_device_info * hw,u32 filter_no,bool en,bool ipv6,bool sa,bool inv,u32 match)1037 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1038 bool en, bool ipv6, bool sa, bool inv,
1039 u32 match)
1040 {
1041 void __iomem *ioaddr = hw->pcsr;
1042 u32 value;
1043
1044 value = readl(ioaddr + GMAC_PACKET_FILTER);
1045 value |= GMAC_PACKET_FILTER_IPFE;
1046 writel(value, ioaddr + GMAC_PACKET_FILTER);
1047
1048 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1049
1050 /* For IPv6 not both SA/DA filters can be active */
1051 if (ipv6) {
1052 value |= GMAC_L3PEN0;
1053 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1054 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1055 if (sa) {
1056 value |= GMAC_L3SAM0;
1057 if (inv)
1058 value |= GMAC_L3SAIM0;
1059 } else {
1060 value |= GMAC_L3DAM0;
1061 if (inv)
1062 value |= GMAC_L3DAIM0;
1063 }
1064 } else {
1065 value &= ~GMAC_L3PEN0;
1066 if (sa) {
1067 value |= GMAC_L3SAM0;
1068 if (inv)
1069 value |= GMAC_L3SAIM0;
1070 } else {
1071 value |= GMAC_L3DAM0;
1072 if (inv)
1073 value |= GMAC_L3DAIM0;
1074 }
1075 }
1076
1077 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1078
1079 if (sa) {
1080 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1081 } else {
1082 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1083 }
1084
1085 if (!en)
1086 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1087
1088 return 0;
1089 }
1090
dwmac4_config_l4_filter(struct mac_device_info * hw,u32 filter_no,bool en,bool udp,bool sa,bool inv,u32 match)1091 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1092 bool en, bool udp, bool sa, bool inv,
1093 u32 match)
1094 {
1095 void __iomem *ioaddr = hw->pcsr;
1096 u32 value;
1097
1098 value = readl(ioaddr + GMAC_PACKET_FILTER);
1099 value |= GMAC_PACKET_FILTER_IPFE;
1100 writel(value, ioaddr + GMAC_PACKET_FILTER);
1101
1102 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1103 if (udp) {
1104 value |= GMAC_L4PEN0;
1105 } else {
1106 value &= ~GMAC_L4PEN0;
1107 }
1108
1109 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1110 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1111 if (sa) {
1112 value |= GMAC_L4SPM0;
1113 if (inv)
1114 value |= GMAC_L4SPIM0;
1115 } else {
1116 value |= GMAC_L4DPM0;
1117 if (inv)
1118 value |= GMAC_L4DPIM0;
1119 }
1120
1121 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1122
1123 if (sa) {
1124 value = match & GMAC_L4SP0;
1125 } else {
1126 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1127 }
1128
1129 writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1130
1131 if (!en)
1132 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1133
1134 return 0;
1135 }
1136
1137 const struct stmmac_ops dwmac4_ops = {
1138 .core_init = dwmac4_core_init,
1139 .phylink_get_caps = dwmac4_phylink_get_caps,
1140 .set_mac = stmmac_set_mac,
1141 .rx_ipc = dwmac4_rx_ipc_enable,
1142 .rx_queue_enable = dwmac4_rx_queue_enable,
1143 .rx_queue_prio = dwmac4_rx_queue_priority,
1144 .tx_queue_prio = dwmac4_tx_queue_priority,
1145 .rx_queue_routing = dwmac4_rx_queue_routing,
1146 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1147 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1148 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1149 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1150 .config_cbs = dwmac4_config_cbs,
1151 .dump_regs = dwmac4_dump_regs,
1152 .host_irq_status = dwmac4_irq_status,
1153 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1154 .flow_ctrl = dwmac4_flow_ctrl,
1155 .pmt = dwmac4_pmt,
1156 .set_umac_addr = dwmac4_set_umac_addr,
1157 .get_umac_addr = dwmac4_get_umac_addr,
1158 .set_eee_mode = dwmac4_set_eee_mode,
1159 .reset_eee_mode = dwmac4_reset_eee_mode,
1160 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1161 .set_eee_timer = dwmac4_set_eee_timer,
1162 .set_eee_pls = dwmac4_set_eee_pls,
1163 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1164 .pcs_rane = dwmac4_rane,
1165 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1166 .debug = dwmac4_debug,
1167 .set_filter = dwmac4_set_filter,
1168 .set_mac_loopback = dwmac4_set_mac_loopback,
1169 .update_vlan_hash = dwmac4_update_vlan_hash,
1170 .sarc_configure = dwmac4_sarc_configure,
1171 .enable_vlan = dwmac4_enable_vlan,
1172 .set_arp_offload = dwmac4_set_arp_offload,
1173 .config_l3_filter = dwmac4_config_l3_filter,
1174 .config_l4_filter = dwmac4_config_l4_filter,
1175 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1176 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1177 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1178 };
1179
1180 const struct stmmac_ops dwmac410_ops = {
1181 .core_init = dwmac4_core_init,
1182 .phylink_get_caps = dwmac4_phylink_get_caps,
1183 .set_mac = stmmac_dwmac4_set_mac,
1184 .rx_ipc = dwmac4_rx_ipc_enable,
1185 .rx_queue_enable = dwmac4_rx_queue_enable,
1186 .rx_queue_prio = dwmac4_rx_queue_priority,
1187 .tx_queue_prio = dwmac4_tx_queue_priority,
1188 .rx_queue_routing = dwmac4_rx_queue_routing,
1189 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1190 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1191 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1192 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1193 .config_cbs = dwmac4_config_cbs,
1194 .dump_regs = dwmac4_dump_regs,
1195 .host_irq_status = dwmac4_irq_status,
1196 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1197 .flow_ctrl = dwmac4_flow_ctrl,
1198 .pmt = dwmac4_pmt,
1199 .set_umac_addr = dwmac4_set_umac_addr,
1200 .get_umac_addr = dwmac4_get_umac_addr,
1201 .set_eee_mode = dwmac4_set_eee_mode,
1202 .reset_eee_mode = dwmac4_reset_eee_mode,
1203 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1204 .set_eee_timer = dwmac4_set_eee_timer,
1205 .set_eee_pls = dwmac4_set_eee_pls,
1206 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1207 .pcs_rane = dwmac4_rane,
1208 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1209 .debug = dwmac4_debug,
1210 .set_filter = dwmac4_set_filter,
1211 .flex_pps_config = dwmac5_flex_pps_config,
1212 .set_mac_loopback = dwmac4_set_mac_loopback,
1213 .update_vlan_hash = dwmac4_update_vlan_hash,
1214 .sarc_configure = dwmac4_sarc_configure,
1215 .enable_vlan = dwmac4_enable_vlan,
1216 .set_arp_offload = dwmac4_set_arp_offload,
1217 .config_l3_filter = dwmac4_config_l3_filter,
1218 .config_l4_filter = dwmac4_config_l4_filter,
1219 .est_configure = dwmac5_est_configure,
1220 .est_irq_status = dwmac5_est_irq_status,
1221 .fpe_configure = dwmac5_fpe_configure,
1222 .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1223 .fpe_irq_status = dwmac5_fpe_irq_status,
1224 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1225 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1226 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1227 };
1228
1229 const struct stmmac_ops dwmac510_ops = {
1230 .core_init = dwmac4_core_init,
1231 .phylink_get_caps = dwmac4_phylink_get_caps,
1232 .set_mac = stmmac_dwmac4_set_mac,
1233 .rx_ipc = dwmac4_rx_ipc_enable,
1234 .rx_queue_enable = dwmac4_rx_queue_enable,
1235 .rx_queue_prio = dwmac4_rx_queue_priority,
1236 .tx_queue_prio = dwmac4_tx_queue_priority,
1237 .rx_queue_routing = dwmac4_rx_queue_routing,
1238 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1239 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1240 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1241 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1242 .config_cbs = dwmac4_config_cbs,
1243 .dump_regs = dwmac4_dump_regs,
1244 .host_irq_status = dwmac4_irq_status,
1245 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1246 .flow_ctrl = dwmac4_flow_ctrl,
1247 .pmt = dwmac4_pmt,
1248 .set_umac_addr = dwmac4_set_umac_addr,
1249 .get_umac_addr = dwmac4_get_umac_addr,
1250 .set_eee_mode = dwmac4_set_eee_mode,
1251 .reset_eee_mode = dwmac4_reset_eee_mode,
1252 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1253 .set_eee_timer = dwmac4_set_eee_timer,
1254 .set_eee_pls = dwmac4_set_eee_pls,
1255 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1256 .pcs_rane = dwmac4_rane,
1257 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1258 .debug = dwmac4_debug,
1259 .set_filter = dwmac4_set_filter,
1260 .safety_feat_config = dwmac5_safety_feat_config,
1261 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1262 .safety_feat_dump = dwmac5_safety_feat_dump,
1263 .rxp_config = dwmac5_rxp_config,
1264 .flex_pps_config = dwmac5_flex_pps_config,
1265 .set_mac_loopback = dwmac4_set_mac_loopback,
1266 .update_vlan_hash = dwmac4_update_vlan_hash,
1267 .sarc_configure = dwmac4_sarc_configure,
1268 .enable_vlan = dwmac4_enable_vlan,
1269 .set_arp_offload = dwmac4_set_arp_offload,
1270 .config_l3_filter = dwmac4_config_l3_filter,
1271 .config_l4_filter = dwmac4_config_l4_filter,
1272 .est_configure = dwmac5_est_configure,
1273 .est_irq_status = dwmac5_est_irq_status,
1274 .fpe_configure = dwmac5_fpe_configure,
1275 .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1276 .fpe_irq_status = dwmac5_fpe_irq_status,
1277 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1278 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1279 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1280 };
1281
dwmac4_get_num_vlan(void __iomem * ioaddr)1282 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1283 {
1284 u32 val, num_vlan;
1285
1286 val = readl(ioaddr + GMAC_HW_FEATURE3);
1287 switch (val & GMAC_HW_FEAT_NRVF) {
1288 case 0:
1289 num_vlan = 1;
1290 break;
1291 case 1:
1292 num_vlan = 4;
1293 break;
1294 case 2:
1295 num_vlan = 8;
1296 break;
1297 case 3:
1298 num_vlan = 16;
1299 break;
1300 case 4:
1301 num_vlan = 24;
1302 break;
1303 case 5:
1304 num_vlan = 32;
1305 break;
1306 default:
1307 num_vlan = 1;
1308 }
1309
1310 return num_vlan;
1311 }
1312
dwmac4_setup(struct stmmac_priv * priv)1313 int dwmac4_setup(struct stmmac_priv *priv)
1314 {
1315 struct mac_device_info *mac = priv->hw;
1316
1317 dev_info(priv->device, "\tDWMAC4/5\n");
1318
1319 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1320 mac->pcsr = priv->ioaddr;
1321 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1322 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1323 mac->mcast_bits_log2 = 0;
1324
1325 if (mac->multicast_filter_bins)
1326 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1327
1328 mac->link.duplex = GMAC_CONFIG_DM;
1329 mac->link.speed10 = GMAC_CONFIG_PS;
1330 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1331 mac->link.speed1000 = 0;
1332 mac->link.speed2500 = GMAC_CONFIG_FES;
1333 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1334 mac->mii.addr = GMAC_MDIO_ADDR;
1335 mac->mii.data = GMAC_MDIO_DATA;
1336 mac->mii.addr_shift = 21;
1337 mac->mii.addr_mask = GENMASK(25, 21);
1338 mac->mii.reg_shift = 16;
1339 mac->mii.reg_mask = GENMASK(20, 16);
1340 mac->mii.clk_csr_shift = 8;
1341 mac->mii.clk_csr_mask = GENMASK(11, 8);
1342 mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1343
1344 return 0;
1345 }
1346