1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44
45 /**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
dwc3_get_dr_mode(struct dwc3 * dwc)49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
50 {
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
83
84 /*
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
88 */
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105 }
106
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
108 {
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
115
116 dwc->current_dr_role = mode;
117 }
118
__dwc3_set_mode(struct work_struct * work)119 static void __dwc3_set_mode(struct work_struct *work)
120 {
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
124 u32 reg;
125
126 mutex_lock(&dwc->mutex);
127
128 pm_runtime_get_sync(dwc->dev);
129
130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
131 dwc3_otg_update(dwc, 0);
132
133 if (!dwc->desired_dr_role)
134 goto out;
135
136 if (dwc->desired_dr_role == dwc->current_dr_role)
137 goto out;
138
139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
140 goto out;
141
142 switch (dwc->current_dr_role) {
143 case DWC3_GCTL_PRTCAP_HOST:
144 dwc3_host_exit(dwc);
145 break;
146 case DWC3_GCTL_PRTCAP_DEVICE:
147 dwc3_gadget_exit(dwc);
148 dwc3_event_buffers_cleanup(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_OTG:
151 dwc3_otg_exit(dwc);
152 spin_lock_irqsave(&dwc->lock, flags);
153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
154 spin_unlock_irqrestore(&dwc->lock, flags);
155 dwc3_otg_update(dwc, 1);
156 break;
157 default:
158 break;
159 }
160
161 /*
162 * When current_dr_role is not set, there's no role switching.
163 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
164 */
165 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
166 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
167 dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
168 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
169 reg |= DWC3_GCTL_CORESOFTRESET;
170 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
171
172 /*
173 * Wait for internal clocks to synchronized. DWC_usb31 and
174 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
175 * keep it consistent across different IPs, let's wait up to
176 * 100ms before clearing GCTL.CORESOFTRESET.
177 */
178 msleep(100);
179
180 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
181 reg &= ~DWC3_GCTL_CORESOFTRESET;
182 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
183 }
184
185 spin_lock_irqsave(&dwc->lock, flags);
186
187 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
188
189 spin_unlock_irqrestore(&dwc->lock, flags);
190
191 switch (dwc->desired_dr_role) {
192 case DWC3_GCTL_PRTCAP_HOST:
193 ret = dwc3_host_init(dwc);
194 if (ret) {
195 dev_err(dwc->dev, "failed to initialize host\n");
196 } else {
197 if (dwc->usb2_phy)
198 otg_set_vbus(dwc->usb2_phy->otg, true);
199 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
200 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
201 if (dwc->dis_split_quirk) {
202 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
203 reg |= DWC3_GUCTL3_SPLITDISABLE;
204 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
205 }
206 }
207 break;
208 case DWC3_GCTL_PRTCAP_DEVICE:
209 dwc3_core_soft_reset(dwc);
210
211 dwc3_event_buffers_setup(dwc);
212
213 if (dwc->usb2_phy)
214 otg_set_vbus(dwc->usb2_phy->otg, false);
215 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
216 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
217
218 ret = dwc3_gadget_init(dwc);
219 if (ret)
220 dev_err(dwc->dev, "failed to initialize peripheral\n");
221 break;
222 case DWC3_GCTL_PRTCAP_OTG:
223 dwc3_otg_init(dwc);
224 dwc3_otg_update(dwc, 0);
225 break;
226 default:
227 break;
228 }
229
230 out:
231 pm_runtime_mark_last_busy(dwc->dev);
232 pm_runtime_put_autosuspend(dwc->dev);
233 mutex_unlock(&dwc->mutex);
234 }
235
dwc3_set_mode(struct dwc3 * dwc,u32 mode)236 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
237 {
238 unsigned long flags;
239
240 if (dwc->dr_mode != USB_DR_MODE_OTG)
241 return;
242
243 spin_lock_irqsave(&dwc->lock, flags);
244 dwc->desired_dr_role = mode;
245 spin_unlock_irqrestore(&dwc->lock, flags);
246
247 queue_work(system_freezable_wq, &dwc->drd_work);
248 }
249
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)250 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
251 {
252 struct dwc3 *dwc = dep->dwc;
253 u32 reg;
254
255 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
256 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
257 DWC3_GDBGFIFOSPACE_TYPE(type));
258
259 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
260
261 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
262 }
263
264 /**
265 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
266 * @dwc: pointer to our context structure
267 */
dwc3_core_soft_reset(struct dwc3 * dwc)268 int dwc3_core_soft_reset(struct dwc3 *dwc)
269 {
270 u32 reg;
271 int retries = 1000;
272
273 /*
274 * We're resetting only the device side because, if we're in host mode,
275 * XHCI driver will reset the host block. If dwc3 was configured for
276 * host-only mode, then we can return early.
277 */
278 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
279 return 0;
280
281 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
282 reg |= DWC3_DCTL_CSFTRST;
283 reg &= ~DWC3_DCTL_RUN_STOP;
284 dwc3_gadget_dctl_write_safe(dwc, reg);
285
286 /*
287 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
288 * is cleared only after all the clocks are synchronized. This can
289 * take a little more than 50ms. Set the polling rate at 20ms
290 * for 10 times instead.
291 */
292 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
293 retries = 10;
294
295 do {
296 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
297 if (!(reg & DWC3_DCTL_CSFTRST))
298 goto done;
299
300 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
301 msleep(20);
302 else
303 udelay(1);
304 } while (--retries);
305
306 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
307 return -ETIMEDOUT;
308
309 done:
310 /*
311 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
312 * is cleared, we must wait at least 50ms before accessing the PHY
313 * domain (synchronization delay).
314 */
315 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
316 msleep(50);
317
318 return 0;
319 }
320
321 /*
322 * dwc3_frame_length_adjustment - Adjusts frame length if required
323 * @dwc3: Pointer to our controller context structure
324 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)325 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
326 {
327 u32 reg;
328 u32 dft;
329
330 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
331 return;
332
333 if (dwc->fladj == 0)
334 return;
335
336 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
337 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
338 if (dft != dwc->fladj) {
339 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
340 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
341 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
342 }
343 }
344
345 /**
346 * dwc3_ref_clk_period - Reference clock period configuration
347 * Default reference clock period depends on hardware
348 * configuration. For systems with reference clock that differs
349 * from the default, this will set clock period in DWC3_GUCTL
350 * register.
351 * @dwc: Pointer to our controller context structure
352 */
dwc3_ref_clk_period(struct dwc3 * dwc)353 static void dwc3_ref_clk_period(struct dwc3 *dwc)
354 {
355 unsigned long period;
356 unsigned long fladj;
357 unsigned long decr;
358 unsigned long rate;
359 u32 reg;
360
361 if (dwc->ref_clk) {
362 rate = clk_get_rate(dwc->ref_clk);
363 if (!rate)
364 return;
365 period = NSEC_PER_SEC / rate;
366 } else if (dwc->ref_clk_per) {
367 period = dwc->ref_clk_per;
368 rate = NSEC_PER_SEC / period;
369 } else {
370 return;
371 }
372
373 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
374 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
375 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
376 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
377
378 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
379 return;
380
381 /*
382 * The calculation below is
383 *
384 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
385 *
386 * but rearranged for fixed-point arithmetic. The division must be
387 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
388 * neither does rate * period).
389 *
390 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
391 * nanoseconds of error caused by the truncation which happened during
392 * the division when calculating rate or period (whichever one was
393 * derived from the other). We first calculate the relative error, then
394 * scale it to units of 8 ppm.
395 */
396 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
397 fladj -= 125000;
398
399 /*
400 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
401 */
402 decr = 480000000 / rate;
403
404 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
405 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
406 & ~DWC3_GFLADJ_240MHZDECR
407 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
408 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
409 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
410 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
411 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
412 }
413
414 /**
415 * dwc3_free_one_event_buffer - Frees one event buffer
416 * @dwc: Pointer to our controller context structure
417 * @evt: Pointer to event buffer to be freed
418 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)419 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
420 struct dwc3_event_buffer *evt)
421 {
422 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
423 }
424
425 /**
426 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
427 * @dwc: Pointer to our controller context structure
428 * @length: size of the event buffer
429 *
430 * Returns a pointer to the allocated event buffer structure on success
431 * otherwise ERR_PTR(errno).
432 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)433 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
434 unsigned length)
435 {
436 struct dwc3_event_buffer *evt;
437
438 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
439 if (!evt)
440 return ERR_PTR(-ENOMEM);
441
442 evt->dwc = dwc;
443 evt->length = length;
444 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
445 if (!evt->cache)
446 return ERR_PTR(-ENOMEM);
447
448 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
449 &evt->dma, GFP_KERNEL);
450 if (!evt->buf)
451 return ERR_PTR(-ENOMEM);
452
453 return evt;
454 }
455
456 /**
457 * dwc3_free_event_buffers - frees all allocated event buffers
458 * @dwc: Pointer to our controller context structure
459 */
dwc3_free_event_buffers(struct dwc3 * dwc)460 static void dwc3_free_event_buffers(struct dwc3 *dwc)
461 {
462 struct dwc3_event_buffer *evt;
463
464 evt = dwc->ev_buf;
465 if (evt)
466 dwc3_free_one_event_buffer(dwc, evt);
467 }
468
469 /**
470 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
471 * @dwc: pointer to our controller context structure
472 * @length: size of event buffer
473 *
474 * Returns 0 on success otherwise negative errno. In the error case, dwc
475 * may contain some buffers allocated but not all which were requested.
476 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)477 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
478 {
479 struct dwc3_event_buffer *evt;
480
481 evt = dwc3_alloc_one_event_buffer(dwc, length);
482 if (IS_ERR(evt)) {
483 dev_err(dwc->dev, "can't allocate event buffer\n");
484 return PTR_ERR(evt);
485 }
486 dwc->ev_buf = evt;
487
488 return 0;
489 }
490
491 /**
492 * dwc3_event_buffers_setup - setup our allocated event buffers
493 * @dwc: pointer to our controller context structure
494 *
495 * Returns 0 on success otherwise negative errno.
496 */
dwc3_event_buffers_setup(struct dwc3 * dwc)497 int dwc3_event_buffers_setup(struct dwc3 *dwc)
498 {
499 struct dwc3_event_buffer *evt;
500
501 evt = dwc->ev_buf;
502 evt->lpos = 0;
503 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
504 lower_32_bits(evt->dma));
505 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
506 upper_32_bits(evt->dma));
507 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
508 DWC3_GEVNTSIZ_SIZE(evt->length));
509 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
510
511 return 0;
512 }
513
dwc3_event_buffers_cleanup(struct dwc3 * dwc)514 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
515 {
516 struct dwc3_event_buffer *evt;
517
518 evt = dwc->ev_buf;
519
520 evt->lpos = 0;
521
522 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
523 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
524 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
525 | DWC3_GEVNTSIZ_SIZE(0));
526 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
527 }
528
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)529 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
530 {
531 if (!dwc->has_hibernation)
532 return 0;
533
534 if (!dwc->nr_scratch)
535 return 0;
536
537 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
538 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
539 if (!dwc->scratchbuf)
540 return -ENOMEM;
541
542 return 0;
543 }
544
dwc3_setup_scratch_buffers(struct dwc3 * dwc)545 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
546 {
547 dma_addr_t scratch_addr;
548 u32 param;
549 int ret;
550
551 if (!dwc->has_hibernation)
552 return 0;
553
554 if (!dwc->nr_scratch)
555 return 0;
556
557 /* should never fall here */
558 if (!WARN_ON(dwc->scratchbuf))
559 return 0;
560
561 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
562 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
563 DMA_BIDIRECTIONAL);
564 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
565 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
566 ret = -EFAULT;
567 goto err0;
568 }
569
570 dwc->scratch_addr = scratch_addr;
571
572 param = lower_32_bits(scratch_addr);
573
574 ret = dwc3_send_gadget_generic_command(dwc,
575 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
576 if (ret < 0)
577 goto err1;
578
579 param = upper_32_bits(scratch_addr);
580
581 ret = dwc3_send_gadget_generic_command(dwc,
582 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
583 if (ret < 0)
584 goto err1;
585
586 return 0;
587
588 err1:
589 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
590 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
591
592 err0:
593 return ret;
594 }
595
dwc3_free_scratch_buffers(struct dwc3 * dwc)596 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
597 {
598 if (!dwc->has_hibernation)
599 return;
600
601 if (!dwc->nr_scratch)
602 return;
603
604 /* should never fall here */
605 if (!WARN_ON(dwc->scratchbuf))
606 return;
607
608 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
609 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
610 kfree(dwc->scratchbuf);
611 }
612
dwc3_core_num_eps(struct dwc3 * dwc)613 static void dwc3_core_num_eps(struct dwc3 *dwc)
614 {
615 struct dwc3_hwparams *parms = &dwc->hwparams;
616
617 dwc->num_eps = DWC3_NUM_EPS(parms);
618 }
619
dwc3_cache_hwparams(struct dwc3 * dwc)620 static void dwc3_cache_hwparams(struct dwc3 *dwc)
621 {
622 struct dwc3_hwparams *parms = &dwc->hwparams;
623
624 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
625 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
626 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
627 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
628 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
629 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
630 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
631 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
632 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
633
634 if (DWC3_IP_IS(DWC32))
635 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
636 }
637
dwc3_core_ulpi_init(struct dwc3 * dwc)638 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
639 {
640 int intf;
641 int ret = 0;
642
643 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
644
645 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
646 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
647 dwc->hsphy_interface &&
648 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
649 ret = dwc3_ulpi_init(dwc);
650
651 return ret;
652 }
653
654 /**
655 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
656 * @dwc: Pointer to our controller context structure
657 *
658 * Returns 0 on success. The USB PHY interfaces are configured but not
659 * initialized. The PHY interfaces and the PHYs get initialized together with
660 * the core in dwc3_core_init.
661 */
dwc3_phy_setup(struct dwc3 * dwc)662 static int dwc3_phy_setup(struct dwc3 *dwc)
663 {
664 unsigned int hw_mode;
665 u32 reg;
666
667 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
668
669 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
670
671 /*
672 * Make sure UX_EXIT_PX is cleared as that causes issues with some
673 * PHYs. Also, this bit is not supposed to be used in normal operation.
674 */
675 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
676
677 /*
678 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
679 * to '0' during coreConsultant configuration. So default value
680 * will be '0' when the core is reset. Application needs to set it
681 * to '1' after the core initialization is completed.
682 */
683 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
684 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
685
686 /*
687 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
688 * power-on reset, and it can be set after core initialization, which is
689 * after device soft-reset during initialization.
690 */
691 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
692 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
693
694 if (dwc->u2ss_inp3_quirk)
695 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
696
697 if (dwc->dis_rxdet_inp3_quirk)
698 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
699
700 if (dwc->req_p1p2p3_quirk)
701 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
702
703 if (dwc->del_p1p2p3_quirk)
704 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
705
706 if (dwc->del_phy_power_chg_quirk)
707 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
708
709 if (dwc->lfps_filter_quirk)
710 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
711
712 if (dwc->rx_detect_poll_quirk)
713 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
714
715 if (dwc->tx_de_emphasis_quirk)
716 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
717
718 if (dwc->dis_u3_susphy_quirk)
719 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
720
721 if (dwc->dis_del_phy_power_chg_quirk)
722 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
723
724 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
725
726 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
727
728 /* Select the HS PHY interface */
729 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
730 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
731 if (dwc->hsphy_interface &&
732 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
733 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
734 break;
735 } else if (dwc->hsphy_interface &&
736 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
737 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
738 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
739 } else {
740 /* Relying on default value. */
741 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
742 break;
743 }
744 fallthrough;
745 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
746 default:
747 break;
748 }
749
750 switch (dwc->hsphy_mode) {
751 case USBPHY_INTERFACE_MODE_UTMI:
752 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
753 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
754 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
755 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
756 break;
757 case USBPHY_INTERFACE_MODE_UTMIW:
758 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
759 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
760 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
761 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
762 break;
763 default:
764 break;
765 }
766
767 /*
768 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
769 * '0' during coreConsultant configuration. So default value will
770 * be '0' when the core is reset. Application needs to set it to
771 * '1' after the core initialization is completed.
772 */
773 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
774 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
775
776 /*
777 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
778 * power-on reset, and it can be set after core initialization, which is
779 * after device soft-reset during initialization.
780 */
781 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
782 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
783
784 if (dwc->dis_u2_susphy_quirk)
785 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
786
787 if (dwc->dis_enblslpm_quirk)
788 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
789 else
790 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
791
792 if (dwc->dis_u2_freeclk_exists_quirk)
793 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
794
795 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
796
797 return 0;
798 }
799
dwc3_clk_enable(struct dwc3 * dwc)800 static int dwc3_clk_enable(struct dwc3 *dwc)
801 {
802 int ret;
803
804 ret = clk_prepare_enable(dwc->bus_clk);
805 if (ret)
806 return ret;
807
808 ret = clk_prepare_enable(dwc->ref_clk);
809 if (ret)
810 goto disable_bus_clk;
811
812 ret = clk_prepare_enable(dwc->susp_clk);
813 if (ret)
814 goto disable_ref_clk;
815
816 return 0;
817
818 disable_ref_clk:
819 clk_disable_unprepare(dwc->ref_clk);
820 disable_bus_clk:
821 clk_disable_unprepare(dwc->bus_clk);
822 return ret;
823 }
824
dwc3_clk_disable(struct dwc3 * dwc)825 static void dwc3_clk_disable(struct dwc3 *dwc)
826 {
827 clk_disable_unprepare(dwc->susp_clk);
828 clk_disable_unprepare(dwc->ref_clk);
829 clk_disable_unprepare(dwc->bus_clk);
830 }
831
dwc3_core_exit(struct dwc3 * dwc)832 static void dwc3_core_exit(struct dwc3 *dwc)
833 {
834 dwc3_event_buffers_cleanup(dwc);
835
836 usb_phy_set_suspend(dwc->usb2_phy, 1);
837 usb_phy_set_suspend(dwc->usb3_phy, 1);
838 phy_power_off(dwc->usb2_generic_phy);
839 phy_power_off(dwc->usb3_generic_phy);
840
841 usb_phy_shutdown(dwc->usb2_phy);
842 usb_phy_shutdown(dwc->usb3_phy);
843 phy_exit(dwc->usb2_generic_phy);
844 phy_exit(dwc->usb3_generic_phy);
845
846 dwc3_clk_disable(dwc);
847 reset_control_assert(dwc->reset);
848 }
849
dwc3_core_is_valid(struct dwc3 * dwc)850 static bool dwc3_core_is_valid(struct dwc3 *dwc)
851 {
852 u32 reg;
853
854 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
855 dwc->ip = DWC3_GSNPS_ID(reg);
856
857 /* This should read as U3 followed by revision number */
858 if (DWC3_IP_IS(DWC3)) {
859 dwc->revision = reg;
860 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
861 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
862 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
863 } else {
864 return false;
865 }
866
867 return true;
868 }
869
dwc3_core_setup_global_control(struct dwc3 * dwc)870 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
871 {
872 u32 hwparams4 = dwc->hwparams.hwparams4;
873 u32 reg;
874
875 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
876 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
877
878 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
879 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
880 /**
881 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
882 * issue which would cause xHCI compliance tests to fail.
883 *
884 * Because of that we cannot enable clock gating on such
885 * configurations.
886 *
887 * Refers to:
888 *
889 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
890 * SOF/ITP Mode Used
891 */
892 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
893 dwc->dr_mode == USB_DR_MODE_OTG) &&
894 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
895 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
896 else
897 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
898 break;
899 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
900 /* enable hibernation here */
901 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
902
903 /*
904 * REVISIT Enabling this bit so that host-mode hibernation
905 * will work. Device-mode hibernation is not yet implemented.
906 */
907 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
908 break;
909 default:
910 /* nothing */
911 break;
912 }
913
914 /* check if current dwc3 is on simulation board */
915 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
916 dev_info(dwc->dev, "Running with FPGA optimizations\n");
917 dwc->is_fpga = true;
918 }
919
920 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
921 "disable_scramble cannot be used on non-FPGA builds\n");
922
923 if (dwc->disable_scramble_quirk && dwc->is_fpga)
924 reg |= DWC3_GCTL_DISSCRAMBLE;
925 else
926 reg &= ~DWC3_GCTL_DISSCRAMBLE;
927
928 if (dwc->u2exit_lfps_quirk)
929 reg |= DWC3_GCTL_U2EXIT_LFPS;
930
931 /*
932 * WORKAROUND: DWC3 revisions <1.90a have a bug
933 * where the device can fail to connect at SuperSpeed
934 * and falls back to high-speed mode which causes
935 * the device to enter a Connect/Disconnect loop
936 */
937 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
938 reg |= DWC3_GCTL_U2RSTECN;
939
940 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
941 }
942
943 static int dwc3_core_get_phy(struct dwc3 *dwc);
944 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
945
946 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)947 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
948 {
949 struct device *dev = dwc->dev;
950 /* incrx_mode : for INCR burst type. */
951 bool incrx_mode;
952 /* incrx_size : for size of INCRX burst. */
953 u32 incrx_size;
954 u32 *vals;
955 u32 cfg;
956 int ntype;
957 int ret;
958 int i;
959
960 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
961
962 /*
963 * Handle property "snps,incr-burst-type-adjustment".
964 * Get the number of value from this property:
965 * result <= 0, means this property is not supported.
966 * result = 1, means INCRx burst mode supported.
967 * result > 1, means undefined length burst mode supported.
968 */
969 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
970 if (ntype <= 0)
971 return;
972
973 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
974 if (!vals)
975 return;
976
977 /* Get INCR burst type, and parse it */
978 ret = device_property_read_u32_array(dev,
979 "snps,incr-burst-type-adjustment", vals, ntype);
980 if (ret) {
981 kfree(vals);
982 dev_err(dev, "Error to get property\n");
983 return;
984 }
985
986 incrx_size = *vals;
987
988 if (ntype > 1) {
989 /* INCRX (undefined length) burst mode */
990 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
991 for (i = 1; i < ntype; i++) {
992 if (vals[i] > incrx_size)
993 incrx_size = vals[i];
994 }
995 } else {
996 /* INCRX burst mode */
997 incrx_mode = INCRX_BURST_MODE;
998 }
999
1000 kfree(vals);
1001
1002 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1003 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1004 if (incrx_mode)
1005 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1006 switch (incrx_size) {
1007 case 256:
1008 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1009 break;
1010 case 128:
1011 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1012 break;
1013 case 64:
1014 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1015 break;
1016 case 32:
1017 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1018 break;
1019 case 16:
1020 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1021 break;
1022 case 8:
1023 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1024 break;
1025 case 4:
1026 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1027 break;
1028 case 1:
1029 break;
1030 default:
1031 dev_err(dev, "Invalid property\n");
1032 break;
1033 }
1034
1035 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1036 }
1037
1038 /**
1039 * dwc3_core_init - Low-level initialization of DWC3 Core
1040 * @dwc: Pointer to our controller context structure
1041 *
1042 * Returns 0 on success otherwise negative errno.
1043 */
dwc3_core_init(struct dwc3 * dwc)1044 static int dwc3_core_init(struct dwc3 *dwc)
1045 {
1046 unsigned int hw_mode;
1047 u32 reg;
1048 int ret;
1049
1050 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1051
1052 /*
1053 * Write Linux Version Code to our GUID register so it's easy to figure
1054 * out which kernel version a bug was found.
1055 */
1056 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1057
1058 ret = dwc3_phy_setup(dwc);
1059 if (ret)
1060 goto err0;
1061
1062 if (!dwc->ulpi_ready) {
1063 ret = dwc3_core_ulpi_init(dwc);
1064 if (ret)
1065 goto err0;
1066 dwc->ulpi_ready = true;
1067 }
1068
1069 if (!dwc->phys_ready) {
1070 ret = dwc3_core_get_phy(dwc);
1071 if (ret)
1072 goto err0a;
1073 dwc->phys_ready = true;
1074 }
1075
1076 usb_phy_init(dwc->usb2_phy);
1077 usb_phy_init(dwc->usb3_phy);
1078 ret = phy_init(dwc->usb2_generic_phy);
1079 if (ret < 0)
1080 goto err0a;
1081
1082 ret = phy_init(dwc->usb3_generic_phy);
1083 if (ret < 0) {
1084 phy_exit(dwc->usb2_generic_phy);
1085 goto err0a;
1086 }
1087
1088 ret = dwc3_core_soft_reset(dwc);
1089 if (ret)
1090 goto err1;
1091
1092 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1093 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1094 if (!dwc->dis_u3_susphy_quirk) {
1095 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1096 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1097 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1098 }
1099
1100 if (!dwc->dis_u2_susphy_quirk) {
1101 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1102 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1103 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1104 }
1105 }
1106
1107 dwc3_core_setup_global_control(dwc);
1108 dwc3_core_num_eps(dwc);
1109
1110 ret = dwc3_setup_scratch_buffers(dwc);
1111 if (ret)
1112 goto err1;
1113
1114 /* Adjust Frame Length */
1115 dwc3_frame_length_adjustment(dwc);
1116
1117 /* Adjust Reference Clock Period */
1118 dwc3_ref_clk_period(dwc);
1119
1120 dwc3_set_incr_burst_type(dwc);
1121
1122 usb_phy_set_suspend(dwc->usb2_phy, 0);
1123 usb_phy_set_suspend(dwc->usb3_phy, 0);
1124 ret = phy_power_on(dwc->usb2_generic_phy);
1125 if (ret < 0)
1126 goto err2;
1127
1128 ret = phy_power_on(dwc->usb3_generic_phy);
1129 if (ret < 0)
1130 goto err3;
1131
1132 ret = dwc3_event_buffers_setup(dwc);
1133 if (ret) {
1134 dev_err(dwc->dev, "failed to setup event buffers\n");
1135 goto err4;
1136 }
1137
1138 /*
1139 * ENDXFER polling is available on version 3.10a and later of
1140 * the DWC_usb3 controller. It is NOT available in the
1141 * DWC_usb31 controller.
1142 */
1143 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1144 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1145 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1146 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1147 }
1148
1149 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1150 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1151
1152 /*
1153 * Enable hardware control of sending remote wakeup
1154 * in HS when the device is in the L1 state.
1155 */
1156 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1157 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1158
1159 /*
1160 * Decouple USB 2.0 L1 & L2 events which will allow for
1161 * gadget driver to only receive U3/L2 suspend & wakeup
1162 * events and prevent the more frequent L1 LPM transitions
1163 * from interrupting the driver.
1164 */
1165 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1166 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1167
1168 if (dwc->dis_tx_ipgap_linecheck_quirk)
1169 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1170
1171 if (dwc->parkmode_disable_ss_quirk)
1172 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1173
1174 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1175 (dwc->maximum_speed == USB_SPEED_HIGH ||
1176 dwc->maximum_speed == USB_SPEED_FULL))
1177 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1178
1179 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1180 }
1181
1182 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1183 dwc->dr_mode == USB_DR_MODE_OTG) {
1184 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1185
1186 /*
1187 * Enable Auto retry Feature to make the controller operating in
1188 * Host mode on seeing transaction errors(CRC errors or internal
1189 * overrun scenerios) on IN transfers to reply to the device
1190 * with a non-terminating retry ACK (i.e, an ACK transcation
1191 * packet with Retry=1 & Nump != 0)
1192 */
1193 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1194
1195 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1196 }
1197
1198 /*
1199 * Must config both number of packets and max burst settings to enable
1200 * RX and/or TX threshold.
1201 */
1202 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1203 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1204 u8 rx_maxburst = dwc->rx_max_burst_prd;
1205 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1206 u8 tx_maxburst = dwc->tx_max_burst_prd;
1207
1208 if (rx_thr_num && rx_maxburst) {
1209 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1210 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1211
1212 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1213 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1214
1215 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1216 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1217
1218 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1219 }
1220
1221 if (tx_thr_num && tx_maxburst) {
1222 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1223 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1224
1225 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1226 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1227
1228 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1229 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1230
1231 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1232 }
1233 }
1234
1235 return 0;
1236
1237 err4:
1238 phy_power_off(dwc->usb3_generic_phy);
1239
1240 err3:
1241 phy_power_off(dwc->usb2_generic_phy);
1242
1243 err2:
1244 usb_phy_set_suspend(dwc->usb2_phy, 1);
1245 usb_phy_set_suspend(dwc->usb3_phy, 1);
1246
1247 err1:
1248 usb_phy_shutdown(dwc->usb2_phy);
1249 usb_phy_shutdown(dwc->usb3_phy);
1250 phy_exit(dwc->usb2_generic_phy);
1251 phy_exit(dwc->usb3_generic_phy);
1252
1253 err0a:
1254 dwc3_ulpi_exit(dwc);
1255
1256 err0:
1257 return ret;
1258 }
1259
dwc3_core_get_phy(struct dwc3 * dwc)1260 static int dwc3_core_get_phy(struct dwc3 *dwc)
1261 {
1262 struct device *dev = dwc->dev;
1263 struct device_node *node = dev->of_node;
1264 int ret;
1265
1266 if (node) {
1267 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1268 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1269 } else {
1270 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1271 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1272 }
1273
1274 if (IS_ERR(dwc->usb2_phy)) {
1275 ret = PTR_ERR(dwc->usb2_phy);
1276 if (ret == -ENXIO || ret == -ENODEV)
1277 dwc->usb2_phy = NULL;
1278 else
1279 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1280 }
1281
1282 if (IS_ERR(dwc->usb3_phy)) {
1283 ret = PTR_ERR(dwc->usb3_phy);
1284 if (ret == -ENXIO || ret == -ENODEV)
1285 dwc->usb3_phy = NULL;
1286 else
1287 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1288 }
1289
1290 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1291 if (IS_ERR(dwc->usb2_generic_phy)) {
1292 ret = PTR_ERR(dwc->usb2_generic_phy);
1293 if (ret == -ENOSYS || ret == -ENODEV)
1294 dwc->usb2_generic_phy = NULL;
1295 else
1296 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1297 }
1298
1299 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1300 if (IS_ERR(dwc->usb3_generic_phy)) {
1301 ret = PTR_ERR(dwc->usb3_generic_phy);
1302 if (ret == -ENOSYS || ret == -ENODEV)
1303 dwc->usb3_generic_phy = NULL;
1304 else
1305 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1306 }
1307
1308 return 0;
1309 }
1310
dwc3_core_init_mode(struct dwc3 * dwc)1311 static int dwc3_core_init_mode(struct dwc3 *dwc)
1312 {
1313 struct device *dev = dwc->dev;
1314 int ret;
1315
1316 switch (dwc->dr_mode) {
1317 case USB_DR_MODE_PERIPHERAL:
1318 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1319
1320 if (dwc->usb2_phy)
1321 otg_set_vbus(dwc->usb2_phy->otg, false);
1322 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1323 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1324
1325 ret = dwc3_gadget_init(dwc);
1326 if (ret)
1327 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1328 break;
1329 case USB_DR_MODE_HOST:
1330 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1331
1332 if (dwc->usb2_phy)
1333 otg_set_vbus(dwc->usb2_phy->otg, true);
1334 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1335 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1336
1337 ret = dwc3_host_init(dwc);
1338 if (ret)
1339 return dev_err_probe(dev, ret, "failed to initialize host\n");
1340 break;
1341 case USB_DR_MODE_OTG:
1342 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1343 ret = dwc3_drd_init(dwc);
1344 if (ret)
1345 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1346 break;
1347 default:
1348 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1349 return -EINVAL;
1350 }
1351
1352 return 0;
1353 }
1354
dwc3_core_exit_mode(struct dwc3 * dwc)1355 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1356 {
1357 switch (dwc->dr_mode) {
1358 case USB_DR_MODE_PERIPHERAL:
1359 dwc3_gadget_exit(dwc);
1360 break;
1361 case USB_DR_MODE_HOST:
1362 dwc3_host_exit(dwc);
1363 break;
1364 case USB_DR_MODE_OTG:
1365 dwc3_drd_exit(dwc);
1366 break;
1367 default:
1368 /* do nothing */
1369 break;
1370 }
1371
1372 /* de-assert DRVVBUS for HOST and OTG mode */
1373 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1374 }
1375
dwc3_get_properties(struct dwc3 * dwc)1376 static void dwc3_get_properties(struct dwc3 *dwc)
1377 {
1378 struct device *dev = dwc->dev;
1379 u8 lpm_nyet_threshold;
1380 u8 tx_de_emphasis;
1381 u8 hird_threshold;
1382 u8 rx_thr_num_pkt_prd = 0;
1383 u8 rx_max_burst_prd = 0;
1384 u8 tx_thr_num_pkt_prd = 0;
1385 u8 tx_max_burst_prd = 0;
1386 u8 tx_fifo_resize_max_num;
1387 const char *usb_psy_name;
1388 int ret;
1389
1390 /* default to highest possible threshold */
1391 lpm_nyet_threshold = 0xf;
1392
1393 /* default to -3.5dB de-emphasis */
1394 tx_de_emphasis = 1;
1395
1396 /*
1397 * default to assert utmi_sleep_n and use maximum allowed HIRD
1398 * threshold value of 0b1100
1399 */
1400 hird_threshold = 12;
1401
1402 /*
1403 * default to a TXFIFO size large enough to fit 6 max packets. This
1404 * allows for systems with larger bus latencies to have some headroom
1405 * for endpoints that have a large bMaxBurst value.
1406 */
1407 tx_fifo_resize_max_num = 6;
1408
1409 dwc->maximum_speed = usb_get_maximum_speed(dev);
1410 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1411 dwc->dr_mode = usb_get_dr_mode(dev);
1412 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1413
1414 dwc->sysdev_is_parent = device_property_read_bool(dev,
1415 "linux,sysdev_is_parent");
1416 if (dwc->sysdev_is_parent)
1417 dwc->sysdev = dwc->dev->parent;
1418 else
1419 dwc->sysdev = dwc->dev;
1420
1421 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1422 if (ret >= 0) {
1423 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1424 if (!dwc->usb_psy)
1425 dev_err(dev, "couldn't get usb power supply\n");
1426 }
1427
1428 dwc->has_lpm_erratum = device_property_read_bool(dev,
1429 "snps,has-lpm-erratum");
1430 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1431 &lpm_nyet_threshold);
1432 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1433 "snps,is-utmi-l1-suspend");
1434 device_property_read_u8(dev, "snps,hird-threshold",
1435 &hird_threshold);
1436 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1437 "snps,dis-start-transfer-quirk");
1438 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1439 "snps,usb3_lpm_capable");
1440 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1441 "snps,usb2-lpm-disable");
1442 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1443 "snps,usb2-gadget-lpm-disable");
1444 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1445 &rx_thr_num_pkt_prd);
1446 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1447 &rx_max_burst_prd);
1448 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1449 &tx_thr_num_pkt_prd);
1450 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1451 &tx_max_burst_prd);
1452 dwc->do_fifo_resize = device_property_read_bool(dev,
1453 "tx-fifo-resize");
1454 if (dwc->do_fifo_resize)
1455 device_property_read_u8(dev, "tx-fifo-max-num",
1456 &tx_fifo_resize_max_num);
1457
1458 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1459 "snps,disable_scramble_quirk");
1460 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1461 "snps,u2exit_lfps_quirk");
1462 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1463 "snps,u2ss_inp3_quirk");
1464 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1465 "snps,req_p1p2p3_quirk");
1466 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1467 "snps,del_p1p2p3_quirk");
1468 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1469 "snps,del_phy_power_chg_quirk");
1470 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1471 "snps,lfps_filter_quirk");
1472 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1473 "snps,rx_detect_poll_quirk");
1474 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1475 "snps,dis_u3_susphy_quirk");
1476 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1477 "snps,dis_u2_susphy_quirk");
1478 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1479 "snps,dis_enblslpm_quirk");
1480 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1481 "snps,dis-u1-entry-quirk");
1482 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1483 "snps,dis-u2-entry-quirk");
1484 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1485 "snps,dis_rxdet_inp3_quirk");
1486 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1487 "snps,dis-u2-freeclk-exists-quirk");
1488 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1489 "snps,dis-del-phy-power-chg-quirk");
1490 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1491 "snps,dis-tx-ipgap-linecheck-quirk");
1492 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1493 "snps,parkmode-disable-ss-quirk");
1494
1495 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1496 "snps,tx_de_emphasis_quirk");
1497 device_property_read_u8(dev, "snps,tx_de_emphasis",
1498 &tx_de_emphasis);
1499 device_property_read_string(dev, "snps,hsphy_interface",
1500 &dwc->hsphy_interface);
1501 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1502 &dwc->fladj);
1503 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1504 &dwc->ref_clk_per);
1505
1506 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1507 "snps,dis_metastability_quirk");
1508
1509 dwc->dis_split_quirk = device_property_read_bool(dev,
1510 "snps,dis-split-quirk");
1511
1512 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1513 dwc->tx_de_emphasis = tx_de_emphasis;
1514
1515 dwc->hird_threshold = hird_threshold;
1516
1517 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1518 dwc->rx_max_burst_prd = rx_max_burst_prd;
1519
1520 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1521 dwc->tx_max_burst_prd = tx_max_burst_prd;
1522
1523 dwc->imod_interval = 0;
1524
1525 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1526 }
1527
1528 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1529 bool dwc3_has_imod(struct dwc3 *dwc)
1530 {
1531 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1532 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1533 DWC3_IP_IS(DWC32);
1534 }
1535
dwc3_check_params(struct dwc3 * dwc)1536 static void dwc3_check_params(struct dwc3 *dwc)
1537 {
1538 struct device *dev = dwc->dev;
1539 unsigned int hwparam_gen =
1540 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1541
1542 /* Check for proper value of imod_interval */
1543 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1544 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1545 dwc->imod_interval = 0;
1546 }
1547
1548 /*
1549 * Workaround for STAR 9000961433 which affects only version
1550 * 3.00a of the DWC_usb3 core. This prevents the controller
1551 * interrupt from being masked while handling events. IMOD
1552 * allows us to work around this issue. Enable it for the
1553 * affected version.
1554 */
1555 if (!dwc->imod_interval &&
1556 DWC3_VER_IS(DWC3, 300A))
1557 dwc->imod_interval = 1;
1558
1559 /* Check the maximum_speed parameter */
1560 switch (dwc->maximum_speed) {
1561 case USB_SPEED_FULL:
1562 case USB_SPEED_HIGH:
1563 break;
1564 case USB_SPEED_SUPER:
1565 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1566 dev_warn(dev, "UDC doesn't support Gen 1\n");
1567 break;
1568 case USB_SPEED_SUPER_PLUS:
1569 if ((DWC3_IP_IS(DWC32) &&
1570 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1571 (!DWC3_IP_IS(DWC32) &&
1572 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1573 dev_warn(dev, "UDC doesn't support SSP\n");
1574 break;
1575 default:
1576 dev_err(dev, "invalid maximum_speed parameter %d\n",
1577 dwc->maximum_speed);
1578 fallthrough;
1579 case USB_SPEED_UNKNOWN:
1580 switch (hwparam_gen) {
1581 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1582 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1583 break;
1584 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1585 if (DWC3_IP_IS(DWC32))
1586 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1587 else
1588 dwc->maximum_speed = USB_SPEED_SUPER;
1589 break;
1590 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1591 dwc->maximum_speed = USB_SPEED_HIGH;
1592 break;
1593 default:
1594 dwc->maximum_speed = USB_SPEED_SUPER;
1595 break;
1596 }
1597 break;
1598 }
1599
1600 /*
1601 * Currently the controller does not have visibility into the HW
1602 * parameter to determine the maximum number of lanes the HW supports.
1603 * If the number of lanes is not specified in the device property, then
1604 * set the default to support dual-lane for DWC_usb32 and single-lane
1605 * for DWC_usb31 for super-speed-plus.
1606 */
1607 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1608 switch (dwc->max_ssp_rate) {
1609 case USB_SSP_GEN_2x1:
1610 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1611 dev_warn(dev, "UDC only supports Gen 1\n");
1612 break;
1613 case USB_SSP_GEN_1x2:
1614 case USB_SSP_GEN_2x2:
1615 if (DWC3_IP_IS(DWC31))
1616 dev_warn(dev, "UDC only supports single lane\n");
1617 break;
1618 case USB_SSP_GEN_UNKNOWN:
1619 default:
1620 switch (hwparam_gen) {
1621 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1622 if (DWC3_IP_IS(DWC32))
1623 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1624 else
1625 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1626 break;
1627 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1628 if (DWC3_IP_IS(DWC32))
1629 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1630 break;
1631 }
1632 break;
1633 }
1634 }
1635 }
1636
dwc3_get_extcon(struct dwc3 * dwc)1637 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1638 {
1639 struct device *dev = dwc->dev;
1640 struct device_node *np_phy;
1641 struct extcon_dev *edev = NULL;
1642 const char *name;
1643
1644 if (device_property_read_bool(dev, "extcon"))
1645 return extcon_get_edev_by_phandle(dev, 0);
1646
1647 /*
1648 * Device tree platforms should get extcon via phandle.
1649 * On ACPI platforms, we get the name from a device property.
1650 * This device property is for kernel internal use only and
1651 * is expected to be set by the glue code.
1652 */
1653 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1654 return extcon_get_extcon_dev(name);
1655
1656 /*
1657 * Try to get an extcon device from the USB PHY controller's "port"
1658 * node. Check if it has the "port" node first, to avoid printing the
1659 * error message from underlying code, as it's a valid case: extcon
1660 * device (and "port" node) may be missing in case of "usb-role-switch"
1661 * or OTG mode.
1662 */
1663 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1664 if (of_graph_is_present(np_phy)) {
1665 struct device_node *np_conn;
1666
1667 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1668 if (np_conn)
1669 edev = extcon_find_edev_by_node(np_conn);
1670 of_node_put(np_conn);
1671 }
1672 of_node_put(np_phy);
1673
1674 return edev;
1675 }
1676
dwc3_probe(struct platform_device * pdev)1677 static int dwc3_probe(struct platform_device *pdev)
1678 {
1679 struct device *dev = &pdev->dev;
1680 struct resource *res, dwc_res;
1681 struct dwc3 *dwc;
1682
1683 int ret;
1684
1685 void __iomem *regs;
1686
1687 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1688 if (!dwc)
1689 return -ENOMEM;
1690
1691 dwc->dev = dev;
1692
1693 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1694 if (!res) {
1695 dev_err(dev, "missing memory resource\n");
1696 return -ENODEV;
1697 }
1698
1699 dwc->xhci_resources[0].start = res->start;
1700 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1701 DWC3_XHCI_REGS_END;
1702 dwc->xhci_resources[0].flags = res->flags;
1703 dwc->xhci_resources[0].name = res->name;
1704
1705 /*
1706 * Request memory region but exclude xHCI regs,
1707 * since it will be requested by the xhci-plat driver.
1708 */
1709 dwc_res = *res;
1710 dwc_res.start += DWC3_GLOBALS_REGS_START;
1711
1712 regs = devm_ioremap_resource(dev, &dwc_res);
1713 if (IS_ERR(regs))
1714 return PTR_ERR(regs);
1715
1716 dwc->regs = regs;
1717 dwc->regs_size = resource_size(&dwc_res);
1718
1719 dwc3_get_properties(dwc);
1720
1721 if (!dwc->sysdev_is_parent) {
1722 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1723 if (ret)
1724 return ret;
1725 }
1726
1727 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1728 if (IS_ERR(dwc->reset))
1729 return PTR_ERR(dwc->reset);
1730
1731 if (dev->of_node) {
1732 /*
1733 * Clocks are optional, but new DT platforms should support all
1734 * clocks as required by the DT-binding.
1735 * Some devices have different clock names in legacy device trees,
1736 * check for them to retain backwards compatibility.
1737 */
1738 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1739 if (IS_ERR(dwc->bus_clk))
1740 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1741 "could not get bus clock\n");
1742
1743 if (dwc->bus_clk == NULL) {
1744 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1745 if (IS_ERR(dwc->bus_clk))
1746 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1747 "could not get bus clock\n");
1748 }
1749
1750 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1751 if (IS_ERR(dwc->ref_clk))
1752 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1753 "could not get ref clock\n");
1754
1755 if (dwc->ref_clk == NULL) {
1756 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1757 if (IS_ERR(dwc->ref_clk))
1758 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1759 "could not get ref clock\n");
1760 }
1761
1762 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1763 if (IS_ERR(dwc->susp_clk))
1764 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1765 "could not get suspend clock\n");
1766
1767 if (dwc->susp_clk == NULL) {
1768 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1769 if (IS_ERR(dwc->susp_clk))
1770 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1771 "could not get suspend clock\n");
1772 }
1773 }
1774
1775 ret = reset_control_deassert(dwc->reset);
1776 if (ret)
1777 return ret;
1778
1779 ret = dwc3_clk_enable(dwc);
1780 if (ret)
1781 goto assert_reset;
1782
1783 if (!dwc3_core_is_valid(dwc)) {
1784 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1785 ret = -ENODEV;
1786 goto disable_clks;
1787 }
1788
1789 platform_set_drvdata(pdev, dwc);
1790 dwc3_cache_hwparams(dwc);
1791
1792 spin_lock_init(&dwc->lock);
1793 mutex_init(&dwc->mutex);
1794
1795 pm_runtime_set_active(dev);
1796 pm_runtime_use_autosuspend(dev);
1797 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1798 pm_runtime_enable(dev);
1799 ret = pm_runtime_get_sync(dev);
1800 if (ret < 0)
1801 goto err1;
1802
1803 pm_runtime_forbid(dev);
1804
1805 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1806 if (ret) {
1807 dev_err(dwc->dev, "failed to allocate event buffers\n");
1808 ret = -ENOMEM;
1809 goto err2;
1810 }
1811
1812 dwc->edev = dwc3_get_extcon(dwc);
1813 if (IS_ERR(dwc->edev)) {
1814 ret = PTR_ERR(dwc->edev);
1815 dev_err_probe(dwc->dev, ret, "failed to get extcon\n");
1816 goto err3;
1817 }
1818
1819 ret = dwc3_get_dr_mode(dwc);
1820 if (ret)
1821 goto err3;
1822
1823 ret = dwc3_alloc_scratch_buffers(dwc);
1824 if (ret)
1825 goto err3;
1826
1827 ret = dwc3_core_init(dwc);
1828 if (ret) {
1829 dev_err_probe(dev, ret, "failed to initialize core\n");
1830 goto err4;
1831 }
1832
1833 dwc3_check_params(dwc);
1834 dwc3_debugfs_init(dwc);
1835
1836 ret = dwc3_core_init_mode(dwc);
1837 if (ret)
1838 goto err5;
1839
1840 pm_runtime_put(dev);
1841
1842 return 0;
1843
1844 err5:
1845 dwc3_debugfs_exit(dwc);
1846 dwc3_event_buffers_cleanup(dwc);
1847
1848 usb_phy_set_suspend(dwc->usb2_phy, 1);
1849 usb_phy_set_suspend(dwc->usb3_phy, 1);
1850 phy_power_off(dwc->usb2_generic_phy);
1851 phy_power_off(dwc->usb3_generic_phy);
1852
1853 usb_phy_shutdown(dwc->usb2_phy);
1854 usb_phy_shutdown(dwc->usb3_phy);
1855 phy_exit(dwc->usb2_generic_phy);
1856 phy_exit(dwc->usb3_generic_phy);
1857
1858 dwc3_ulpi_exit(dwc);
1859
1860 err4:
1861 dwc3_free_scratch_buffers(dwc);
1862
1863 err3:
1864 dwc3_free_event_buffers(dwc);
1865
1866 err2:
1867 pm_runtime_allow(&pdev->dev);
1868
1869 err1:
1870 pm_runtime_put_sync(&pdev->dev);
1871 pm_runtime_disable(&pdev->dev);
1872
1873 disable_clks:
1874 dwc3_clk_disable(dwc);
1875 assert_reset:
1876 reset_control_assert(dwc->reset);
1877
1878 if (dwc->usb_psy)
1879 power_supply_put(dwc->usb_psy);
1880
1881 return ret;
1882 }
1883
dwc3_remove(struct platform_device * pdev)1884 static int dwc3_remove(struct platform_device *pdev)
1885 {
1886 struct dwc3 *dwc = platform_get_drvdata(pdev);
1887
1888 pm_runtime_get_sync(&pdev->dev);
1889
1890 dwc3_core_exit_mode(dwc);
1891 dwc3_debugfs_exit(dwc);
1892
1893 dwc3_core_exit(dwc);
1894 dwc3_ulpi_exit(dwc);
1895
1896 pm_runtime_disable(&pdev->dev);
1897 pm_runtime_put_noidle(&pdev->dev);
1898 pm_runtime_set_suspended(&pdev->dev);
1899
1900 dwc3_free_event_buffers(dwc);
1901 dwc3_free_scratch_buffers(dwc);
1902
1903 if (dwc->usb_psy)
1904 power_supply_put(dwc->usb_psy);
1905
1906 return 0;
1907 }
1908
1909 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1910 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1911 {
1912 int ret;
1913
1914 ret = reset_control_deassert(dwc->reset);
1915 if (ret)
1916 return ret;
1917
1918 ret = dwc3_clk_enable(dwc);
1919 if (ret)
1920 goto assert_reset;
1921
1922 ret = dwc3_core_init(dwc);
1923 if (ret)
1924 goto disable_clks;
1925
1926 return 0;
1927
1928 disable_clks:
1929 dwc3_clk_disable(dwc);
1930 assert_reset:
1931 reset_control_assert(dwc->reset);
1932
1933 return ret;
1934 }
1935
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1936 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1937 {
1938 unsigned long flags;
1939 u32 reg;
1940
1941 switch (dwc->current_dr_role) {
1942 case DWC3_GCTL_PRTCAP_DEVICE:
1943 if (pm_runtime_suspended(dwc->dev))
1944 break;
1945 spin_lock_irqsave(&dwc->lock, flags);
1946 dwc3_gadget_suspend(dwc);
1947 spin_unlock_irqrestore(&dwc->lock, flags);
1948 synchronize_irq(dwc->irq_gadget);
1949 dwc3_core_exit(dwc);
1950 break;
1951 case DWC3_GCTL_PRTCAP_HOST:
1952 if (!PMSG_IS_AUTO(msg)) {
1953 dwc3_core_exit(dwc);
1954 break;
1955 }
1956
1957 /* Let controller to suspend HSPHY before PHY driver suspends */
1958 if (dwc->dis_u2_susphy_quirk ||
1959 dwc->dis_enblslpm_quirk) {
1960 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1961 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1962 DWC3_GUSB2PHYCFG_SUSPHY;
1963 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1964
1965 /* Give some time for USB2 PHY to suspend */
1966 usleep_range(5000, 6000);
1967 }
1968
1969 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1970 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1971 break;
1972 case DWC3_GCTL_PRTCAP_OTG:
1973 /* do nothing during runtime_suspend */
1974 if (PMSG_IS_AUTO(msg))
1975 break;
1976
1977 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1978 spin_lock_irqsave(&dwc->lock, flags);
1979 dwc3_gadget_suspend(dwc);
1980 spin_unlock_irqrestore(&dwc->lock, flags);
1981 synchronize_irq(dwc->irq_gadget);
1982 }
1983
1984 dwc3_otg_exit(dwc);
1985 dwc3_core_exit(dwc);
1986 break;
1987 default:
1988 /* do nothing */
1989 break;
1990 }
1991
1992 return 0;
1993 }
1994
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1995 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1996 {
1997 unsigned long flags;
1998 int ret;
1999 u32 reg;
2000
2001 switch (dwc->current_dr_role) {
2002 case DWC3_GCTL_PRTCAP_DEVICE:
2003 ret = dwc3_core_init_for_resume(dwc);
2004 if (ret)
2005 return ret;
2006
2007 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2008 spin_lock_irqsave(&dwc->lock, flags);
2009 dwc3_gadget_resume(dwc);
2010 spin_unlock_irqrestore(&dwc->lock, flags);
2011 break;
2012 case DWC3_GCTL_PRTCAP_HOST:
2013 if (!PMSG_IS_AUTO(msg)) {
2014 ret = dwc3_core_init_for_resume(dwc);
2015 if (ret)
2016 return ret;
2017 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2018 break;
2019 }
2020 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2021 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2022 if (dwc->dis_u2_susphy_quirk)
2023 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2024
2025 if (dwc->dis_enblslpm_quirk)
2026 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2027
2028 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2029
2030 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2031 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2032 break;
2033 case DWC3_GCTL_PRTCAP_OTG:
2034 /* nothing to do on runtime_resume */
2035 if (PMSG_IS_AUTO(msg))
2036 break;
2037
2038 ret = dwc3_core_init_for_resume(dwc);
2039 if (ret)
2040 return ret;
2041
2042 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2043
2044 dwc3_otg_init(dwc);
2045 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2046 dwc3_otg_host_init(dwc);
2047 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2048 spin_lock_irqsave(&dwc->lock, flags);
2049 dwc3_gadget_resume(dwc);
2050 spin_unlock_irqrestore(&dwc->lock, flags);
2051 }
2052
2053 break;
2054 default:
2055 /* do nothing */
2056 break;
2057 }
2058
2059 return 0;
2060 }
2061
dwc3_runtime_checks(struct dwc3 * dwc)2062 static int dwc3_runtime_checks(struct dwc3 *dwc)
2063 {
2064 switch (dwc->current_dr_role) {
2065 case DWC3_GCTL_PRTCAP_DEVICE:
2066 if (dwc->connected)
2067 return -EBUSY;
2068 break;
2069 case DWC3_GCTL_PRTCAP_HOST:
2070 default:
2071 /* do nothing */
2072 break;
2073 }
2074
2075 return 0;
2076 }
2077
dwc3_runtime_suspend(struct device * dev)2078 static int dwc3_runtime_suspend(struct device *dev)
2079 {
2080 struct dwc3 *dwc = dev_get_drvdata(dev);
2081 int ret;
2082
2083 if (dwc3_runtime_checks(dwc))
2084 return -EBUSY;
2085
2086 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2087 if (ret)
2088 return ret;
2089
2090 device_init_wakeup(dev, true);
2091
2092 return 0;
2093 }
2094
dwc3_runtime_resume(struct device * dev)2095 static int dwc3_runtime_resume(struct device *dev)
2096 {
2097 struct dwc3 *dwc = dev_get_drvdata(dev);
2098 int ret;
2099
2100 device_init_wakeup(dev, false);
2101
2102 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2103 if (ret)
2104 return ret;
2105
2106 switch (dwc->current_dr_role) {
2107 case DWC3_GCTL_PRTCAP_DEVICE:
2108 dwc3_gadget_process_pending_events(dwc);
2109 break;
2110 case DWC3_GCTL_PRTCAP_HOST:
2111 default:
2112 /* do nothing */
2113 break;
2114 }
2115
2116 pm_runtime_mark_last_busy(dev);
2117
2118 return 0;
2119 }
2120
dwc3_runtime_idle(struct device * dev)2121 static int dwc3_runtime_idle(struct device *dev)
2122 {
2123 struct dwc3 *dwc = dev_get_drvdata(dev);
2124
2125 switch (dwc->current_dr_role) {
2126 case DWC3_GCTL_PRTCAP_DEVICE:
2127 if (dwc3_runtime_checks(dwc))
2128 return -EBUSY;
2129 break;
2130 case DWC3_GCTL_PRTCAP_HOST:
2131 default:
2132 /* do nothing */
2133 break;
2134 }
2135
2136 pm_runtime_mark_last_busy(dev);
2137 pm_runtime_autosuspend(dev);
2138
2139 return 0;
2140 }
2141 #endif /* CONFIG_PM */
2142
2143 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2144 static int dwc3_suspend(struct device *dev)
2145 {
2146 struct dwc3 *dwc = dev_get_drvdata(dev);
2147 int ret;
2148
2149 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2150 if (ret)
2151 return ret;
2152
2153 pinctrl_pm_select_sleep_state(dev);
2154
2155 return 0;
2156 }
2157
dwc3_resume(struct device * dev)2158 static int dwc3_resume(struct device *dev)
2159 {
2160 struct dwc3 *dwc = dev_get_drvdata(dev);
2161 int ret;
2162
2163 pinctrl_pm_select_default_state(dev);
2164
2165 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2166 if (ret)
2167 return ret;
2168
2169 pm_runtime_disable(dev);
2170 pm_runtime_set_active(dev);
2171 pm_runtime_enable(dev);
2172
2173 return 0;
2174 }
2175
dwc3_complete(struct device * dev)2176 static void dwc3_complete(struct device *dev)
2177 {
2178 struct dwc3 *dwc = dev_get_drvdata(dev);
2179 u32 reg;
2180
2181 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2182 dwc->dis_split_quirk) {
2183 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2184 reg |= DWC3_GUCTL3_SPLITDISABLE;
2185 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2186 }
2187 }
2188 #else
2189 #define dwc3_complete NULL
2190 #endif /* CONFIG_PM_SLEEP */
2191
2192 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2193 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2194 .complete = dwc3_complete,
2195 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2196 dwc3_runtime_idle)
2197 };
2198
2199 #ifdef CONFIG_OF
2200 static const struct of_device_id of_dwc3_match[] = {
2201 {
2202 .compatible = "snps,dwc3"
2203 },
2204 {
2205 .compatible = "synopsys,dwc3"
2206 },
2207 { },
2208 };
2209 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2210 #endif
2211
2212 #ifdef CONFIG_ACPI
2213
2214 #define ACPI_ID_INTEL_BSW "808622B7"
2215
2216 static const struct acpi_device_id dwc3_acpi_match[] = {
2217 { ACPI_ID_INTEL_BSW, 0 },
2218 { },
2219 };
2220 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2221 #endif
2222
2223 static struct platform_driver dwc3_driver = {
2224 .probe = dwc3_probe,
2225 .remove = dwc3_remove,
2226 .driver = {
2227 .name = "dwc3",
2228 .of_match_table = of_match_ptr(of_dwc3_match),
2229 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2230 .pm = &dwc3_dev_pm_ops,
2231 },
2232 };
2233
2234 module_platform_driver(dwc3_driver);
2235
2236 MODULE_ALIAS("platform:dwc3");
2237 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2238 MODULE_LICENSE("GPL v2");
2239 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2240