1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44
45 /**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
dwc3_get_dr_mode(struct dwc3 * dwc)49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
50 {
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
83
84 /*
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
88 */
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105 }
106
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
108 {
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
115
116 dwc->current_dr_role = mode;
117 }
118
__dwc3_set_mode(struct work_struct * work)119 static void __dwc3_set_mode(struct work_struct *work)
120 {
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
124 u32 reg;
125 u32 desired_dr_role;
126
127 mutex_lock(&dwc->mutex);
128 spin_lock_irqsave(&dwc->lock, flags);
129 desired_dr_role = dwc->desired_dr_role;
130 spin_unlock_irqrestore(&dwc->lock, flags);
131
132 pm_runtime_get_sync(dwc->dev);
133
134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
135 dwc3_otg_update(dwc, 0);
136
137 if (!desired_dr_role)
138 goto out;
139
140 if (desired_dr_role == dwc->current_dr_role)
141 goto out;
142
143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
144 goto out;
145
146 switch (dwc->current_dr_role) {
147 case DWC3_GCTL_PRTCAP_HOST:
148 dwc3_host_exit(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_DEVICE:
151 dwc3_gadget_exit(dwc);
152 dwc3_event_buffers_cleanup(dwc);
153 break;
154 case DWC3_GCTL_PRTCAP_OTG:
155 dwc3_otg_exit(dwc);
156 spin_lock_irqsave(&dwc->lock, flags);
157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
158 spin_unlock_irqrestore(&dwc->lock, flags);
159 dwc3_otg_update(dwc, 1);
160 break;
161 default:
162 break;
163 }
164
165 /*
166 * When current_dr_role is not set, there's no role switching.
167 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
168 */
169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
170 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
172 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
173 reg |= DWC3_GCTL_CORESOFTRESET;
174 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
175
176 /*
177 * Wait for internal clocks to synchronized. DWC_usb31 and
178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
179 * keep it consistent across different IPs, let's wait up to
180 * 100ms before clearing GCTL.CORESOFTRESET.
181 */
182 msleep(100);
183
184 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
185 reg &= ~DWC3_GCTL_CORESOFTRESET;
186 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
187 }
188
189 spin_lock_irqsave(&dwc->lock, flags);
190
191 dwc3_set_prtcap(dwc, desired_dr_role);
192
193 spin_unlock_irqrestore(&dwc->lock, flags);
194
195 switch (desired_dr_role) {
196 case DWC3_GCTL_PRTCAP_HOST:
197 ret = dwc3_host_init(dwc);
198 if (ret) {
199 dev_err(dwc->dev, "failed to initialize host\n");
200 } else {
201 if (dwc->usb2_phy)
202 otg_set_vbus(dwc->usb2_phy->otg, true);
203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
205 if (dwc->dis_split_quirk) {
206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
207 reg |= DWC3_GUCTL3_SPLITDISABLE;
208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
209 }
210 }
211 break;
212 case DWC3_GCTL_PRTCAP_DEVICE:
213 dwc3_core_soft_reset(dwc);
214
215 dwc3_event_buffers_setup(dwc);
216
217 if (dwc->usb2_phy)
218 otg_set_vbus(dwc->usb2_phy->otg, false);
219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
221
222 ret = dwc3_gadget_init(dwc);
223 if (ret)
224 dev_err(dwc->dev, "failed to initialize peripheral\n");
225 break;
226 case DWC3_GCTL_PRTCAP_OTG:
227 dwc3_otg_init(dwc);
228 dwc3_otg_update(dwc, 0);
229 break;
230 default:
231 break;
232 }
233
234 out:
235 pm_runtime_mark_last_busy(dwc->dev);
236 pm_runtime_put_autosuspend(dwc->dev);
237 mutex_unlock(&dwc->mutex);
238 }
239
dwc3_set_mode(struct dwc3 * dwc,u32 mode)240 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
241 {
242 unsigned long flags;
243
244 if (dwc->dr_mode != USB_DR_MODE_OTG)
245 return;
246
247 spin_lock_irqsave(&dwc->lock, flags);
248 dwc->desired_dr_role = mode;
249 spin_unlock_irqrestore(&dwc->lock, flags);
250
251 queue_work(system_freezable_wq, &dwc->drd_work);
252 }
253
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)254 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
255 {
256 struct dwc3 *dwc = dep->dwc;
257 u32 reg;
258
259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
260 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
261 DWC3_GDBGFIFOSPACE_TYPE(type));
262
263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
264
265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
266 }
267
268 /**
269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
270 * @dwc: pointer to our context structure
271 */
dwc3_core_soft_reset(struct dwc3 * dwc)272 int dwc3_core_soft_reset(struct dwc3 *dwc)
273 {
274 u32 reg;
275 int retries = 1000;
276
277 /*
278 * We're resetting only the device side because, if we're in host mode,
279 * XHCI driver will reset the host block. If dwc3 was configured for
280 * host-only mode, then we can return early.
281 */
282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
283 return 0;
284
285 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
286 reg |= DWC3_DCTL_CSFTRST;
287 reg &= ~DWC3_DCTL_RUN_STOP;
288 dwc3_gadget_dctl_write_safe(dwc, reg);
289
290 /*
291 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
292 * is cleared only after all the clocks are synchronized. This can
293 * take a little more than 50ms. Set the polling rate at 20ms
294 * for 10 times instead.
295 */
296 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
297 retries = 10;
298
299 do {
300 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
301 if (!(reg & DWC3_DCTL_CSFTRST))
302 goto done;
303
304 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
305 msleep(20);
306 else
307 udelay(1);
308 } while (--retries);
309
310 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
311 return -ETIMEDOUT;
312
313 done:
314 /*
315 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
316 * is cleared, we must wait at least 50ms before accessing the PHY
317 * domain (synchronization delay).
318 */
319 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
320 msleep(50);
321
322 return 0;
323 }
324
325 /*
326 * dwc3_frame_length_adjustment - Adjusts frame length if required
327 * @dwc3: Pointer to our controller context structure
328 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)329 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
330 {
331 u32 reg;
332 u32 dft;
333
334 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
335 return;
336
337 if (dwc->fladj == 0)
338 return;
339
340 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
341 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
342 if (dft != dwc->fladj) {
343 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
344 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
345 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
346 }
347 }
348
349 /**
350 * dwc3_ref_clk_period - Reference clock period configuration
351 * Default reference clock period depends on hardware
352 * configuration. For systems with reference clock that differs
353 * from the default, this will set clock period in DWC3_GUCTL
354 * register.
355 * @dwc: Pointer to our controller context structure
356 */
dwc3_ref_clk_period(struct dwc3 * dwc)357 static void dwc3_ref_clk_period(struct dwc3 *dwc)
358 {
359 unsigned long period;
360 unsigned long fladj;
361 unsigned long decr;
362 unsigned long rate;
363 u32 reg;
364
365 if (dwc->ref_clk) {
366 rate = clk_get_rate(dwc->ref_clk);
367 if (!rate)
368 return;
369 period = NSEC_PER_SEC / rate;
370 } else if (dwc->ref_clk_per) {
371 period = dwc->ref_clk_per;
372 rate = NSEC_PER_SEC / period;
373 } else {
374 return;
375 }
376
377 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
378 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
379 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
380 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
381
382 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
383 return;
384
385 /*
386 * The calculation below is
387 *
388 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
389 *
390 * but rearranged for fixed-point arithmetic. The division must be
391 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
392 * neither does rate * period).
393 *
394 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
395 * nanoseconds of error caused by the truncation which happened during
396 * the division when calculating rate or period (whichever one was
397 * derived from the other). We first calculate the relative error, then
398 * scale it to units of 8 ppm.
399 */
400 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
401 fladj -= 125000;
402
403 /*
404 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
405 */
406 decr = 480000000 / rate;
407
408 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
409 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
410 & ~DWC3_GFLADJ_240MHZDECR
411 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
412 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
413 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
414 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
415
416 if (dwc->gfladj_refclk_lpm_sel)
417 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
418
419 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
420 }
421
422 /**
423 * dwc3_free_one_event_buffer - Frees one event buffer
424 * @dwc: Pointer to our controller context structure
425 * @evt: Pointer to event buffer to be freed
426 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)427 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
428 struct dwc3_event_buffer *evt)
429 {
430 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
431 }
432
433 /**
434 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
435 * @dwc: Pointer to our controller context structure
436 * @length: size of the event buffer
437 *
438 * Returns a pointer to the allocated event buffer structure on success
439 * otherwise ERR_PTR(errno).
440 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned int length)441 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
442 unsigned int length)
443 {
444 struct dwc3_event_buffer *evt;
445
446 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
447 if (!evt)
448 return ERR_PTR(-ENOMEM);
449
450 evt->dwc = dwc;
451 evt->length = length;
452 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
453 if (!evt->cache)
454 return ERR_PTR(-ENOMEM);
455
456 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
457 &evt->dma, GFP_KERNEL);
458 if (!evt->buf)
459 return ERR_PTR(-ENOMEM);
460
461 return evt;
462 }
463
464 /**
465 * dwc3_free_event_buffers - frees all allocated event buffers
466 * @dwc: Pointer to our controller context structure
467 */
dwc3_free_event_buffers(struct dwc3 * dwc)468 static void dwc3_free_event_buffers(struct dwc3 *dwc)
469 {
470 struct dwc3_event_buffer *evt;
471
472 evt = dwc->ev_buf;
473 if (evt)
474 dwc3_free_one_event_buffer(dwc, evt);
475 }
476
477 /**
478 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
479 * @dwc: pointer to our controller context structure
480 * @length: size of event buffer
481 *
482 * Returns 0 on success otherwise negative errno. In the error case, dwc
483 * may contain some buffers allocated but not all which were requested.
484 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned int length)485 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
486 {
487 struct dwc3_event_buffer *evt;
488
489 evt = dwc3_alloc_one_event_buffer(dwc, length);
490 if (IS_ERR(evt)) {
491 dev_err(dwc->dev, "can't allocate event buffer\n");
492 return PTR_ERR(evt);
493 }
494 dwc->ev_buf = evt;
495
496 return 0;
497 }
498
499 /**
500 * dwc3_event_buffers_setup - setup our allocated event buffers
501 * @dwc: pointer to our controller context structure
502 *
503 * Returns 0 on success otherwise negative errno.
504 */
dwc3_event_buffers_setup(struct dwc3 * dwc)505 int dwc3_event_buffers_setup(struct dwc3 *dwc)
506 {
507 struct dwc3_event_buffer *evt;
508
509 evt = dwc->ev_buf;
510 evt->lpos = 0;
511 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
512 lower_32_bits(evt->dma));
513 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
514 upper_32_bits(evt->dma));
515 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
516 DWC3_GEVNTSIZ_SIZE(evt->length));
517 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
518
519 return 0;
520 }
521
dwc3_event_buffers_cleanup(struct dwc3 * dwc)522 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
523 {
524 struct dwc3_event_buffer *evt;
525
526 evt = dwc->ev_buf;
527
528 evt->lpos = 0;
529
530 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
531 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
532 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
533 | DWC3_GEVNTSIZ_SIZE(0));
534 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
535 }
536
dwc3_core_num_eps(struct dwc3 * dwc)537 static void dwc3_core_num_eps(struct dwc3 *dwc)
538 {
539 struct dwc3_hwparams *parms = &dwc->hwparams;
540
541 dwc->num_eps = DWC3_NUM_EPS(parms);
542 }
543
dwc3_cache_hwparams(struct dwc3 * dwc)544 static void dwc3_cache_hwparams(struct dwc3 *dwc)
545 {
546 struct dwc3_hwparams *parms = &dwc->hwparams;
547
548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
557
558 if (DWC3_IP_IS(DWC32))
559 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
560 }
561
dwc3_core_ulpi_init(struct dwc3 * dwc)562 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
563 {
564 int intf;
565 int ret = 0;
566
567 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
568
569 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
570 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
571 dwc->hsphy_interface &&
572 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
573 ret = dwc3_ulpi_init(dwc);
574
575 return ret;
576 }
577
578 /**
579 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
580 * @dwc: Pointer to our controller context structure
581 *
582 * Returns 0 on success. The USB PHY interfaces are configured but not
583 * initialized. The PHY interfaces and the PHYs get initialized together with
584 * the core in dwc3_core_init.
585 */
dwc3_phy_setup(struct dwc3 * dwc)586 static int dwc3_phy_setup(struct dwc3 *dwc)
587 {
588 unsigned int hw_mode;
589 u32 reg;
590
591 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
592
593 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
594
595 /*
596 * Make sure UX_EXIT_PX is cleared as that causes issues with some
597 * PHYs. Also, this bit is not supposed to be used in normal operation.
598 */
599 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
600
601 /*
602 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
603 * to '0' during coreConsultant configuration. So default value
604 * will be '0' when the core is reset. Application needs to set it
605 * to '1' after the core initialization is completed.
606 */
607 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
608 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
609
610 /*
611 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
612 * power-on reset, and it can be set after core initialization, which is
613 * after device soft-reset during initialization.
614 */
615 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
616 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
617
618 if (dwc->u2ss_inp3_quirk)
619 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
620
621 if (dwc->dis_rxdet_inp3_quirk)
622 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
623
624 if (dwc->req_p1p2p3_quirk)
625 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
626
627 if (dwc->del_p1p2p3_quirk)
628 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
629
630 if (dwc->del_phy_power_chg_quirk)
631 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
632
633 if (dwc->lfps_filter_quirk)
634 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
635
636 if (dwc->rx_detect_poll_quirk)
637 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
638
639 if (dwc->tx_de_emphasis_quirk)
640 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
641
642 if (dwc->dis_u3_susphy_quirk)
643 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
644
645 if (dwc->dis_del_phy_power_chg_quirk)
646 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
647
648 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
649
650 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
651
652 /* Select the HS PHY interface */
653 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
654 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
655 if (dwc->hsphy_interface &&
656 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
657 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
658 break;
659 } else if (dwc->hsphy_interface &&
660 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
661 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
662 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
663 } else {
664 /* Relying on default value. */
665 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
666 break;
667 }
668 fallthrough;
669 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
670 default:
671 break;
672 }
673
674 switch (dwc->hsphy_mode) {
675 case USBPHY_INTERFACE_MODE_UTMI:
676 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
677 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
678 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
679 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
680 break;
681 case USBPHY_INTERFACE_MODE_UTMIW:
682 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
683 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
684 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
685 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
686 break;
687 default:
688 break;
689 }
690
691 /*
692 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
693 * '0' during coreConsultant configuration. So default value will
694 * be '0' when the core is reset. Application needs to set it to
695 * '1' after the core initialization is completed.
696 */
697 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
698 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
699
700 /*
701 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
702 * power-on reset, and it can be set after core initialization, which is
703 * after device soft-reset during initialization.
704 */
705 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
707
708 if (dwc->dis_u2_susphy_quirk)
709 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
710
711 if (dwc->dis_enblslpm_quirk)
712 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
713 else
714 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
715
716 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
717 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
718
719 /*
720 * Some ULPI USB PHY does not support internal VBUS supply, to drive
721 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
722 * bit of OTG_CTRL register. Controller configures the USB2 PHY
723 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
724 * with an external supply.
725 */
726 if (dwc->ulpi_ext_vbus_drv)
727 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
728
729 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
730
731 return 0;
732 }
733
dwc3_phy_init(struct dwc3 * dwc)734 static int dwc3_phy_init(struct dwc3 *dwc)
735 {
736 int ret;
737
738 usb_phy_init(dwc->usb2_phy);
739 usb_phy_init(dwc->usb3_phy);
740
741 ret = phy_init(dwc->usb2_generic_phy);
742 if (ret < 0)
743 goto err_shutdown_usb3_phy;
744
745 ret = phy_init(dwc->usb3_generic_phy);
746 if (ret < 0)
747 goto err_exit_usb2_phy;
748
749 return 0;
750
751 err_exit_usb2_phy:
752 phy_exit(dwc->usb2_generic_phy);
753 err_shutdown_usb3_phy:
754 usb_phy_shutdown(dwc->usb3_phy);
755 usb_phy_shutdown(dwc->usb2_phy);
756
757 return ret;
758 }
759
dwc3_phy_exit(struct dwc3 * dwc)760 static void dwc3_phy_exit(struct dwc3 *dwc)
761 {
762 phy_exit(dwc->usb3_generic_phy);
763 phy_exit(dwc->usb2_generic_phy);
764
765 usb_phy_shutdown(dwc->usb3_phy);
766 usb_phy_shutdown(dwc->usb2_phy);
767 }
768
dwc3_phy_power_on(struct dwc3 * dwc)769 static int dwc3_phy_power_on(struct dwc3 *dwc)
770 {
771 int ret;
772
773 usb_phy_set_suspend(dwc->usb2_phy, 0);
774 usb_phy_set_suspend(dwc->usb3_phy, 0);
775
776 ret = phy_power_on(dwc->usb2_generic_phy);
777 if (ret < 0)
778 goto err_suspend_usb3_phy;
779
780 ret = phy_power_on(dwc->usb3_generic_phy);
781 if (ret < 0)
782 goto err_power_off_usb2_phy;
783
784 return 0;
785
786 err_power_off_usb2_phy:
787 phy_power_off(dwc->usb2_generic_phy);
788 err_suspend_usb3_phy:
789 usb_phy_set_suspend(dwc->usb3_phy, 1);
790 usb_phy_set_suspend(dwc->usb2_phy, 1);
791
792 return ret;
793 }
794
dwc3_phy_power_off(struct dwc3 * dwc)795 static void dwc3_phy_power_off(struct dwc3 *dwc)
796 {
797 phy_power_off(dwc->usb3_generic_phy);
798 phy_power_off(dwc->usb2_generic_phy);
799
800 usb_phy_set_suspend(dwc->usb3_phy, 1);
801 usb_phy_set_suspend(dwc->usb2_phy, 1);
802 }
803
dwc3_clk_enable(struct dwc3 * dwc)804 static int dwc3_clk_enable(struct dwc3 *dwc)
805 {
806 int ret;
807
808 ret = clk_prepare_enable(dwc->bus_clk);
809 if (ret)
810 return ret;
811
812 ret = clk_prepare_enable(dwc->ref_clk);
813 if (ret)
814 goto disable_bus_clk;
815
816 ret = clk_prepare_enable(dwc->susp_clk);
817 if (ret)
818 goto disable_ref_clk;
819
820 return 0;
821
822 disable_ref_clk:
823 clk_disable_unprepare(dwc->ref_clk);
824 disable_bus_clk:
825 clk_disable_unprepare(dwc->bus_clk);
826 return ret;
827 }
828
dwc3_clk_disable(struct dwc3 * dwc)829 static void dwc3_clk_disable(struct dwc3 *dwc)
830 {
831 clk_disable_unprepare(dwc->susp_clk);
832 clk_disable_unprepare(dwc->ref_clk);
833 clk_disable_unprepare(dwc->bus_clk);
834 }
835
dwc3_core_exit(struct dwc3 * dwc)836 static void dwc3_core_exit(struct dwc3 *dwc)
837 {
838 dwc3_event_buffers_cleanup(dwc);
839 dwc3_phy_power_off(dwc);
840 dwc3_phy_exit(dwc);
841 dwc3_clk_disable(dwc);
842 reset_control_assert(dwc->reset);
843 }
844
dwc3_core_is_valid(struct dwc3 * dwc)845 static bool dwc3_core_is_valid(struct dwc3 *dwc)
846 {
847 u32 reg;
848
849 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
850 dwc->ip = DWC3_GSNPS_ID(reg);
851
852 /* This should read as U3 followed by revision number */
853 if (DWC3_IP_IS(DWC3)) {
854 dwc->revision = reg;
855 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
856 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
857 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
858 } else {
859 return false;
860 }
861
862 return true;
863 }
864
dwc3_core_setup_global_control(struct dwc3 * dwc)865 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
866 {
867 u32 reg;
868
869 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
870 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
871
872 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
873 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
874 /**
875 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
876 * issue which would cause xHCI compliance tests to fail.
877 *
878 * Because of that we cannot enable clock gating on such
879 * configurations.
880 *
881 * Refers to:
882 *
883 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
884 * SOF/ITP Mode Used
885 */
886 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
887 dwc->dr_mode == USB_DR_MODE_OTG) &&
888 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
889 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
890 else
891 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
892 break;
893 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
894 /*
895 * REVISIT Enabling this bit so that host-mode hibernation
896 * will work. Device-mode hibernation is not yet implemented.
897 */
898 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
899 break;
900 default:
901 /* nothing */
902 break;
903 }
904
905 /* check if current dwc3 is on simulation board */
906 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
907 dev_info(dwc->dev, "Running with FPGA optimizations\n");
908 dwc->is_fpga = true;
909 }
910
911 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
912 "disable_scramble cannot be used on non-FPGA builds\n");
913
914 if (dwc->disable_scramble_quirk && dwc->is_fpga)
915 reg |= DWC3_GCTL_DISSCRAMBLE;
916 else
917 reg &= ~DWC3_GCTL_DISSCRAMBLE;
918
919 if (dwc->u2exit_lfps_quirk)
920 reg |= DWC3_GCTL_U2EXIT_LFPS;
921
922 /*
923 * WORKAROUND: DWC3 revisions <1.90a have a bug
924 * where the device can fail to connect at SuperSpeed
925 * and falls back to high-speed mode which causes
926 * the device to enter a Connect/Disconnect loop
927 */
928 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
929 reg |= DWC3_GCTL_U2RSTECN;
930
931 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
932 }
933
934 static int dwc3_core_get_phy(struct dwc3 *dwc);
935 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
936
937 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)938 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
939 {
940 struct device *dev = dwc->dev;
941 /* incrx_mode : for INCR burst type. */
942 bool incrx_mode;
943 /* incrx_size : for size of INCRX burst. */
944 u32 incrx_size;
945 u32 *vals;
946 u32 cfg;
947 int ntype;
948 int ret;
949 int i;
950
951 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
952
953 /*
954 * Handle property "snps,incr-burst-type-adjustment".
955 * Get the number of value from this property:
956 * result <= 0, means this property is not supported.
957 * result = 1, means INCRx burst mode supported.
958 * result > 1, means undefined length burst mode supported.
959 */
960 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
961 if (ntype <= 0)
962 return;
963
964 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
965 if (!vals)
966 return;
967
968 /* Get INCR burst type, and parse it */
969 ret = device_property_read_u32_array(dev,
970 "snps,incr-burst-type-adjustment", vals, ntype);
971 if (ret) {
972 kfree(vals);
973 dev_err(dev, "Error to get property\n");
974 return;
975 }
976
977 incrx_size = *vals;
978
979 if (ntype > 1) {
980 /* INCRX (undefined length) burst mode */
981 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
982 for (i = 1; i < ntype; i++) {
983 if (vals[i] > incrx_size)
984 incrx_size = vals[i];
985 }
986 } else {
987 /* INCRX burst mode */
988 incrx_mode = INCRX_BURST_MODE;
989 }
990
991 kfree(vals);
992
993 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
994 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
995 if (incrx_mode)
996 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
997 switch (incrx_size) {
998 case 256:
999 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1000 break;
1001 case 128:
1002 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1003 break;
1004 case 64:
1005 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1006 break;
1007 case 32:
1008 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1009 break;
1010 case 16:
1011 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1012 break;
1013 case 8:
1014 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1015 break;
1016 case 4:
1017 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1018 break;
1019 case 1:
1020 break;
1021 default:
1022 dev_err(dev, "Invalid property\n");
1023 break;
1024 }
1025
1026 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1027 }
1028
dwc3_set_power_down_clk_scale(struct dwc3 * dwc)1029 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1030 {
1031 u32 scale;
1032 u32 reg;
1033
1034 if (!dwc->susp_clk)
1035 return;
1036
1037 /*
1038 * The power down scale field specifies how many suspend_clk
1039 * periods fit into a 16KHz clock period. When performing
1040 * the division, round up the remainder.
1041 *
1042 * The power down scale value is calculated using the fastest
1043 * frequency of the suspend_clk. If it isn't fixed (but within
1044 * the accuracy requirement), the driver may not know the max
1045 * rate of the suspend_clk, so only update the power down scale
1046 * if the default is less than the calculated value from
1047 * clk_get_rate() or if the default is questionably high
1048 * (3x or more) to be within the requirement.
1049 */
1050 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1051 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1052 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1053 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1054 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1055 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1056 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1057 }
1058 }
1059
dwc3_config_threshold(struct dwc3 * dwc)1060 static void dwc3_config_threshold(struct dwc3 *dwc)
1061 {
1062 u32 reg;
1063 u8 rx_thr_num;
1064 u8 rx_maxburst;
1065 u8 tx_thr_num;
1066 u8 tx_maxburst;
1067
1068 /*
1069 * Must config both number of packets and max burst settings to enable
1070 * RX and/or TX threshold.
1071 */
1072 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1073 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1074 rx_maxburst = dwc->rx_max_burst_prd;
1075 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1076 tx_maxburst = dwc->tx_max_burst_prd;
1077
1078 if (rx_thr_num && rx_maxburst) {
1079 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1080 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1081
1082 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1083 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1084
1085 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1086 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1087
1088 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1089 }
1090
1091 if (tx_thr_num && tx_maxburst) {
1092 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1093 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1094
1095 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1096 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1097
1098 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1099 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1100
1101 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1102 }
1103 }
1104
1105 rx_thr_num = dwc->rx_thr_num_pkt;
1106 rx_maxburst = dwc->rx_max_burst;
1107 tx_thr_num = dwc->tx_thr_num_pkt;
1108 tx_maxburst = dwc->tx_max_burst;
1109
1110 if (DWC3_IP_IS(DWC3)) {
1111 if (rx_thr_num && rx_maxburst) {
1112 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1113 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1114
1115 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1116 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1117
1118 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1119 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1120
1121 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1122 }
1123
1124 if (tx_thr_num && tx_maxburst) {
1125 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1126 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1127
1128 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1129 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1130
1131 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1132 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1133
1134 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1135 }
1136 } else {
1137 if (rx_thr_num && rx_maxburst) {
1138 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1139 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1140
1141 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1142 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1143
1144 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1145 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1146
1147 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1148 }
1149
1150 if (tx_thr_num && tx_maxburst) {
1151 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1152 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1153
1154 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1155 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1156
1157 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1158 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1159
1160 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1161 }
1162 }
1163 }
1164
1165 /**
1166 * dwc3_core_init - Low-level initialization of DWC3 Core
1167 * @dwc: Pointer to our controller context structure
1168 *
1169 * Returns 0 on success otherwise negative errno.
1170 */
dwc3_core_init(struct dwc3 * dwc)1171 static int dwc3_core_init(struct dwc3 *dwc)
1172 {
1173 unsigned int hw_mode;
1174 u32 reg;
1175 int ret;
1176
1177 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1178
1179 /*
1180 * Write Linux Version Code to our GUID register so it's easy to figure
1181 * out which kernel version a bug was found.
1182 */
1183 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1184
1185 ret = dwc3_phy_setup(dwc);
1186 if (ret)
1187 return ret;
1188
1189 if (!dwc->ulpi_ready) {
1190 ret = dwc3_core_ulpi_init(dwc);
1191 if (ret) {
1192 if (ret == -ETIMEDOUT) {
1193 dwc3_core_soft_reset(dwc);
1194 ret = -EPROBE_DEFER;
1195 }
1196 return ret;
1197 }
1198 dwc->ulpi_ready = true;
1199 }
1200
1201 if (!dwc->phys_ready) {
1202 ret = dwc3_core_get_phy(dwc);
1203 if (ret)
1204 goto err_exit_ulpi;
1205 dwc->phys_ready = true;
1206 }
1207
1208 ret = dwc3_phy_init(dwc);
1209 if (ret)
1210 goto err_exit_ulpi;
1211
1212 ret = dwc3_core_soft_reset(dwc);
1213 if (ret)
1214 goto err_exit_phy;
1215
1216 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1217 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1218 if (!dwc->dis_u3_susphy_quirk) {
1219 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1220 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1221 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1222 }
1223
1224 if (!dwc->dis_u2_susphy_quirk) {
1225 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1226 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1227 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1228 }
1229 }
1230
1231 dwc3_core_setup_global_control(dwc);
1232 dwc3_core_num_eps(dwc);
1233
1234 /* Set power down scale of suspend_clk */
1235 dwc3_set_power_down_clk_scale(dwc);
1236
1237 /* Adjust Frame Length */
1238 dwc3_frame_length_adjustment(dwc);
1239
1240 /* Adjust Reference Clock Period */
1241 dwc3_ref_clk_period(dwc);
1242
1243 dwc3_set_incr_burst_type(dwc);
1244
1245 ret = dwc3_phy_power_on(dwc);
1246 if (ret)
1247 goto err_exit_phy;
1248
1249 ret = dwc3_event_buffers_setup(dwc);
1250 if (ret) {
1251 dev_err(dwc->dev, "failed to setup event buffers\n");
1252 goto err_power_off_phy;
1253 }
1254
1255 /*
1256 * ENDXFER polling is available on version 3.10a and later of
1257 * the DWC_usb3 controller. It is NOT available in the
1258 * DWC_usb31 controller.
1259 */
1260 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1261 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1262 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1263 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1264 }
1265
1266 /*
1267 * When configured in HOST mode, after issuing U3/L2 exit controller
1268 * fails to send proper CRC checksum in CRC5 feild. Because of this
1269 * behaviour Transaction Error is generated, resulting in reset and
1270 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1271 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1272 * will correct this problem. This option is to support certain
1273 * legacy ULPI PHYs.
1274 */
1275 if (dwc->resume_hs_terminations) {
1276 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1277 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1278 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1279 }
1280
1281 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1282 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1283
1284 /*
1285 * Enable hardware control of sending remote wakeup
1286 * in HS when the device is in the L1 state.
1287 */
1288 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1289 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1290
1291 /*
1292 * Decouple USB 2.0 L1 & L2 events which will allow for
1293 * gadget driver to only receive U3/L2 suspend & wakeup
1294 * events and prevent the more frequent L1 LPM transitions
1295 * from interrupting the driver.
1296 */
1297 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1298 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1299
1300 if (dwc->dis_tx_ipgap_linecheck_quirk)
1301 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1302
1303 if (dwc->parkmode_disable_ss_quirk)
1304 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1305
1306 if (dwc->parkmode_disable_hs_quirk)
1307 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1308
1309 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1310 (dwc->maximum_speed == USB_SPEED_HIGH ||
1311 dwc->maximum_speed == USB_SPEED_FULL))
1312 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1313
1314 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1315 }
1316
1317 dwc3_config_threshold(dwc);
1318
1319 return 0;
1320
1321 err_power_off_phy:
1322 dwc3_phy_power_off(dwc);
1323 err_exit_phy:
1324 dwc3_phy_exit(dwc);
1325 err_exit_ulpi:
1326 dwc3_ulpi_exit(dwc);
1327
1328 return ret;
1329 }
1330
dwc3_core_get_phy(struct dwc3 * dwc)1331 static int dwc3_core_get_phy(struct dwc3 *dwc)
1332 {
1333 struct device *dev = dwc->dev;
1334 struct device_node *node = dev->of_node;
1335 int ret;
1336
1337 if (node) {
1338 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1339 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1340 } else {
1341 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1342 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1343 }
1344
1345 if (IS_ERR(dwc->usb2_phy)) {
1346 ret = PTR_ERR(dwc->usb2_phy);
1347 if (ret == -ENXIO || ret == -ENODEV)
1348 dwc->usb2_phy = NULL;
1349 else
1350 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1351 }
1352
1353 if (IS_ERR(dwc->usb3_phy)) {
1354 ret = PTR_ERR(dwc->usb3_phy);
1355 if (ret == -ENXIO || ret == -ENODEV)
1356 dwc->usb3_phy = NULL;
1357 else
1358 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1359 }
1360
1361 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1362 if (IS_ERR(dwc->usb2_generic_phy)) {
1363 ret = PTR_ERR(dwc->usb2_generic_phy);
1364 if (ret == -ENOSYS || ret == -ENODEV)
1365 dwc->usb2_generic_phy = NULL;
1366 else
1367 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1368 }
1369
1370 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1371 if (IS_ERR(dwc->usb3_generic_phy)) {
1372 ret = PTR_ERR(dwc->usb3_generic_phy);
1373 if (ret == -ENOSYS || ret == -ENODEV)
1374 dwc->usb3_generic_phy = NULL;
1375 else
1376 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1377 }
1378
1379 return 0;
1380 }
1381
dwc3_core_init_mode(struct dwc3 * dwc)1382 static int dwc3_core_init_mode(struct dwc3 *dwc)
1383 {
1384 struct device *dev = dwc->dev;
1385 int ret;
1386
1387 switch (dwc->dr_mode) {
1388 case USB_DR_MODE_PERIPHERAL:
1389 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1390
1391 if (dwc->usb2_phy)
1392 otg_set_vbus(dwc->usb2_phy->otg, false);
1393 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1394 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1395
1396 ret = dwc3_gadget_init(dwc);
1397 if (ret)
1398 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1399 break;
1400 case USB_DR_MODE_HOST:
1401 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1402
1403 if (dwc->usb2_phy)
1404 otg_set_vbus(dwc->usb2_phy->otg, true);
1405 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1406 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1407
1408 ret = dwc3_host_init(dwc);
1409 if (ret)
1410 return dev_err_probe(dev, ret, "failed to initialize host\n");
1411 break;
1412 case USB_DR_MODE_OTG:
1413 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1414 ret = dwc3_drd_init(dwc);
1415 if (ret)
1416 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1417 break;
1418 default:
1419 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1420 return -EINVAL;
1421 }
1422
1423 return 0;
1424 }
1425
dwc3_core_exit_mode(struct dwc3 * dwc)1426 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1427 {
1428 switch (dwc->dr_mode) {
1429 case USB_DR_MODE_PERIPHERAL:
1430 dwc3_gadget_exit(dwc);
1431 break;
1432 case USB_DR_MODE_HOST:
1433 dwc3_host_exit(dwc);
1434 break;
1435 case USB_DR_MODE_OTG:
1436 dwc3_drd_exit(dwc);
1437 break;
1438 default:
1439 /* do nothing */
1440 break;
1441 }
1442
1443 /* de-assert DRVVBUS for HOST and OTG mode */
1444 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1445 }
1446
dwc3_get_properties(struct dwc3 * dwc)1447 static void dwc3_get_properties(struct dwc3 *dwc)
1448 {
1449 struct device *dev = dwc->dev;
1450 u8 lpm_nyet_threshold;
1451 u8 tx_de_emphasis;
1452 u8 hird_threshold;
1453 u8 rx_thr_num_pkt = 0;
1454 u8 rx_max_burst = 0;
1455 u8 tx_thr_num_pkt = 0;
1456 u8 tx_max_burst = 0;
1457 u8 rx_thr_num_pkt_prd = 0;
1458 u8 rx_max_burst_prd = 0;
1459 u8 tx_thr_num_pkt_prd = 0;
1460 u8 tx_max_burst_prd = 0;
1461 u8 tx_fifo_resize_max_num;
1462 const char *usb_psy_name;
1463 int ret;
1464
1465 /* default to highest possible threshold */
1466 lpm_nyet_threshold = 0xf;
1467
1468 /* default to -3.5dB de-emphasis */
1469 tx_de_emphasis = 1;
1470
1471 /*
1472 * default to assert utmi_sleep_n and use maximum allowed HIRD
1473 * threshold value of 0b1100
1474 */
1475 hird_threshold = 12;
1476
1477 /*
1478 * default to a TXFIFO size large enough to fit 6 max packets. This
1479 * allows for systems with larger bus latencies to have some headroom
1480 * for endpoints that have a large bMaxBurst value.
1481 */
1482 tx_fifo_resize_max_num = 6;
1483
1484 dwc->maximum_speed = usb_get_maximum_speed(dev);
1485 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1486 dwc->dr_mode = usb_get_dr_mode(dev);
1487 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1488
1489 dwc->sysdev_is_parent = device_property_read_bool(dev,
1490 "linux,sysdev_is_parent");
1491 if (dwc->sysdev_is_parent)
1492 dwc->sysdev = dwc->dev->parent;
1493 else
1494 dwc->sysdev = dwc->dev;
1495
1496 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1497 if (ret >= 0) {
1498 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1499 if (!dwc->usb_psy)
1500 dev_err(dev, "couldn't get usb power supply\n");
1501 }
1502
1503 dwc->has_lpm_erratum = device_property_read_bool(dev,
1504 "snps,has-lpm-erratum");
1505 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1506 &lpm_nyet_threshold);
1507 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1508 "snps,is-utmi-l1-suspend");
1509 device_property_read_u8(dev, "snps,hird-threshold",
1510 &hird_threshold);
1511 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1512 "snps,dis-start-transfer-quirk");
1513 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1514 "snps,usb3_lpm_capable");
1515 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1516 "snps,usb2-lpm-disable");
1517 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1518 "snps,usb2-gadget-lpm-disable");
1519 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1520 &rx_thr_num_pkt);
1521 device_property_read_u8(dev, "snps,rx-max-burst",
1522 &rx_max_burst);
1523 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1524 &tx_thr_num_pkt);
1525 device_property_read_u8(dev, "snps,tx-max-burst",
1526 &tx_max_burst);
1527 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1528 &rx_thr_num_pkt_prd);
1529 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1530 &rx_max_burst_prd);
1531 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1532 &tx_thr_num_pkt_prd);
1533 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1534 &tx_max_burst_prd);
1535 dwc->do_fifo_resize = device_property_read_bool(dev,
1536 "tx-fifo-resize");
1537 if (dwc->do_fifo_resize)
1538 device_property_read_u8(dev, "tx-fifo-max-num",
1539 &tx_fifo_resize_max_num);
1540
1541 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1542 "snps,disable_scramble_quirk");
1543 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1544 "snps,u2exit_lfps_quirk");
1545 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1546 "snps,u2ss_inp3_quirk");
1547 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1548 "snps,req_p1p2p3_quirk");
1549 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1550 "snps,del_p1p2p3_quirk");
1551 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1552 "snps,del_phy_power_chg_quirk");
1553 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1554 "snps,lfps_filter_quirk");
1555 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1556 "snps,rx_detect_poll_quirk");
1557 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1558 "snps,dis_u3_susphy_quirk");
1559 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1560 "snps,dis_u2_susphy_quirk");
1561 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1562 "snps,dis_enblslpm_quirk");
1563 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1564 "snps,dis-u1-entry-quirk");
1565 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1566 "snps,dis-u2-entry-quirk");
1567 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1568 "snps,dis_rxdet_inp3_quirk");
1569 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1570 "snps,dis-u2-freeclk-exists-quirk");
1571 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1572 "snps,dis-del-phy-power-chg-quirk");
1573 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1574 "snps,dis-tx-ipgap-linecheck-quirk");
1575 dwc->resume_hs_terminations = device_property_read_bool(dev,
1576 "snps,resume-hs-terminations");
1577 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1578 "snps,ulpi-ext-vbus-drv");
1579 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1580 "snps,parkmode-disable-ss-quirk");
1581 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1582 "snps,parkmode-disable-hs-quirk");
1583 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1584 "snps,gfladj-refclk-lpm-sel-quirk");
1585
1586 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1587 "snps,tx_de_emphasis_quirk");
1588 device_property_read_u8(dev, "snps,tx_de_emphasis",
1589 &tx_de_emphasis);
1590 device_property_read_string(dev, "snps,hsphy_interface",
1591 &dwc->hsphy_interface);
1592 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1593 &dwc->fladj);
1594 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1595 &dwc->ref_clk_per);
1596
1597 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1598 "snps,dis_metastability_quirk");
1599
1600 dwc->dis_split_quirk = device_property_read_bool(dev,
1601 "snps,dis-split-quirk");
1602
1603 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1604 dwc->tx_de_emphasis = tx_de_emphasis;
1605
1606 dwc->hird_threshold = hird_threshold;
1607
1608 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1609 dwc->rx_max_burst = rx_max_burst;
1610
1611 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1612 dwc->tx_max_burst = tx_max_burst;
1613
1614 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1615 dwc->rx_max_burst_prd = rx_max_burst_prd;
1616
1617 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1618 dwc->tx_max_burst_prd = tx_max_burst_prd;
1619
1620 dwc->imod_interval = 0;
1621
1622 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1623 }
1624
1625 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1626 bool dwc3_has_imod(struct dwc3 *dwc)
1627 {
1628 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1629 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1630 DWC3_IP_IS(DWC32);
1631 }
1632
dwc3_check_params(struct dwc3 * dwc)1633 static void dwc3_check_params(struct dwc3 *dwc)
1634 {
1635 struct device *dev = dwc->dev;
1636 unsigned int hwparam_gen =
1637 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1638
1639 /* Check for proper value of imod_interval */
1640 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1641 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1642 dwc->imod_interval = 0;
1643 }
1644
1645 /*
1646 * Workaround for STAR 9000961433 which affects only version
1647 * 3.00a of the DWC_usb3 core. This prevents the controller
1648 * interrupt from being masked while handling events. IMOD
1649 * allows us to work around this issue. Enable it for the
1650 * affected version.
1651 */
1652 if (!dwc->imod_interval &&
1653 DWC3_VER_IS(DWC3, 300A))
1654 dwc->imod_interval = 1;
1655
1656 /* Check the maximum_speed parameter */
1657 switch (dwc->maximum_speed) {
1658 case USB_SPEED_FULL:
1659 case USB_SPEED_HIGH:
1660 break;
1661 case USB_SPEED_SUPER:
1662 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1663 dev_warn(dev, "UDC doesn't support Gen 1\n");
1664 break;
1665 case USB_SPEED_SUPER_PLUS:
1666 if ((DWC3_IP_IS(DWC32) &&
1667 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1668 (!DWC3_IP_IS(DWC32) &&
1669 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1670 dev_warn(dev, "UDC doesn't support SSP\n");
1671 break;
1672 default:
1673 dev_err(dev, "invalid maximum_speed parameter %d\n",
1674 dwc->maximum_speed);
1675 fallthrough;
1676 case USB_SPEED_UNKNOWN:
1677 switch (hwparam_gen) {
1678 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1679 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1680 break;
1681 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1682 if (DWC3_IP_IS(DWC32))
1683 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1684 else
1685 dwc->maximum_speed = USB_SPEED_SUPER;
1686 break;
1687 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1688 dwc->maximum_speed = USB_SPEED_HIGH;
1689 break;
1690 default:
1691 dwc->maximum_speed = USB_SPEED_SUPER;
1692 break;
1693 }
1694 break;
1695 }
1696
1697 /*
1698 * Currently the controller does not have visibility into the HW
1699 * parameter to determine the maximum number of lanes the HW supports.
1700 * If the number of lanes is not specified in the device property, then
1701 * set the default to support dual-lane for DWC_usb32 and single-lane
1702 * for DWC_usb31 for super-speed-plus.
1703 */
1704 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1705 switch (dwc->max_ssp_rate) {
1706 case USB_SSP_GEN_2x1:
1707 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1708 dev_warn(dev, "UDC only supports Gen 1\n");
1709 break;
1710 case USB_SSP_GEN_1x2:
1711 case USB_SSP_GEN_2x2:
1712 if (DWC3_IP_IS(DWC31))
1713 dev_warn(dev, "UDC only supports single lane\n");
1714 break;
1715 case USB_SSP_GEN_UNKNOWN:
1716 default:
1717 switch (hwparam_gen) {
1718 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1719 if (DWC3_IP_IS(DWC32))
1720 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1721 else
1722 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1723 break;
1724 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1725 if (DWC3_IP_IS(DWC32))
1726 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1727 break;
1728 }
1729 break;
1730 }
1731 }
1732 }
1733
dwc3_get_extcon(struct dwc3 * dwc)1734 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1735 {
1736 struct device *dev = dwc->dev;
1737 struct device_node *np_phy;
1738 struct extcon_dev *edev = NULL;
1739 const char *name;
1740
1741 if (device_property_read_bool(dev, "extcon"))
1742 return extcon_get_edev_by_phandle(dev, 0);
1743
1744 /*
1745 * Device tree platforms should get extcon via phandle.
1746 * On ACPI platforms, we get the name from a device property.
1747 * This device property is for kernel internal use only and
1748 * is expected to be set by the glue code.
1749 */
1750 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1751 return extcon_get_extcon_dev(name);
1752
1753 /*
1754 * Check explicitly if "usb-role-switch" is used since
1755 * extcon_find_edev_by_node() can not be used to check the absence of
1756 * an extcon device. In the absence of an device it will always return
1757 * EPROBE_DEFER.
1758 */
1759 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1760 device_property_read_bool(dev, "usb-role-switch"))
1761 return NULL;
1762
1763 /*
1764 * Try to get an extcon device from the USB PHY controller's "port"
1765 * node. Check if it has the "port" node first, to avoid printing the
1766 * error message from underlying code, as it's a valid case: extcon
1767 * device (and "port" node) may be missing in case of "usb-role-switch"
1768 * or OTG mode.
1769 */
1770 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1771 if (of_graph_is_present(np_phy)) {
1772 struct device_node *np_conn;
1773
1774 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1775 if (np_conn)
1776 edev = extcon_find_edev_by_node(np_conn);
1777 of_node_put(np_conn);
1778 }
1779 of_node_put(np_phy);
1780
1781 return edev;
1782 }
1783
dwc3_get_clocks(struct dwc3 * dwc)1784 static int dwc3_get_clocks(struct dwc3 *dwc)
1785 {
1786 struct device *dev = dwc->dev;
1787
1788 if (!dev->of_node)
1789 return 0;
1790
1791 /*
1792 * Clocks are optional, but new DT platforms should support all clocks
1793 * as required by the DT-binding.
1794 * Some devices have different clock names in legacy device trees,
1795 * check for them to retain backwards compatibility.
1796 */
1797 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1798 if (IS_ERR(dwc->bus_clk)) {
1799 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1800 "could not get bus clock\n");
1801 }
1802
1803 if (dwc->bus_clk == NULL) {
1804 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1805 if (IS_ERR(dwc->bus_clk)) {
1806 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1807 "could not get bus clock\n");
1808 }
1809 }
1810
1811 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1812 if (IS_ERR(dwc->ref_clk)) {
1813 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1814 "could not get ref clock\n");
1815 }
1816
1817 if (dwc->ref_clk == NULL) {
1818 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1819 if (IS_ERR(dwc->ref_clk)) {
1820 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1821 "could not get ref clock\n");
1822 }
1823 }
1824
1825 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1826 if (IS_ERR(dwc->susp_clk)) {
1827 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1828 "could not get suspend clock\n");
1829 }
1830
1831 if (dwc->susp_clk == NULL) {
1832 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1833 if (IS_ERR(dwc->susp_clk)) {
1834 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1835 "could not get suspend clock\n");
1836 }
1837 }
1838
1839 return 0;
1840 }
1841
dwc3_probe(struct platform_device * pdev)1842 static int dwc3_probe(struct platform_device *pdev)
1843 {
1844 struct device *dev = &pdev->dev;
1845 struct resource *res, dwc_res;
1846 void __iomem *regs;
1847 struct dwc3 *dwc;
1848 int ret;
1849
1850 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1851 if (!dwc)
1852 return -ENOMEM;
1853
1854 dwc->dev = dev;
1855
1856 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1857 if (!res) {
1858 dev_err(dev, "missing memory resource\n");
1859 return -ENODEV;
1860 }
1861
1862 dwc->xhci_resources[0].start = res->start;
1863 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1864 DWC3_XHCI_REGS_END;
1865 dwc->xhci_resources[0].flags = res->flags;
1866 dwc->xhci_resources[0].name = res->name;
1867
1868 /*
1869 * Request memory region but exclude xHCI regs,
1870 * since it will be requested by the xhci-plat driver.
1871 */
1872 dwc_res = *res;
1873 dwc_res.start += DWC3_GLOBALS_REGS_START;
1874
1875 if (dev->of_node) {
1876 struct device_node *parent = of_get_parent(dev->of_node);
1877
1878 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1879 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1880 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1881 }
1882
1883 of_node_put(parent);
1884 }
1885
1886 regs = devm_ioremap_resource(dev, &dwc_res);
1887 if (IS_ERR(regs))
1888 return PTR_ERR(regs);
1889
1890 dwc->regs = regs;
1891 dwc->regs_size = resource_size(&dwc_res);
1892
1893 dwc3_get_properties(dwc);
1894
1895 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1896 if (IS_ERR(dwc->reset)) {
1897 ret = PTR_ERR(dwc->reset);
1898 goto err_put_psy;
1899 }
1900
1901 ret = dwc3_get_clocks(dwc);
1902 if (ret)
1903 goto err_put_psy;
1904
1905 ret = reset_control_deassert(dwc->reset);
1906 if (ret)
1907 goto err_put_psy;
1908
1909 ret = dwc3_clk_enable(dwc);
1910 if (ret)
1911 goto err_assert_reset;
1912
1913 if (!dwc3_core_is_valid(dwc)) {
1914 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1915 ret = -ENODEV;
1916 goto err_disable_clks;
1917 }
1918
1919 platform_set_drvdata(pdev, dwc);
1920 dwc3_cache_hwparams(dwc);
1921
1922 if (!dwc->sysdev_is_parent &&
1923 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1924 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1925 if (ret)
1926 goto err_disable_clks;
1927 }
1928
1929 spin_lock_init(&dwc->lock);
1930 mutex_init(&dwc->mutex);
1931
1932 pm_runtime_get_noresume(dev);
1933 pm_runtime_set_active(dev);
1934 pm_runtime_use_autosuspend(dev);
1935 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1936 pm_runtime_enable(dev);
1937
1938 pm_runtime_forbid(dev);
1939
1940 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1941 if (ret) {
1942 dev_err(dwc->dev, "failed to allocate event buffers\n");
1943 ret = -ENOMEM;
1944 goto err_allow_rpm;
1945 }
1946
1947 dwc->edev = dwc3_get_extcon(dwc);
1948 if (IS_ERR(dwc->edev)) {
1949 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
1950 goto err_free_event_buffers;
1951 }
1952
1953 ret = dwc3_get_dr_mode(dwc);
1954 if (ret)
1955 goto err_free_event_buffers;
1956
1957 ret = dwc3_core_init(dwc);
1958 if (ret) {
1959 dev_err_probe(dev, ret, "failed to initialize core\n");
1960 goto err_free_event_buffers;
1961 }
1962
1963 dwc3_check_params(dwc);
1964 dwc3_debugfs_init(dwc);
1965
1966 ret = dwc3_core_init_mode(dwc);
1967 if (ret)
1968 goto err_exit_debugfs;
1969
1970 pm_runtime_put(dev);
1971
1972 dma_set_max_seg_size(dev, UINT_MAX);
1973
1974 return 0;
1975
1976 err_exit_debugfs:
1977 dwc3_debugfs_exit(dwc);
1978 dwc3_event_buffers_cleanup(dwc);
1979 dwc3_phy_power_off(dwc);
1980 dwc3_phy_exit(dwc);
1981 dwc3_ulpi_exit(dwc);
1982 err_free_event_buffers:
1983 dwc3_free_event_buffers(dwc);
1984 err_allow_rpm:
1985 pm_runtime_allow(dev);
1986 pm_runtime_disable(dev);
1987 pm_runtime_dont_use_autosuspend(dev);
1988 pm_runtime_set_suspended(dev);
1989 pm_runtime_put_noidle(dev);
1990 err_disable_clks:
1991 dwc3_clk_disable(dwc);
1992 err_assert_reset:
1993 reset_control_assert(dwc->reset);
1994 err_put_psy:
1995 if (dwc->usb_psy)
1996 power_supply_put(dwc->usb_psy);
1997
1998 return ret;
1999 }
2000
dwc3_remove(struct platform_device * pdev)2001 static void dwc3_remove(struct platform_device *pdev)
2002 {
2003 struct dwc3 *dwc = platform_get_drvdata(pdev);
2004
2005 pm_runtime_get_sync(&pdev->dev);
2006
2007 dwc3_core_exit_mode(dwc);
2008 dwc3_debugfs_exit(dwc);
2009
2010 dwc3_core_exit(dwc);
2011 dwc3_ulpi_exit(dwc);
2012
2013 pm_runtime_allow(&pdev->dev);
2014 pm_runtime_disable(&pdev->dev);
2015 pm_runtime_dont_use_autosuspend(&pdev->dev);
2016 pm_runtime_put_noidle(&pdev->dev);
2017 /*
2018 * HACK: Clear the driver data, which is currently accessed by parent
2019 * glue drivers, before allowing the parent to suspend.
2020 */
2021 platform_set_drvdata(pdev, NULL);
2022 pm_runtime_set_suspended(&pdev->dev);
2023
2024 dwc3_free_event_buffers(dwc);
2025
2026 if (dwc->usb_psy)
2027 power_supply_put(dwc->usb_psy);
2028 }
2029
2030 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)2031 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2032 {
2033 int ret;
2034
2035 ret = reset_control_deassert(dwc->reset);
2036 if (ret)
2037 return ret;
2038
2039 ret = dwc3_clk_enable(dwc);
2040 if (ret)
2041 goto assert_reset;
2042
2043 ret = dwc3_core_init(dwc);
2044 if (ret)
2045 goto disable_clks;
2046
2047 return 0;
2048
2049 disable_clks:
2050 dwc3_clk_disable(dwc);
2051 assert_reset:
2052 reset_control_assert(dwc->reset);
2053
2054 return ret;
2055 }
2056
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)2057 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2058 {
2059 unsigned long flags;
2060 u32 reg;
2061
2062 switch (dwc->current_dr_role) {
2063 case DWC3_GCTL_PRTCAP_DEVICE:
2064 if (pm_runtime_suspended(dwc->dev))
2065 break;
2066 dwc3_gadget_suspend(dwc);
2067 synchronize_irq(dwc->irq_gadget);
2068 dwc3_core_exit(dwc);
2069 break;
2070 case DWC3_GCTL_PRTCAP_HOST:
2071 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2072 dwc3_core_exit(dwc);
2073 break;
2074 }
2075
2076 /* Let controller to suspend HSPHY before PHY driver suspends */
2077 if (dwc->dis_u2_susphy_quirk ||
2078 dwc->dis_enblslpm_quirk) {
2079 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2080 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2081 DWC3_GUSB2PHYCFG_SUSPHY;
2082 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2083
2084 /* Give some time for USB2 PHY to suspend */
2085 usleep_range(5000, 6000);
2086 }
2087
2088 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2089 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2090 break;
2091 case DWC3_GCTL_PRTCAP_OTG:
2092 /* do nothing during runtime_suspend */
2093 if (PMSG_IS_AUTO(msg))
2094 break;
2095
2096 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2097 spin_lock_irqsave(&dwc->lock, flags);
2098 dwc3_gadget_suspend(dwc);
2099 spin_unlock_irqrestore(&dwc->lock, flags);
2100 synchronize_irq(dwc->irq_gadget);
2101 }
2102
2103 dwc3_otg_exit(dwc);
2104 dwc3_core_exit(dwc);
2105 break;
2106 default:
2107 /* do nothing */
2108 break;
2109 }
2110
2111 return 0;
2112 }
2113
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)2114 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2115 {
2116 unsigned long flags;
2117 int ret;
2118 u32 reg;
2119
2120 switch (dwc->current_dr_role) {
2121 case DWC3_GCTL_PRTCAP_DEVICE:
2122 ret = dwc3_core_init_for_resume(dwc);
2123 if (ret)
2124 return ret;
2125
2126 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2127 dwc3_gadget_resume(dwc);
2128 break;
2129 case DWC3_GCTL_PRTCAP_HOST:
2130 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2131 ret = dwc3_core_init_for_resume(dwc);
2132 if (ret)
2133 return ret;
2134 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2135 break;
2136 }
2137 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2138 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2139 if (dwc->dis_u2_susphy_quirk)
2140 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2141
2142 if (dwc->dis_enblslpm_quirk)
2143 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2144
2145 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2146
2147 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2148 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2149 break;
2150 case DWC3_GCTL_PRTCAP_OTG:
2151 /* nothing to do on runtime_resume */
2152 if (PMSG_IS_AUTO(msg))
2153 break;
2154
2155 ret = dwc3_core_init_for_resume(dwc);
2156 if (ret)
2157 return ret;
2158
2159 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2160
2161 dwc3_otg_init(dwc);
2162 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2163 dwc3_otg_host_init(dwc);
2164 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2165 spin_lock_irqsave(&dwc->lock, flags);
2166 dwc3_gadget_resume(dwc);
2167 spin_unlock_irqrestore(&dwc->lock, flags);
2168 }
2169
2170 break;
2171 default:
2172 /* do nothing */
2173 break;
2174 }
2175
2176 return 0;
2177 }
2178
dwc3_runtime_checks(struct dwc3 * dwc)2179 static int dwc3_runtime_checks(struct dwc3 *dwc)
2180 {
2181 switch (dwc->current_dr_role) {
2182 case DWC3_GCTL_PRTCAP_DEVICE:
2183 if (dwc->connected)
2184 return -EBUSY;
2185 break;
2186 case DWC3_GCTL_PRTCAP_HOST:
2187 default:
2188 /* do nothing */
2189 break;
2190 }
2191
2192 return 0;
2193 }
2194
dwc3_runtime_suspend(struct device * dev)2195 static int dwc3_runtime_suspend(struct device *dev)
2196 {
2197 struct dwc3 *dwc = dev_get_drvdata(dev);
2198 int ret;
2199
2200 if (dwc3_runtime_checks(dwc))
2201 return -EBUSY;
2202
2203 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2204 if (ret)
2205 return ret;
2206
2207 return 0;
2208 }
2209
dwc3_runtime_resume(struct device * dev)2210 static int dwc3_runtime_resume(struct device *dev)
2211 {
2212 struct dwc3 *dwc = dev_get_drvdata(dev);
2213 int ret;
2214
2215 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2216 if (ret)
2217 return ret;
2218
2219 switch (dwc->current_dr_role) {
2220 case DWC3_GCTL_PRTCAP_DEVICE:
2221 dwc3_gadget_process_pending_events(dwc);
2222 break;
2223 case DWC3_GCTL_PRTCAP_HOST:
2224 default:
2225 /* do nothing */
2226 break;
2227 }
2228
2229 pm_runtime_mark_last_busy(dev);
2230
2231 return 0;
2232 }
2233
dwc3_runtime_idle(struct device * dev)2234 static int dwc3_runtime_idle(struct device *dev)
2235 {
2236 struct dwc3 *dwc = dev_get_drvdata(dev);
2237
2238 switch (dwc->current_dr_role) {
2239 case DWC3_GCTL_PRTCAP_DEVICE:
2240 if (dwc3_runtime_checks(dwc))
2241 return -EBUSY;
2242 break;
2243 case DWC3_GCTL_PRTCAP_HOST:
2244 default:
2245 /* do nothing */
2246 break;
2247 }
2248
2249 pm_runtime_mark_last_busy(dev);
2250 pm_runtime_autosuspend(dev);
2251
2252 return 0;
2253 }
2254 #endif /* CONFIG_PM */
2255
2256 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2257 static int dwc3_suspend(struct device *dev)
2258 {
2259 struct dwc3 *dwc = dev_get_drvdata(dev);
2260 int ret;
2261
2262 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2263 if (ret)
2264 return ret;
2265
2266 pinctrl_pm_select_sleep_state(dev);
2267
2268 return 0;
2269 }
2270
dwc3_resume(struct device * dev)2271 static int dwc3_resume(struct device *dev)
2272 {
2273 struct dwc3 *dwc = dev_get_drvdata(dev);
2274 int ret;
2275
2276 pinctrl_pm_select_default_state(dev);
2277
2278 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2279 if (ret)
2280 return ret;
2281
2282 pm_runtime_disable(dev);
2283 pm_runtime_set_active(dev);
2284 pm_runtime_enable(dev);
2285
2286 return 0;
2287 }
2288
dwc3_complete(struct device * dev)2289 static void dwc3_complete(struct device *dev)
2290 {
2291 struct dwc3 *dwc = dev_get_drvdata(dev);
2292 u32 reg;
2293
2294 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2295 dwc->dis_split_quirk) {
2296 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2297 reg |= DWC3_GUCTL3_SPLITDISABLE;
2298 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2299 }
2300 }
2301 #else
2302 #define dwc3_complete NULL
2303 #endif /* CONFIG_PM_SLEEP */
2304
2305 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2306 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2307 .complete = dwc3_complete,
2308 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2309 dwc3_runtime_idle)
2310 };
2311
2312 #ifdef CONFIG_OF
2313 static const struct of_device_id of_dwc3_match[] = {
2314 {
2315 .compatible = "snps,dwc3"
2316 },
2317 {
2318 .compatible = "synopsys,dwc3"
2319 },
2320 { },
2321 };
2322 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2323 #endif
2324
2325 #ifdef CONFIG_ACPI
2326
2327 #define ACPI_ID_INTEL_BSW "808622B7"
2328
2329 static const struct acpi_device_id dwc3_acpi_match[] = {
2330 { ACPI_ID_INTEL_BSW, 0 },
2331 { },
2332 };
2333 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2334 #endif
2335
2336 static struct platform_driver dwc3_driver = {
2337 .probe = dwc3_probe,
2338 .remove_new = dwc3_remove,
2339 .driver = {
2340 .name = "dwc3",
2341 .of_match_table = of_match_ptr(of_dwc3_match),
2342 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2343 .pm = &dwc3_dev_pm_ops,
2344 },
2345 };
2346
2347 module_platform_driver(dwc3_driver);
2348
2349 MODULE_ALIAS("platform:dwc3");
2350 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2351 MODULE_LICENSE("GPL v2");
2352 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2353