1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "reg_helper.h"
27 #include "fixed31_32.h"
28 #include "resource.h"
29 #include "basics/conversion.h"
30 #include "dwb.h"
31 #include "dcn30_dwb.h"
32 #include "dcn30_cm_common.h"
33 #include "dcn10/dcn10_cm_common.h"
34 
35 
36 #define REG(reg)\
37 	dwbc30->dwbc_regs->reg
38 
39 #define CTX \
40 	dwbc30->base.ctx
41 
42 #undef FN
43 #define FN(reg_name, field_name) \
44 	dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
45 
46 #define TO_DCN30_DWBC(dwbc_base) \
47 	container_of(dwbc_base, struct dcn30_dwbc, base)
48 
dwb3_get_reg_field_ogam(struct dcn30_dwbc * dwbc30,struct dcn3_xfer_func_reg * reg)49 static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30,
50 	struct dcn3_xfer_func_reg *reg)
51 {
52 	reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
53 	reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
54 	reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;
55 	reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
56 
57 	reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
58 	reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
59 	reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
60 	reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
61 	reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
62 	reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
63 	reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
64 	reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
65 
66 	reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B;
67 	reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B;
68 	reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
69 	reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
70 	reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
71 	reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
72 	reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
73 	reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
74 	reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;
75 	reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B;
76 	reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
77 	reg->masks.exp_resion_start_segment = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
78 }
79 
80 /*program dwb ogam RAM A*/
dwb3_program_ogam_luta_settings(struct dcn30_dwbc * dwbc30,const struct pwl_params * params)81 static void dwb3_program_ogam_luta_settings(
82 	struct dcn30_dwbc *dwbc30,
83 	const struct pwl_params *params)
84 {
85 	struct dcn3_xfer_func_reg gam_regs;
86 
87 	dwb3_get_reg_field_ogam(dwbc30, &gam_regs);
88 
89 	gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);
90 	gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);
91 	gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);
92 	gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);
93 	gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);
94 	gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);
95 	gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);
96 	gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G);
97 	gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R);
98 	gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMA_END_CNTL1_B);
99 	gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMA_END_CNTL2_B);
100 	gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMA_END_CNTL1_G);
101 	gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMA_END_CNTL2_G);
102 	gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMA_END_CNTL1_R);
103 	gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMA_END_CNTL2_R);
104 	gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B);
105 	gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G);
106 	gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R);
107 	gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1);
108 	gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33);
109 	/*todo*/
110 	cm_helper_program_gamcor_xfer_func(dwbc30->base.ctx, params, &gam_regs);
111 }
112 
113 /*program dwb ogam RAM B*/
dwb3_program_ogam_lutb_settings(struct dcn30_dwbc * dwbc30,const struct pwl_params * params)114 static void dwb3_program_ogam_lutb_settings(
115 	struct dcn30_dwbc *dwbc30,
116 	const struct pwl_params *params)
117 {
118 	struct dcn3_xfer_func_reg gam_regs;
119 
120 	dwb3_get_reg_field_ogam(dwbc30, &gam_regs);
121 
122 	gam_regs.start_cntl_b = REG(DWB_OGAM_RAMB_START_CNTL_B);
123 	gam_regs.start_cntl_g = REG(DWB_OGAM_RAMB_START_CNTL_G);
124 	gam_regs.start_cntl_r = REG(DWB_OGAM_RAMB_START_CNTL_R);
125 	gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMB_START_BASE_CNTL_B);
126 	gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMB_START_BASE_CNTL_G);
127 	gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMB_START_BASE_CNTL_R);
128 	gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_B);
129 	gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_G);
130 	gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_R);
131 	gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMB_END_CNTL1_B);
132 	gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMB_END_CNTL2_B);
133 	gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMB_END_CNTL1_G);
134 	gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMB_END_CNTL2_G);
135 	gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMB_END_CNTL1_R);
136 	gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMB_END_CNTL2_R);
137 	gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B);
138 	gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G);
139 	gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R);
140 	gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1);
141 	gam_regs.region_end = REG(DWB_OGAM_RAMB_REGION_32_33);
142 
143 	cm_helper_program_gamcor_xfer_func(dwbc30->base.ctx, params, &gam_regs);
144 }
145 
dwb3_get_ogam_current(struct dcn30_dwbc * dwbc30)146 static enum dc_lut_mode dwb3_get_ogam_current(
147 	struct dcn30_dwbc *dwbc30)
148 {
149 	enum dc_lut_mode mode;
150 	uint32_t state_mode;
151 	uint32_t ram_select;
152 
153 	REG_GET_2(DWB_OGAM_CONTROL,
154 		DWB_OGAM_MODE_CURRENT, &state_mode,
155 		DWB_OGAM_SELECT_CURRENT, &ram_select);
156 
157 	if (state_mode == 0) {
158 		mode = LUT_BYPASS;
159 	} else if (state_mode == 2) {
160 		if (ram_select == 0)
161 			mode = LUT_RAM_A;
162 		else if (ram_select == 1)
163 			mode = LUT_RAM_B;
164 		else
165 			mode = LUT_BYPASS;
166 	} else {
167 		// Reserved value
168 		mode = LUT_BYPASS;
169 		BREAK_TO_DEBUGGER();
170 		return mode;
171 	}
172 	return mode;
173 }
174 
dwb3_configure_ogam_lut(struct dcn30_dwbc * dwbc30,bool is_ram_a)175 static void dwb3_configure_ogam_lut(
176 	struct dcn30_dwbc *dwbc30,
177 	bool is_ram_a)
178 {
179 	REG_UPDATE_2(DWB_OGAM_LUT_CONTROL,
180 		DWB_OGAM_LUT_WRITE_COLOR_MASK, 7,
181 		DWB_OGAM_LUT_HOST_SEL, (is_ram_a == true) ? 0 : 1);
182 
183 	REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
184 }
185 
dwb3_program_ogam_pwl(struct dcn30_dwbc * dwbc30,const struct pwl_result_data * rgb,uint32_t num)186 static void dwb3_program_ogam_pwl(struct dcn30_dwbc *dwbc30,
187 	const struct pwl_result_data *rgb,
188 	uint32_t num)
189 {
190 	uint32_t i;
191 
192 	uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
193 	uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
194 	uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
195 
196 	if (is_rgb_equal(rgb,  num)) {
197 		for (i = 0 ; i < num; i++)
198 			REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
199 
200 		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
201 
202 	} else {
203 
204 		REG_UPDATE(DWB_OGAM_LUT_CONTROL,
205 				DWB_OGAM_LUT_WRITE_COLOR_MASK, 4);
206 
207 		for (i = 0 ; i < num; i++)
208 			REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
209 
210 		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
211 
212 		REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
213 
214 		REG_UPDATE(DWB_OGAM_LUT_CONTROL,
215 				DWB_OGAM_LUT_WRITE_COLOR_MASK, 2);
216 
217 		for (i = 0 ; i < num; i++)
218 			REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg);
219 
220 		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green);
221 
222 		REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
223 
224 		REG_UPDATE(DWB_OGAM_LUT_CONTROL,
225 				DWB_OGAM_LUT_WRITE_COLOR_MASK, 1);
226 
227 		for (i = 0 ; i < num; i++)
228 			REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg);
229 
230 		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_blue);
231 	}
232 }
233 
dwb3_program_ogam_lut(struct dcn30_dwbc * dwbc30,const struct pwl_params * params)234 static bool dwb3_program_ogam_lut(
235 	struct dcn30_dwbc *dwbc30,
236 	const struct pwl_params *params)
237 {
238 	enum dc_lut_mode current_mode;
239 	enum dc_lut_mode next_mode;
240 
241 	if (params == NULL) {
242 		REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0);
243 		return false;
244 	}
245 
246 	REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);
247 
248 	current_mode = dwb3_get_ogam_current(dwbc30);
249 	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
250 		next_mode = LUT_RAM_B;
251 	else
252 		next_mode = LUT_RAM_A;
253 
254 	dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A);
255 
256 	if (next_mode == LUT_RAM_A)
257 		dwb3_program_ogam_luta_settings(dwbc30, params);
258 	else
259 		dwb3_program_ogam_lutb_settings(dwbc30, params);
260 
261 	dwb3_program_ogam_pwl(
262 		dwbc30, params->rgb_resulted, params->hw_points_num);
263 
264 	REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
265 
266 	return true;
267 }
268 
dwb3_ogam_set_input_transfer_func(struct dwbc * dwbc,const struct dc_transfer_func * in_transfer_func_dwb_ogam)269 bool dwb3_ogam_set_input_transfer_func(
270 	struct dwbc *dwbc,
271 	const struct dc_transfer_func *in_transfer_func_dwb_ogam)
272 {
273 	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
274 	bool result = false;
275 	struct pwl_params *dwb_ogam_lut = NULL;
276 
277 	if (in_transfer_func_dwb_ogam == NULL)
278 		return result;
279 
280 	dwb_ogam_lut = kzalloc(sizeof(*dwb_ogam_lut), GFP_KERNEL);
281 
282 	if (dwb_ogam_lut) {
283 		cm_helper_translate_curve_to_hw_format(
284 			in_transfer_func_dwb_ogam,
285 			dwb_ogam_lut, false);
286 
287 		result = dwb3_program_ogam_lut(
288 			dwbc30,
289 			dwb_ogam_lut);
290 		kfree(dwb_ogam_lut);
291 		dwb_ogam_lut = NULL;
292 	}
293 
294 	return result;
295 }
296 
dwb3_program_gamut_remap(struct dwbc * dwbc,const uint16_t * regval,enum cm_gamut_coef_format coef_format,enum cm_gamut_remap_select select)297 static void dwb3_program_gamut_remap(
298 		struct dwbc *dwbc,
299 		const uint16_t *regval,
300 		enum cm_gamut_coef_format coef_format,
301 		enum cm_gamut_remap_select select)
302 {
303 	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
304 
305 	struct color_matrices_reg gam_regs;
306 
307 	if (regval == NULL || select == CM_GAMUT_REMAP_MODE_BYPASS) {
308 		REG_SET(DWB_GAMUT_REMAP_MODE, 0,
309 				DWB_GAMUT_REMAP_MODE, 0);
310 		return;
311 	}
312 
313 	REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format);
314 
315 	gam_regs.shifts.csc_c11 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C11;
316 	gam_regs.masks.csc_c11  = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C11;
317 	gam_regs.shifts.csc_c12 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C12;
318 	gam_regs.masks.csc_c12 = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C12;
319 
320 	switch (select) {
321 	case CM_GAMUT_REMAP_MODE_RAMA_COEFF:
322 		gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);
323 		gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPA_C33_C34);
324 
325 		cm_helper_program_color_matrices(
326 				dwbc30->base.ctx,
327 				regval,
328 				&gam_regs);
329 		break;
330 	case CM_GAMUT_REMAP_MODE_RAMB_COEFF:
331 		gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPB_C11_C12);
332 		gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPB_C33_C34);
333 
334 		cm_helper_program_color_matrices(
335 				dwbc30->base.ctx,
336 				regval,
337 				&gam_regs);
338 		break;
339 	case CM_GAMUT_REMAP_MODE_RESERVED:
340 		/* should never happen, bug */
341 		BREAK_TO_DEBUGGER();
342 		return;
343 	default:
344 		break;
345 	}
346 
347 	REG_SET(DWB_GAMUT_REMAP_MODE, 0,
348 			DWB_GAMUT_REMAP_MODE, select);
349 
350 }
351 
dwb3_set_gamut_remap(struct dwbc * dwbc,const struct dc_dwb_params * params)352 void dwb3_set_gamut_remap(
353 	struct dwbc *dwbc,
354 	const struct dc_dwb_params *params)
355 {
356 	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
357 	struct cm_grph_csc_adjustment adjust = params->csc_params;
358 	int i = 0;
359 
360 	if (adjust.gamut_adjust_type != CM_GAMUT_ADJUST_TYPE_SW) {
361 		/* Bypass if type is bypass or hw */
362 		dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS);
363 	} else {
364 		struct fixed31_32 arr_matrix[12];
365 		uint16_t arr_reg_val[12];
366 		unsigned int current_mode;
367 
368 		for (i = 0; i < 12; i++)
369 			arr_matrix[i] = adjust.temperature_matrix[i];
370 
371 		convert_float_matrix(arr_reg_val, arr_matrix, 12);
372 
373 		REG_GET(DWB_GAMUT_REMAP_MODE, DWB_GAMUT_REMAP_MODE_CURRENT, &current_mode);
374 
375 		if (current_mode == CM_GAMUT_REMAP_MODE_RAMA_COEFF) {
376 			dwb3_program_gamut_remap(dwbc, arr_reg_val,
377 					adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMB_COEFF);
378 		} else {
379 			dwb3_program_gamut_remap(dwbc, arr_reg_val,
380 					adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMA_COEFF);
381 		}
382 	}
383 }
384 
dwb3_program_hdr_mult(struct dwbc * dwbc,const struct dc_dwb_params * params)385 void dwb3_program_hdr_mult(
386 	struct dwbc *dwbc,
387 	const struct dc_dwb_params *params)
388 {
389 	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
390 
391 	REG_UPDATE(DWB_HDR_MULT_COEF, DWB_HDR_MULT_COEF, params->hdr_mult);
392 }
393