1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/types.h>
15
16 #include "../../pci.h"
17 #include "pcie-designware.h"
18
19 /*
20 * These interfaces resemble the pci_find_*capability() interfaces, but these
21 * are for configuring host controllers, which are bridges *to* PCI devices but
22 * are not PCI devices themselves.
23 */
__dw_pcie_find_next_cap(struct dw_pcie * pci,u8 cap_ptr,u8 cap)24 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
25 u8 cap)
26 {
27 u8 cap_id, next_cap_ptr;
28 u16 reg;
29
30 if (!cap_ptr)
31 return 0;
32
33 reg = dw_pcie_readw_dbi(pci, cap_ptr);
34 cap_id = (reg & 0x00ff);
35
36 if (cap_id > PCI_CAP_ID_MAX)
37 return 0;
38
39 if (cap_id == cap)
40 return cap_ptr;
41
42 next_cap_ptr = (reg & 0xff00) >> 8;
43 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
44 }
45
dw_pcie_find_capability(struct dw_pcie * pci,u8 cap)46 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
47 {
48 u8 next_cap_ptr;
49 u16 reg;
50
51 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
52 next_cap_ptr = (reg & 0x00ff);
53
54 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
55 }
56 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
57
dw_pcie_find_next_ext_capability(struct dw_pcie * pci,u16 start,u8 cap)58 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
59 u8 cap)
60 {
61 u32 header;
62 int ttl;
63 int pos = PCI_CFG_SPACE_SIZE;
64
65 /* minimum 8 bytes per capability */
66 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
67
68 if (start)
69 pos = start;
70
71 header = dw_pcie_readl_dbi(pci, pos);
72 /*
73 * If we have no capabilities, this is indicated by cap ID,
74 * cap version and next pointer all being 0.
75 */
76 if (header == 0)
77 return 0;
78
79 while (ttl-- > 0) {
80 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
81 return pos;
82
83 pos = PCI_EXT_CAP_NEXT(header);
84 if (pos < PCI_CFG_SPACE_SIZE)
85 break;
86
87 header = dw_pcie_readl_dbi(pci, pos);
88 }
89
90 return 0;
91 }
92
dw_pcie_find_ext_capability(struct dw_pcie * pci,u8 cap)93 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
94 {
95 return dw_pcie_find_next_ext_capability(pci, 0, cap);
96 }
97 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
98
dw_pcie_read(void __iomem * addr,int size,u32 * val)99 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
100 {
101 if (!IS_ALIGNED((uintptr_t)addr, size)) {
102 *val = 0;
103 return PCIBIOS_BAD_REGISTER_NUMBER;
104 }
105
106 if (size == 4) {
107 *val = readl(addr);
108 } else if (size == 2) {
109 *val = readw(addr);
110 } else if (size == 1) {
111 *val = readb(addr);
112 } else {
113 *val = 0;
114 return PCIBIOS_BAD_REGISTER_NUMBER;
115 }
116
117 return PCIBIOS_SUCCESSFUL;
118 }
119 EXPORT_SYMBOL_GPL(dw_pcie_read);
120
dw_pcie_write(void __iomem * addr,int size,u32 val)121 int dw_pcie_write(void __iomem *addr, int size, u32 val)
122 {
123 if (!IS_ALIGNED((uintptr_t)addr, size))
124 return PCIBIOS_BAD_REGISTER_NUMBER;
125
126 if (size == 4)
127 writel(val, addr);
128 else if (size == 2)
129 writew(val, addr);
130 else if (size == 1)
131 writeb(val, addr);
132 else
133 return PCIBIOS_BAD_REGISTER_NUMBER;
134
135 return PCIBIOS_SUCCESSFUL;
136 }
137 EXPORT_SYMBOL_GPL(dw_pcie_write);
138
dw_pcie_read_dbi(struct dw_pcie * pci,u32 reg,size_t size)139 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
140 {
141 int ret;
142 u32 val;
143
144 if (pci->ops && pci->ops->read_dbi)
145 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
146
147 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
148 if (ret)
149 dev_err(pci->dev, "Read DBI address failed\n");
150
151 return val;
152 }
153 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
154
dw_pcie_write_dbi(struct dw_pcie * pci,u32 reg,size_t size,u32 val)155 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
156 {
157 int ret;
158
159 if (pci->ops && pci->ops->write_dbi) {
160 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
161 return;
162 }
163
164 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
165 if (ret)
166 dev_err(pci->dev, "Write DBI address failed\n");
167 }
168 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
169
dw_pcie_write_dbi2(struct dw_pcie * pci,u32 reg,size_t size,u32 val)170 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
171 {
172 int ret;
173
174 if (pci->ops && pci->ops->write_dbi2) {
175 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
176 return;
177 }
178
179 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
180 if (ret)
181 dev_err(pci->dev, "write DBI address failed\n");
182 }
183
dw_pcie_readl_atu(struct dw_pcie * pci,u32 reg)184 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
185 {
186 int ret;
187 u32 val;
188
189 if (pci->ops && pci->ops->read_dbi)
190 return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);
191
192 ret = dw_pcie_read(pci->atu_base + reg, 4, &val);
193 if (ret)
194 dev_err(pci->dev, "Read ATU address failed\n");
195
196 return val;
197 }
198
dw_pcie_writel_atu(struct dw_pcie * pci,u32 reg,u32 val)199 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
200 {
201 int ret;
202
203 if (pci->ops && pci->ops->write_dbi) {
204 pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);
205 return;
206 }
207
208 ret = dw_pcie_write(pci->atu_base + reg, 4, val);
209 if (ret)
210 dev_err(pci->dev, "Write ATU address failed\n");
211 }
212
dw_pcie_readl_ob_unroll(struct dw_pcie * pci,u32 index,u32 reg)213 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
214 {
215 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
216
217 return dw_pcie_readl_atu(pci, offset + reg);
218 }
219
dw_pcie_writel_ob_unroll(struct dw_pcie * pci,u32 index,u32 reg,u32 val)220 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
221 u32 val)
222 {
223 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
224
225 dw_pcie_writel_atu(pci, offset + reg, val);
226 }
227
dw_pcie_enable_ecrc(u32 val)228 static inline u32 dw_pcie_enable_ecrc(u32 val)
229 {
230 /*
231 * DesignWare core version 4.90A has a design issue where the 'TD'
232 * bit in the Control register-1 of the ATU outbound region acts
233 * like an override for the ECRC setting, i.e., the presence of TLP
234 * Digest (ECRC) in the outgoing TLPs is solely determined by this
235 * bit. This is contrary to the PCIe spec which says that the
236 * enablement of the ECRC is solely determined by the AER
237 * registers.
238 *
239 * Because of this, even when the ECRC is enabled through AER
240 * registers, the transactions going through ATU won't have TLP
241 * Digest as there is no way the PCI core AER code could program
242 * the TD bit which is specific to the DesignWare core.
243 *
244 * The best way to handle this scenario is to program the TD bit
245 * always. It affects only the traffic from root port to downstream
246 * devices.
247 *
248 * At this point,
249 * When ECRC is enabled in AER registers, everything works normally
250 * When ECRC is NOT enabled in AER registers, then,
251 * on Root Port:- TLP Digest (DWord size) gets appended to each packet
252 * even through it is not required. Since downstream
253 * TLPs are mostly for configuration accesses and BAR
254 * accesses, they are not in critical path and won't
255 * have much negative effect on the performance.
256 * on End Point:- TLP Digest is received for some/all the packets coming
257 * from the root port. TLP Digest is ignored because,
258 * as per the PCIe Spec r5.0 v1.0 section 2.2.3
259 * "TLP Digest Rules", when an endpoint receives TLP
260 * Digest when its ECRC check functionality is disabled
261 * in AER registers, received TLP Digest is just ignored.
262 * Since there is no issue or error reported either side, best way to
263 * handle the scenario is to program TD bit by default.
264 */
265
266 return val | PCIE_ATU_TD;
267 }
268
dw_pcie_prog_outbound_atu_unroll(struct dw_pcie * pci,u8 func_no,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)269 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
270 int index, int type,
271 u64 cpu_addr, u64 pci_addr,
272 u64 size)
273 {
274 u32 retries, val;
275 u64 limit_addr = cpu_addr + size - 1;
276
277 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
278 lower_32_bits(cpu_addr));
279 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
280 upper_32_bits(cpu_addr));
281 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
282 lower_32_bits(limit_addr));
283 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
284 upper_32_bits(limit_addr));
285 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
286 lower_32_bits(pci_addr));
287 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
288 upper_32_bits(pci_addr));
289 val = type | PCIE_ATU_FUNC_NUM(func_no);
290 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr))
291 val |= PCIE_ATU_INCREASE_REGION_SIZE;
292 if (pci->version == 0x490A)
293 val = dw_pcie_enable_ecrc(val);
294 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
295 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
296 PCIE_ATU_ENABLE);
297
298 /*
299 * Make sure ATU enable takes effect before any subsequent config
300 * and I/O accesses.
301 */
302 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
303 val = dw_pcie_readl_ob_unroll(pci, index,
304 PCIE_ATU_UNR_REGION_CTRL2);
305 if (val & PCIE_ATU_ENABLE)
306 return;
307
308 mdelay(LINK_WAIT_IATU);
309 }
310 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
311 }
312
__dw_pcie_prog_outbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)313 static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
314 int index, int type, u64 cpu_addr,
315 u64 pci_addr, u64 size)
316 {
317 u32 retries, val;
318 u64 limit_addr;
319
320 if (pci->ops && pci->ops->cpu_addr_fixup)
321 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
322
323 if (pci->iatu_unroll_enabled) {
324 dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
325 cpu_addr, pci_addr, size);
326 return;
327 }
328
329 limit_addr = cpu_addr + size - 1;
330
331 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
332 PCIE_ATU_REGION_OUTBOUND | index);
333 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
334 lower_32_bits(cpu_addr));
335 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
336 upper_32_bits(cpu_addr));
337 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
338 lower_32_bits(limit_addr));
339 if (pci->version >= 0x460A)
340 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
341 upper_32_bits(limit_addr));
342 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
343 lower_32_bits(pci_addr));
344 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
345 upper_32_bits(pci_addr));
346 val = type | PCIE_ATU_FUNC_NUM(func_no);
347 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
348 pci->version >= 0x460A)
349 val |= PCIE_ATU_INCREASE_REGION_SIZE;
350 if (pci->version == 0x490A)
351 val = dw_pcie_enable_ecrc(val);
352 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
353 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
354
355 /*
356 * Make sure ATU enable takes effect before any subsequent config
357 * and I/O accesses.
358 */
359 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
360 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
361 if (val & PCIE_ATU_ENABLE)
362 return;
363
364 mdelay(LINK_WAIT_IATU);
365 }
366 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
367 }
368
dw_pcie_prog_outbound_atu(struct dw_pcie * pci,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)369 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
370 u64 cpu_addr, u64 pci_addr, u64 size)
371 {
372 __dw_pcie_prog_outbound_atu(pci, 0, index, type,
373 cpu_addr, pci_addr, size);
374 }
375
dw_pcie_prog_ep_outbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 cpu_addr,u64 pci_addr,u64 size)376 void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
377 int type, u64 cpu_addr, u64 pci_addr,
378 u64 size)
379 {
380 __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
381 cpu_addr, pci_addr, size);
382 }
383
dw_pcie_readl_ib_unroll(struct dw_pcie * pci,u32 index,u32 reg)384 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
385 {
386 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
387
388 return dw_pcie_readl_atu(pci, offset + reg);
389 }
390
dw_pcie_writel_ib_unroll(struct dw_pcie * pci,u32 index,u32 reg,u32 val)391 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
392 u32 val)
393 {
394 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
395
396 dw_pcie_writel_atu(pci, offset + reg, val);
397 }
398
dw_pcie_prog_inbound_atu_unroll(struct dw_pcie * pci,u8 func_no,int index,int bar,u64 cpu_addr,enum dw_pcie_as_type as_type)399 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
400 int index, int bar, u64 cpu_addr,
401 enum dw_pcie_as_type as_type)
402 {
403 int type;
404 u32 retries, val;
405
406 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
407 lower_32_bits(cpu_addr));
408 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
409 upper_32_bits(cpu_addr));
410
411 switch (as_type) {
412 case DW_PCIE_AS_MEM:
413 type = PCIE_ATU_TYPE_MEM;
414 break;
415 case DW_PCIE_AS_IO:
416 type = PCIE_ATU_TYPE_IO;
417 break;
418 default:
419 return -EINVAL;
420 }
421
422 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
423 PCIE_ATU_FUNC_NUM(func_no));
424 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
425 PCIE_ATU_FUNC_NUM_MATCH_EN |
426 PCIE_ATU_ENABLE |
427 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
428
429 /*
430 * Make sure ATU enable takes effect before any subsequent config
431 * and I/O accesses.
432 */
433 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
434 val = dw_pcie_readl_ib_unroll(pci, index,
435 PCIE_ATU_UNR_REGION_CTRL2);
436 if (val & PCIE_ATU_ENABLE)
437 return 0;
438
439 mdelay(LINK_WAIT_IATU);
440 }
441 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
442
443 return -EBUSY;
444 }
445
dw_pcie_prog_inbound_atu(struct dw_pcie * pci,u8 func_no,int index,int bar,u64 cpu_addr,enum dw_pcie_as_type as_type)446 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
447 int bar, u64 cpu_addr,
448 enum dw_pcie_as_type as_type)
449 {
450 int type;
451 u32 retries, val;
452
453 if (pci->iatu_unroll_enabled)
454 return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
455 cpu_addr, as_type);
456
457 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
458 index);
459 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
460 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
461
462 switch (as_type) {
463 case DW_PCIE_AS_MEM:
464 type = PCIE_ATU_TYPE_MEM;
465 break;
466 case DW_PCIE_AS_IO:
467 type = PCIE_ATU_TYPE_IO;
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
474 PCIE_ATU_FUNC_NUM(func_no));
475 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
476 PCIE_ATU_FUNC_NUM_MATCH_EN |
477 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
478
479 /*
480 * Make sure ATU enable takes effect before any subsequent config
481 * and I/O accesses.
482 */
483 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
484 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
485 if (val & PCIE_ATU_ENABLE)
486 return 0;
487
488 mdelay(LINK_WAIT_IATU);
489 }
490 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
491
492 return -EBUSY;
493 }
494
dw_pcie_disable_atu(struct dw_pcie * pci,int index,enum dw_pcie_region_type type)495 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
496 enum dw_pcie_region_type type)
497 {
498 u32 region;
499
500 switch (type) {
501 case DW_PCIE_REGION_INBOUND:
502 region = PCIE_ATU_REGION_INBOUND;
503 break;
504 case DW_PCIE_REGION_OUTBOUND:
505 region = PCIE_ATU_REGION_OUTBOUND;
506 break;
507 default:
508 return;
509 }
510
511 if (pci->iatu_unroll_enabled) {
512 if (region == PCIE_ATU_REGION_INBOUND) {
513 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
514 ~(u32)PCIE_ATU_ENABLE);
515 } else {
516 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
517 ~(u32)PCIE_ATU_ENABLE);
518 }
519 } else {
520 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
521 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
522 }
523 }
524
dw_pcie_wait_for_link(struct dw_pcie * pci)525 int dw_pcie_wait_for_link(struct dw_pcie *pci)
526 {
527 int retries;
528
529 /* Check if the link is up or not */
530 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
531 if (dw_pcie_link_up(pci)) {
532 dev_info(pci->dev, "Link up\n");
533 return 0;
534 }
535 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
536 }
537
538 dev_info(pci->dev, "Phy link never came up\n");
539
540 return -ETIMEDOUT;
541 }
542 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
543
dw_pcie_link_up(struct dw_pcie * pci)544 int dw_pcie_link_up(struct dw_pcie *pci)
545 {
546 u32 val;
547
548 if (pci->ops && pci->ops->link_up)
549 return pci->ops->link_up(pci);
550
551 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
552 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
553 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
554 }
555 EXPORT_SYMBOL_GPL(dw_pcie_link_up);
556
dw_pcie_upconfig_setup(struct dw_pcie * pci)557 void dw_pcie_upconfig_setup(struct dw_pcie *pci)
558 {
559 u32 val;
560
561 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
562 val |= PORT_MLTI_UPCFG_SUPPORT;
563 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
564 }
565 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
566
dw_pcie_link_set_max_speed(struct dw_pcie * pci,u32 link_gen)567 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
568 {
569 u32 cap, ctrl2, link_speed;
570 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
571
572 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
573 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
574 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
575
576 switch (pcie_link_speed[link_gen]) {
577 case PCIE_SPEED_2_5GT:
578 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
579 break;
580 case PCIE_SPEED_5_0GT:
581 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
582 break;
583 case PCIE_SPEED_8_0GT:
584 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
585 break;
586 case PCIE_SPEED_16_0GT:
587 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
588 break;
589 default:
590 /* Use hardware capability */
591 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
592 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
593 break;
594 }
595
596 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
597
598 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
599 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
600
601 }
602
dw_pcie_iatu_unroll_enabled(struct dw_pcie * pci)603 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
604 {
605 u32 val;
606
607 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
608 if (val == 0xffffffff)
609 return 1;
610
611 return 0;
612 }
613
dw_pcie_iatu_detect_regions_unroll(struct dw_pcie * pci)614 static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci)
615 {
616 int max_region, i, ob = 0, ib = 0;
617 u32 val;
618
619 max_region = min((int)pci->atu_size / 512, 256);
620
621 for (i = 0; i < max_region; i++) {
622 dw_pcie_writel_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET,
623 0x11110000);
624
625 val = dw_pcie_readl_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET);
626 if (val == 0x11110000)
627 ob++;
628 else
629 break;
630 }
631
632 for (i = 0; i < max_region; i++) {
633 dw_pcie_writel_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET,
634 0x11110000);
635
636 val = dw_pcie_readl_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET);
637 if (val == 0x11110000)
638 ib++;
639 else
640 break;
641 }
642 pci->num_ib_windows = ib;
643 pci->num_ob_windows = ob;
644 }
645
dw_pcie_iatu_detect_regions(struct dw_pcie * pci)646 static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
647 {
648 int max_region, i, ob = 0, ib = 0;
649 u32 val;
650
651 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
652 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
653
654 for (i = 0; i < max_region; i++) {
655 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | i);
656 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000);
657 val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET);
658 if (val == 0x11110000)
659 ob++;
660 else
661 break;
662 }
663
664 for (i = 0; i < max_region; i++) {
665 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | i);
666 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000);
667 val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET);
668 if (val == 0x11110000)
669 ib++;
670 else
671 break;
672 }
673
674 pci->num_ib_windows = ib;
675 pci->num_ob_windows = ob;
676 }
677
dw_pcie_iatu_detect(struct dw_pcie * pci)678 void dw_pcie_iatu_detect(struct dw_pcie *pci)
679 {
680 struct device *dev = pci->dev;
681 struct platform_device *pdev = to_platform_device(dev);
682
683 if (pci->version >= 0x480A || (!pci->version &&
684 dw_pcie_iatu_unroll_enabled(pci))) {
685 pci->iatu_unroll_enabled = true;
686 if (!pci->atu_base) {
687 struct resource *res =
688 platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
689 if (res) {
690 pci->atu_size = resource_size(res);
691 pci->atu_base = devm_ioremap_resource(dev, res);
692 }
693 if (!pci->atu_base || IS_ERR(pci->atu_base))
694 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
695 }
696
697 if (!pci->atu_size)
698 /* Pick a minimal default, enough for 8 in and 8 out windows */
699 pci->atu_size = SZ_4K;
700
701 dw_pcie_iatu_detect_regions_unroll(pci);
702 } else
703 dw_pcie_iatu_detect_regions(pci);
704
705 dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
706 "enabled" : "disabled");
707
708 dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound",
709 pci->num_ob_windows, pci->num_ib_windows);
710 }
711
dw_pcie_setup(struct dw_pcie * pci)712 void dw_pcie_setup(struct dw_pcie *pci)
713 {
714 u32 val;
715 struct device *dev = pci->dev;
716 struct device_node *np = dev->of_node;
717
718 if (pci->link_gen > 0)
719 dw_pcie_link_set_max_speed(pci, pci->link_gen);
720
721 /* Configure Gen1 N_FTS */
722 if (pci->n_fts[0]) {
723 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
724 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
725 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
726 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
727 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
728 }
729
730 /* Configure Gen2+ N_FTS */
731 if (pci->n_fts[1]) {
732 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
733 val &= ~PORT_LOGIC_N_FTS_MASK;
734 val |= pci->n_fts[pci->link_gen - 1];
735 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
736 }
737
738 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
739 val &= ~PORT_LINK_FAST_LINK_MODE;
740 val |= PORT_LINK_DLL_LINK_EN;
741 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
742
743 if (of_property_read_bool(np, "snps,enable-cdm-check")) {
744 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
745 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
746 PCIE_PL_CHK_REG_CHK_REG_START;
747 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
748 }
749
750 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
751 if (!pci->num_lanes) {
752 dev_dbg(pci->dev, "Using h/w default number of lanes\n");
753 return;
754 }
755
756 /* Set the number of lanes */
757 val &= ~PORT_LINK_FAST_LINK_MODE;
758 val &= ~PORT_LINK_MODE_MASK;
759 switch (pci->num_lanes) {
760 case 1:
761 val |= PORT_LINK_MODE_1_LANES;
762 break;
763 case 2:
764 val |= PORT_LINK_MODE_2_LANES;
765 break;
766 case 4:
767 val |= PORT_LINK_MODE_4_LANES;
768 break;
769 case 8:
770 val |= PORT_LINK_MODE_8_LANES;
771 break;
772 default:
773 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
774 return;
775 }
776 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
777
778 /* Set link width speed control register */
779 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
780 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
781 switch (pci->num_lanes) {
782 case 1:
783 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
784 break;
785 case 2:
786 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
787 break;
788 case 4:
789 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
790 break;
791 case 8:
792 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
793 break;
794 }
795 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
796 }
797