1 /*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/err.h>
23 #include <linux/slab.h>
24
25 #include <plat/display.h>
26 #include <plat/cpu.h>
27
28 #include "dss.h"
29 #include "dss_features.h"
30
31 /* Defines a generic omap register field */
32 struct dss_reg_field {
33 u8 start, end;
34 };
35
36 struct dss_param_range {
37 int min, max;
38 };
39
40 struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
44 const u32 has_feature;
45
46 const int num_mgrs;
47 const int num_ovls;
48 const enum omap_display_type *supported_displays;
49 const enum omap_color_mode *supported_color_modes;
50 const char * const *clksrc_names;
51 const struct dss_param_range *dss_params;
52 };
53
54 /* This struct is assigned to one of the below during initialization */
55 static struct omap_dss_features *omap_current_dss_features;
56
57 static const struct dss_reg_field omap2_dss_reg_fields[] = {
58 [FEAT_REG_FIRHINC] = { 11, 0 },
59 [FEAT_REG_FIRVINC] = { 27, 16 },
60 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
61 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
62 [FEAT_REG_FIFOSIZE] = { 8, 0 },
63 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
64 [FEAT_REG_VERTICALACCU] = { 25, 16 },
65 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
66 [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
67 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
68 [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
69 [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
70 };
71
72 static const struct dss_reg_field omap3_dss_reg_fields[] = {
73 [FEAT_REG_FIRHINC] = { 12, 0 },
74 [FEAT_REG_FIRVINC] = { 28, 16 },
75 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
76 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
77 [FEAT_REG_FIFOSIZE] = { 10, 0 },
78 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
79 [FEAT_REG_VERTICALACCU] = { 25, 16 },
80 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
81 [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
82 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
83 [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
84 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
85 };
86
87 static const struct dss_reg_field omap4_dss_reg_fields[] = {
88 [FEAT_REG_FIRHINC] = { 12, 0 },
89 [FEAT_REG_FIRVINC] = { 28, 16 },
90 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
91 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
92 [FEAT_REG_FIFOSIZE] = { 15, 0 },
93 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
94 [FEAT_REG_VERTICALACCU] = { 26, 16 },
95 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
96 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
97 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
98 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
99 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
100 };
101
102 static const enum omap_display_type omap2_dss_supported_displays[] = {
103 /* OMAP_DSS_CHANNEL_LCD */
104 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
105
106 /* OMAP_DSS_CHANNEL_DIGIT */
107 OMAP_DISPLAY_TYPE_VENC,
108 };
109
110 static const enum omap_display_type omap3430_dss_supported_displays[] = {
111 /* OMAP_DSS_CHANNEL_LCD */
112 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
113 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
114
115 /* OMAP_DSS_CHANNEL_DIGIT */
116 OMAP_DISPLAY_TYPE_VENC,
117 };
118
119 static const enum omap_display_type omap3630_dss_supported_displays[] = {
120 /* OMAP_DSS_CHANNEL_LCD */
121 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
122 OMAP_DISPLAY_TYPE_DSI,
123
124 /* OMAP_DSS_CHANNEL_DIGIT */
125 OMAP_DISPLAY_TYPE_VENC,
126 };
127
128 static const enum omap_display_type omap4_dss_supported_displays[] = {
129 /* OMAP_DSS_CHANNEL_LCD */
130 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
131
132 /* OMAP_DSS_CHANNEL_DIGIT */
133 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
134
135 /* OMAP_DSS_CHANNEL_LCD2 */
136 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
137 OMAP_DISPLAY_TYPE_DSI,
138 };
139
140 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
141 /* OMAP_DSS_GFX */
142 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
143 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
144 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
145 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
146
147 /* OMAP_DSS_VIDEO1 */
148 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
149 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
150 OMAP_DSS_COLOR_UYVY,
151
152 /* OMAP_DSS_VIDEO2 */
153 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
154 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
155 OMAP_DSS_COLOR_UYVY,
156 };
157
158 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
159 /* OMAP_DSS_GFX */
160 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
161 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
162 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
163 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
164 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
165 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
166
167 /* OMAP_DSS_VIDEO1 */
168 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
169 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
170 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
171
172 /* OMAP_DSS_VIDEO2 */
173 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
174 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
175 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
176 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
177 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
178 };
179
180 static const char * const omap2_dss_clk_source_names[] = {
181 [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
182 [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
183 [DSS_CLK_SRC_FCK] = "DSS_FCLK1",
184 };
185
186 static const char * const omap3_dss_clk_source_names[] = {
187 [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
188 [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
189 [DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
190 };
191
192 static const char * const omap4_dss_clk_source_names[] = {
193 [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
194 [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
195 [DSS_CLK_SRC_FCK] = "DSS_FCLK",
196 };
197
198 static const struct dss_param_range omap2_dss_param_range[] = {
199 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
200 [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
201 [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
202 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
203 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
204 [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
205 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
206 };
207
208 static const struct dss_param_range omap3_dss_param_range[] = {
209 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
210 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
211 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
212 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
213 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
214 [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
215 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
216 };
217
218 static const struct dss_param_range omap4_dss_param_range[] = {
219 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
220 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
221 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
222 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
223 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
224 [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
225 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
226 };
227
228 /* OMAP2 DSS Features */
229 static struct omap_dss_features omap2_dss_features = {
230 .reg_fields = omap2_dss_reg_fields,
231 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
232
233 .has_feature =
234 FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
235 FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
236 FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
237
238 .num_mgrs = 2,
239 .num_ovls = 3,
240 .supported_displays = omap2_dss_supported_displays,
241 .supported_color_modes = omap2_dss_supported_color_modes,
242 .clksrc_names = omap2_dss_clk_source_names,
243 .dss_params = omap2_dss_param_range,
244 };
245
246 /* OMAP3 DSS Features */
247 static struct omap_dss_features omap3430_dss_features = {
248 .reg_fields = omap3_dss_reg_fields,
249 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
250
251 .has_feature =
252 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
253 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
254 FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
255 FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF,
256
257 .num_mgrs = 2,
258 .num_ovls = 3,
259 .supported_displays = omap3430_dss_supported_displays,
260 .supported_color_modes = omap3_dss_supported_color_modes,
261 .clksrc_names = omap3_dss_clk_source_names,
262 .dss_params = omap3_dss_param_range,
263 };
264
265 static struct omap_dss_features omap3630_dss_features = {
266 .reg_fields = omap3_dss_reg_fields,
267 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
268
269 .has_feature =
270 FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
271 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
272 FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
273 FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
274 FEAT_RESIZECONF,
275
276 .num_mgrs = 2,
277 .num_ovls = 3,
278 .supported_displays = omap3630_dss_supported_displays,
279 .supported_color_modes = omap3_dss_supported_color_modes,
280 .clksrc_names = omap3_dss_clk_source_names,
281 .dss_params = omap3_dss_param_range,
282 };
283
284 /* OMAP4 DSS Features */
285 static struct omap_dss_features omap4_dss_features = {
286 .reg_fields = omap4_dss_reg_fields,
287 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
288
289 .has_feature =
290 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
291 FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
292 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC,
293
294 .num_mgrs = 3,
295 .num_ovls = 3,
296 .supported_displays = omap4_dss_supported_displays,
297 .supported_color_modes = omap3_dss_supported_color_modes,
298 .clksrc_names = omap4_dss_clk_source_names,
299 .dss_params = omap4_dss_param_range,
300 };
301
302 /* Functions returning values related to a DSS feature */
dss_feat_get_num_mgrs(void)303 int dss_feat_get_num_mgrs(void)
304 {
305 return omap_current_dss_features->num_mgrs;
306 }
307
dss_feat_get_num_ovls(void)308 int dss_feat_get_num_ovls(void)
309 {
310 return omap_current_dss_features->num_ovls;
311 }
312
dss_feat_get_param_min(enum dss_range_param param)313 unsigned long dss_feat_get_param_min(enum dss_range_param param)
314 {
315 return omap_current_dss_features->dss_params[param].min;
316 }
317
dss_feat_get_param_max(enum dss_range_param param)318 unsigned long dss_feat_get_param_max(enum dss_range_param param)
319 {
320 return omap_current_dss_features->dss_params[param].max;
321 }
322
dss_feat_get_supported_displays(enum omap_channel channel)323 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
324 {
325 return omap_current_dss_features->supported_displays[channel];
326 }
327
dss_feat_get_supported_color_modes(enum omap_plane plane)328 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
329 {
330 return omap_current_dss_features->supported_color_modes[plane];
331 }
332
dss_feat_color_mode_supported(enum omap_plane plane,enum omap_color_mode color_mode)333 bool dss_feat_color_mode_supported(enum omap_plane plane,
334 enum omap_color_mode color_mode)
335 {
336 return omap_current_dss_features->supported_color_modes[plane] &
337 color_mode;
338 }
339
dss_feat_get_clk_source_name(enum dss_clk_source id)340 const char *dss_feat_get_clk_source_name(enum dss_clk_source id)
341 {
342 return omap_current_dss_features->clksrc_names[id];
343 }
344
345 /* DSS has_feature check */
dss_has_feature(enum dss_feat_id id)346 bool dss_has_feature(enum dss_feat_id id)
347 {
348 return omap_current_dss_features->has_feature & id;
349 }
350
dss_feat_get_reg_field(enum dss_feat_reg_field id,u8 * start,u8 * end)351 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
352 {
353 if (id >= omap_current_dss_features->num_reg_fields)
354 BUG();
355
356 *start = omap_current_dss_features->reg_fields[id].start;
357 *end = omap_current_dss_features->reg_fields[id].end;
358 }
359
dss_features_init(void)360 void dss_features_init(void)
361 {
362 if (cpu_is_omap24xx())
363 omap_current_dss_features = &omap2_dss_features;
364 else if (cpu_is_omap3630())
365 omap_current_dss_features = &omap3630_dss_features;
366 else if (cpu_is_omap34xx())
367 omap_current_dss_features = &omap3430_dss_features;
368 else
369 omap_current_dss_features = &omap4_dss_features;
370 }
371