1 /*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/err.h>
23 #include <linux/slab.h>
24
25 #include <video/omapdss.h>
26 #include <plat/cpu.h>
27
28 #include "dss.h"
29 #include "dss_features.h"
30
31 /* Defines a generic omap register field */
32 struct dss_reg_field {
33 u8 start, end;
34 };
35
36 struct dss_param_range {
37 int min, max;
38 };
39
40 struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
44 const enum dss_feat_id *features;
45 const int num_features;
46
47 const int num_mgrs;
48 const int num_ovls;
49 const enum omap_display_type *supported_displays;
50 const enum omap_color_mode *supported_color_modes;
51 const enum omap_overlay_caps *overlay_caps;
52 const char * const *clksrc_names;
53 const struct dss_param_range *dss_params;
54
55 const u32 buffer_size_unit;
56 const u32 burst_size_unit;
57 };
58
59 /* This struct is assigned to one of the below during initialization */
60 static const struct omap_dss_features *omap_current_dss_features;
61
62 static const struct dss_reg_field omap2_dss_reg_fields[] = {
63 [FEAT_REG_FIRHINC] = { 11, 0 },
64 [FEAT_REG_FIRVINC] = { 27, 16 },
65 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
66 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
67 [FEAT_REG_FIFOSIZE] = { 8, 0 },
68 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
69 [FEAT_REG_VERTICALACCU] = { 25, 16 },
70 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
71 [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
72 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
73 [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
74 [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
75 };
76
77 static const struct dss_reg_field omap3_dss_reg_fields[] = {
78 [FEAT_REG_FIRHINC] = { 12, 0 },
79 [FEAT_REG_FIRVINC] = { 28, 16 },
80 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
81 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
82 [FEAT_REG_FIFOSIZE] = { 10, 0 },
83 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
84 [FEAT_REG_VERTICALACCU] = { 25, 16 },
85 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
86 [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
87 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
88 [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
89 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
90 };
91
92 static const struct dss_reg_field omap4_dss_reg_fields[] = {
93 [FEAT_REG_FIRHINC] = { 12, 0 },
94 [FEAT_REG_FIRVINC] = { 28, 16 },
95 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
96 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
97 [FEAT_REG_FIFOSIZE] = { 15, 0 },
98 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
99 [FEAT_REG_VERTICALACCU] = { 26, 16 },
100 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
101 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
102 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
103 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
104 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
105 };
106
107 static const enum omap_display_type omap2_dss_supported_displays[] = {
108 /* OMAP_DSS_CHANNEL_LCD */
109 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
110
111 /* OMAP_DSS_CHANNEL_DIGIT */
112 OMAP_DISPLAY_TYPE_VENC,
113 };
114
115 static const enum omap_display_type omap3430_dss_supported_displays[] = {
116 /* OMAP_DSS_CHANNEL_LCD */
117 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
118 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
119
120 /* OMAP_DSS_CHANNEL_DIGIT */
121 OMAP_DISPLAY_TYPE_VENC,
122 };
123
124 static const enum omap_display_type omap3630_dss_supported_displays[] = {
125 /* OMAP_DSS_CHANNEL_LCD */
126 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
127 OMAP_DISPLAY_TYPE_DSI,
128
129 /* OMAP_DSS_CHANNEL_DIGIT */
130 OMAP_DISPLAY_TYPE_VENC,
131 };
132
133 static const enum omap_display_type omap4_dss_supported_displays[] = {
134 /* OMAP_DSS_CHANNEL_LCD */
135 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
136
137 /* OMAP_DSS_CHANNEL_DIGIT */
138 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
139
140 /* OMAP_DSS_CHANNEL_LCD2 */
141 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
142 OMAP_DISPLAY_TYPE_DSI,
143 };
144
145 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
146 /* OMAP_DSS_GFX */
147 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
148 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
149 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
150 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
151
152 /* OMAP_DSS_VIDEO1 */
153 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
154 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
155 OMAP_DSS_COLOR_UYVY,
156
157 /* OMAP_DSS_VIDEO2 */
158 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
159 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
160 OMAP_DSS_COLOR_UYVY,
161 };
162
163 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
164 /* OMAP_DSS_GFX */
165 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
166 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
167 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
168 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
169 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
170 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
171
172 /* OMAP_DSS_VIDEO1 */
173 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
174 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
175 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
176
177 /* OMAP_DSS_VIDEO2 */
178 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
179 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
180 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
181 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
182 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
183 };
184
185 static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
186 /* OMAP_DSS_GFX */
187 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
188 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
189 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
190 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
191 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
192 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
193 OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
194 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
195
196 /* OMAP_DSS_VIDEO1 */
197 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
198 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
199 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
200 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
201 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
202 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
203 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
204 OMAP_DSS_COLOR_RGBX32,
205
206 /* OMAP_DSS_VIDEO2 */
207 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
208 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
209 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
210 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
211 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
212 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
213 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
214 OMAP_DSS_COLOR_RGBX32,
215
216 /* OMAP_DSS_VIDEO3 */
217 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
218 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
219 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
220 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
221 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
222 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
223 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
224 OMAP_DSS_COLOR_RGBX32,
225 };
226
227 static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
228 /* OMAP_DSS_GFX */
229 0,
230
231 /* OMAP_DSS_VIDEO1 */
232 OMAP_DSS_OVL_CAP_SCALE,
233
234 /* OMAP_DSS_VIDEO2 */
235 OMAP_DSS_OVL_CAP_SCALE,
236 };
237
238 static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
239 /* OMAP_DSS_GFX */
240 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
241
242 /* OMAP_DSS_VIDEO1 */
243 OMAP_DSS_OVL_CAP_SCALE,
244
245 /* OMAP_DSS_VIDEO2 */
246 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
247 };
248
249 static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
250 /* OMAP_DSS_GFX */
251 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
252
253 /* OMAP_DSS_VIDEO1 */
254 OMAP_DSS_OVL_CAP_SCALE,
255
256 /* OMAP_DSS_VIDEO2 */
257 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
258 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
259 };
260
261 static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
262 /* OMAP_DSS_GFX */
263 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
264 OMAP_DSS_OVL_CAP_ZORDER,
265
266 /* OMAP_DSS_VIDEO1 */
267 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
268 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
269
270 /* OMAP_DSS_VIDEO2 */
271 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
272 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
273
274 /* OMAP_DSS_VIDEO3 */
275 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
276 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
277 };
278
279 static const char * const omap2_dss_clk_source_names[] = {
280 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
281 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
282 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
283 };
284
285 static const char * const omap3_dss_clk_source_names[] = {
286 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
287 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
288 [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
289 };
290
291 static const char * const omap4_dss_clk_source_names[] = {
292 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
293 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
294 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
295 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
296 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
297 };
298
299 static const struct dss_param_range omap2_dss_param_range[] = {
300 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
301 [FEAT_PARAM_DSS_PCD] = { 2, 255 },
302 [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
303 [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
304 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
305 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
306 [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
307 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
308 [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
309 /*
310 * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
311 * scaler cannot scale a image with width more than 768.
312 */
313 [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
314 };
315
316 static const struct dss_param_range omap3_dss_param_range[] = {
317 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
318 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
319 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
320 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
321 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
322 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
323 [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
324 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
325 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
326 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
327 };
328
329 static const struct dss_param_range omap4_dss_param_range[] = {
330 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
331 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
332 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
333 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
334 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
335 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
336 [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
337 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
338 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
339 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
340 };
341
342 static const enum dss_feat_id omap2_dss_feat_list[] = {
343 FEAT_LCDENABLEPOL,
344 FEAT_LCDENABLESIGNAL,
345 FEAT_PCKFREEENABLE,
346 FEAT_FUNCGATED,
347 FEAT_ROWREPEATENABLE,
348 FEAT_RESIZECONF,
349 };
350
351 static const enum dss_feat_id omap3430_dss_feat_list[] = {
352 FEAT_LCDENABLEPOL,
353 FEAT_LCDENABLESIGNAL,
354 FEAT_PCKFREEENABLE,
355 FEAT_FUNCGATED,
356 FEAT_LINEBUFFERSPLIT,
357 FEAT_ROWREPEATENABLE,
358 FEAT_RESIZECONF,
359 FEAT_DSI_PLL_FREQSEL,
360 FEAT_DSI_REVERSE_TXCLKESC,
361 FEAT_VENC_REQUIRES_TV_DAC_CLK,
362 FEAT_CPR,
363 FEAT_PRELOAD,
364 FEAT_FIR_COEF_V,
365 FEAT_ALPHA_FIXED_ZORDER,
366 FEAT_FIFO_MERGE,
367 FEAT_OMAP3_DSI_FIFO_BUG,
368 };
369
370 static const enum dss_feat_id omap3630_dss_feat_list[] = {
371 FEAT_LCDENABLEPOL,
372 FEAT_LCDENABLESIGNAL,
373 FEAT_PCKFREEENABLE,
374 FEAT_FUNCGATED,
375 FEAT_LINEBUFFERSPLIT,
376 FEAT_ROWREPEATENABLE,
377 FEAT_RESIZECONF,
378 FEAT_DSI_PLL_PWR_BUG,
379 FEAT_DSI_PLL_FREQSEL,
380 FEAT_CPR,
381 FEAT_PRELOAD,
382 FEAT_FIR_COEF_V,
383 FEAT_ALPHA_FIXED_ZORDER,
384 FEAT_FIFO_MERGE,
385 FEAT_OMAP3_DSI_FIFO_BUG,
386 };
387
388 static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
389 FEAT_MGR_LCD2,
390 FEAT_CORE_CLK_DIV,
391 FEAT_LCD_CLK_SRC,
392 FEAT_DSI_DCS_CMD_CONFIG_VC,
393 FEAT_DSI_VC_OCP_WIDTH,
394 FEAT_DSI_GNQ,
395 FEAT_HANDLE_UV_SEPARATE,
396 FEAT_ATTR2,
397 FEAT_CPR,
398 FEAT_PRELOAD,
399 FEAT_FIR_COEF_V,
400 FEAT_ALPHA_FREE_ZORDER,
401 FEAT_FIFO_MERGE,
402 };
403
404 static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
405 FEAT_MGR_LCD2,
406 FEAT_CORE_CLK_DIV,
407 FEAT_LCD_CLK_SRC,
408 FEAT_DSI_DCS_CMD_CONFIG_VC,
409 FEAT_DSI_VC_OCP_WIDTH,
410 FEAT_DSI_GNQ,
411 FEAT_HDMI_CTS_SWMODE,
412 FEAT_HANDLE_UV_SEPARATE,
413 FEAT_ATTR2,
414 FEAT_CPR,
415 FEAT_PRELOAD,
416 FEAT_FIR_COEF_V,
417 FEAT_ALPHA_FREE_ZORDER,
418 FEAT_FIFO_MERGE,
419 };
420
421 static const enum dss_feat_id omap4_dss_feat_list[] = {
422 FEAT_MGR_LCD2,
423 FEAT_CORE_CLK_DIV,
424 FEAT_LCD_CLK_SRC,
425 FEAT_DSI_DCS_CMD_CONFIG_VC,
426 FEAT_DSI_VC_OCP_WIDTH,
427 FEAT_DSI_GNQ,
428 FEAT_HDMI_CTS_SWMODE,
429 FEAT_HDMI_AUDIO_USE_MCLK,
430 FEAT_HANDLE_UV_SEPARATE,
431 FEAT_ATTR2,
432 FEAT_CPR,
433 FEAT_PRELOAD,
434 FEAT_FIR_COEF_V,
435 FEAT_ALPHA_FREE_ZORDER,
436 FEAT_FIFO_MERGE,
437 };
438
439 /* OMAP2 DSS Features */
440 static const struct omap_dss_features omap2_dss_features = {
441 .reg_fields = omap2_dss_reg_fields,
442 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
443
444 .features = omap2_dss_feat_list,
445 .num_features = ARRAY_SIZE(omap2_dss_feat_list),
446
447 .num_mgrs = 2,
448 .num_ovls = 3,
449 .supported_displays = omap2_dss_supported_displays,
450 .supported_color_modes = omap2_dss_supported_color_modes,
451 .overlay_caps = omap2_dss_overlay_caps,
452 .clksrc_names = omap2_dss_clk_source_names,
453 .dss_params = omap2_dss_param_range,
454 .buffer_size_unit = 1,
455 .burst_size_unit = 8,
456 };
457
458 /* OMAP3 DSS Features */
459 static const struct omap_dss_features omap3430_dss_features = {
460 .reg_fields = omap3_dss_reg_fields,
461 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
462
463 .features = omap3430_dss_feat_list,
464 .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
465
466 .num_mgrs = 2,
467 .num_ovls = 3,
468 .supported_displays = omap3430_dss_supported_displays,
469 .supported_color_modes = omap3_dss_supported_color_modes,
470 .overlay_caps = omap3430_dss_overlay_caps,
471 .clksrc_names = omap3_dss_clk_source_names,
472 .dss_params = omap3_dss_param_range,
473 .buffer_size_unit = 1,
474 .burst_size_unit = 8,
475 };
476
477 static const struct omap_dss_features omap3630_dss_features = {
478 .reg_fields = omap3_dss_reg_fields,
479 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
480
481 .features = omap3630_dss_feat_list,
482 .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
483
484 .num_mgrs = 2,
485 .num_ovls = 3,
486 .supported_displays = omap3630_dss_supported_displays,
487 .supported_color_modes = omap3_dss_supported_color_modes,
488 .overlay_caps = omap3630_dss_overlay_caps,
489 .clksrc_names = omap3_dss_clk_source_names,
490 .dss_params = omap3_dss_param_range,
491 .buffer_size_unit = 1,
492 .burst_size_unit = 8,
493 };
494
495 /* OMAP4 DSS Features */
496 /* For OMAP4430 ES 1.0 revision */
497 static const struct omap_dss_features omap4430_es1_0_dss_features = {
498 .reg_fields = omap4_dss_reg_fields,
499 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
500
501 .features = omap4430_es1_0_dss_feat_list,
502 .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
503
504 .num_mgrs = 3,
505 .num_ovls = 4,
506 .supported_displays = omap4_dss_supported_displays,
507 .supported_color_modes = omap4_dss_supported_color_modes,
508 .overlay_caps = omap4_dss_overlay_caps,
509 .clksrc_names = omap4_dss_clk_source_names,
510 .dss_params = omap4_dss_param_range,
511 .buffer_size_unit = 16,
512 .burst_size_unit = 16,
513 };
514
515 /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
516 static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
517 .reg_fields = omap4_dss_reg_fields,
518 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
519
520 .features = omap4430_es2_0_1_2_dss_feat_list,
521 .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
522
523 .num_mgrs = 3,
524 .num_ovls = 4,
525 .supported_displays = omap4_dss_supported_displays,
526 .supported_color_modes = omap4_dss_supported_color_modes,
527 .overlay_caps = omap4_dss_overlay_caps,
528 .clksrc_names = omap4_dss_clk_source_names,
529 .dss_params = omap4_dss_param_range,
530 .buffer_size_unit = 16,
531 .burst_size_unit = 16,
532 };
533
534 /* For all the other OMAP4 versions */
535 static const struct omap_dss_features omap4_dss_features = {
536 .reg_fields = omap4_dss_reg_fields,
537 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
538
539 .features = omap4_dss_feat_list,
540 .num_features = ARRAY_SIZE(omap4_dss_feat_list),
541
542 .num_mgrs = 3,
543 .num_ovls = 4,
544 .supported_displays = omap4_dss_supported_displays,
545 .supported_color_modes = omap4_dss_supported_color_modes,
546 .overlay_caps = omap4_dss_overlay_caps,
547 .clksrc_names = omap4_dss_clk_source_names,
548 .dss_params = omap4_dss_param_range,
549 .buffer_size_unit = 16,
550 .burst_size_unit = 16,
551 };
552
553 #if defined(CONFIG_OMAP4_DSS_HDMI)
554 /* HDMI OMAP4 Functions*/
555 static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
556
557 .video_configure = ti_hdmi_4xxx_basic_configure,
558 .phy_enable = ti_hdmi_4xxx_phy_enable,
559 .phy_disable = ti_hdmi_4xxx_phy_disable,
560 .read_edid = ti_hdmi_4xxx_read_edid,
561 .detect = ti_hdmi_4xxx_detect,
562 .pll_enable = ti_hdmi_4xxx_pll_enable,
563 .pll_disable = ti_hdmi_4xxx_pll_disable,
564 .video_enable = ti_hdmi_4xxx_wp_video_start,
565 .dump_wrapper = ti_hdmi_4xxx_wp_dump,
566 .dump_core = ti_hdmi_4xxx_core_dump,
567 .dump_pll = ti_hdmi_4xxx_pll_dump,
568 .dump_phy = ti_hdmi_4xxx_phy_dump,
569 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
570 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
571 .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
572 #endif
573
574 };
575
dss_init_hdmi_ip_ops(struct hdmi_ip_data * ip_data)576 void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
577 {
578 if (cpu_is_omap44xx())
579 ip_data->ops = &omap4_hdmi_functions;
580 }
581 #endif
582
583 /* Functions returning values related to a DSS feature */
dss_feat_get_num_mgrs(void)584 int dss_feat_get_num_mgrs(void)
585 {
586 return omap_current_dss_features->num_mgrs;
587 }
588
dss_feat_get_num_ovls(void)589 int dss_feat_get_num_ovls(void)
590 {
591 return omap_current_dss_features->num_ovls;
592 }
593
dss_feat_get_param_min(enum dss_range_param param)594 unsigned long dss_feat_get_param_min(enum dss_range_param param)
595 {
596 return omap_current_dss_features->dss_params[param].min;
597 }
598
dss_feat_get_param_max(enum dss_range_param param)599 unsigned long dss_feat_get_param_max(enum dss_range_param param)
600 {
601 return omap_current_dss_features->dss_params[param].max;
602 }
603
dss_feat_get_supported_displays(enum omap_channel channel)604 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
605 {
606 return omap_current_dss_features->supported_displays[channel];
607 }
608
dss_feat_get_supported_color_modes(enum omap_plane plane)609 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
610 {
611 return omap_current_dss_features->supported_color_modes[plane];
612 }
613
dss_feat_get_overlay_caps(enum omap_plane plane)614 enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
615 {
616 return omap_current_dss_features->overlay_caps[plane];
617 }
618
dss_feat_color_mode_supported(enum omap_plane plane,enum omap_color_mode color_mode)619 bool dss_feat_color_mode_supported(enum omap_plane plane,
620 enum omap_color_mode color_mode)
621 {
622 return omap_current_dss_features->supported_color_modes[plane] &
623 color_mode;
624 }
625
dss_feat_get_clk_source_name(enum omap_dss_clk_source id)626 const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
627 {
628 return omap_current_dss_features->clksrc_names[id];
629 }
630
dss_feat_get_buffer_size_unit(void)631 u32 dss_feat_get_buffer_size_unit(void)
632 {
633 return omap_current_dss_features->buffer_size_unit;
634 }
635
dss_feat_get_burst_size_unit(void)636 u32 dss_feat_get_burst_size_unit(void)
637 {
638 return omap_current_dss_features->burst_size_unit;
639 }
640
641 /* DSS has_feature check */
dss_has_feature(enum dss_feat_id id)642 bool dss_has_feature(enum dss_feat_id id)
643 {
644 int i;
645 const enum dss_feat_id *features = omap_current_dss_features->features;
646 const int num_features = omap_current_dss_features->num_features;
647
648 for (i = 0; i < num_features; i++) {
649 if (features[i] == id)
650 return true;
651 }
652
653 return false;
654 }
655
dss_feat_get_reg_field(enum dss_feat_reg_field id,u8 * start,u8 * end)656 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
657 {
658 if (id >= omap_current_dss_features->num_reg_fields)
659 BUG();
660
661 *start = omap_current_dss_features->reg_fields[id].start;
662 *end = omap_current_dss_features->reg_fields[id].end;
663 }
664
dss_features_init(void)665 void dss_features_init(void)
666 {
667 if (cpu_is_omap24xx())
668 omap_current_dss_features = &omap2_dss_features;
669 else if (cpu_is_omap3630())
670 omap_current_dss_features = &omap3630_dss_features;
671 else if (cpu_is_omap34xx())
672 omap_current_dss_features = &omap3430_dss_features;
673 else if (omap_rev() == OMAP4430_REV_ES1_0)
674 omap_current_dss_features = &omap4430_es1_0_dss_features;
675 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
676 omap_rev() == OMAP4430_REV_ES2_1 ||
677 omap_rev() == OMAP4430_REV_ES2_2)
678 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
679 else if (cpu_is_omap44xx())
680 omap_current_dss_features = &omap4_dss_features;
681 else
682 DSSWARN("Unsupported OMAP version");
683 }
684