1 /*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #ifndef __OMAP2_DSS_H
24 #define __OMAP2_DSS_H
25
26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
27 #define DEBUG
28 #endif
29
30 #ifdef DEBUG
31 extern unsigned int dss_debug;
32 #ifdef DSS_SUBSYS_NAME
33 #define DSSDBG(format, ...) \
34 if (dss_debug) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
36 ## __VA_ARGS__)
37 #else
38 #define DSSDBG(format, ...) \
39 if (dss_debug) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
41 #endif
42
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSDBGF(format, ...) \
45 if (dss_debug) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
48 __func__, \
49 ## __VA_ARGS__)
50 #else
51 #define DSSDBGF(format, ...) \
52 if (dss_debug) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
55 __func__, \
56 ## __VA_ARGS__)
57 #endif
58
59 #else /* DEBUG */
60 #define DSSDBG(format, ...)
61 #define DSSDBGF(format, ...)
62 #endif
63
64
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
68 ## __VA_ARGS__)
69 #else
70 #define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
72 #endif
73
74 #ifdef DSS_SUBSYS_NAME
75 #define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
77 ## __VA_ARGS__)
78 #else
79 #define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
81 #endif
82
83 #ifdef DSS_SUBSYS_NAME
84 #define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
86 ## __VA_ARGS__)
87 #else
88 #define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
90 #endif
91
92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97 #define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
99
100 enum omap_burst_size {
101 OMAP_DSS_BURST_4x32 = 0,
102 OMAP_DSS_BURST_8x32 = 1,
103 OMAP_DSS_BURST_16x32 = 2,
104 };
105
106 enum omap_parallel_interface_mode {
107 OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */
108 OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */
109 OMAP_DSS_PARALLELMODE_DSI,
110 };
111
112 enum dss_clock {
113 DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */
114 DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */
115 DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */
116 DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */
117 DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/
118 };
119
120 enum dss_clk_source {
121 DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
122 * OMAP4: PLL1_CLK1 */
123 DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
124 * OMAP4: PLL1_CLK2 */
125 DSS_CLK_SRC_FCK, /* OMAP2/3: DSS1_ALWON_FCLK
126 * OMAP4: DSS_FCLK */
127 };
128
129 enum dss_hdmi_venc_clk_source_select {
130 DSS_VENC_TV_CLK = 0,
131 DSS_HDMI_M_PCLK = 1,
132 };
133
134 struct dss_clock_info {
135 /* rates that we get with dividers below */
136 unsigned long fck;
137
138 /* dividers */
139 u16 fck_div;
140 };
141
142 struct dispc_clock_info {
143 /* rates that we get with dividers below */
144 unsigned long lck;
145 unsigned long pck;
146
147 /* dividers */
148 u16 lck_div;
149 u16 pck_div;
150 };
151
152 struct dsi_clock_info {
153 /* rates that we get with dividers below */
154 unsigned long fint;
155 unsigned long clkin4ddr;
156 unsigned long clkin;
157 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
158 * OMAP4: PLLx_CLK1 */
159 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
160 * OMAP4: PLLx_CLK2 */
161 unsigned long lp_clk;
162
163 /* dividers */
164 u16 regn;
165 u16 regm;
166 u16 regm_dispc; /* OMAP3: REGM3
167 * OMAP4: REGM4 */
168 u16 regm_dsi; /* OMAP3: REGM4
169 * OMAP4: REGM5 */
170 u16 lp_clk_div;
171
172 u8 highfreq;
173 bool use_sys_clk;
174 };
175
176 /* HDMI PLL structure */
177 struct hdmi_pll_info {
178 u16 regn;
179 u16 regm;
180 u32 regmf;
181 u16 regm2;
182 u16 regsd;
183 u16 dcofreq;
184 };
185
186 struct seq_file;
187 struct platform_device;
188
189 /* core */
190 struct bus_type *dss_get_bus(void);
191 struct regulator *dss_get_vdds_dsi(void);
192 struct regulator *dss_get_vdds_sdi(void);
193
194 /* display */
195 int dss_suspend_all_devices(void);
196 int dss_resume_all_devices(void);
197 void dss_disable_all_devices(void);
198
199 void dss_init_device(struct platform_device *pdev,
200 struct omap_dss_device *dssdev);
201 void dss_uninit_device(struct platform_device *pdev,
202 struct omap_dss_device *dssdev);
203 bool dss_use_replication(struct omap_dss_device *dssdev,
204 enum omap_color_mode mode);
205 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
206 u32 fifo_size, enum omap_burst_size *burst_size,
207 u32 *fifo_low, u32 *fifo_high);
208
209 /* manager */
210 int dss_init_overlay_managers(struct platform_device *pdev);
211 void dss_uninit_overlay_managers(struct platform_device *pdev);
212 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
213 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
214 u16 *x, u16 *y, u16 *w, u16 *h,
215 bool enlarge_update_area);
216 void dss_start_update(struct omap_dss_device *dssdev);
217
218 /* overlay */
219 void dss_init_overlays(struct platform_device *pdev);
220 void dss_uninit_overlays(struct platform_device *pdev);
221 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
222 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
223 #ifdef L4_EXAMPLE
224 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
225 #endif
226 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
227
228 /* DSS */
229 int dss_init_platform_driver(void);
230 void dss_uninit_platform_driver(void);
231
232 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
233 void dss_save_context(void);
234 void dss_restore_context(void);
235 void dss_clk_enable(enum dss_clock clks);
236 void dss_clk_disable(enum dss_clock clks);
237 unsigned long dss_clk_get_rate(enum dss_clock clk);
238 int dss_need_ctx_restore(void);
239 const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);
240 void dss_dump_clocks(struct seq_file *s);
241
242 void dss_dump_regs(struct seq_file *s);
243 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
244 void dss_debug_dump_clocks(struct seq_file *s);
245 #endif
246
247 void dss_sdi_init(u8 datapairs);
248 int dss_sdi_enable(void);
249 void dss_sdi_disable(void);
250
251 void dss_select_dispc_clk_source(enum dss_clk_source clk_src);
252 void dss_select_dsi_clk_source(enum dss_clk_source clk_src);
253 void dss_select_lcd_clk_source(enum omap_channel channel,
254 enum dss_clk_source clk_src);
255 enum dss_clk_source dss_get_dispc_clk_source(void);
256 enum dss_clk_source dss_get_dsi_clk_source(void);
257 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
258
259 void dss_set_venc_output(enum omap_dss_venc_type type);
260 void dss_set_dac_pwrdn_bgz(bool enable);
261
262 unsigned long dss_get_dpll4_rate(void);
263 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
264 int dss_set_clock_div(struct dss_clock_info *cinfo);
265 int dss_get_clock_div(struct dss_clock_info *cinfo);
266 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
267 struct dss_clock_info *dss_cinfo,
268 struct dispc_clock_info *dispc_cinfo);
269
270 /* SDI */
271 #ifdef CONFIG_OMAP2_DSS_SDI
272 int sdi_init(void);
273 void sdi_exit(void);
274 int sdi_init_display(struct omap_dss_device *display);
275 #else
sdi_init(void)276 static inline int sdi_init(void)
277 {
278 return 0;
279 }
sdi_exit(void)280 static inline void sdi_exit(void)
281 {
282 }
283 #endif
284
285 /* DSI */
286 #ifdef CONFIG_OMAP2_DSS_DSI
287 int dsi_init_platform_driver(void);
288 void dsi_uninit_platform_driver(void);
289
290 void dsi_dump_clocks(struct seq_file *s);
291 void dsi_dump_irqs(struct seq_file *s);
292 void dsi_dump_regs(struct seq_file *s);
293
294 void dsi_save_context(void);
295 void dsi_restore_context(void);
296
297 int dsi_init_display(struct omap_dss_device *display);
298 void dsi_irq_handler(void);
299 unsigned long dsi_get_pll_hsdiv_dispc_rate(void);
300 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
301 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
302 struct dsi_clock_info *cinfo,
303 struct dispc_clock_info *dispc_cinfo);
304 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
305 bool enable_hsdiv);
306 void dsi_pll_uninit(void);
307 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
308 u32 fifo_size, enum omap_burst_size *burst_size,
309 u32 *fifo_low, u32 *fifo_high);
310 void dsi_wait_pll_hsdiv_dispc_active(void);
311 void dsi_wait_pll_hsdiv_dsi_active(void);
312 #else
dsi_init_platform_driver(void)313 static inline int dsi_init_platform_driver(void)
314 {
315 return 0;
316 }
dsi_uninit_platform_driver(void)317 static inline void dsi_uninit_platform_driver(void)
318 {
319 }
dsi_get_pll_hsdiv_dispc_rate(void)320 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
321 {
322 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
323 return 0;
324 }
dsi_wait_pll_hsdiv_dispc_active(void)325 static inline void dsi_wait_pll_hsdiv_dispc_active(void)
326 {
327 }
dsi_wait_pll_hsdiv_dsi_active(void)328 static inline void dsi_wait_pll_hsdiv_dsi_active(void)
329 {
330 }
331 #endif
332
333 /* DPI */
334 #ifdef CONFIG_OMAP2_DSS_DPI
335 int dpi_init(void);
336 void dpi_exit(void);
337 int dpi_init_display(struct omap_dss_device *dssdev);
338 #else
dpi_init(void)339 static inline int dpi_init(void)
340 {
341 return 0;
342 }
dpi_exit(void)343 static inline void dpi_exit(void)
344 {
345 }
346 #endif
347
348 /* DISPC */
349 int dispc_init_platform_driver(void);
350 void dispc_uninit_platform_driver(void);
351 void dispc_dump_clocks(struct seq_file *s);
352 void dispc_dump_irqs(struct seq_file *s);
353 void dispc_dump_regs(struct seq_file *s);
354 void dispc_irq_handler(void);
355 void dispc_fake_vsync_irq(void);
356
357 void dispc_save_context(void);
358 void dispc_restore_context(void);
359
360 void dispc_enable_sidle(void);
361 void dispc_disable_sidle(void);
362
363 void dispc_lcd_enable_signal_polarity(bool act_high);
364 void dispc_lcd_enable_signal(bool enable);
365 void dispc_pck_free_enable(bool enable);
366 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
367
368 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
369 void dispc_set_digit_size(u16 width, u16 height);
370 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
371 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
372 void dispc_enable_fifomerge(bool enable);
373 void dispc_set_burst_size(enum omap_plane plane,
374 enum omap_burst_size burst_size);
375
376 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
377 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
378 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
379 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
380 void dispc_set_channel_out(enum omap_plane plane,
381 enum omap_channel channel_out);
382
383 void dispc_enable_gamma_table(bool enable);
384 int dispc_setup_plane(enum omap_plane plane,
385 u32 paddr, u16 screen_width,
386 u16 pos_x, u16 pos_y,
387 u16 width, u16 height,
388 u16 out_width, u16 out_height,
389 enum omap_color_mode color_mode,
390 bool ilace,
391 enum omap_dss_rotation_type rotation_type,
392 u8 rotation, bool mirror,
393 u8 global_alpha, u8 pre_mult_alpha,
394 enum omap_channel channel);
395
396 bool dispc_go_busy(enum omap_channel channel);
397 void dispc_go(enum omap_channel channel);
398 void dispc_enable_channel(enum omap_channel channel, bool enable);
399 bool dispc_is_channel_enabled(enum omap_channel channel);
400 int dispc_enable_plane(enum omap_plane plane, bool enable);
401 void dispc_enable_replication(enum omap_plane plane, bool enable);
402
403 void dispc_set_parallel_interface_mode(enum omap_channel channel,
404 enum omap_parallel_interface_mode mode);
405 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
406 void dispc_set_lcd_display_type(enum omap_channel channel,
407 enum omap_lcd_display_type type);
408 void dispc_set_loadmode(enum omap_dss_load_mode mode);
409
410 void dispc_set_default_color(enum omap_channel channel, u32 color);
411 u32 dispc_get_default_color(enum omap_channel channel);
412 void dispc_set_trans_key(enum omap_channel ch,
413 enum omap_dss_trans_key_type type,
414 u32 trans_key);
415 void dispc_get_trans_key(enum omap_channel ch,
416 enum omap_dss_trans_key_type *type,
417 u32 *trans_key);
418 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
419 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
420 bool dispc_trans_key_enabled(enum omap_channel ch);
421 bool dispc_alpha_blending_enabled(enum omap_channel ch);
422
423 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
424 void dispc_set_lcd_timings(enum omap_channel channel,
425 struct omap_video_timings *timings);
426 unsigned long dispc_fclk_rate(void);
427 unsigned long dispc_lclk_rate(enum omap_channel channel);
428 unsigned long dispc_pclk_rate(enum omap_channel channel);
429 void dispc_set_pol_freq(enum omap_channel channel,
430 enum omap_panel_config config, u8 acbi, u8 acb);
431 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
432 struct dispc_clock_info *cinfo);
433 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
434 struct dispc_clock_info *cinfo);
435 int dispc_set_clock_div(enum omap_channel channel,
436 struct dispc_clock_info *cinfo);
437 int dispc_get_clock_div(enum omap_channel channel,
438 struct dispc_clock_info *cinfo);
439
440
441 /* VENC */
442 #ifdef CONFIG_OMAP2_DSS_VENC
443 int venc_init_platform_driver(void);
444 void venc_uninit_platform_driver(void);
445 void venc_dump_regs(struct seq_file *s);
446 int venc_init_display(struct omap_dss_device *display);
447 #else
venc_init_platform_driver(void)448 static inline int venc_init_platform_driver(void)
449 {
450 return 0;
451 }
venc_uninit_platform_driver(void)452 static inline void venc_uninit_platform_driver(void)
453 {
454 }
455 #endif
456
457 /* HDMI */
458 #ifdef CONFIG_OMAP4_DSS_HDMI
459 int hdmi_init_platform_driver(void);
460 void hdmi_uninit_platform_driver(void);
461 int hdmi_init_display(struct omap_dss_device *dssdev);
462 #else
hdmi_init_display(struct omap_dss_device * dssdev)463 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
464 {
465 return 0;
466 }
hdmi_init_platform_driver(void)467 static inline int hdmi_init_platform_driver(void)
468 {
469 return 0;
470 }
hdmi_uninit_platform_driver(void)471 static inline void hdmi_uninit_platform_driver(void)
472 {
473 }
474 #endif
475 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
476 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
477 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
478 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
479 struct omap_video_timings *timings);
480 int hdmi_panel_init(void);
481 void hdmi_panel_exit(void);
482
483 /* RFBI */
484 #ifdef CONFIG_OMAP2_DSS_RFBI
485 int rfbi_init_platform_driver(void);
486 void rfbi_uninit_platform_driver(void);
487 void rfbi_dump_regs(struct seq_file *s);
488
489 int rfbi_configure(int rfbi_module, int bpp, int lines);
490 void rfbi_enable_rfbi(bool enable);
491 void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
492 u16 height, void (callback)(void *data), void *data);
493 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
494 unsigned long rfbi_get_max_tx_rate(void);
495 int rfbi_init_display(struct omap_dss_device *display);
496 #else
rfbi_init_platform_driver(void)497 static inline int rfbi_init_platform_driver(void)
498 {
499 return 0;
500 }
rfbi_uninit_platform_driver(void)501 static inline void rfbi_uninit_platform_driver(void)
502 {
503 }
504 #endif
505
506
507 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
dss_collect_irq_stats(u32 irqstatus,unsigned * irq_arr)508 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
509 {
510 int b;
511 for (b = 0; b < 32; ++b) {
512 if (irqstatus & (1 << b))
513 irq_arr[b]++;
514 }
515 }
516 #endif
517
518 #endif
519