1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/err.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_opp.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spinlock.h>
21
22 #include <video/mipi_display.h>
23
24 #include <drm/display/drm_dsc_helper.h>
25 #include <drm/drm_of.h>
26
27 #include "dsi.h"
28 #include "dsi.xml.h"
29 #include "sfpb.xml.h"
30 #include "dsi_cfg.h"
31 #include "msm_kms.h"
32 #include "msm_gem.h"
33 #include "phy/dsi_phy.h"
34
35 #define DSI_RESET_TOGGLE_DELAY_MS 20
36
37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
38
dsi_get_version(const void __iomem * base,u32 * major,u32 * minor)39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
40 {
41 u32 ver;
42
43 if (!major || !minor)
44 return -EINVAL;
45
46 /*
47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
48 * makes all other registers 4-byte shifted down.
49 *
50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
51 * older, we read the DSI_VERSION register without any shift(offset
52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
53 * the case of DSI6G, this has to be zero (the offset points to a
54 * scratch register which we never touch)
55 */
56
57 ver = msm_readl(base + REG_DSI_VERSION);
58 if (ver) {
59 /* older dsi host, there is no register shift */
60 ver = FIELD(ver, DSI_VERSION_MAJOR);
61 if (ver <= MSM_DSI_VER_MAJOR_V2) {
62 /* old versions */
63 *major = ver;
64 *minor = 0;
65 return 0;
66 } else {
67 return -EINVAL;
68 }
69 } else {
70 /*
71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
72 * registers are shifted down, read DSI_VERSION again with
73 * the shifted offset
74 */
75 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
76 ver = FIELD(ver, DSI_VERSION_MAJOR);
77 if (ver == MSM_DSI_VER_MAJOR_6G) {
78 /* 6G version */
79 *major = ver;
80 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
81 return 0;
82 } else {
83 return -EINVAL;
84 }
85 }
86 }
87
88 #define DSI_ERR_STATE_ACK 0x0000
89 #define DSI_ERR_STATE_TIMEOUT 0x0001
90 #define DSI_ERR_STATE_DLN0_PHY 0x0002
91 #define DSI_ERR_STATE_FIFO 0x0004
92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
95
96 #define DSI_CLK_CTRL_ENABLE_CLKS \
97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
101
102 struct msm_dsi_host {
103 struct mipi_dsi_host base;
104
105 struct platform_device *pdev;
106 struct drm_device *dev;
107
108 int id;
109
110 void __iomem *ctrl_base;
111 phys_addr_t ctrl_size;
112 struct regulator_bulk_data *supplies;
113
114 int num_bus_clks;
115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX];
116
117 struct clk *byte_clk;
118 struct clk *esc_clk;
119 struct clk *pixel_clk;
120 struct clk *byte_clk_src;
121 struct clk *pixel_clk_src;
122 struct clk *byte_intf_clk;
123
124 unsigned long byte_clk_rate;
125 unsigned long pixel_clk_rate;
126 unsigned long esc_clk_rate;
127
128 /* DSI v2 specific clocks */
129 struct clk *src_clk;
130 struct clk *esc_clk_src;
131 struct clk *dsi_clk_src;
132
133 unsigned long src_clk_rate;
134
135 struct gpio_desc *disp_en_gpio;
136 struct gpio_desc *te_gpio;
137
138 const struct msm_dsi_cfg_handler *cfg_hnd;
139
140 struct completion dma_comp;
141 struct completion video_comp;
142 struct mutex dev_mutex;
143 struct mutex cmd_mutex;
144 spinlock_t intr_lock; /* Protect interrupt ctrl register */
145
146 u32 err_work_state;
147 struct work_struct err_work;
148 struct workqueue_struct *workqueue;
149
150 /* DSI 6G TX buffer*/
151 struct drm_gem_object *tx_gem_obj;
152
153 /* DSI v2 TX buffer */
154 void *tx_buf;
155 dma_addr_t tx_buf_paddr;
156
157 int tx_size;
158
159 u8 *rx_buf;
160
161 struct regmap *sfpb;
162
163 struct drm_display_mode *mode;
164 struct drm_dsc_config *dsc;
165
166 /* connected device info */
167 unsigned int channel;
168 unsigned int lanes;
169 enum mipi_dsi_pixel_format format;
170 unsigned long mode_flags;
171
172 /* lane data parsed via DT */
173 int dlane_swap;
174 int num_data_lanes;
175
176 /* from phy DT */
177 bool cphy_mode;
178
179 u32 dma_cmd_ctrl_restore;
180
181 bool registered;
182 bool power_on;
183 bool enabled;
184 int irq;
185 };
186
dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)187 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
188 {
189 switch (fmt) {
190 case MIPI_DSI_FMT_RGB565: return 16;
191 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
192 case MIPI_DSI_FMT_RGB666:
193 case MIPI_DSI_FMT_RGB888:
194 default: return 24;
195 }
196 }
197
dsi_read(struct msm_dsi_host * msm_host,u32 reg)198 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
199 {
200 return msm_readl(msm_host->ctrl_base + reg);
201 }
dsi_write(struct msm_dsi_host * msm_host,u32 reg,u32 data)202 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
203 {
204 msm_writel(data, msm_host->ctrl_base + reg);
205 }
206
dsi_get_config(struct msm_dsi_host * msm_host)207 static const struct msm_dsi_cfg_handler *dsi_get_config(
208 struct msm_dsi_host *msm_host)
209 {
210 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
211 struct device *dev = &msm_host->pdev->dev;
212 struct clk *ahb_clk;
213 int ret;
214 u32 major = 0, minor = 0;
215
216 cfg_hnd = device_get_match_data(dev);
217 if (cfg_hnd)
218 return cfg_hnd;
219
220 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
221 if (IS_ERR(ahb_clk)) {
222 pr_err("%s: cannot get interface clock\n", __func__);
223 goto exit;
224 }
225
226 pm_runtime_get_sync(dev);
227
228 ret = clk_prepare_enable(ahb_clk);
229 if (ret) {
230 pr_err("%s: unable to enable ahb_clk\n", __func__);
231 goto runtime_put;
232 }
233
234 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
235 if (ret) {
236 pr_err("%s: Invalid version\n", __func__);
237 goto disable_clks;
238 }
239
240 cfg_hnd = msm_dsi_cfg_get(major, minor);
241
242 DBG("%s: Version %x:%x\n", __func__, major, minor);
243
244 disable_clks:
245 clk_disable_unprepare(ahb_clk);
246 runtime_put:
247 pm_runtime_put_sync(dev);
248 exit:
249 return cfg_hnd;
250 }
251
to_msm_dsi_host(struct mipi_dsi_host * host)252 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
253 {
254 return container_of(host, struct msm_dsi_host, base);
255 }
256
dsi_clk_init_v2(struct msm_dsi_host * msm_host)257 int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
258 {
259 struct platform_device *pdev = msm_host->pdev;
260 int ret = 0;
261
262 msm_host->src_clk = msm_clk_get(pdev, "src");
263
264 if (IS_ERR(msm_host->src_clk)) {
265 ret = PTR_ERR(msm_host->src_clk);
266 pr_err("%s: can't find src clock. ret=%d\n",
267 __func__, ret);
268 msm_host->src_clk = NULL;
269 return ret;
270 }
271
272 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
273 if (!msm_host->esc_clk_src) {
274 ret = -ENODEV;
275 pr_err("%s: can't get esc clock parent. ret=%d\n",
276 __func__, ret);
277 return ret;
278 }
279
280 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
281 if (!msm_host->dsi_clk_src) {
282 ret = -ENODEV;
283 pr_err("%s: can't get src clock parent. ret=%d\n",
284 __func__, ret);
285 }
286
287 return ret;
288 }
289
dsi_clk_init_6g_v2(struct msm_dsi_host * msm_host)290 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
291 {
292 struct platform_device *pdev = msm_host->pdev;
293 int ret = 0;
294
295 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
296 if (IS_ERR(msm_host->byte_intf_clk)) {
297 ret = PTR_ERR(msm_host->byte_intf_clk);
298 pr_err("%s: can't find byte_intf clock. ret=%d\n",
299 __func__, ret);
300 }
301
302 return ret;
303 }
304
dsi_clk_init(struct msm_dsi_host * msm_host)305 static int dsi_clk_init(struct msm_dsi_host *msm_host)
306 {
307 struct platform_device *pdev = msm_host->pdev;
308 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
309 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
310 int i, ret = 0;
311
312 /* get bus clocks */
313 for (i = 0; i < cfg->num_bus_clks; i++)
314 msm_host->bus_clks[i].id = cfg->bus_clk_names[i];
315 msm_host->num_bus_clks = cfg->num_bus_clks;
316
317 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks);
318 if (ret < 0) {
319 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret);
320 goto exit;
321 }
322
323 /* get link and source clocks */
324 msm_host->byte_clk = msm_clk_get(pdev, "byte");
325 if (IS_ERR(msm_host->byte_clk)) {
326 ret = PTR_ERR(msm_host->byte_clk);
327 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
328 __func__, ret);
329 msm_host->byte_clk = NULL;
330 goto exit;
331 }
332
333 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
334 if (IS_ERR(msm_host->pixel_clk)) {
335 ret = PTR_ERR(msm_host->pixel_clk);
336 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
337 __func__, ret);
338 msm_host->pixel_clk = NULL;
339 goto exit;
340 }
341
342 msm_host->esc_clk = msm_clk_get(pdev, "core");
343 if (IS_ERR(msm_host->esc_clk)) {
344 ret = PTR_ERR(msm_host->esc_clk);
345 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
346 __func__, ret);
347 msm_host->esc_clk = NULL;
348 goto exit;
349 }
350
351 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
352 if (IS_ERR(msm_host->byte_clk_src)) {
353 ret = PTR_ERR(msm_host->byte_clk_src);
354 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
355 goto exit;
356 }
357
358 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
359 if (IS_ERR(msm_host->pixel_clk_src)) {
360 ret = PTR_ERR(msm_host->pixel_clk_src);
361 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
362 goto exit;
363 }
364
365 if (cfg_hnd->ops->clk_init_ver)
366 ret = cfg_hnd->ops->clk_init_ver(msm_host);
367 exit:
368 return ret;
369 }
370
msm_dsi_runtime_suspend(struct device * dev)371 int msm_dsi_runtime_suspend(struct device *dev)
372 {
373 struct platform_device *pdev = to_platform_device(dev);
374 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
375 struct mipi_dsi_host *host = msm_dsi->host;
376 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
377
378 if (!msm_host->cfg_hnd)
379 return 0;
380
381 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks);
382
383 return 0;
384 }
385
msm_dsi_runtime_resume(struct device * dev)386 int msm_dsi_runtime_resume(struct device *dev)
387 {
388 struct platform_device *pdev = to_platform_device(dev);
389 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
390 struct mipi_dsi_host *host = msm_dsi->host;
391 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
392
393 if (!msm_host->cfg_hnd)
394 return 0;
395
396 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks);
397 }
398
dsi_link_clk_set_rate_6g(struct msm_dsi_host * msm_host)399 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
400 {
401 unsigned long byte_intf_rate;
402 int ret;
403
404 DBG("Set clk rates: pclk=%d, byteclk=%lu",
405 msm_host->mode->clock, msm_host->byte_clk_rate);
406
407 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
408 msm_host->byte_clk_rate);
409 if (ret) {
410 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
411 return ret;
412 }
413
414 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
415 if (ret) {
416 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
417 return ret;
418 }
419
420 if (msm_host->byte_intf_clk) {
421 /* For CPHY, byte_intf_clk is same as byte_clk */
422 if (msm_host->cphy_mode)
423 byte_intf_rate = msm_host->byte_clk_rate;
424 else
425 byte_intf_rate = msm_host->byte_clk_rate / 2;
426
427 ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate);
428 if (ret) {
429 pr_err("%s: Failed to set rate byte intf clk, %d\n",
430 __func__, ret);
431 return ret;
432 }
433 }
434
435 return 0;
436 }
437
438
dsi_link_clk_enable_6g(struct msm_dsi_host * msm_host)439 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
440 {
441 int ret;
442
443 ret = clk_prepare_enable(msm_host->esc_clk);
444 if (ret) {
445 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
446 goto error;
447 }
448
449 ret = clk_prepare_enable(msm_host->byte_clk);
450 if (ret) {
451 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
452 goto byte_clk_err;
453 }
454
455 ret = clk_prepare_enable(msm_host->pixel_clk);
456 if (ret) {
457 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
458 goto pixel_clk_err;
459 }
460
461 ret = clk_prepare_enable(msm_host->byte_intf_clk);
462 if (ret) {
463 pr_err("%s: Failed to enable byte intf clk\n",
464 __func__);
465 goto byte_intf_clk_err;
466 }
467
468 return 0;
469
470 byte_intf_clk_err:
471 clk_disable_unprepare(msm_host->pixel_clk);
472 pixel_clk_err:
473 clk_disable_unprepare(msm_host->byte_clk);
474 byte_clk_err:
475 clk_disable_unprepare(msm_host->esc_clk);
476 error:
477 return ret;
478 }
479
dsi_link_clk_set_rate_v2(struct msm_dsi_host * msm_host)480 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
481 {
482 int ret;
483
484 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
485 msm_host->mode->clock, msm_host->byte_clk_rate,
486 msm_host->esc_clk_rate, msm_host->src_clk_rate);
487
488 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
489 if (ret) {
490 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
491 return ret;
492 }
493
494 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
495 if (ret) {
496 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
497 return ret;
498 }
499
500 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
501 if (ret) {
502 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
503 return ret;
504 }
505
506 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
507 if (ret) {
508 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
509 return ret;
510 }
511
512 return 0;
513 }
514
dsi_link_clk_enable_v2(struct msm_dsi_host * msm_host)515 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
516 {
517 int ret;
518
519 ret = clk_prepare_enable(msm_host->byte_clk);
520 if (ret) {
521 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
522 goto error;
523 }
524
525 ret = clk_prepare_enable(msm_host->esc_clk);
526 if (ret) {
527 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
528 goto esc_clk_err;
529 }
530
531 ret = clk_prepare_enable(msm_host->src_clk);
532 if (ret) {
533 pr_err("%s: Failed to enable dsi src clk\n", __func__);
534 goto src_clk_err;
535 }
536
537 ret = clk_prepare_enable(msm_host->pixel_clk);
538 if (ret) {
539 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
540 goto pixel_clk_err;
541 }
542
543 return 0;
544
545 pixel_clk_err:
546 clk_disable_unprepare(msm_host->src_clk);
547 src_clk_err:
548 clk_disable_unprepare(msm_host->esc_clk);
549 esc_clk_err:
550 clk_disable_unprepare(msm_host->byte_clk);
551 error:
552 return ret;
553 }
554
dsi_link_clk_disable_6g(struct msm_dsi_host * msm_host)555 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
556 {
557 /* Drop the performance state vote */
558 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
559 clk_disable_unprepare(msm_host->esc_clk);
560 clk_disable_unprepare(msm_host->pixel_clk);
561 clk_disable_unprepare(msm_host->byte_intf_clk);
562 clk_disable_unprepare(msm_host->byte_clk);
563 }
564
dsi_link_clk_disable_v2(struct msm_dsi_host * msm_host)565 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
566 {
567 clk_disable_unprepare(msm_host->pixel_clk);
568 clk_disable_unprepare(msm_host->src_clk);
569 clk_disable_unprepare(msm_host->esc_clk);
570 clk_disable_unprepare(msm_host->byte_clk);
571 }
572
dsi_get_pclk_rate(struct msm_dsi_host * msm_host,bool is_bonded_dsi)573 static unsigned long dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
574 {
575 struct drm_display_mode *mode = msm_host->mode;
576 unsigned long pclk_rate;
577
578 pclk_rate = mode->clock * 1000;
579
580 /*
581 * For bonded DSI mode, the current DRM mode has the complete width of the
582 * panel. Since, the complete panel is driven by two DSI controllers,
583 * the clock rates have to be split between the two dsi controllers.
584 * Adjust the byte and pixel clock rates for each dsi host accordingly.
585 */
586 if (is_bonded_dsi)
587 pclk_rate /= 2;
588
589 return pclk_rate;
590 }
591
dsi_calc_pclk(struct msm_dsi_host * msm_host,bool is_bonded_dsi)592 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
593 {
594 u8 lanes = msm_host->lanes;
595 u32 bpp = dsi_get_bpp(msm_host->format);
596 unsigned long pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi);
597 u64 pclk_bpp = (u64)pclk_rate * bpp;
598
599 if (lanes == 0) {
600 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
601 lanes = 1;
602 }
603
604 /* CPHY "byte_clk" is in units of 16 bits */
605 if (msm_host->cphy_mode)
606 do_div(pclk_bpp, (16 * lanes));
607 else
608 do_div(pclk_bpp, (8 * lanes));
609
610 msm_host->pixel_clk_rate = pclk_rate;
611 msm_host->byte_clk_rate = pclk_bpp;
612
613 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate,
614 msm_host->byte_clk_rate);
615
616 }
617
dsi_calc_clk_rate_6g(struct msm_dsi_host * msm_host,bool is_bonded_dsi)618 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
619 {
620 if (!msm_host->mode) {
621 pr_err("%s: mode not set\n", __func__);
622 return -EINVAL;
623 }
624
625 dsi_calc_pclk(msm_host, is_bonded_dsi);
626 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
627 return 0;
628 }
629
dsi_calc_clk_rate_v2(struct msm_dsi_host * msm_host,bool is_bonded_dsi)630 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
631 {
632 u32 bpp = dsi_get_bpp(msm_host->format);
633 u64 pclk_bpp;
634 unsigned int esc_mhz, esc_div;
635 unsigned long byte_mhz;
636
637 dsi_calc_pclk(msm_host, is_bonded_dsi);
638
639 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_bonded_dsi) * bpp;
640 do_div(pclk_bpp, 8);
641 msm_host->src_clk_rate = pclk_bpp;
642
643 /*
644 * esc clock is byte clock followed by a 4 bit divider,
645 * we need to find an escape clock frequency within the
646 * mipi DSI spec range within the maximum divider limit
647 * We iterate here between an escape clock frequencey
648 * between 20 Mhz to 5 Mhz and pick up the first one
649 * that can be supported by our divider
650 */
651
652 byte_mhz = msm_host->byte_clk_rate / 1000000;
653
654 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
655 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
656
657 /*
658 * TODO: Ideally, we shouldn't know what sort of divider
659 * is available in mmss_cc, we're just assuming that
660 * it'll always be a 4 bit divider. Need to come up with
661 * a better way here.
662 */
663 if (esc_div >= 1 && esc_div <= 16)
664 break;
665 }
666
667 if (esc_mhz < 5)
668 return -EINVAL;
669
670 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
671
672 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate,
673 msm_host->src_clk_rate);
674
675 return 0;
676 }
677
dsi_intr_ctrl(struct msm_dsi_host * msm_host,u32 mask,int enable)678 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
679 {
680 u32 intr;
681 unsigned long flags;
682
683 spin_lock_irqsave(&msm_host->intr_lock, flags);
684 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
685
686 if (enable)
687 intr |= mask;
688 else
689 intr &= ~mask;
690
691 DBG("intr=%x enable=%d", intr, enable);
692
693 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
694 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
695 }
696
dsi_get_traffic_mode(const u32 mode_flags)697 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
698 {
699 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
700 return BURST_MODE;
701 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
702 return NON_BURST_SYNCH_PULSE;
703
704 return NON_BURST_SYNCH_EVENT;
705 }
706
dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt)707 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
708 const enum mipi_dsi_pixel_format mipi_fmt)
709 {
710 switch (mipi_fmt) {
711 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
712 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
713 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
714 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
715 default: return VID_DST_FORMAT_RGB888;
716 }
717 }
718
dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt)719 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
720 const enum mipi_dsi_pixel_format mipi_fmt)
721 {
722 switch (mipi_fmt) {
723 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
724 case MIPI_DSI_FMT_RGB666_PACKED:
725 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
726 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
727 default: return CMD_DST_FORMAT_RGB888;
728 }
729 }
730
dsi_ctrl_config(struct msm_dsi_host * msm_host,bool enable,struct msm_dsi_phy_shared_timings * phy_shared_timings,struct msm_dsi_phy * phy)731 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
732 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy)
733 {
734 u32 flags = msm_host->mode_flags;
735 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
736 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
737 u32 data = 0, lane_ctrl = 0;
738
739 if (!enable) {
740 dsi_write(msm_host, REG_DSI_CTRL, 0);
741 return;
742 }
743
744 if (flags & MIPI_DSI_MODE_VIDEO) {
745 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
746 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
747 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
748 data |= DSI_VID_CFG0_HFP_POWER_STOP;
749 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
750 data |= DSI_VID_CFG0_HBP_POWER_STOP;
751 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
752 data |= DSI_VID_CFG0_HSA_POWER_STOP;
753 /* Always set low power stop mode for BLLP
754 * to let command engine send packets
755 */
756 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
757 DSI_VID_CFG0_BLLP_POWER_STOP;
758 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
759 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
760 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
761 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
762
763 /* Do not swap RGB colors */
764 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
765 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
766 } else {
767 /* Do not swap RGB colors */
768 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
769 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
770 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
771
772 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
773 DSI_CMD_CFG1_WR_MEM_CONTINUE(
774 MIPI_DCS_WRITE_MEMORY_CONTINUE);
775 /* Always insert DCS command */
776 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
777 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
778 }
779
780 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
781 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
782 DSI_CMD_DMA_CTRL_LOW_POWER);
783
784 data = 0;
785 /* Always assume dedicated TE pin */
786 data |= DSI_TRIG_CTRL_TE;
787 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
788 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
789 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
790 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
791 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
792 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
793 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
794
795 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
796 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
797 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
798
799 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
800 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
801 phy_shared_timings->clk_pre_inc_by_2)
802 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
803 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
804
805 data = 0;
806 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
807 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
808 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
809
810 /* allow only ack-err-status to generate interrupt */
811 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
812
813 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
814
815 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
816
817 data = DSI_CTRL_CLK_EN;
818
819 DBG("lane number=%d", msm_host->lanes);
820 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
821
822 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
823 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
824
825 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
826 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
827
828 if (msm_dsi_phy_set_continuous_clock(phy, enable))
829 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY;
830
831 dsi_write(msm_host, REG_DSI_LANE_CTRL,
832 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
833 }
834
835 data |= DSI_CTRL_ENABLE;
836
837 dsi_write(msm_host, REG_DSI_CTRL, data);
838
839 if (msm_host->cphy_mode)
840 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
841 }
842
dsi_update_dsc_timing(struct msm_dsi_host * msm_host,bool is_cmd_mode,u32 hdisplay)843 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
844 {
845 struct drm_dsc_config *dsc = msm_host->dsc;
846 u32 reg, reg_ctrl, reg_ctrl2;
847 u32 slice_per_intf, total_bytes_per_intf;
848 u32 pkt_per_line;
849 u32 eol_byte_num;
850
851 /* first calculate dsc parameters and then program
852 * compress mode registers
853 */
854 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
855
856 /* If slice_per_pkt is greater than slice_per_intf
857 * then default to 1. This can happen during partial
858 * update.
859 */
860 if (slice_per_intf > dsc->slice_count)
861 dsc->slice_count = 1;
862
863 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
864
865 eol_byte_num = total_bytes_per_intf % 3;
866 pkt_per_line = slice_per_intf / dsc->slice_count;
867
868 if (is_cmd_mode) /* packet data type */
869 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
870 else
871 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM);
872
873 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
874 * registers have similar offsets, so for below common code use
875 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits
876 */
877 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
878 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
879 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN;
880
881 if (is_cmd_mode) {
882 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
883 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
884
885 reg_ctrl &= ~0xffff;
886 reg_ctrl |= reg;
887
888 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
889 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);
890
891 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
892 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
893 } else {
894 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
895 }
896 }
897
dsi_timing_setup(struct msm_dsi_host * msm_host,bool is_bonded_dsi)898 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
899 {
900 struct drm_display_mode *mode = msm_host->mode;
901 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
902 u32 h_total = mode->htotal;
903 u32 v_total = mode->vtotal;
904 u32 hs_end = mode->hsync_end - mode->hsync_start;
905 u32 vs_end = mode->vsync_end - mode->vsync_start;
906 u32 ha_start = h_total - mode->hsync_start;
907 u32 ha_end = ha_start + mode->hdisplay;
908 u32 va_start = v_total - mode->vsync_start;
909 u32 va_end = va_start + mode->vdisplay;
910 u32 hdisplay = mode->hdisplay;
911 u32 wc;
912 int ret;
913
914 DBG("");
915
916 /*
917 * For bonded DSI mode, the current DRM mode has
918 * the complete width of the panel. Since, the complete
919 * panel is driven by two DSI controllers, the horizontal
920 * timings have to be split between the two dsi controllers.
921 * Adjust the DSI host timing values accordingly.
922 */
923 if (is_bonded_dsi) {
924 h_total /= 2;
925 hs_end /= 2;
926 ha_start /= 2;
927 ha_end /= 2;
928 hdisplay /= 2;
929 }
930
931 if (msm_host->dsc) {
932 struct drm_dsc_config *dsc = msm_host->dsc;
933
934 /* update dsc params with timing params */
935 if (!dsc || !mode->hdisplay || !mode->vdisplay) {
936 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n",
937 mode->hdisplay, mode->vdisplay);
938 return;
939 }
940
941 dsc->pic_width = mode->hdisplay;
942 dsc->pic_height = mode->vdisplay;
943 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
944
945 /* we do the calculations for dsc parameters here so that
946 * panel can use these parameters
947 */
948 ret = dsi_populate_dsc_params(msm_host, dsc);
949 if (ret)
950 return;
951
952 /* Divide the display by 3 but keep back/font porch and
953 * pulse width same
954 */
955 h_total -= hdisplay;
956 hdisplay /= 3;
957 h_total += hdisplay;
958 ha_end = ha_start + hdisplay;
959 }
960
961 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
962 if (msm_host->dsc)
963 dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
964
965 dsi_write(msm_host, REG_DSI_ACTIVE_H,
966 DSI_ACTIVE_H_START(ha_start) |
967 DSI_ACTIVE_H_END(ha_end));
968 dsi_write(msm_host, REG_DSI_ACTIVE_V,
969 DSI_ACTIVE_V_START(va_start) |
970 DSI_ACTIVE_V_END(va_end));
971 dsi_write(msm_host, REG_DSI_TOTAL,
972 DSI_TOTAL_H_TOTAL(h_total - 1) |
973 DSI_TOTAL_V_TOTAL(v_total - 1));
974
975 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
976 DSI_ACTIVE_HSYNC_START(hs_start) |
977 DSI_ACTIVE_HSYNC_END(hs_end));
978 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
979 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
980 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
981 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
982 } else { /* command mode */
983 if (msm_host->dsc)
984 dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
985
986 /* image data and 1 byte write_memory_start cmd */
987 if (!msm_host->dsc)
988 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
989 else
990 wc = mode->hdisplay / 2 + 1;
991
992 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
993 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
994 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
995 msm_host->channel) |
996 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
997 MIPI_DSI_DCS_LONG_WRITE));
998
999 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
1000 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
1001 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
1002 }
1003 }
1004
dsi_sw_reset(struct msm_dsi_host * msm_host)1005 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
1006 {
1007 u32 ctrl;
1008
1009 ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1010
1011 if (ctrl & DSI_CTRL_ENABLE) {
1012 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);
1013 /*
1014 * dsi controller need to be disabled before
1015 * clocks turned on
1016 */
1017 wmb();
1018 }
1019
1020 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1021 wmb(); /* clocks need to be enabled before reset */
1022
1023 /* dsi controller can only be reset while clocks are running */
1024 dsi_write(msm_host, REG_DSI_RESET, 1);
1025 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1026 dsi_write(msm_host, REG_DSI_RESET, 0);
1027 wmb(); /* controller out of reset */
1028
1029 if (ctrl & DSI_CTRL_ENABLE) {
1030 dsi_write(msm_host, REG_DSI_CTRL, ctrl);
1031 wmb(); /* make sure dsi controller enabled again */
1032 }
1033 }
1034
dsi_op_mode_config(struct msm_dsi_host * msm_host,bool video_mode,bool enable)1035 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1036 bool video_mode, bool enable)
1037 {
1038 u32 dsi_ctrl;
1039
1040 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1041
1042 if (!enable) {
1043 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1044 DSI_CTRL_CMD_MODE_EN);
1045 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1046 DSI_IRQ_MASK_VIDEO_DONE, 0);
1047 } else {
1048 if (video_mode) {
1049 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1050 } else { /* command mode */
1051 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1052 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1053 }
1054 dsi_ctrl |= DSI_CTRL_ENABLE;
1055 }
1056
1057 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1058 }
1059
dsi_set_tx_power_mode(int mode,struct msm_dsi_host * msm_host)1060 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1061 {
1062 u32 data;
1063
1064 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1065
1066 if (mode == 0)
1067 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1068 else
1069 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1070
1071 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1072 }
1073
dsi_wait4video_done(struct msm_dsi_host * msm_host)1074 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1075 {
1076 u32 ret = 0;
1077 struct device *dev = &msm_host->pdev->dev;
1078
1079 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1080
1081 reinit_completion(&msm_host->video_comp);
1082
1083 ret = wait_for_completion_timeout(&msm_host->video_comp,
1084 msecs_to_jiffies(70));
1085
1086 if (ret == 0)
1087 DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1088
1089 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1090 }
1091
dsi_wait4video_eng_busy(struct msm_dsi_host * msm_host)1092 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1093 {
1094 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1095 return;
1096
1097 if (msm_host->power_on && msm_host->enabled) {
1098 dsi_wait4video_done(msm_host);
1099 /* delay 4 ms to skip BLLP */
1100 usleep_range(2000, 4000);
1101 }
1102 }
1103
dsi_tx_buf_alloc_6g(struct msm_dsi_host * msm_host,int size)1104 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1105 {
1106 struct drm_device *dev = msm_host->dev;
1107 struct msm_drm_private *priv = dev->dev_private;
1108 uint64_t iova;
1109 u8 *data;
1110
1111 data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1112 priv->kms->aspace,
1113 &msm_host->tx_gem_obj, &iova);
1114
1115 if (IS_ERR(data)) {
1116 msm_host->tx_gem_obj = NULL;
1117 return PTR_ERR(data);
1118 }
1119
1120 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1121
1122 msm_host->tx_size = msm_host->tx_gem_obj->size;
1123
1124 return 0;
1125 }
1126
dsi_tx_buf_alloc_v2(struct msm_dsi_host * msm_host,int size)1127 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1128 {
1129 struct drm_device *dev = msm_host->dev;
1130
1131 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1132 &msm_host->tx_buf_paddr, GFP_KERNEL);
1133 if (!msm_host->tx_buf)
1134 return -ENOMEM;
1135
1136 msm_host->tx_size = size;
1137
1138 return 0;
1139 }
1140
dsi_tx_buf_free(struct msm_dsi_host * msm_host)1141 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1142 {
1143 struct drm_device *dev = msm_host->dev;
1144 struct msm_drm_private *priv;
1145
1146 /*
1147 * This is possible if we're tearing down before we've had a chance to
1148 * fully initialize. A very real possibility if our probe is deferred,
1149 * in which case we'll hit msm_dsi_host_destroy() without having run
1150 * through the dsi_tx_buf_alloc().
1151 */
1152 if (!dev)
1153 return;
1154
1155 priv = dev->dev_private;
1156 if (msm_host->tx_gem_obj) {
1157 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1158 drm_gem_object_put(msm_host->tx_gem_obj);
1159 msm_host->tx_gem_obj = NULL;
1160 }
1161
1162 if (msm_host->tx_buf)
1163 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1164 msm_host->tx_buf_paddr);
1165 }
1166
dsi_tx_buf_get_6g(struct msm_dsi_host * msm_host)1167 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1168 {
1169 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1170 }
1171
dsi_tx_buf_get_v2(struct msm_dsi_host * msm_host)1172 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1173 {
1174 return msm_host->tx_buf;
1175 }
1176
dsi_tx_buf_put_6g(struct msm_dsi_host * msm_host)1177 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1178 {
1179 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1180 }
1181
1182 /*
1183 * prepare cmd buffer to be txed
1184 */
dsi_cmd_dma_add(struct msm_dsi_host * msm_host,const struct mipi_dsi_msg * msg)1185 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1186 const struct mipi_dsi_msg *msg)
1187 {
1188 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1189 struct mipi_dsi_packet packet;
1190 int len;
1191 int ret;
1192 u8 *data;
1193
1194 ret = mipi_dsi_create_packet(&packet, msg);
1195 if (ret) {
1196 pr_err("%s: create packet failed, %d\n", __func__, ret);
1197 return ret;
1198 }
1199 len = (packet.size + 3) & (~0x3);
1200
1201 if (len > msm_host->tx_size) {
1202 pr_err("%s: packet size is too big\n", __func__);
1203 return -EINVAL;
1204 }
1205
1206 data = cfg_hnd->ops->tx_buf_get(msm_host);
1207 if (IS_ERR(data)) {
1208 ret = PTR_ERR(data);
1209 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1210 return ret;
1211 }
1212
1213 /* MSM specific command format in memory */
1214 data[0] = packet.header[1];
1215 data[1] = packet.header[2];
1216 data[2] = packet.header[0];
1217 data[3] = BIT(7); /* Last packet */
1218 if (mipi_dsi_packet_format_is_long(msg->type))
1219 data[3] |= BIT(6);
1220 if (msg->rx_buf && msg->rx_len)
1221 data[3] |= BIT(5);
1222
1223 /* Long packet */
1224 if (packet.payload && packet.payload_length)
1225 memcpy(data + 4, packet.payload, packet.payload_length);
1226
1227 /* Append 0xff to the end */
1228 if (packet.size < len)
1229 memset(data + packet.size, 0xff, len - packet.size);
1230
1231 if (cfg_hnd->ops->tx_buf_put)
1232 cfg_hnd->ops->tx_buf_put(msm_host);
1233
1234 return len;
1235 }
1236
1237 /*
1238 * dsi_short_read1_resp: 1 parameter
1239 */
dsi_short_read1_resp(u8 * buf,const struct mipi_dsi_msg * msg)1240 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1241 {
1242 u8 *data = msg->rx_buf;
1243 if (data && (msg->rx_len >= 1)) {
1244 *data = buf[1]; /* strip out dcs type */
1245 return 1;
1246 } else {
1247 pr_err("%s: read data does not match with rx_buf len %zu\n",
1248 __func__, msg->rx_len);
1249 return -EINVAL;
1250 }
1251 }
1252
1253 /*
1254 * dsi_short_read2_resp: 2 parameter
1255 */
dsi_short_read2_resp(u8 * buf,const struct mipi_dsi_msg * msg)1256 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1257 {
1258 u8 *data = msg->rx_buf;
1259 if (data && (msg->rx_len >= 2)) {
1260 data[0] = buf[1]; /* strip out dcs type */
1261 data[1] = buf[2];
1262 return 2;
1263 } else {
1264 pr_err("%s: read data does not match with rx_buf len %zu\n",
1265 __func__, msg->rx_len);
1266 return -EINVAL;
1267 }
1268 }
1269
dsi_long_read_resp(u8 * buf,const struct mipi_dsi_msg * msg)1270 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1271 {
1272 /* strip out 4 byte dcs header */
1273 if (msg->rx_buf && msg->rx_len)
1274 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1275
1276 return msg->rx_len;
1277 }
1278
dsi_dma_base_get_6g(struct msm_dsi_host * msm_host,uint64_t * dma_base)1279 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1280 {
1281 struct drm_device *dev = msm_host->dev;
1282 struct msm_drm_private *priv = dev->dev_private;
1283
1284 if (!dma_base)
1285 return -EINVAL;
1286
1287 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1288 priv->kms->aspace, dma_base);
1289 }
1290
dsi_dma_base_get_v2(struct msm_dsi_host * msm_host,uint64_t * dma_base)1291 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1292 {
1293 if (!dma_base)
1294 return -EINVAL;
1295
1296 *dma_base = msm_host->tx_buf_paddr;
1297 return 0;
1298 }
1299
dsi_cmd_dma_tx(struct msm_dsi_host * msm_host,int len)1300 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1301 {
1302 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1303 int ret;
1304 uint64_t dma_base;
1305 bool triggered;
1306
1307 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1308 if (ret) {
1309 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1310 return ret;
1311 }
1312
1313 reinit_completion(&msm_host->dma_comp);
1314
1315 dsi_wait4video_eng_busy(msm_host);
1316
1317 triggered = msm_dsi_manager_cmd_xfer_trigger(
1318 msm_host->id, dma_base, len);
1319 if (triggered) {
1320 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1321 msecs_to_jiffies(200));
1322 DBG("ret=%d", ret);
1323 if (ret == 0)
1324 ret = -ETIMEDOUT;
1325 else
1326 ret = len;
1327 } else
1328 ret = len;
1329
1330 return ret;
1331 }
1332
dsi_cmd_dma_rx(struct msm_dsi_host * msm_host,u8 * buf,int rx_byte,int pkt_size)1333 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1334 u8 *buf, int rx_byte, int pkt_size)
1335 {
1336 u32 *temp, data;
1337 int i, j = 0, cnt;
1338 u32 read_cnt;
1339 u8 reg[16];
1340 int repeated_bytes = 0;
1341 int buf_offset = buf - msm_host->rx_buf;
1342
1343 temp = (u32 *)reg;
1344 cnt = (rx_byte + 3) >> 2;
1345 if (cnt > 4)
1346 cnt = 4; /* 4 x 32 bits registers only */
1347
1348 if (rx_byte == 4)
1349 read_cnt = 4;
1350 else
1351 read_cnt = pkt_size + 6;
1352
1353 /*
1354 * In case of multiple reads from the panel, after the first read, there
1355 * is possibility that there are some bytes in the payload repeating in
1356 * the RDBK_DATA registers. Since we read all the parameters from the
1357 * panel right from the first byte for every pass. We need to skip the
1358 * repeating bytes and then append the new parameters to the rx buffer.
1359 */
1360 if (read_cnt > 16) {
1361 int bytes_shifted;
1362 /* Any data more than 16 bytes will be shifted out.
1363 * The temp read buffer should already contain these bytes.
1364 * The remaining bytes in read buffer are the repeated bytes.
1365 */
1366 bytes_shifted = read_cnt - 16;
1367 repeated_bytes = buf_offset - bytes_shifted;
1368 }
1369
1370 for (i = cnt - 1; i >= 0; i--) {
1371 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1372 *temp++ = ntohl(data); /* to host byte order */
1373 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1374 }
1375
1376 for (i = repeated_bytes; i < 16; i++)
1377 buf[j++] = reg[i];
1378
1379 return j;
1380 }
1381
dsi_cmds2buf_tx(struct msm_dsi_host * msm_host,const struct mipi_dsi_msg * msg)1382 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1383 const struct mipi_dsi_msg *msg)
1384 {
1385 int len, ret;
1386 int bllp_len = msm_host->mode->hdisplay *
1387 dsi_get_bpp(msm_host->format) / 8;
1388
1389 len = dsi_cmd_dma_add(msm_host, msg);
1390 if (len < 0) {
1391 pr_err("%s: failed to add cmd type = 0x%x\n",
1392 __func__, msg->type);
1393 return len;
1394 }
1395
1396 /* for video mode, do not send cmds more than
1397 * one pixel line, since it only transmit it
1398 * during BLLP.
1399 */
1400 /* TODO: if the command is sent in LP mode, the bit rate is only
1401 * half of esc clk rate. In this case, if the video is already
1402 * actively streaming, we need to check more carefully if the
1403 * command can be fit into one BLLP.
1404 */
1405 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1406 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1407 __func__, len);
1408 return -EINVAL;
1409 }
1410
1411 ret = dsi_cmd_dma_tx(msm_host, len);
1412 if (ret < 0) {
1413 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
1414 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
1415 return ret;
1416 } else if (ret < len) {
1417 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
1418 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
1419 return -EIO;
1420 }
1421
1422 return len;
1423 }
1424
dsi_err_worker(struct work_struct * work)1425 static void dsi_err_worker(struct work_struct *work)
1426 {
1427 struct msm_dsi_host *msm_host =
1428 container_of(work, struct msm_dsi_host, err_work);
1429 u32 status = msm_host->err_work_state;
1430
1431 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1432 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1433 dsi_sw_reset(msm_host);
1434
1435 /* It is safe to clear here because error irq is disabled. */
1436 msm_host->err_work_state = 0;
1437
1438 /* enable dsi error interrupt */
1439 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1440 }
1441
dsi_ack_err_status(struct msm_dsi_host * msm_host)1442 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1443 {
1444 u32 status;
1445
1446 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1447
1448 if (status) {
1449 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1450 /* Writing of an extra 0 needed to clear error bits */
1451 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1452 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1453 }
1454 }
1455
dsi_timeout_status(struct msm_dsi_host * msm_host)1456 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1457 {
1458 u32 status;
1459
1460 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1461
1462 if (status) {
1463 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1464 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1465 }
1466 }
1467
dsi_dln0_phy_err(struct msm_dsi_host * msm_host)1468 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1469 {
1470 u32 status;
1471
1472 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1473
1474 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1475 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1476 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1477 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1478 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1479 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1480 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1481 }
1482 }
1483
dsi_fifo_status(struct msm_dsi_host * msm_host)1484 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1485 {
1486 u32 status;
1487
1488 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1489
1490 /* fifo underflow, overflow */
1491 if (status) {
1492 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1493 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1494 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1495 msm_host->err_work_state |=
1496 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1497 }
1498 }
1499
dsi_status(struct msm_dsi_host * msm_host)1500 static void dsi_status(struct msm_dsi_host *msm_host)
1501 {
1502 u32 status;
1503
1504 status = dsi_read(msm_host, REG_DSI_STATUS0);
1505
1506 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1507 dsi_write(msm_host, REG_DSI_STATUS0, status);
1508 msm_host->err_work_state |=
1509 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1510 }
1511 }
1512
dsi_clk_status(struct msm_dsi_host * msm_host)1513 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1514 {
1515 u32 status;
1516
1517 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1518
1519 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1520 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1521 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1522 }
1523 }
1524
dsi_error(struct msm_dsi_host * msm_host)1525 static void dsi_error(struct msm_dsi_host *msm_host)
1526 {
1527 /* disable dsi error interrupt */
1528 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1529
1530 dsi_clk_status(msm_host);
1531 dsi_fifo_status(msm_host);
1532 dsi_ack_err_status(msm_host);
1533 dsi_timeout_status(msm_host);
1534 dsi_status(msm_host);
1535 dsi_dln0_phy_err(msm_host);
1536
1537 queue_work(msm_host->workqueue, &msm_host->err_work);
1538 }
1539
dsi_host_irq(int irq,void * ptr)1540 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1541 {
1542 struct msm_dsi_host *msm_host = ptr;
1543 u32 isr;
1544 unsigned long flags;
1545
1546 if (!msm_host->ctrl_base)
1547 return IRQ_HANDLED;
1548
1549 spin_lock_irqsave(&msm_host->intr_lock, flags);
1550 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1551 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1552 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1553
1554 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1555
1556 if (isr & DSI_IRQ_ERROR)
1557 dsi_error(msm_host);
1558
1559 if (isr & DSI_IRQ_VIDEO_DONE)
1560 complete(&msm_host->video_comp);
1561
1562 if (isr & DSI_IRQ_CMD_DMA_DONE)
1563 complete(&msm_host->dma_comp);
1564
1565 return IRQ_HANDLED;
1566 }
1567
dsi_host_init_panel_gpios(struct msm_dsi_host * msm_host,struct device * panel_device)1568 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1569 struct device *panel_device)
1570 {
1571 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1572 "disp-enable",
1573 GPIOD_OUT_LOW);
1574 if (IS_ERR(msm_host->disp_en_gpio)) {
1575 DBG("cannot get disp-enable-gpios %ld",
1576 PTR_ERR(msm_host->disp_en_gpio));
1577 return PTR_ERR(msm_host->disp_en_gpio);
1578 }
1579
1580 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1581 GPIOD_IN);
1582 if (IS_ERR(msm_host->te_gpio)) {
1583 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1584 return PTR_ERR(msm_host->te_gpio);
1585 }
1586
1587 return 0;
1588 }
1589
dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)1590 static int dsi_host_attach(struct mipi_dsi_host *host,
1591 struct mipi_dsi_device *dsi)
1592 {
1593 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1594 int ret;
1595
1596 if (dsi->lanes > msm_host->num_data_lanes)
1597 return -EINVAL;
1598
1599 msm_host->channel = dsi->channel;
1600 msm_host->lanes = dsi->lanes;
1601 msm_host->format = dsi->format;
1602 msm_host->mode_flags = dsi->mode_flags;
1603 if (dsi->dsc)
1604 msm_host->dsc = dsi->dsc;
1605
1606 /* Some gpios defined in panel DT need to be controlled by host */
1607 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1608 if (ret)
1609 return ret;
1610
1611 ret = dsi_dev_attach(msm_host->pdev);
1612 if (ret)
1613 return ret;
1614
1615 DBG("id=%d", msm_host->id);
1616
1617 return 0;
1618 }
1619
dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)1620 static int dsi_host_detach(struct mipi_dsi_host *host,
1621 struct mipi_dsi_device *dsi)
1622 {
1623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1624
1625 dsi_dev_detach(msm_host->pdev);
1626
1627 DBG("id=%d", msm_host->id);
1628
1629 return 0;
1630 }
1631
dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1632 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1633 const struct mipi_dsi_msg *msg)
1634 {
1635 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1636 int ret;
1637
1638 if (!msg || !msm_host->power_on)
1639 return -EINVAL;
1640
1641 mutex_lock(&msm_host->cmd_mutex);
1642 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1643 mutex_unlock(&msm_host->cmd_mutex);
1644
1645 return ret;
1646 }
1647
1648 static const struct mipi_dsi_host_ops dsi_host_ops = {
1649 .attach = dsi_host_attach,
1650 .detach = dsi_host_detach,
1651 .transfer = dsi_host_transfer,
1652 };
1653
1654 /*
1655 * List of supported physical to logical lane mappings.
1656 * For example, the 2nd entry represents the following mapping:
1657 *
1658 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1659 */
1660 static const int supported_data_lane_swaps[][4] = {
1661 { 0, 1, 2, 3 },
1662 { 3, 0, 1, 2 },
1663 { 2, 3, 0, 1 },
1664 { 1, 2, 3, 0 },
1665 { 0, 3, 2, 1 },
1666 { 1, 0, 3, 2 },
1667 { 2, 1, 0, 3 },
1668 { 3, 2, 1, 0 },
1669 };
1670
dsi_host_parse_lane_data(struct msm_dsi_host * msm_host,struct device_node * ep)1671 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1672 struct device_node *ep)
1673 {
1674 struct device *dev = &msm_host->pdev->dev;
1675 struct property *prop;
1676 u32 lane_map[4];
1677 int ret, i, len, num_lanes;
1678
1679 prop = of_find_property(ep, "data-lanes", &len);
1680 if (!prop) {
1681 DRM_DEV_DEBUG(dev,
1682 "failed to find data lane mapping, using default\n");
1683 /* Set the number of date lanes to 4 by default. */
1684 msm_host->num_data_lanes = 4;
1685 return 0;
1686 }
1687
1688 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4);
1689 if (num_lanes < 0) {
1690 DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1691 return num_lanes;
1692 }
1693
1694 msm_host->num_data_lanes = num_lanes;
1695
1696 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1697 num_lanes);
1698 if (ret) {
1699 DRM_DEV_ERROR(dev, "failed to read lane data\n");
1700 return ret;
1701 }
1702
1703 /*
1704 * compare DT specified physical-logical lane mappings with the ones
1705 * supported by hardware
1706 */
1707 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1708 const int *swap = supported_data_lane_swaps[i];
1709 int j;
1710
1711 /*
1712 * the data-lanes array we get from DT has a logical->physical
1713 * mapping. The "data lane swap" register field represents
1714 * supported configurations in a physical->logical mapping.
1715 * Translate the DT mapping to what we understand and find a
1716 * configuration that works.
1717 */
1718 for (j = 0; j < num_lanes; j++) {
1719 if (lane_map[j] < 0 || lane_map[j] > 3)
1720 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1721 lane_map[j]);
1722
1723 if (swap[lane_map[j]] != j)
1724 break;
1725 }
1726
1727 if (j == num_lanes) {
1728 msm_host->dlane_swap = i;
1729 return 0;
1730 }
1731 }
1732
1733 return -EINVAL;
1734 }
1735
1736 static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
1737 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
1738 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
1739 };
1740
1741 /* only 8bpc, 8bpp added */
1742 static char min_qp[DSC_NUM_BUF_RANGES] = {
1743 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
1744 };
1745
1746 static char max_qp[DSC_NUM_BUF_RANGES] = {
1747 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
1748 };
1749
1750 static char bpg_offset[DSC_NUM_BUF_RANGES] = {
1751 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
1752 };
1753
dsi_populate_dsc_params(struct msm_dsi_host * msm_host,struct drm_dsc_config * dsc)1754 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
1755 {
1756 int i;
1757 u16 bpp = dsc->bits_per_pixel >> 4;
1758
1759 if (dsc->bits_per_pixel & 0xf) {
1760 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
1761 return -EINVAL;
1762 }
1763
1764 if (dsc->bits_per_component != 8) {
1765 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n");
1766 return -EOPNOTSUPP;
1767 }
1768
1769 dsc->rc_model_size = 8192;
1770 dsc->first_line_bpg_offset = 12;
1771 dsc->rc_edge_factor = 6;
1772 dsc->rc_tgt_offset_high = 3;
1773 dsc->rc_tgt_offset_low = 3;
1774 dsc->simple_422 = 0;
1775 dsc->convert_rgb = 1;
1776 dsc->vbr_enable = 0;
1777
1778 /* handle only bpp = bpc = 8 */
1779 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
1780 dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
1781
1782 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
1783 dsc->rc_range_params[i].range_min_qp = min_qp[i];
1784 dsc->rc_range_params[i].range_max_qp = max_qp[i];
1785 /*
1786 * Range BPG Offset contains two's-complement signed values that fill
1787 * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
1788 */
1789 dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
1790 }
1791
1792 dsc->initial_offset = 6144; /* Not bpp 12 */
1793 if (bpp != 8)
1794 dsc->initial_offset = 2048; /* bpp = 12 */
1795
1796 if (dsc->bits_per_component <= 10)
1797 dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
1798 else
1799 dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
1800
1801 dsc->initial_xmit_delay = 512;
1802 dsc->initial_scale_value = 32;
1803 dsc->first_line_bpg_offset = 12;
1804 dsc->line_buf_depth = dsc->bits_per_component + 1;
1805
1806 /* bpc 8 */
1807 dsc->flatness_min_qp = 3;
1808 dsc->flatness_max_qp = 12;
1809 dsc->rc_quant_incr_limit0 = 11;
1810 dsc->rc_quant_incr_limit1 = 11;
1811
1812 return drm_dsc_compute_rc_parameters(dsc);
1813 }
1814
dsi_host_parse_dt(struct msm_dsi_host * msm_host)1815 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1816 {
1817 struct device *dev = &msm_host->pdev->dev;
1818 struct device_node *np = dev->of_node;
1819 struct device_node *endpoint;
1820 int ret = 0;
1821
1822 /*
1823 * Get the endpoint of the output port of the DSI host. In our case,
1824 * this is mapped to port number with reg = 1. Don't return an error if
1825 * the remote endpoint isn't defined. It's possible that there is
1826 * nothing connected to the dsi output.
1827 */
1828 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1829 if (!endpoint) {
1830 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1831 return 0;
1832 }
1833
1834 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1835 if (ret) {
1836 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1837 __func__, ret);
1838 ret = -EINVAL;
1839 goto err;
1840 }
1841
1842 if (of_property_read_bool(np, "syscon-sfpb")) {
1843 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1844 "syscon-sfpb");
1845 if (IS_ERR(msm_host->sfpb)) {
1846 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1847 __func__);
1848 ret = PTR_ERR(msm_host->sfpb);
1849 }
1850 }
1851
1852 err:
1853 of_node_put(endpoint);
1854
1855 return ret;
1856 }
1857
dsi_host_get_id(struct msm_dsi_host * msm_host)1858 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1859 {
1860 struct platform_device *pdev = msm_host->pdev;
1861 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1862 struct resource *res;
1863 int i;
1864
1865 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1866 if (!res)
1867 return -EINVAL;
1868
1869 for (i = 0; i < cfg->num_dsi; i++) {
1870 if (cfg->io_start[i] == res->start)
1871 return i;
1872 }
1873
1874 return -EINVAL;
1875 }
1876
msm_dsi_host_init(struct msm_dsi * msm_dsi)1877 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1878 {
1879 struct msm_dsi_host *msm_host = NULL;
1880 struct platform_device *pdev = msm_dsi->pdev;
1881 const struct msm_dsi_config *cfg;
1882 int ret;
1883
1884 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1885 if (!msm_host) {
1886 ret = -ENOMEM;
1887 goto fail;
1888 }
1889
1890 msm_host->pdev = pdev;
1891 msm_dsi->host = &msm_host->base;
1892
1893 ret = dsi_host_parse_dt(msm_host);
1894 if (ret) {
1895 pr_err("%s: failed to parse dt\n", __func__);
1896 goto fail;
1897 }
1898
1899 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size);
1900 if (IS_ERR(msm_host->ctrl_base)) {
1901 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1902 ret = PTR_ERR(msm_host->ctrl_base);
1903 goto fail;
1904 }
1905
1906 pm_runtime_enable(&pdev->dev);
1907
1908 msm_host->cfg_hnd = dsi_get_config(msm_host);
1909 if (!msm_host->cfg_hnd) {
1910 ret = -EINVAL;
1911 pr_err("%s: get config failed\n", __func__);
1912 goto fail;
1913 }
1914 cfg = msm_host->cfg_hnd->cfg;
1915
1916 msm_host->id = dsi_host_get_id(msm_host);
1917 if (msm_host->id < 0) {
1918 ret = msm_host->id;
1919 pr_err("%s: unable to identify DSI host index\n", __func__);
1920 goto fail;
1921 }
1922
1923 /* fixup base address by io offset */
1924 msm_host->ctrl_base += cfg->io_offset;
1925
1926 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators,
1927 cfg->regulator_data,
1928 &msm_host->supplies);
1929 if (ret)
1930 goto fail;
1931
1932 ret = dsi_clk_init(msm_host);
1933 if (ret) {
1934 pr_err("%s: unable to initialize dsi clks\n", __func__);
1935 goto fail;
1936 }
1937
1938 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1939 if (!msm_host->rx_buf) {
1940 ret = -ENOMEM;
1941 pr_err("%s: alloc rx temp buf failed\n", __func__);
1942 goto fail;
1943 }
1944
1945 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1946 if (ret)
1947 return ret;
1948 /* OPP table is optional */
1949 ret = devm_pm_opp_of_add_table(&pdev->dev);
1950 if (ret && ret != -ENODEV) {
1951 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1952 return ret;
1953 }
1954
1955 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1956 if (msm_host->irq < 0) {
1957 ret = msm_host->irq;
1958 dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
1959 return ret;
1960 }
1961
1962 /* do not autoenable, will be enabled later */
1963 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq,
1964 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1965 "dsi_isr", msm_host);
1966 if (ret < 0) {
1967 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1968 msm_host->irq, ret);
1969 return ret;
1970 }
1971
1972 init_completion(&msm_host->dma_comp);
1973 init_completion(&msm_host->video_comp);
1974 mutex_init(&msm_host->dev_mutex);
1975 mutex_init(&msm_host->cmd_mutex);
1976 spin_lock_init(&msm_host->intr_lock);
1977
1978 /* setup workqueue */
1979 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1980 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1981
1982 msm_dsi->id = msm_host->id;
1983
1984 DBG("Dsi Host %d initialized", msm_host->id);
1985 return 0;
1986
1987 fail:
1988 return ret;
1989 }
1990
msm_dsi_host_destroy(struct mipi_dsi_host * host)1991 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1992 {
1993 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1994
1995 DBG("");
1996 dsi_tx_buf_free(msm_host);
1997 if (msm_host->workqueue) {
1998 destroy_workqueue(msm_host->workqueue);
1999 msm_host->workqueue = NULL;
2000 }
2001
2002 mutex_destroy(&msm_host->cmd_mutex);
2003 mutex_destroy(&msm_host->dev_mutex);
2004
2005 pm_runtime_disable(&msm_host->pdev->dev);
2006 }
2007
msm_dsi_host_modeset_init(struct mipi_dsi_host * host,struct drm_device * dev)2008 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
2009 struct drm_device *dev)
2010 {
2011 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2012 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2013 int ret;
2014
2015 msm_host->dev = dev;
2016
2017 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
2018 if (ret) {
2019 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
2020 return ret;
2021 }
2022
2023 return 0;
2024 }
2025
msm_dsi_host_register(struct mipi_dsi_host * host)2026 int msm_dsi_host_register(struct mipi_dsi_host *host)
2027 {
2028 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2029 int ret;
2030
2031 /* Register mipi dsi host */
2032 if (!msm_host->registered) {
2033 host->dev = &msm_host->pdev->dev;
2034 host->ops = &dsi_host_ops;
2035 ret = mipi_dsi_host_register(host);
2036 if (ret)
2037 return ret;
2038
2039 msm_host->registered = true;
2040 }
2041
2042 return 0;
2043 }
2044
msm_dsi_host_unregister(struct mipi_dsi_host * host)2045 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
2046 {
2047 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2048
2049 if (msm_host->registered) {
2050 mipi_dsi_host_unregister(host);
2051 host->dev = NULL;
2052 host->ops = NULL;
2053 msm_host->registered = false;
2054 }
2055 }
2056
msm_dsi_host_xfer_prepare(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)2057 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
2058 const struct mipi_dsi_msg *msg)
2059 {
2060 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2061 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2062
2063 /* TODO: make sure dsi_cmd_mdp is idle.
2064 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
2065 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2066 * How to handle the old versions? Wait for mdp cmd done?
2067 */
2068
2069 /*
2070 * mdss interrupt is generated in mdp core clock domain
2071 * mdp clock need to be enabled to receive dsi interrupt
2072 */
2073 pm_runtime_get_sync(&msm_host->pdev->dev);
2074 cfg_hnd->ops->link_clk_set_rate(msm_host);
2075 cfg_hnd->ops->link_clk_enable(msm_host);
2076
2077 /* TODO: vote for bus bandwidth */
2078
2079 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2080 dsi_set_tx_power_mode(0, msm_host);
2081
2082 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2083 dsi_write(msm_host, REG_DSI_CTRL,
2084 msm_host->dma_cmd_ctrl_restore |
2085 DSI_CTRL_CMD_MODE_EN |
2086 DSI_CTRL_ENABLE);
2087 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2088
2089 return 0;
2090 }
2091
msm_dsi_host_xfer_restore(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)2092 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2093 const struct mipi_dsi_msg *msg)
2094 {
2095 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2096 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2097
2098 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2099 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2100
2101 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2102 dsi_set_tx_power_mode(1, msm_host);
2103
2104 /* TODO: unvote for bus bandwidth */
2105
2106 cfg_hnd->ops->link_clk_disable(msm_host);
2107 pm_runtime_put(&msm_host->pdev->dev);
2108 }
2109
msm_dsi_host_cmd_tx(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)2110 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2111 const struct mipi_dsi_msg *msg)
2112 {
2113 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2114
2115 return dsi_cmds2buf_tx(msm_host, msg);
2116 }
2117
msm_dsi_host_cmd_rx(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)2118 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2119 const struct mipi_dsi_msg *msg)
2120 {
2121 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2122 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2123 int data_byte, rx_byte, dlen, end;
2124 int short_response, diff, pkt_size, ret = 0;
2125 char cmd;
2126 int rlen = msg->rx_len;
2127 u8 *buf;
2128
2129 if (rlen <= 2) {
2130 short_response = 1;
2131 pkt_size = rlen;
2132 rx_byte = 4;
2133 } else {
2134 short_response = 0;
2135 data_byte = 10; /* first read */
2136 if (rlen < data_byte)
2137 pkt_size = rlen;
2138 else
2139 pkt_size = data_byte;
2140 rx_byte = data_byte + 6; /* 4 header + 2 crc */
2141 }
2142
2143 buf = msm_host->rx_buf;
2144 end = 0;
2145 while (!end) {
2146 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2147 struct mipi_dsi_msg max_pkt_size_msg = {
2148 .channel = msg->channel,
2149 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2150 .tx_len = 2,
2151 .tx_buf = tx,
2152 };
2153
2154 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2155 rlen, pkt_size, rx_byte);
2156
2157 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2158 if (ret < 2) {
2159 pr_err("%s: Set max pkt size failed, %d\n",
2160 __func__, ret);
2161 return -EINVAL;
2162 }
2163
2164 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2165 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2166 /* Clear the RDBK_DATA registers */
2167 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2168 DSI_RDBK_DATA_CTRL_CLR);
2169 wmb(); /* make sure the RDBK registers are cleared */
2170 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2171 wmb(); /* release cleared status before transfer */
2172 }
2173
2174 ret = dsi_cmds2buf_tx(msm_host, msg);
2175 if (ret < 0) {
2176 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2177 return ret;
2178 } else if (ret < msg->tx_len) {
2179 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
2180 return -ECOMM;
2181 }
2182
2183 /*
2184 * once cmd_dma_done interrupt received,
2185 * return data from client is ready and stored
2186 * at RDBK_DATA register already
2187 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2188 * after that dcs header lost during shift into registers
2189 */
2190 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2191
2192 if (dlen <= 0)
2193 return 0;
2194
2195 if (short_response)
2196 break;
2197
2198 if (rlen <= data_byte) {
2199 diff = data_byte - rlen;
2200 end = 1;
2201 } else {
2202 diff = 0;
2203 rlen -= data_byte;
2204 }
2205
2206 if (!end) {
2207 dlen -= 2; /* 2 crc */
2208 dlen -= diff;
2209 buf += dlen; /* next start position */
2210 data_byte = 14; /* NOT first read */
2211 if (rlen < data_byte)
2212 pkt_size += rlen;
2213 else
2214 pkt_size += data_byte;
2215 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2216 }
2217 }
2218
2219 /*
2220 * For single Long read, if the requested rlen < 10,
2221 * we need to shift the start position of rx
2222 * data buffer to skip the bytes which are not
2223 * updated.
2224 */
2225 if (pkt_size < 10 && !short_response)
2226 buf = msm_host->rx_buf + (10 - rlen);
2227 else
2228 buf = msm_host->rx_buf;
2229
2230 cmd = buf[0];
2231 switch (cmd) {
2232 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2233 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2234 ret = 0;
2235 break;
2236 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2237 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2238 ret = dsi_short_read1_resp(buf, msg);
2239 break;
2240 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2241 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2242 ret = dsi_short_read2_resp(buf, msg);
2243 break;
2244 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2245 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2246 ret = dsi_long_read_resp(buf, msg);
2247 break;
2248 default:
2249 pr_warn("%s:Invalid response cmd\n", __func__);
2250 ret = 0;
2251 }
2252
2253 return ret;
2254 }
2255
msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host * host,u32 dma_base,u32 len)2256 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2257 u32 len)
2258 {
2259 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2260
2261 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2262 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2263 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2264
2265 /* Make sure trigger happens */
2266 wmb();
2267 }
2268
msm_dsi_host_set_phy_mode(struct mipi_dsi_host * host,struct msm_dsi_phy * src_phy)2269 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host,
2270 struct msm_dsi_phy *src_phy)
2271 {
2272 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2273
2274 msm_host->cphy_mode = src_phy->cphy_mode;
2275 }
2276
msm_dsi_host_reset_phy(struct mipi_dsi_host * host)2277 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2278 {
2279 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2280
2281 DBG("");
2282 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2283 /* Make sure fully reset */
2284 wmb();
2285 udelay(1000);
2286 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2287 udelay(100);
2288 }
2289
msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host * host,struct msm_dsi_phy_clk_request * clk_req,bool is_bonded_dsi)2290 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2291 struct msm_dsi_phy_clk_request *clk_req,
2292 bool is_bonded_dsi)
2293 {
2294 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2295 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2296 int ret;
2297
2298 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
2299 if (ret) {
2300 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2301 return;
2302 }
2303
2304 /* CPHY transmits 16 bits over 7 clock cycles
2305 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk),
2306 * so multiply by 7 to get the "bitclk rate"
2307 */
2308 if (msm_host->cphy_mode)
2309 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7;
2310 else
2311 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2312 clk_req->escclk_rate = msm_host->esc_clk_rate;
2313 }
2314
msm_dsi_host_enable_irq(struct mipi_dsi_host * host)2315 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host)
2316 {
2317 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2318
2319 enable_irq(msm_host->irq);
2320 }
2321
msm_dsi_host_disable_irq(struct mipi_dsi_host * host)2322 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host)
2323 {
2324 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2325
2326 disable_irq(msm_host->irq);
2327 }
2328
msm_dsi_host_enable(struct mipi_dsi_host * host)2329 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2330 {
2331 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2332
2333 dsi_op_mode_config(msm_host,
2334 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2335
2336 /* TODO: clock should be turned off for command mode,
2337 * and only turned on before MDP START.
2338 * This part of code should be enabled once mdp driver support it.
2339 */
2340 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2341 * dsi_link_clk_disable(msm_host);
2342 * pm_runtime_put(&msm_host->pdev->dev);
2343 * }
2344 */
2345 msm_host->enabled = true;
2346 return 0;
2347 }
2348
msm_dsi_host_disable(struct mipi_dsi_host * host)2349 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2350 {
2351 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2352
2353 msm_host->enabled = false;
2354 dsi_op_mode_config(msm_host,
2355 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2356
2357 /* Since we have disabled INTF, the video engine won't stop so that
2358 * the cmd engine will be blocked.
2359 * Reset to disable video engine so that we can send off cmd.
2360 */
2361 dsi_sw_reset(msm_host);
2362
2363 return 0;
2364 }
2365
msm_dsi_sfpb_config(struct msm_dsi_host * msm_host,bool enable)2366 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2367 {
2368 enum sfpb_ahb_arb_master_port_en en;
2369
2370 if (!msm_host->sfpb)
2371 return;
2372
2373 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2374
2375 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2376 SFPB_GPREG_MASTER_PORT_EN__MASK,
2377 SFPB_GPREG_MASTER_PORT_EN(en));
2378 }
2379
msm_dsi_host_power_on(struct mipi_dsi_host * host,struct msm_dsi_phy_shared_timings * phy_shared_timings,bool is_bonded_dsi,struct msm_dsi_phy * phy)2380 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2381 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2382 bool is_bonded_dsi, struct msm_dsi_phy *phy)
2383 {
2384 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2385 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2386 int ret = 0;
2387
2388 mutex_lock(&msm_host->dev_mutex);
2389 if (msm_host->power_on) {
2390 DBG("dsi host already on");
2391 goto unlock_ret;
2392 }
2393
2394 msm_dsi_sfpb_config(msm_host, true);
2395
2396 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators,
2397 msm_host->supplies);
2398 if (ret) {
2399 pr_err("%s:Failed to enable vregs.ret=%d\n",
2400 __func__, ret);
2401 goto unlock_ret;
2402 }
2403
2404 pm_runtime_get_sync(&msm_host->pdev->dev);
2405 ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
2406 if (!ret)
2407 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2408 if (ret) {
2409 pr_err("%s: failed to enable link clocks. ret=%d\n",
2410 __func__, ret);
2411 goto fail_disable_reg;
2412 }
2413
2414 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2415 if (ret) {
2416 pr_err("%s: failed to set pinctrl default state, %d\n",
2417 __func__, ret);
2418 goto fail_disable_clk;
2419 }
2420
2421 dsi_timing_setup(msm_host, is_bonded_dsi);
2422 dsi_sw_reset(msm_host);
2423 dsi_ctrl_config(msm_host, true, phy_shared_timings, phy);
2424
2425 if (msm_host->disp_en_gpio)
2426 gpiod_set_value(msm_host->disp_en_gpio, 1);
2427
2428 msm_host->power_on = true;
2429 mutex_unlock(&msm_host->dev_mutex);
2430
2431 return 0;
2432
2433 fail_disable_clk:
2434 cfg_hnd->ops->link_clk_disable(msm_host);
2435 pm_runtime_put(&msm_host->pdev->dev);
2436 fail_disable_reg:
2437 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2438 msm_host->supplies);
2439 unlock_ret:
2440 mutex_unlock(&msm_host->dev_mutex);
2441 return ret;
2442 }
2443
msm_dsi_host_power_off(struct mipi_dsi_host * host)2444 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2445 {
2446 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2447 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2448
2449 mutex_lock(&msm_host->dev_mutex);
2450 if (!msm_host->power_on) {
2451 DBG("dsi host already off");
2452 goto unlock_ret;
2453 }
2454
2455 dsi_ctrl_config(msm_host, false, NULL, NULL);
2456
2457 if (msm_host->disp_en_gpio)
2458 gpiod_set_value(msm_host->disp_en_gpio, 0);
2459
2460 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2461
2462 cfg_hnd->ops->link_clk_disable(msm_host);
2463 pm_runtime_put(&msm_host->pdev->dev);
2464
2465 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2466 msm_host->supplies);
2467
2468 msm_dsi_sfpb_config(msm_host, false);
2469
2470 DBG("-");
2471
2472 msm_host->power_on = false;
2473
2474 unlock_ret:
2475 mutex_unlock(&msm_host->dev_mutex);
2476 return 0;
2477 }
2478
msm_dsi_host_set_display_mode(struct mipi_dsi_host * host,const struct drm_display_mode * mode)2479 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2480 const struct drm_display_mode *mode)
2481 {
2482 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2483
2484 if (msm_host->mode) {
2485 drm_mode_destroy(msm_host->dev, msm_host->mode);
2486 msm_host->mode = NULL;
2487 }
2488
2489 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2490 if (!msm_host->mode) {
2491 pr_err("%s: cannot duplicate mode\n", __func__);
2492 return -ENOMEM;
2493 }
2494
2495 return 0;
2496 }
2497
msm_dsi_host_check_dsc(struct mipi_dsi_host * host,const struct drm_display_mode * mode)2498 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
2499 const struct drm_display_mode *mode)
2500 {
2501 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2502 struct drm_dsc_config *dsc = msm_host->dsc;
2503 int pic_width = mode->hdisplay;
2504 int pic_height = mode->vdisplay;
2505
2506 if (!msm_host->dsc)
2507 return MODE_OK;
2508
2509 if (pic_width % dsc->slice_width) {
2510 pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
2511 pic_width, dsc->slice_width);
2512 return MODE_H_ILLEGAL;
2513 }
2514
2515 if (pic_height % dsc->slice_height) {
2516 pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
2517 pic_height, dsc->slice_height);
2518 return MODE_V_ILLEGAL;
2519 }
2520
2521 return MODE_OK;
2522 }
2523
msm_dsi_host_get_mode_flags(struct mipi_dsi_host * host)2524 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2525 {
2526 return to_msm_dsi_host(host)->mode_flags;
2527 }
2528
msm_dsi_host_snapshot(struct msm_disp_state * disp_state,struct mipi_dsi_host * host)2529 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2530 {
2531 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2532
2533 pm_runtime_get_sync(&msm_host->pdev->dev);
2534
2535 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2536 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2537
2538 pm_runtime_put_sync(&msm_host->pdev->dev);
2539 }
2540
msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host * msm_host)2541 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host)
2542 {
2543 u32 reg;
2544
2545 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2546
2547 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);
2548 /* draw checkered rectangle pattern */
2549 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,
2550 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN);
2551 /* use 24-bit RGB test pttern */
2552 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,
2553 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) |
2554 DSI_TPG_VIDEO_CONFIG_RGB);
2555
2556 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN);
2557 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2558
2559 DBG("Video test pattern setup done\n");
2560 }
2561
msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host * msm_host)2562 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host)
2563 {
2564 u32 reg;
2565
2566 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2567
2568 /* initial value for test pattern */
2569 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
2570
2571 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN);
2572
2573 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2574 /* draw checkered rectangle pattern */
2575 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,
2576 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN);
2577
2578 DBG("Cmd test pattern setup done\n");
2579 }
2580
msm_dsi_host_test_pattern_en(struct mipi_dsi_host * host)2581 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
2582 {
2583 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2584 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);
2585 u32 reg;
2586
2587 if (is_video_mode)
2588 msm_dsi_host_video_test_pattern_setup(msm_host);
2589 else
2590 msm_dsi_host_cmd_test_pattern_setup(msm_host);
2591
2592 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2593 /* enable the test pattern generator */
2594 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));
2595
2596 /* for command mode need to trigger one frame from tpg */
2597 if (!is_video_mode)
2598 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
2599 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
2600 }
2601
msm_dsi_host_get_dsc_config(struct mipi_dsi_host * host)2602 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
2603 {
2604 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2605
2606 return msm_host->dsc;
2607 }
2608