1 /*
2 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27
28 #include <drm/display/drm_scdc_helper.h>
29 #include <drm/drm_print.h>
30
31 /**
32 * DOC: scdc helpers
33 *
34 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
35 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
36 * HDMI source and HDMI sink to exchange data. The same I2C interface that
37 * is used to access EDID serves as the transport mechanism for SCDC.
38 */
39
40 #define SCDC_I2C_SLAVE_ADDRESS 0x54
41
42 /**
43 * drm_scdc_read - read a block of data from SCDC
44 * @adapter: I2C controller
45 * @offset: start offset of block to read
46 * @buffer: return location for the block to read
47 * @size: size of the block to read
48 *
49 * Reads a block of data from SCDC, starting at a given offset.
50 *
51 * Returns:
52 * 0 on success, negative error code on failure.
53 */
drm_scdc_read(struct i2c_adapter * adapter,u8 offset,void * buffer,size_t size)54 ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
55 size_t size)
56 {
57 int ret;
58 struct i2c_msg msgs[2] = {
59 {
60 .addr = SCDC_I2C_SLAVE_ADDRESS,
61 .flags = 0,
62 .len = 1,
63 .buf = &offset,
64 }, {
65 .addr = SCDC_I2C_SLAVE_ADDRESS,
66 .flags = I2C_M_RD,
67 .len = size,
68 .buf = buffer,
69 }
70 };
71
72 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
73 if (ret < 0)
74 return ret;
75 if (ret != ARRAY_SIZE(msgs))
76 return -EPROTO;
77
78 return 0;
79 }
80 EXPORT_SYMBOL(drm_scdc_read);
81
82 /**
83 * drm_scdc_write - write a block of data to SCDC
84 * @adapter: I2C controller
85 * @offset: start offset of block to write
86 * @buffer: block of data to write
87 * @size: size of the block to write
88 *
89 * Writes a block of data to SCDC, starting at a given offset.
90 *
91 * Returns:
92 * 0 on success, negative error code on failure.
93 */
drm_scdc_write(struct i2c_adapter * adapter,u8 offset,const void * buffer,size_t size)94 ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
95 const void *buffer, size_t size)
96 {
97 struct i2c_msg msg = {
98 .addr = SCDC_I2C_SLAVE_ADDRESS,
99 .flags = 0,
100 .len = 1 + size,
101 .buf = NULL,
102 };
103 void *data;
104 int err;
105
106 data = kmalloc(1 + size, GFP_KERNEL);
107 if (!data)
108 return -ENOMEM;
109
110 msg.buf = data;
111
112 memcpy(data, &offset, sizeof(offset));
113 memcpy(data + 1, buffer, size);
114
115 err = i2c_transfer(adapter, &msg, 1);
116
117 kfree(data);
118
119 if (err < 0)
120 return err;
121 if (err != 1)
122 return -EPROTO;
123
124 return 0;
125 }
126 EXPORT_SYMBOL(drm_scdc_write);
127
128 /**
129 * drm_scdc_get_scrambling_status - what is status of scrambling?
130 * @adapter: I2C adapter for DDC channel
131 *
132 * Reads the scrambler status over SCDC, and checks the
133 * scrambling status.
134 *
135 * Returns:
136 * True if the scrambling is enabled, false otherwise.
137 */
drm_scdc_get_scrambling_status(struct i2c_adapter * adapter)138 bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
139 {
140 u8 status;
141 int ret;
142
143 ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
144 if (ret < 0) {
145 DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
146 return false;
147 }
148
149 return status & SCDC_SCRAMBLING_STATUS;
150 }
151 EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
152
153 /**
154 * drm_scdc_set_scrambling - enable scrambling
155 * @adapter: I2C adapter for DDC channel
156 * @enable: bool to indicate if scrambling is to be enabled/disabled
157 *
158 * Writes the TMDS config register over SCDC channel, and:
159 * enables scrambling when enable = 1
160 * disables scrambling when enable = 0
161 *
162 * Returns:
163 * True if scrambling is set/reset successfully, false otherwise.
164 */
drm_scdc_set_scrambling(struct i2c_adapter * adapter,bool enable)165 bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
166 {
167 u8 config;
168 int ret;
169
170 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
171 if (ret < 0) {
172 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
173 return false;
174 }
175
176 if (enable)
177 config |= SCDC_SCRAMBLING_ENABLE;
178 else
179 config &= ~SCDC_SCRAMBLING_ENABLE;
180
181 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
182 if (ret < 0) {
183 DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret);
184 return false;
185 }
186
187 return true;
188 }
189 EXPORT_SYMBOL(drm_scdc_set_scrambling);
190
191 /**
192 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
193 * @adapter: I2C adapter for DDC channel
194 * @set: ret or reset the high clock ratio
195 *
196 *
197 * TMDS clock ratio calculations go like this:
198 * TMDS character = 10 bit TMDS encoded value
199 *
200 * TMDS character rate = The rate at which TMDS characters are
201 * transmitted (Mcsc)
202 *
203 * TMDS bit rate = 10x TMDS character rate
204 *
205 * As per the spec:
206 * TMDS clock rate for pixel clock < 340 MHz = 1x the character
207 * rate = 1/10 pixel clock rate
208 *
209 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
210 * rate = 1/40 pixel clock rate
211 *
212 * Writes to the TMDS config register over SCDC channel, and:
213 * sets TMDS clock ratio to 1/40 when set = 1
214 *
215 * sets TMDS clock ratio to 1/10 when set = 0
216 *
217 * Returns:
218 * True if write is successful, false otherwise.
219 */
drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter * adapter,bool set)220 bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
221 {
222 u8 config;
223 int ret;
224
225 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
226 if (ret < 0) {
227 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
228 return false;
229 }
230
231 if (set)
232 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
233 else
234 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
235
236 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
237 if (ret < 0) {
238 DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret);
239 return false;
240 }
241
242 /*
243 * The spec says that a source should wait minimum 1ms and maximum
244 * 100ms after writing the TMDS config for clock ratio. Lets allow a
245 * wait of up to 2ms here.
246 */
247 usleep_range(1000, 2000);
248 return true;
249 }
250 EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
251