1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25 #ifndef AMDGPU_AMDKFD_H_INCLUDED
26 #define AMDGPU_AMDKFD_H_INCLUDED
27
28 #include <linux/types.h>
29 #include <linux/mm.h>
30 #include <linux/kthread.h>
31 #include <linux/workqueue.h>
32 #include <kgd_kfd_interface.h>
33 #include <drm/ttm/ttm_execbuf_util.h>
34 #include "amdgpu_sync.h"
35 #include "amdgpu_vm.h"
36
37 extern uint64_t amdgpu_amdkfd_total_mem_size;
38
39 enum TLB_FLUSH_TYPE {
40 TLB_FLUSH_LEGACY = 0,
41 TLB_FLUSH_LIGHTWEIGHT,
42 TLB_FLUSH_HEAVYWEIGHT
43 };
44
45 struct amdgpu_device;
46
47 enum kfd_mem_attachment_type {
48 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
49 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
50 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
51 };
52
53 struct kfd_mem_attachment {
54 struct list_head list;
55 enum kfd_mem_attachment_type type;
56 bool is_mapped;
57 struct amdgpu_bo_va *bo_va;
58 struct amdgpu_device *adev;
59 uint64_t va;
60 uint64_t pte_flags;
61 };
62
63 struct kgd_mem {
64 struct mutex lock;
65 struct amdgpu_bo *bo;
66 struct dma_buf *dmabuf;
67 struct list_head attachments;
68 /* protected by amdkfd_process_info.lock */
69 struct ttm_validate_buffer validate_list;
70 struct ttm_validate_buffer resv_list;
71 uint32_t domain;
72 unsigned int mapped_to_gpu_memory;
73 uint64_t va;
74
75 uint32_t alloc_flags;
76
77 atomic_t invalid;
78 struct amdkfd_process_info *process_info;
79
80 struct amdgpu_sync sync;
81
82 bool aql_queue;
83 bool is_imported;
84 };
85
86 /* KFD Memory Eviction */
87 struct amdgpu_amdkfd_fence {
88 struct dma_fence base;
89 struct mm_struct *mm;
90 spinlock_t lock;
91 char timeline_name[TASK_COMM_LEN];
92 struct svm_range_bo *svm_bo;
93 };
94
95 struct amdgpu_kfd_dev {
96 struct kfd_dev *dev;
97 uint64_t vram_used;
98 bool init_complete;
99 };
100
101 enum kgd_engine_type {
102 KGD_ENGINE_PFP = 1,
103 KGD_ENGINE_ME,
104 KGD_ENGINE_CE,
105 KGD_ENGINE_MEC1,
106 KGD_ENGINE_MEC2,
107 KGD_ENGINE_RLC,
108 KGD_ENGINE_SDMA1,
109 KGD_ENGINE_SDMA2,
110 KGD_ENGINE_MAX
111 };
112
113
114 struct amdkfd_process_info {
115 /* List head of all VMs that belong to a KFD process */
116 struct list_head vm_list_head;
117 /* List head for all KFD BOs that belong to a KFD process. */
118 struct list_head kfd_bo_list;
119 /* List of userptr BOs that are valid or invalid */
120 struct list_head userptr_valid_list;
121 struct list_head userptr_inval_list;
122 /* Lock to protect kfd_bo_list */
123 struct mutex lock;
124
125 /* Number of VMs */
126 unsigned int n_vms;
127 /* Eviction Fence */
128 struct amdgpu_amdkfd_fence *eviction_fence;
129
130 /* MMU-notifier related fields */
131 atomic_t evicted_bos;
132 struct delayed_work restore_userptr_work;
133 struct pid *pid;
134 bool block_mmu_notifications;
135 };
136
137 int amdgpu_amdkfd_init(void);
138 void amdgpu_amdkfd_fini(void);
139
140 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
141 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
142 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
143 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
144 const void *ih_ring_entry);
145 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
146 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
147 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
148 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
149 enum kgd_engine_type engine,
150 uint32_t vmid, uint64_t gpu_addr,
151 uint32_t *ib_cmd, uint32_t ib_len);
152 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
153 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
154 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
155 uint16_t vmid);
156 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
157 uint16_t pasid, enum TLB_FLUSH_TYPE flush_type);
158
159 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
160
161 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
162
163 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
164
165 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
166
167 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
168 int queue_bit);
169
170 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
171 struct mm_struct *mm,
172 struct svm_range_bo *svm_bo);
173 #if IS_ENABLED(CONFIG_HSA_AMD)
174 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
175 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
176 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
177 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
178 #else
179 static inline
amdkfd_fence_check_mm(struct dma_fence * f,struct mm_struct * mm)180 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
181 {
182 return false;
183 }
184
185 static inline
to_amdgpu_amdkfd_fence(struct dma_fence * f)186 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
187 {
188 return NULL;
189 }
190
191 static inline
amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo * bo)192 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
193 {
194 return 0;
195 }
196
197 static inline
amdgpu_amdkfd_evict_userptr(struct kgd_mem * mem,struct mm_struct * mm)198 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
199 {
200 return 0;
201 }
202 #endif
203 /* Shared API */
204 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
205 void **mem_obj, uint64_t *gpu_addr,
206 void **cpu_ptr, bool mqd_gfx9);
207 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);
208 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
209 void **mem_obj);
210 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
211 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
212 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
213 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
214 enum kgd_engine_type type);
215 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
216 struct kfd_local_mem_info *mem_info);
217 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
218
219 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
220 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev,
221 struct kfd_cu_info *cu_info);
222 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
223 struct amdgpu_device **dmabuf_adev,
224 uint64_t *bo_size, void *metadata_buffer,
225 size_t buffer_size, uint32_t *metadata_size,
226 uint32_t *flags);
227 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
228 struct amdgpu_device *src);
229 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
230 struct amdgpu_device *src,
231 bool is_min);
232 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
233
234 /* Read user wptr from a specified user address space with page fault
235 * disabled. The memory must be pinned and mapped to the hardware when
236 * this is called in hqd_load functions, so it should never fault in
237 * the first place. This resolves a circular lock dependency involving
238 * four locks, including the DQM lock and mmap_lock.
239 */
240 #define read_user_wptr(mmptr, wptr, dst) \
241 ({ \
242 bool valid = false; \
243 if ((mmptr) && (wptr)) { \
244 pagefault_disable(); \
245 if ((mmptr) == current->mm) { \
246 valid = !get_user((dst), (wptr)); \
247 } else if (current->flags & PF_KTHREAD) { \
248 kthread_use_mm(mmptr); \
249 valid = !get_user((dst), (wptr)); \
250 kthread_unuse_mm(mmptr); \
251 } \
252 pagefault_enable(); \
253 } \
254 valid; \
255 })
256
257 /* GPUVM API */
258 #define drm_priv_to_vm(drm_priv) \
259 (&((struct amdgpu_fpriv *) \
260 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
261
262 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
263 struct file *filp, u32 pasid,
264 void **process_info,
265 struct dma_fence **ef);
266 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
267 void *drm_priv);
268 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
269 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
270 struct amdgpu_device *adev, uint64_t va, uint64_t size,
271 void *drm_priv, struct kgd_mem **mem,
272 uint64_t *offset, uint32_t flags, bool criu_resume);
273 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
274 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
275 uint64_t *size);
276 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
277 struct kgd_mem *mem, void *drm_priv);
278 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
279 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
280 int amdgpu_amdkfd_gpuvm_sync_memory(
281 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
282 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
283 struct kgd_mem *mem, void **kptr, uint64_t *size);
284 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
285 struct kgd_mem *mem);
286
287 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
288 struct dma_fence **ef);
289 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
290 struct kfd_vm_fault_info *info);
291 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
292 struct dma_buf *dmabuf,
293 uint64_t va, void *drm_priv,
294 struct kgd_mem **mem, uint64_t *size,
295 uint64_t *mmap_offset);
296 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
297 struct tile_config *config);
298 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
299 bool reset);
300 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
301 void amdgpu_amdkfd_block_mmu_notifications(void *p);
302 int amdgpu_amdkfd_criu_resume(void *p);
303 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
304
305 #if IS_ENABLED(CONFIG_HSA_AMD)
306 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
307 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
308 struct amdgpu_vm *vm);
309
310 /**
311 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
312 *
313 * Allows KFD to release its resources associated with the GEM object.
314 */
315 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
316 void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
317 #else
318 static inline
amdgpu_amdkfd_gpuvm_init_mem_limits(void)319 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
320 {
321 }
322
323 static inline
amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device * adev,struct amdgpu_vm * vm)324 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
325 struct amdgpu_vm *vm)
326 {
327 }
328
329 static inline
amdgpu_amdkfd_release_notify(struct amdgpu_bo * bo)330 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
331 {
332 }
333 #endif
334 /* KGD2KFD callbacks */
335 int kgd2kfd_quiesce_mm(struct mm_struct *mm);
336 int kgd2kfd_resume_mm(struct mm_struct *mm);
337 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
338 struct dma_fence *fence);
339 #if IS_ENABLED(CONFIG_HSA_AMD)
340 int kgd2kfd_init(void);
341 void kgd2kfd_exit(void);
342 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
343 bool kgd2kfd_device_init(struct kfd_dev *kfd,
344 struct drm_device *ddev,
345 const struct kgd2kfd_shared_resources *gpu_resources);
346 void kgd2kfd_device_exit(struct kfd_dev *kfd);
347 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
348 int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
349 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
350 int kgd2kfd_pre_reset(struct kfd_dev *kfd);
351 int kgd2kfd_post_reset(struct kfd_dev *kfd);
352 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
353 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
354 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
355 #else
kgd2kfd_init(void)356 static inline int kgd2kfd_init(void)
357 {
358 return -ENOENT;
359 }
360
kgd2kfd_exit(void)361 static inline void kgd2kfd_exit(void)
362 {
363 }
364
365 static inline
kgd2kfd_probe(struct amdgpu_device * adev,bool vf)366 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
367 {
368 return NULL;
369 }
370
371 static inline
kgd2kfd_device_init(struct kfd_dev * kfd,struct drm_device * ddev,const struct kgd2kfd_shared_resources * gpu_resources)372 bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev,
373 const struct kgd2kfd_shared_resources *gpu_resources)
374 {
375 return false;
376 }
377
kgd2kfd_device_exit(struct kfd_dev * kfd)378 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
379 {
380 }
381
kgd2kfd_suspend(struct kfd_dev * kfd,bool run_pm)382 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
383 {
384 }
385
kgd2kfd_resume_iommu(struct kfd_dev * kfd)386 static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
387 {
388 return 0;
389 }
390
kgd2kfd_resume(struct kfd_dev * kfd,bool run_pm)391 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
392 {
393 return 0;
394 }
395
kgd2kfd_pre_reset(struct kfd_dev * kfd)396 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
397 {
398 return 0;
399 }
400
kgd2kfd_post_reset(struct kfd_dev * kfd)401 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
402 {
403 return 0;
404 }
405
406 static inline
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)407 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
408 {
409 }
410
411 static inline
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)412 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
413 {
414 }
415
416 static inline
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint64_t throttle_bitmask)417 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
418 {
419 }
420 #endif
421 #endif /* AMDGPU_AMDKFD_H_INCLUDED */
422